Semiconductor structure and method of preparation, optimization method

Abstract

The present disclosure provides a semiconductor structure and a preparation method and an optimization method thereof, and relates to the technical field of semiconductor chips. The semiconductor structure comprises: a first transistor structure. The first transistor structure comprises a first semiconductor body, a first gate and a first gate dielectric layer. The first semiconductor body extends along a first direction, the first gate is arranged on one side of the first semiconductor body along a second direction, and the first gate dielectric layer is arranged between the first gate and the first semiconductor body. The first gate dielectric layer comprises a first sub-gate dielectric layer and a second sub-gate dielectric layer, the first sub-gate dielectric layer and the second sub-gate dielectric layer are arranged in a stack along the first direction, and the first sub-gate dielectric layer is arranged close to one end of the first gate in the first direction. The material of the first sub-gate dielectric layer comprises a non-volatile material, and the materials of the first sub-gate dielectric layer and the second sub-gate dielectric layer are different. The above semiconductor structure is applied in a dynamic random access memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its preparation and optimization methods. Background Technology

[0002] With advancements in process technology, circuit design, and manufacturing processes, dynamic random access memory (DRAM) has been scaled down to smaller sizes. However, as the feature size of memory cells within the memory approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, causing memory cell density to approach its upper limit.

[0003] Therefore, how to further miniaturize DRAM has become a technical problem that is currently difficult for engineers to solve. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor structure and its preparation and optimization methods.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes a first transistor structure. The first transistor structure includes a first semiconductor body, a first gate, and a first gate dielectric layer. The first semiconductor body extends along a first direction, the first gate is disposed on one side of the first semiconductor body along a second direction, and the first gate dielectric layer is disposed between the first gate and the first semiconductor body. The first direction and the second direction intersect. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, which are stacked along the first direction, and the first sub-gate dielectric layer is disposed near one end of the first gate in the first direction. The material of the first sub-gate dielectric layer includes a non-volatile material, and the material of the first sub-gate dielectric layer is different from the material of the second sub-gate dielectric layer.

[0007] In some embodiments, the first gate dielectric layer further includes a third sub-gate dielectric layer, which is disposed on the side of the second sub-gate dielectric layer opposite to the first sub-gate dielectric layer, and is disposed near the other end of the first gate in the first direction. The material of the third sub-gate dielectric layer includes a non-volatile material.

[0008] In some embodiments, the first gate includes a first end and a second end in a first direction, a portion of the first sub-gate dielectric layer is disposed between the first end and the first semiconductor body, and a portion of the third sub-gate dielectric layer is disposed between the second end and the first semiconductor body.

[0009] In some embodiments, the ratio of the dimension of the first sub-gate dielectric layer in the first direction to the dimension of the first gate in the first direction is greater than or equal to 0.02 and less than or equal to 0.2.

[0010] In some embodiments, the non-volatile material includes a ferroelectric material.

[0011] In some embodiments, the semiconductor structure further includes a second gate dielectric layer disposed between the first semiconductor body and the first gate dielectric layer, wherein the material of the second gate dielectric layer is different from the material of the first sub-gate dielectric layer.

[0012] In some embodiments, the materials of both the second sub-gate dielectric layer and the second gate dielectric layer include oxide materials.

[0013] In some embodiments, the semiconductor structure further includes a second transistor structure and an isolation structure, wherein the second transistor structure and the first transistor structure are arranged at intervals along a second direction. The second transistor structure includes a second semiconductor body and a second gate, the second semiconductor body extending along a first direction, and the second gate disposed on one side of the second semiconductor body along the second direction. Both the second gate and the first gate are located between the first semiconductor body and the second semiconductor body. The isolation structure is located on the side of the second semiconductor body opposite to the second gate.

[0014] In some embodiments, the semiconductor structure further includes bit lines that extend along a second direction and are connected to one end of the first semiconductor body and one end of the second semiconductor body.

[0015] In some embodiments, the semiconductor structure further includes a capacitor structure layer, which is stacked and disposed on one side of the first semiconductor body away from the bit line. The capacitor structure layer includes a plurality of capacitor units, one capacitor unit being connected to the other end of a first semiconductor body or the other end of a second semiconductor body.

[0016] On the other hand, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising: forming a first semiconductor body extending along a first direction; forming a first gate dielectric layer along a second direction on one side of the first semiconductor body, the first gate dielectric layer including a first sub-gate dielectric layer and a second sub-gate dielectric layer; wherein the first sub-gate dielectric layer and the second sub-gate dielectric layer are stacked along the second direction, the material of the first gate dielectric layer includes a non-volatile material, the material of the first sub-gate dielectric layer is different from the material of the second sub-gate dielectric layer, and the first direction and the second direction intersect; forming a first gate on the side of the first gate dielectric layer opposite to the first semiconductor body, thereby forming a first transistor structure including the first semiconductor body, the first gate, and the first gate dielectric layer; wherein one end of the first gate in the first direction is close to the first sub-gate dielectric layer.

[0017] In some embodiments, forming a first gate dielectric layer along a second direction on one side of a first semiconductor body includes: stacking a first insulating layer and a first ferroelectric layer along a first direction on one side of the first semiconductor body; removing a portion of the first insulating layer and a portion of the first ferroelectric layer to form a first trench and a first gate dielectric layer. The first trench extends along the first direction, penetrates the first ferroelectric layer, and extends into the first insulating layer. The size of the first trench in the second direction is smaller than the size of the first ferroelectric layer in the second direction. The first ferroelectric layer exposed on the sidewalls of the first trench is a first sub-gate dielectric layer, and the first insulating layer exposed on the sidewalls of the first trench is a second sub-gate dielectric layer.

[0018] In some embodiments, forming a first gate dielectric layer along a second direction on one side of a first semiconductor body includes: stacking a second insulating layer, a second ferroelectric layer, a third insulating layer, and a third ferroelectric layer along a first direction on one side of the first semiconductor body, with the second ferroelectric layer and the third insulating layer formed between the second insulating layer and the third ferroelectric layer, and the second ferroelectric layer being closer to the second insulating layer than the third insulating layer. A portion of the second ferroelectric layer, a portion of the third insulating layer, and a portion of the third ferroelectric layer are removed to form a second trench and a first gate dielectric layer. The second trench extends along the first direction, penetrating the second ferroelectric layer, the third insulating layer, and the third ferroelectric layer, and the size of the second trench in the second direction is smaller than the size of the second ferroelectric layer in the second direction. Wherein, the second ferroelectric layer exposed on the sidewall of the second trench is the third sub-gate dielectric layer, the third insulating layer exposed on the sidewall of the second trench is the second sub-gate dielectric layer, and the third ferroelectric layer exposed on the sidewall of the second trench is the first sub-gate dielectric layer.

[0019] In some embodiments, before forming a first gate dielectric layer on one side of the first semiconductor body along the second direction, the method for fabricating the semiconductor structure further includes forming a second gate dielectric layer on one side of the first semiconductor body along the second direction.

[0020] In another aspect, embodiments of this disclosure provide a method for optimizing a semiconductor structure. The method includes: providing a semiconductor structure, comprising a first transistor structure. The first transistor structure includes a first semiconductor body, a first gate, and a first gate dielectric layer. The first semiconductor body extends along a first direction, the first gate is disposed on one side of the first semiconductor body along a second direction, and the first gate dielectric layer is disposed between the first gate and the first semiconductor body. The first direction and the second direction intersect. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, which are stacked along the first direction, with the first sub-gate dielectric layer disposed near one end of the first gate in the first direction. The material of the first sub-gate dielectric layer includes a non-volatile material, and the material of the first sub-gate dielectric layer is different from that of the second sub-gate dielectric layer. An optimized voltage is applied to the first gate of the first transistor structure, forming an optimized electric field within the first sub-gate dielectric layer of the first transistor structure. The optimized voltage applied to the first gate is stopped, and the optimized electric field is retained within the first sub-gate dielectric layer. The optimized electric field is used to optimize the turn-off electric field at the location of the first sub-gate dielectric layer when the first transistor structure is in a turn-off state. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a structural block diagram of an electronic device provided in some embodiments of the present disclosure;

[0023] Figure 2 A structural block diagram of a memory provided in some embodiments of this disclosure;

[0024] Figure 3 This is a schematic diagram of a first transistor structure provided in some embodiments of the present disclosure;

[0025] Figure 4 This is a schematic diagram of another first transistor structure provided in some embodiments of the present disclosure;

[0026] Figure 5 This is a schematic diagram of another first transistor structure provided in some embodiments of the present disclosure;

[0027] Figure 6This is a schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0028] Figure 7 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0029] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;

[0030] Figure 9 A flowchart illustrating a method for fabricating a first semiconductor body according to some embodiments of this disclosure;

[0031] Figure 10 To and Figure 9 A schematic diagram of a semiconductor structure corresponding to the preparation method described in the figure;

[0032] Figure 11 To and Figure 9 A schematic diagram of another semiconductor structure corresponding to the preparation method described in the figure;

[0033] Figure 12 To and Figure 9 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0034] Figure 13 A flowchart illustrating a method for fabricating a first gate dielectric layer according to some embodiments of this disclosure;

[0035] Figure 14 To and Figure 13 A schematic diagram of a semiconductor structure corresponding to the preparation method described in the figure;

[0036] Figure 15 To and Figure 13 A schematic diagram of another semiconductor structure corresponding to the preparation method described in the figure;

[0037] Figure 16 This is a flowchart illustrating another method for fabricating a first gate dielectric layer according to some embodiments of the present disclosure;

[0038] Figure 17 To and Figure 16 A schematic diagram of a semiconductor structure corresponding to the preparation method described in the figure;

[0039] Figure 18 To and Figure 16 A schematic diagram of another semiconductor structure corresponding to the preparation method described in the figure;

[0040] Figure 19 To and Figure 16 A schematic diagram of another semiconductor structure corresponding to the preparation method described above;

[0041] Figure 20 A schematic diagram of a semiconductor structure corresponding to a semiconductor structure fabrication method;

[0042] Figure 21 This is a schematic diagram of another semiconductor structure corresponding to the semiconductor structure fabrication method.

[0043] Figure 22 This is a schematic diagram of another semiconductor structure corresponding to the fabrication method of semiconductor structure 100;

[0044] Figure 23 A flowchart illustrating a method for optimizing a semiconductor structure provided in some embodiments of this disclosure;

[0045] Figure 24 To and Figure 23 An electric field diagram of a first transistor structure corresponding to the optimization method described in the diagram;

[0046] Figure 25 To and Figure 23 A schematic diagram of the electric field of another first transistor structure corresponding to the optimization method in the diagram;

[0047] Figure 26 To and Figure 23 The electric field diagram of another first transistor structure corresponding to the optimization method in the diagram. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0051] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0052] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0053] Figure 1 This is a structural block diagram of an electronic device 9000 provided for some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0054] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0055] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to or receive data from memory.

[0056] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., the host).

[0057] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram illustrates three memories 911 as an example. Controller 912 manages the data stored in each memory 911 and communicates with host 920. Controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. Controller 912 can also be configured to manage various functions related to data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Controller 912 may also perform any other suitable functions. Controller 912 can communicate with external devices (e.g., host 920) according to specific communication protocols. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0058] Figure 2 This is a structural block diagram of a memory 911 provided for some embodiments of this disclosure. For example... Figure 2 As shown, memory 911 includes memory cell array 913 and peripheral circuitry 914 for controlling memory cell array 913. Peripheral circuitry 914 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0059] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0060] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0061] In some embodiments, the memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. For example, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, a DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to a DRAM cell array, and may include, for example, any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, a ferroelectric random access memory (FRAM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc.

[0062] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor for storing data bits as positive or negative charges, and one or more transistor structures for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a 1T1C cell consisting of a transistor structure and a capacitor. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0063] Figure 3 This is a schematic diagram of a first transistor structure 110 provided in some embodiments of the present disclosure.

[0064] in, Figure 3 For illustrative purposes only, and may not actually reflect the actual device structure (e.g., interconnects).

[0065] like Figure 3 As shown, in some embodiments, the semiconductor structure includes a first transistor structure 110. The first transistor junction 110 includes a first semiconductor body 111, wherein the first semiconductor body 111 may extend along a first direction Z. Exemplarily, the first direction Z may be as described above. Figure 2 The first semiconductor structure 901 and the second semiconductor structure 902 are shown in the direction in which they are stacked.

[0066] The first transistor junction 110 may further include a first gate 112 and a first gate dielectric layer 113. The first gate 112 is disposed on one side of the first semiconductor body 111 along the second direction X, and the first gate dielectric layer 113 is disposed between the first gate 112 and the first semiconductor body 111. The first direction Z intersects the second direction X.

[0067] In this embodiment, by providing a first gate 112 on one side of the first semiconductor body 111, the first gate 112 can be used to control the on / off state of the first transistor structure 110, thereby controlling the DRAM cell where the first transistor structure 110 is located to perform data reading or writing operations.

[0068] In some examples, the first gate 112 may be made of a conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In this embodiment, the material of the first gate 112 may include tungsten, and this disclosure does not impose any limitation on the material.

[0069] In one feasible implementation, the first gate dielectric layer 113 may include a first sub-gate dielectric layer 1131 and a second sub-gate dielectric layer 1132. The first sub-gate dielectric layer 1131 and the second sub-gate dielectric layer 1132 are stacked along a first direction Z, and the first sub-gate dielectric layer 1131 is disposed near one end of the first gate 112 in the first direction Z. The material of the first sub-gate dielectric layer 1131 may include a non-volatile material, and the material of the first sub-gate dielectric layer 1131 may be different from the material of the second sub-gate dielectric layer 1132.

[0070] The first semiconductor body 111 of the first transistor structure 110 can be fabricated using semiconductor materials. For example, semiconductor materials may include indium gallium zinc oxide (IGZO), silicon, doped silicon, germanium, or any other suitable material; this disclosure does not limit the scope of the embodiments. Based on this, the first transistor structure 110, formed by the first semiconductor body 111, the first gate 112, and the first gate dielectric layer 113, may include a source terminal and a drain terminal in the first direction Z.

[0071] In this embodiment, by providing a first sub-gate dielectric layer 1131 of non-volatile material at one end near the first gate 112, the non-volatility of the non-volatile material can be used to reduce the leakage current at the source or drain end of the first transistor structure 110 in the first direction Z, thereby improving the retention time of the DRAM cell where the first transistor structure 110 is located for data storage.

[0072] In some embodiments, the non-volatile material may include a ferroelectric material. For example, the ferroelectric material may include any suitable ferroelectric material such as hafnium oxide-based ferroelectric material, and this disclosure does not impose specific limitations on the embodiments thereof.

[0073] In one feasible implementation, since the leakage current of the first transistor structure 110 is related to the electric field of the source or drain terminal in the operating state of the first transistor structure 110, by providing a first sub-gate dielectric layer 1131 of ferroelectric material in the first transistor structure 110, an optimized voltage can be applied to the first gate dielectric layer 113 and the first semiconductor body 111 by the first gate 112 during the testing phase before the first transistor structure 110 is put into use. Then, under the action of the electric field, the ferroelectric material of the first sub-gate dielectric layer 1131 is ferroelectrically polarized. In this way, after the optimized voltage is removed, the optimized voltage can still be retained on the first sub-gate dielectric layer 1131.

[0074] With this configuration, after the first transistor structure 110 is put into use, the optimized voltage retained on the first sub-gate dielectric layer 1131 can be used to cancel the turn-off voltage applied to the first gate 112, thereby weakening the turn-off electric field at the source or drain of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current at the source or drain of the first transistor structure 110 and increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0075] Furthermore, in scenarios where semiconductor structures are in the pre-production testing phase, multiple semiconductor structures 100 can be mounted on the same wafer. This configuration allows for unified optimization of multiple semiconductor structures on the same wafer, thereby reducing leakage current and ultimately optimizing the overall semiconductor structure on the wafer. This compensates for process defects in the semiconductor structure and improves the product yield of the multiple semiconductor structures on the entire wafer.

[0076] Furthermore, ferroelectric polarization can generate the ferroelectric effect, which is an inherent polarization polarization characteristic of ferroelectric materials and is independent of electromagnetic interactions. Therefore, by using ferroelectric materials to fabricate the first sub-gate dielectric layer 1131 of the first transistor structure 110, the storage capacity of the DRAM cells can be increased while reducing leakage charge in the DRAM cells. Moreover, with the number of DRAM cells in the semiconductor structure remaining unchanged, this arrangement can increase the overall storage capacity of the semiconductor structure.

[0077] Furthermore, since DRAM cells fabricated from ferroelectric materials have lower leakage current, the problem of multi-level signal misreading caused by high leakage current can be avoided in practical applications, thereby improving the accuracy of DRAM cell control. Moreover, this configuration can also utilize the high-speed polarization switching and rapid charge capture or release characteristics of ferroelectric materials to improve the read and write speeds of DRAM cells.

[0078] Figure 4 This is a schematic diagram of another first transistor structure 110 provided in some embodiments of the present disclosure.

[0079] like Figure 4 As shown, in some embodiments, the first gate dielectric layer 113 further includes a third sub-gate dielectric layer 1133, which is disposed on the side of the second sub-gate dielectric layer 1132 away from the first sub-gate dielectric layer 1131, and the third sub-gate dielectric layer 1133 is disposed near the other end of the first gate 112 in the first direction Y.

[0080] For example, the material of the third sub-gate dielectric layer 1133 may also include non-volatile materials, such as ferroelectric materials, etc., and this disclosure does not limit this embodiment.

[0081] In this embodiment, by providing a third sub-gate dielectric layer 1133 near the other end of the first gate 112 in the first direction Y, the ferroelectric material of the third sub-gate dielectric layer 113 can be ferroelectrically polarized during the process of applying an optimized voltage to the first gate dielectric layer 113 to ferroelectrically polarize the ferroelectric material of the first sub-gate dielectric layer 1131. Thus, after the optimized voltage is removed, the optimized voltage can be retained on both the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133.

[0082] With this configuration, the third sub-gate dielectric layer 1133 can be combined with the first sub-gate dielectric layer 1131 in the aforementioned embodiment to jointly weaken the turn-off electric field of the source and drain terminals of the first transistor structure 110 in the off state, thereby reducing the leakage current of the source and drain terminals of the first transistor structure 110 and thus improving the retention time of the stored data in the DRAM cell where the first transistor structure 110 is located.

[0083] Please continue reading. Figure 4 In some embodiments, the first gate 112 includes a first end 1121 and a second end 1122 in the first direction Z, a portion of the first sub-gate dielectric layer 1131 is disposed between the first end 1121 and the first semiconductor body 111, and a portion of the third sub-gate dielectric layer 1133 is disposed between the second end 1122 and the first semiconductor body 111.

[0084] In this embodiment, the semiconductor structure is described using the scenario where the first end 1121 of the first gate 112 is close to the source end of the first semiconductor body 111 and the second end 1122 of the first gate 112 is close to the drain end of the first semiconductor body 111 as an example.

[0085] For example, by disposing a portion of the first sub-gate dielectric layer 1131 between the first end 1121 of the first gate 112 and the first semiconductor body 111, it can be ensured that the first sub-gate dielectric layer 1131 is disposed close to the source end of the first semiconductor body 111.

[0086] In one feasible implementation, during the testing phase before the semiconductor structure is put into production, an optimized voltage can be applied to the first sub-gate dielectric layer 1131 and the first semiconductor body 111 using the first gate 112. Then, under the action of the electric field, the ferroelectric material of the first sub-gate dielectric layer 1131 is ferroelectrically polarized. Thus, after the optimized voltage is removed, the optimized voltage can still be retained on the first sub-gate dielectric layer 1131.

[0087] With this configuration, after the first transistor structure 110 is put into production and used, the optimized voltage retained on the first sub-gate dielectric layer 1131 can be used to cancel the turn-off voltage applied to the first gate 112, thereby weakening the turn-off electric field at the source end of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current at the source end of the first transistor structure 110 and increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0088] Similarly, by disposing a portion of the third sub-gate dielectric layer 1133 between the second end 1122 of the first gate 112 and the first semiconductor body 111, the third sub-gate dielectric layer 1133 can be positioned close to the drain end of the first semiconductor body 111. In this way, during the testing phase before semiconductor structure production, an optimized voltage can be applied to the third sub-gate dielectric layer 1133 and the first semiconductor body 111 using the first gate 112, thereby ferroelectrically polarizing the ferroelectric material of the third sub-gate dielectric layer 1133 under the influence of an electric field. Furthermore, the optimized voltage can still be retained on the third sub-gate dielectric layer 1133 after the optimized voltage is removed.

[0089] With this configuration, after the first transistor structure 110 is put into production and use, the optimized voltage retained on the third sub-gate dielectric layer 1133 can be used to cancel the turn-off voltage applied to the first gate 112, thereby weakening the turn-off electric field at the source end of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current at the drain end of the first transistor structure 110 and increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0090] Please continue reading. Figure 4 In some embodiments, the ratio N of the size H1 of the first sub-gate dielectric layer 1131 in the first direction Z to the size H2 of the first gate 112 in the first direction Z is greater than or equal to 0.02 and less than or equal to 0.2.

[0091] In some examples, the ratio N of the dimension H1 of the first sub-gate dielectric layer 1131 in the first direction Z to the dimension H2 of the first gate 112 in the first direction Z is ≥0.02. This can prevent the first sub-gate dielectric layer 1131 from being too short in the first direction Z; for example, N < 0.02. For instance, if the first sub-gate dielectric layer 1131 is too short in the first direction Z, for example, N < 0.01, then the area of ​​the first sub-gate dielectric layer 1131 facing the first gate 112 is too small, resulting in the area of ​​the first sub-gate dielectric layer 1131 that can be controlled by the first gate 112 being too small.

[0092] With this configuration, during the process of applying an optimized voltage to the first sub-gate dielectric layer 1131 using the first gate 112, the optimized voltage of the remaining layer after the first sub-gate dielectric layer 1131 is ferroelectrically polarized is too small. Consequently, the optimized voltage remaining on the first sub-gate dielectric layer 1131 cannot weaken the turn-off electric field of the source or drain of the first transistor structure 110 in the off state, and thus cannot reduce the leakage current of the source or drain of the first transistor structure 110.

[0093] Therefore, N ≥ 0.02. By increasing the value of N, the weakening effect of the optimized voltage remaining on the first sub-gate dielectric layer 1131 on the turn-off electric field of the first transistor structure 110 in the turn-off state can be improved, while ensuring that the optimized voltage remaining on the first sub-gate dielectric layer 1131 can weaken the turn-off electric field of the source or drain of the first transistor structure 110 in the turn-off state. This reduces the leakage current at the source or drain of the first transistor structure 110, thereby increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0094] In other examples, N ≤ 0.2, thus preventing the first sub-gate dielectric layer 1131 from being too long in the first direction Z, for example, N > 0.2. For instance, if the first sub-gate dielectric layer 1131 is too long in the first direction Z, for example, N > 0.3, it would occupy too much of the first gate dielectric layer 113 in the first direction Z, thereby reducing the size of the second sub-gate dielectric layer 1132 in the first direction Z, and consequently increasing the cost of the transistor structure and even the entire semiconductor structure 100. Therefore, setting N ≤ 0.2 allows for improved storage performance of the entire semiconductor structure 100 while reducing its fabrication cost.

[0095] For example, the ratio N of the size H1 of the first sub-gate dielectric layer 1131 in the first direction Z to the size H2 of the first gate 112 in the first direction Z may include any suitable ratio such as 0.02, 0.03, 0.05, 0.1, 0.15, 0.16, 0.18, 0.2, etc., and this embodiment of the present disclosure does not limit it.

[0096] Figure 5 This is a schematic diagram of another first transistor structure 110 provided in some embodiments of the present disclosure.

[0097] like Figure 5As shown, in some embodiments, the material of the first semiconductor body 111 may include an oxide semiconductor material, such as silicon. In this scenario, the semiconductor structure may further include a second gate dielectric layer 115, and the second gate dielectric layer 115 is disposed between the first semiconductor body 111 and the first gate dielectric layer 113. The material of the second gate dielectric layer 115 is different from the material of the first sub-gate dielectric layer 1131. For example, the material of the second gate dielectric layer may include an oxide material.

[0098] In this embodiment, since the oxide semiconductor material of the first semiconductor body 111 may include silicon, based on the characteristic that the semiconductor material is easy to oxidize, the side of the first semiconductor body 111 near the first gate dielectric layer 113 can be oxidized to form the second gate dielectric layer 115.

[0099] Furthermore, in this embodiment, the material of the second sub-gate dielectric layer 1132 may also include an oxide material. This configuration can reduce the fabrication cost of the semiconductor structure 100.

[0100] The oxide material of the second gate dielectric layer 115 and the oxide material of the second sub-gate dielectric layer 1132 can both include any suitable oxide material such as silicon oxide, and this embodiment of the present disclosure does not limit this.

[0101] Figure 6 This is a schematic diagram of a semiconductor structure 100 provided in some embodiments of the present disclosure.

[0102] like Figure 6 As shown, in some embodiments, the number of transistor structures can be one or more, and in the case of multiple transistor structures, the multiple transistor structures can be arranged in multiple rows and columns. In this scenario, the semiconductor structure 100 may further include a second transistor structure 120.

[0103] For example, in this embodiment, a combination of adjacent first transistor structures 110 and second transistor structures 120 in a row of transistor structures is used as the smallest constituent unit. In this scenario, a row of transistor structures may include multiple smallest constituent units arranged along the second direction X. The second transistor structure 120 and the first transistor structure 110 within a single smallest constituent unit may be arranged at intervals along the second direction X.

[0104] The second transistor structure 120 may include a second semiconductor body 121 and a second gate 122. The second semiconductor body 121 extends along a first direction Z, and the second gate 122 is disposed on one side of the second semiconductor body 121 along a second direction X. The second gate 122 and the first gate 112 are both located between the first semiconductor body 111 and the second semiconductor body 121.

[0105] With this configuration, in the fabrication method of semiconductor structure 100, the first gate 112 corresponding to the first transistor structure 110 and the second gate 122 corresponding to the second transistor structure 120 can be fabricated in the same fabrication process, thereby simplifying the fabrication process of the first gate 112 and the second gate 122 and reducing the fabrication process difficulty of the first gate 112 and the second gate 122.

[0106] Furthermore, when there are multiple transistor structures, the first gate 112 of a column of first transistor structures 110 and the second gate 122 of a column of second transistor structures 120 can be obtained in the same fabrication process, and the first gate 112 of the column of first transistor structures 110 can be a single integrated structure, and the second gate 122 of the column of second transistor structures 120 can also be a single integrated structure. For example, when the column of first gates 112 is a single integrated structure, the column of first gates 112 can constitute a word line; similarly, when the column of second gates 122 is a single integrated structure, the column of second gates 122 can also constitute a word line.

[0107] With this configuration, the selection of a column of first transistor structure 110 or a column of second transistor structure 120 can be achieved by controlling a word line composed of a column of first gate 112 or a column of second gate 122, and the subsequent bit line 130 can be used to control the on and off of a single transistor structure, thereby enabling a single DRAM cell to read or write data.

[0108] Furthermore, in this scenario, the semiconductor structure 100 may also include an isolation structure 150. The isolation structure 150 is located on the side of the second semiconductor body 121 opposite to the second gate 122.

[0109] With this configuration, in scenarios where there are multiple transistor structures, the isolation structure 150 can be used to isolate the semiconductor bodies of two adjacent transistor structures (e.g., the second transistor structure 120 and the first transistor structure 110), thereby improving the stability and reliability of the first transistor structure 110 and the second transistor structure 120.

[0110] In one feasible implementation, the isolation structure 150 may include a conductive structure 151 and an insulating structure 152. This arrangement allows the conductive structure 151 to enhance the isolation effect of the isolation structure 150 on the semiconductor bodies of two adjacent transistor structures.

[0111] The insulating structure 152 can surround the conductive structure 151 to isolate the conductive structure 151 from the adjacent first semiconductor body 111 and second semiconductor body 121, thereby improving the stability and reliability of the transistor structure.

[0112] For example, the conductive structure 151 may be made of a conductive material, such as W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The material of the insulating structure 152 may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials, and may be any suitable insulating material such as silicon oxide; this is not limited in the embodiments disclosed herein. In this embodiment, the conductive material of the first conductive structure 151 may include W, and the insulating material of the insulating structure 152 may include silicon oxide.

[0113] Please continue reading. Figure 6 In some embodiments, the semiconductor structure 100 further includes a bit line 130 extending along a second direction X, and the bit line 130 is connected to one end of the first semiconductor body 111 and one end of the second semiconductor body 121.

[0114] In this embodiment, by setting bit line 130, it can cooperate with word line composed of a column of first gates 112 or a column of second gates 122. When word line composed of a column of first gates 112 or a column of second gates 122 selects a column of first transistor structure 110 or a column of second transistor structure 120, bit line 130 can be used to control the on and off of a single first transistor structure 110 or second transistor structure 120, thereby enabling a single DRAM cell to read or write data.

[0115] Please continue reading. Figure 6 In some embodiments, the semiconductor structure further includes an insulating fill structure 160. The insulating fill structure 160 is disposed between the first semiconductor body 111 and the second semiconductor body 121, and the first gate 112 corresponding to the first semiconductor body 111 and the second gate 122 corresponding to the second semiconductor body 121 are both embedded in the insulating fill structure 160.

[0116] In this embodiment, by providing an insulating filling structure 160 between the first semiconductor body 111 and the second semiconductor body 121, isolation between the first semiconductor body 111 and the second semiconductor body 121 can be achieved. Furthermore, by embedding the first gate 112 corresponding to the first semiconductor body 111 and the second gate 122 corresponding to the second semiconductor body 121 within the insulating filling structure 160, isolation between adjacent first gates 112 and second gates 122, isolation between the first gate 112 and its corresponding first semiconductor body 111, and isolation between the second gate 122 and its corresponding second semiconductor body 121 can be achieved.

[0117] This configuration avoids interfering with the storage states of other adjacent transistor structures when using word lines and bit lines 130 to control the transistor structure for data reading, writing, or erasing operations. This improves the accuracy of word lines and bit lines 130 in controlling the transistor structure and enhances the stability and reliability of the transistor structure and semiconductor structure 100.

[0118] The insulating filling structure 160 can be made of insulating material. For example, the insulating material can include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride). It can be any suitable insulating material such as silicon oxide. This disclosure does not limit the embodiments.

[0119] Figure 7 This is a schematic diagram of another semiconductor structure 100 provided in some embodiments of this disclosure.

[0120] like Figure 7 As shown, in some embodiments, the semiconductor structure 100 further includes an interconnect layer 170, which is disposed along a first direction Z on one side of the first transistor structure 110 away from the bit line 130.

[0121] For example, an interconnect structure 171 may be provided in the interconnect layer 170, wherein the interconnect structure 171 may extend along the first direction Z, and one end of the interconnect structure 171 may be connected to one end of the first semiconductor body 111, and the other end of the interconnect structure 171 may be connected to other device structures (e.g., capacitor cells).

[0122] With this configuration, the first transistor structure 110 can be brought out using the connection structure 171, thereby enabling signal transmission between the first transistor structure 110 and other device structures. The connection can include electrical or physical connections.

[0123] In some examples, the connection structure 171 may include a through silicon contact (TSC), a through silicon contact, etc. Furthermore, when there are multiple transistor structures, there may also be multiple connection structures 171, and the shapes of the multiple connection structures 171 may be the same or different; this disclosure does not limit the specific form of these connection structures.

[0124] In addition, as a feasible implementation, when there are multiple interconnect structures 171, the interconnect layer 170 may also include an interlayer dielectric layer 172, with multiple interconnect structures 171 spaced apart within the interlayer dielectric layer 172, thereby achieving isolation between the multiple interconnect structures 171 and improving the reliability and stability of the semiconductor structure 100.

[0125] The material of the connecting structure 171 may include a conductive material. For example, conductive materials include, but are not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. This disclosure does not limit the scope of the embodiments.

[0126] Please continue reading. Figure 7 In some embodiments, the semiconductor structure 100 further includes a capacitor structure layer 180, which is stacked on one side of the first semiconductor body 111 away from the bit line 130. The capacitor structure layer 180 includes a plurality of capacitor units 181, and one capacitor unit 181 is connected to the other end of a first semiconductor body 111 or the other end of a second semiconductor body 121.

[0127] In this embodiment, the first semiconductor body 111 is connected to the bit line 130 and the capacitor unit 181 at both ends in the first direction Z, thereby forming a 1T1C DRAM unit in combination with the aforementioned first gate 112. With the cooperation of the bit line 130 and the first gate 112, the first semiconductor body 111 is used to control the charging and discharging of the capacitor unit 181, thereby realizing the DRAM unit's data reading, writing or erasing operations.

[0128] Similarly, the two ends of the second semiconductor body 121 in the first direction Z are connected to the bit line 130 and the capacitor unit 181 respectively, thereby forming a 1T1C DRAM cell in combination with the aforementioned second gate 122. With the cooperation of the bit line 130 and the second gate 122, the second semiconductor body 121 is used to control the charging and discharging of the capacitor unit 181, thereby realizing the DRAM cell's data reading, writing or erasing operations.

[0129] For example, when there are multiple connection structures 171, there can also be multiple capacitor units 181. Each capacitor unit 181 is connected to a first semiconductor body 111 or a second semiconductor body 121 through a connection structure 171, thereby forming a DRAM cell array.

[0130] Based on the semiconductor structure 100 provided in the above embodiments, this disclosure also provides a method for preparing the semiconductor structure 100, wherein the semiconductor structure 100 can be prepared by the method for preparing the semiconductor structure 100.

[0131] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure 100 according to some embodiments of the present disclosure.

[0132] like Figure 8 As shown, in some embodiments, the method for fabricating the semiconductor structure 100 includes the following steps S1 to S3.

[0133] S1. A first semiconductor body is formed, and the first semiconductor body extends along a first direction.

[0134] Figure 9 This is a flowchart illustrating a method for fabricating a first semiconductor body 111 according to some embodiments of the present disclosure. Figure 10 To and Figure 9 The preparation method in the diagram is a schematic diagram of a semiconductor structure 100.

[0135] like Figure 9 As shown, step S1 above may also include steps S11 to S14.

[0136] S11, Forming a semiconductor layer.

[0137] like Figure 10 As shown, for example, the semiconductor layer 200 can be a single-crystal silicon (Si) semiconductor layer, a single-crystal germanium (Ge) semiconductor layer, a silicon-on-insulator (SOI) semiconductor layer, or a germanium-on-insulator (GOI) semiconductor layer, etc. Alternatively, the material of the semiconductor layer 200 can also be a compound semiconductor. For example, the semiconductor layer 200 can be a gallium arsenide (GaAs) semiconductor layer, an indium phosphide (InP) semiconductor layer, or a silicon carbide (SiC) semiconductor layer, etc. Alternatively, the semiconductor layer 200 can also be made of other semiconductor materials commonly used in the art, and this disclosure does not limit the embodiments thereto.

[0138] In this embodiment, taking the semiconductor layer 200 as an example where the material includes single-crystal silicon, the first semiconductor body 111 (see [reference]) is used. Figure 7 The preparation of ) will be introduced.

[0139] S12. A plurality of third trenches are formed on one side of the semiconductor layer. The third trenches extend along the second direction and are arranged at intervals along the third direction to separate a plurality of semiconductor wafers on the semiconductor layer. The third direction passes through the plane containing the first direction and the second direction.

[0140] In this step S12, a suitable method such as static spin coating or dynamic spray coating can be used to form a photoresist layer on one side surface of the semiconductor layer 200, and the photoresist layer can be patterned to obtain a first mask layer with multiple first openings.

[0141] Please continue reading. Figure 10The semiconductor layer 200 is etched based on the first mask layer to form a plurality of semiconductor wafers 210. For example, in this embodiment, any suitable process such as self-aligned double patterning (SADP) can be used to etch the semiconductor layer 200 to form a plurality of semiconductor wafers 210, and a third trench is formed between two adjacent semiconductor wafers 210.

[0142] For example, the first direction Z can represent the direction in which the semiconductor wafer 210 is stacked with the remaining semiconductor layer 200.

[0143] Each semiconductor wafer 210 can extend along the second direction X, and multiple semiconductor wafers 210 can be arranged at intervals along the third direction Y. In one feasible implementation, the multiple semiconductor wafers 210 arranged at intervals along the third direction Y can be staggered. Such an arrangement can reduce the difficulty of extracting the device structure based on the semiconductor wafers 210 in subsequent fabrication processes (e.g., bonding processes).

[0144] S13. A plurality of fourth trenches are formed on one side of the semiconductor wafer. The fourth trenches extend along a third direction and are arranged at intervals along a second direction to form a plurality of semiconductor blocks.

[0145] Please continue reading. Figure 10 A photoresist layer is formed on one side surface of multiple semiconductor wafers 210, and the photoresist layer is patterned to obtain a second mask layer with multiple second openings.

[0146] For example, in this step S13, either static spin coating or dynamic spray coating can be used to apply the photoresist.

[0147] Figure 11 To and Figure 9 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0148] like Figure 10 and Figure 11 As shown, the semiconductor wafer 210 is etched based on the second mask layer to form a plurality of fourth trenches 230. Exemplarily, in this embodiment, any suitable process such as self-aligned reverse patterning (SARP) can be used to etch the semiconductor wafer 210 to form a plurality of fourth trenches 230, and the side of each semiconductor wafer 210 facing away from the semiconductor layer 200 can be divided into a plurality of semiconductor blocks 114 by the plurality of fourth trenches 230.

[0149] Each fourth slot 230 extends along the third direction Y, and multiple fourth slots 230 are arranged at intervals along the second direction X.

[0150] In one feasible implementation, the depth of each fourth groove 230 in the first direction Z can be less than or equal to the height of the semiconductor wafer 210 in the first direction Z, and when the depth of the fourth groove 230 in the first direction Z is less than the height of the semiconductor wafer 210 in the first direction Z, multiple semiconductor blocks 114 divided from the same semiconductor wafer 210 can be connected into a single structure.

[0151] In another feasible implementation, when the depth of the fourth groove 230 in the first direction Z is equal to the height of the semiconductor wafer 210 in the first direction Z, the multiple semiconductor blocks 114 divided from the same semiconductor wafer 210 can be divided into multiple independent structures, and this disclosure does not limit this.

[0152] S14. A plurality of fifth trenches are formed on one side of the semiconductor block. The fifth trenches extend along a third direction and are arranged at intervals along a second direction to divide the semiconductor block into a first semiconductor body and a second semiconductor body.

[0153] Figure 12 To and Figure 9 The schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0154] like Figure 11 and Figure 12 As shown, as a feasible implementation, a photoresist layer can be formed on one side surface of the semiconductor block 114 by any suitable method such as static spin coating or dynamic spray coating, and the photoresist layer can be patterned to obtain a third mask layer with multiple third openings.

[0155] The semiconductor block 114 is etched based on the third mask layer to divide the semiconductor block 114 into a first semiconductor body 111 and a second semiconductor body 121. Exemplarily, in this embodiment, any suitable process such as dry etching or wet etching can be used to etch the semiconductor block 114 to form a fifth trench 240, and each semiconductor block 114 can be divided into a first semiconductor body 111 and a second semiconductor body 121 by the fifth trench 240.

[0156] As a feasible implementation, multiple first semiconductor bodies 111 and multiple second semiconductor bodies 121 prepared based on a semiconductor wafer 210 can be used to prepare the channel structure of multiple first transistor structures 110 and multiple second transistor structures 120 in a row of transistor structures.

[0157] S2. A first gate dielectric layer is formed on one side of the first semiconductor body along a second direction. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer. The first sub-gate dielectric layer and the second sub-gate dielectric layer are stacked along the second direction. The material of the first gate dielectric layer includes a non-volatile material. The materials of the first sub-gate dielectric layer and the second sub-gate dielectric layer are different. The first direction and the second direction intersect.

[0158] Figure 13 This is a flowchart illustrating a method for fabricating a first gate dielectric layer 113 according to some embodiments of the present disclosure. Figure 14 To and Figure 13 A schematic diagram of a semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 15 To and Figure 13 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0159] like Figure 13 As shown, step S2 above may also include the following steps S21 to S22.

[0160] S21. On one side of the first semiconductor body, a first insulating layer and a first ferroelectric layer are stacked along a first direction to form a first insulating layer and a first ferroelectric layer.

[0161] like Figure 11 and Figure 14 As shown, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof thin film deposition process can be used to deposit insulating material in the fourth tank 230 to form the first insulating layer 310.

[0162] For example, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride). Any suitable insulating material, such as silicon oxide, may be used, and this disclosure does not limit the specific insulating material. In this embodiment, the material of the first insulating layer 310 may be silicon oxide.

[0163] Ferroelectric material can be deposited on one side of the first insulating layer 310 in the fourth trench 230 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes to form the first ferroelectric layer 320.

[0164] The ferroelectric material may include any suitable ferroelectric material such as hafnium oxide-based ferroelectric material, and the embodiments disclosed herein do not impose specific limitations on it.

[0165] S22. A portion of the first insulating layer and a portion of the first ferroelectric layer are removed to form a first trench and a first gate dielectric layer. The first trench extends along a first direction, penetrating the first ferroelectric layer and extending into the first insulating layer. The dimension of the first trench in a second direction is smaller than the dimension of the first ferroelectric layer in the second direction. The first ferroelectric layer exposed on the sidewall of the first trench is the first sub-gate dielectric layer, and the first insulating layer exposed on the sidewall of the first trench is the second sub-gate dielectric layer.

[0166] like Figure 14 and Figure 15 As shown, a photoresist layer can be formed on the surface of the first ferroelectric layer 320 away from the first insulating layer 310 by a suitable method such as static spin coating or dynamic spray coating, and the photoresist layer can be patterned to obtain a fourth mask layer with multiple fourth openings.

[0167] A portion of the first insulating layer 310 and a portion of the first ferroelectric layer 320 are removed through the fourth opening to form, as shown in the figure. Figure 15 The first trench 330 is shown. The size of the first trench 330 in the second direction X is smaller than the size of the first ferroelectric layer 320 in the second direction X, so that the retained first insulating layer 310 and the first ferroelectric layer 320 can form the first gate dielectric layer 113, and the first ferroelectric layer 320 exposed on the sidewall of the first trench 330 is the first sub-gate dielectric layer 1131, and the first insulating layer 310 exposed on the sidewall of the first trench 330 is the second sub-gate dielectric layer 1132.

[0168] For example, either dry etching or wet etching can be used to remove a portion of the first insulating layer 310 and a portion of the first ferroelectric layer 320, thereby forming a layer as shown in the image. Figure 15 The first gate dielectric layer 113 is shown.

[0169] Since the leakage current of the first transistor structure 110 is related to the electric field of the source or drain terminal when the first transistor structure 110 is in operation, by providing a first sub-gate dielectric layer 1131 of ferroelectric material in the first transistor structure 110, an optimized voltage can be applied to the first gate dielectric layer 113 and the first semiconductor body 111 by the first gate 112 during the testing phase before the first transistor structure 110 is put into use. Then, under the action of the electric field, the ferroelectric material of the first sub-gate dielectric layer 1131 is ferroelectrically polarized. In this way, after the optimized voltage is removed, the optimized voltage can still be retained on the first sub-gate dielectric layer 1131.

[0170] With this configuration, after the first transistor structure 110 is put into use, the optimized voltage retained on the first sub-gate dielectric layer 1131 can be used to cancel the turn-off voltage applied to the first gate 112, thereby weakening the turn-off electric field at the source or drain of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current at the source or drain of the first transistor structure 110 and increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0171] Furthermore, in scenarios where semiconductor structures are in the pre-production testing phase, multiple semiconductor structures 100 can be mounted on the same wafer. This configuration allows for unified optimization of multiple semiconductor structures on the same wafer, thereby reducing leakage current and ultimately optimizing the overall semiconductor structure on the wafer. This compensates for process defects in the semiconductor structure and improves the product yield of the multiple semiconductor structures on the entire wafer.

[0172] Furthermore, since DRAM cells fabricated from ferroelectric materials have lower leakage current, the problem of multi-level signal misreading caused by high leakage current can be avoided in practical applications, thereby improving the accuracy of DRAM cell control. Moreover, this configuration can also utilize the high-speed polarization switching and rapid charge capture or release characteristics of ferroelectric materials to improve the read and write speeds of DRAM cells.

[0173] Figure 16 This is a flowchart illustrating another method for fabricating a first gate dielectric layer 113 according to some embodiments of the present disclosure. Figure 17 To and Figure 16 A schematic diagram of a semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 18 To and Figure 16 A schematic diagram of another semiconductor structure 100 corresponding to the preparation method described in the figure. Figure 19 To and Figure 16 The schematic diagram of another semiconductor structure 100 corresponding to the preparation method in the figure.

[0174] like Figure 16 As shown, in some other embodiments, step S2 may also include steps S201 to S202.

[0175] S201. On one side of the first semiconductor body, a second insulating layer, a second ferroelectric layer, a third insulating layer and a third ferroelectric layer are stacked along a first direction, the second ferroelectric layer and the third insulating layer are formed between the second insulating layer and the third ferroelectric layer, and the second ferroelectric layer is closer to the second insulating layer than the third insulating layer.

[0176] like Figure 17As shown, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof can be used to deposit an insulating material on one side of the first semiconductor body 111 to form a second insulating layer 340.

[0177] For example, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride), and may be any suitable insulating material such as silicon oxide; this disclosure does not limit the embodiments in this regard. In this embodiment, the insulating material of the second insulating layer 340 may include silicon oxide.

[0178] Ferroelectric material can be deposited on one side of the second insulating layer 340 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof to form the second ferroelectric layer 350.

[0179] The ferroelectric material of the second ferroelectric layer 350 may include any suitable ferroelectric material such as hafnium oxide-based ferroelectric material, and this embodiment does not impose specific limitations on it.

[0180] The insulating material can be deposited on the side of the second ferroelectric layer 350 away from the second insulating layer 340 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes to form the third insulating layer 360.

[0181] Similarly, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride), and may be any suitable insulating material such as silicon oxide; this disclosure does not limit the specific insulating material. In this embodiment, the insulating material of the third insulating layer 360 may include silicon oxide.

[0182] Ferroelectric material can be deposited on the side of the third insulating layer 360 away from the second ferroelectric layer 350 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes to form the third ferroelectric layer 370.

[0183] Similarly, the ferroelectric material of the third ferroelectric layer 370 may include any suitable ferroelectric material such as hafnium oxide-based ferroelectric material, and this embodiment does not impose specific limitations on it.

[0184] S202. A portion of the second ferroelectric layer, a portion of the third insulating layer, and a portion of the third ferroelectric layer are removed to form a second trench and a first gate dielectric layer. The second trench extends along a first direction, penetrating the second ferroelectric layer, the third insulating layer, and the third ferroelectric layer. The dimension of the second trench in the second direction is smaller than the dimension of the second ferroelectric layer in the second direction. Specifically, the second ferroelectric layer exposed on the sidewall of the second trench forms the third sub-gate dielectric layer, the third insulating layer exposed on the sidewall of the second trench forms the second sub-gate dielectric layer, and the third ferroelectric layer exposed on the sidewall of the second trench forms the first sub-gate dielectric layer.

[0185] like Figure 17 and Figure 18 As shown, a photoresist layer can be formed on the surface of the third ferroelectric layer 370 away from the third insulating layer 360 by a suitable method such as static spin coating or dynamic spray coating, and the photoresist layer can be patterned to obtain a fifth mask layer with multiple fifth openings.

[0186] Part of the second ferroelectric layer 350, part of the third insulating layer 360, and part of the third ferroelectric layer 370 are removed through the fifth opening to form a structure as follows: Figure 18 The second trench 380 is shown. The dimension of the second trench 380 in the second direction X is smaller than the dimension of the second ferroelectric layer 350 in the second direction, so that the retained second ferroelectric layer 350, third insulating layer 360 and third ferroelectric layer 370 can form the first gate dielectric layer 113, and the second ferroelectric layer 350 exposed on the sidewall of the second trench 380 is the third sub-gate dielectric layer 1133, the third insulating layer 360 exposed on the sidewall of the second trench 380 is the second sub-gate dielectric layer 1132, and the third ferroelectric layer 370 exposed on the sidewall of the second trench 380 is the first sub-gate dielectric layer 1131.

[0187] For example, either dry etching or wet etching can be used to remove a portion of the second ferroelectric layer 350, a portion of the third insulating layer 360, and a portion of the third ferroelectric layer 370, thereby forming a structure as described above. Figure 18 The first gate dielectric layer 113 is shown.

[0188] In this embodiment, by forming a third sub-gate dielectric layer 1133 near the other end of the first gate 112 in the first direction Y, the ferroelectric material of the third sub-gate dielectric layer 1133 can be ferroelectrically polarized during the process of applying an optimized voltage to the first gate dielectric layer 113 to ferroelectrically polarize the ferroelectric material of the first sub-gate dielectric layer 1131. Thus, after the optimized voltage is removed, the optimized voltage can be retained on both the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133.

[0189] Since the leakage current of the first transistor structure 110 is related to the electric fields at the source and drain terminals during the operating state of the first transistor structure 110, by forming the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133 of ferroelectric material, the leakage current can be measured using the first gate 112 (see [reference]) during the testing phase before the first transistor structure 110 is put into use. Figure 7 An optimized voltage is applied to the first gate dielectric layer 113, and then the ferroelectric materials of the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133 are ferroelectrically polarized under the action of an electric field. In this way, after the optimized voltage is removed, the optimized voltage can still be retained on the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133.

[0190] With this configuration, after the first transistor structure 110 is put into use, the optimized voltage retained on the first sub-gate dielectric layer 1131 and the third sub-gate dielectric layer 1133 can be used to control the first gate 112 (see [reference]). Figure 7 The applied turn-off voltage is used to cancel out the turn-off electric field at the source and drain of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current at the source and drain of the first transistor structure 110 and increasing the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0191] Additionally, in step S202, the second gate dielectric layer 123 (see [reference]) can also be fabricated in the same process. Figure 5 The preparation of semiconductor structure 100 is simplified, thereby reducing the difficulty of the semiconductor structure 100 preparation process and improving the preparation efficiency of semiconductor structure 100.

[0192] S3. A first gate is formed on the side of the first gate dielectric layer away from the first semiconductor body to form a first transistor structure including the first semiconductor body, the first gate, and the first gate dielectric layer. The first gate has one end close to the first sub-gate dielectric layer in a first direction.

[0193] like Figure 15 and Figure 18 As shown, in this step S3, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof can be used to deposit conductive material in the first trench 330 or the second trench 380 to form a thin film deposition process as shown. Figure 19 The first gate 112 is shown.

[0194] The first gate 112 can form a first transistor structure 110 together with the first semiconductor body 111 and the first gate dielectric layer 113 prepared in the foregoing embodiments.

[0195] For example, the conductive material may include, but is not limited to, one or more combinations of germanium silicon, tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials may be used. In this embodiment, the conductive material of the first gate 112 may include tungsten, but this embodiment is not limited thereto.

[0196] With this configuration, the first gate 112 can be used to control the on / off state of the first transistor structure 110, thereby enabling the DRAM cell containing the first transistor structure 110 to perform data reading or writing operations.

[0197] Furthermore, in step S3, the second gate 122 can also be fabricated in the same fabrication process, so that the second gate 122 can form a second transistor structure 120 with the second semiconductor body 121 and the second gate dielectric layer 123 fabricated in the aforementioned embodiment.

[0198] This method simplifies the fabrication process of the semiconductor structure 100, reduces the difficulty of the semiconductor structure 100 fabrication process, and improves the fabrication efficiency of the semiconductor structure 100.

[0199] like Figure 15 and Figure 18 As shown, in some embodiments, the method for fabricating the semiconductor structure 100 may further include: depositing an insulating material in the first trench 330 or the second trench 380 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof thin film deposition processes to form a structure as shown in the figure. Figure 19 The insulation filling structure 160 shown is illustrated.

[0200] For example, the insulating material may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride), and may be any suitable insulating material such as silicon oxide; this disclosure does not limit the embodiments in this regard. In this embodiment, the insulating material of the insulating filling structure 160 may include silicon oxide.

[0201] In this embodiment, by forming an insulating filling structure 160 in the first trench 330 or the second trench 380, isolation between the first semiconductor body 111 and the second semiconductor body 121 can be achieved. Furthermore, by embedding the first gate 112 corresponding to the first semiconductor body 111 and the second gate 122 corresponding to the second semiconductor body 121 within the insulating filling structure 160, isolation between adjacent first gates 112 and second gates 122, isolation between the first gate 112 and its corresponding first semiconductor body 111, and isolation between the second gate 122 and its corresponding second semiconductor body 121 can be achieved.

[0202] This configuration avoids interference with the storage states of other adjacent transistor structures when the first gate 112, the second gate 122, and the corresponding bit line 130 are used to control the first transistor structure 110 and the second transistor structure 120 for data reading, writing, or erasing operations. This improves the accuracy of the control of the first transistor structure 110 and the second transistor structure 120 by the first gate 112, the second gate 122, and the bit line 130, and also improves the stability and reliability of the first transistor structure 110, the second transistor structure 120, and the semiconductor structure 100.

[0203] Figure 20 This is a schematic diagram of a semiconductor structure 100 corresponding to the fabrication method of the semiconductor structure 100.

[0204] like Figure 20 As shown, in some embodiments, before forming the first gate dielectric layer 113 along the second direction X on one side of the first semiconductor body 111, the method for fabricating the semiconductor structure 100 further includes forming a second gate dielectric layer 115 along the second direction X on one side of the first semiconductor body 111.

[0205] For example, the material of the first semiconductor body 111 may include an oxide semiconductor material, such as silicon. In this scenario, based on the characteristic that the semiconductor material of the first semiconductor body 111 is easily oxidized, a structure such as... can be formed on one side of the first semiconductor body 111. Figure 20 The second gate dielectric layer 115 is shown.

[0206] Figure 21 This is a schematic diagram of another semiconductor structure 100 corresponding to the fabrication method of semiconductor structure 100. Figure 22 This is a schematic diagram of another semiconductor structure 100 corresponding to the preparation method of semiconductor structure 100.

[0207] In some embodiments, the method for fabricating the semiconductor structure 100 may further include the following step S4.

[0208] S4. An isolation structure is formed in the fifth groove, wherein the isolation structure 150 may include a conductive structure 151 (see [reference]). Figure 6 ) and insulation structure 152 (see Figure 6 ).

[0209] like Figure 12 As shown, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof can be used to form a thin film in the fifth tank 240, as shown. Figure 21 The initial insulation structure 400 is shown.

[0210] A photoresist layer can be formed on one side surface of the initial insulating structure 400 by means of static spin coating or dynamic spray coating, and the photoresist layer can be patterned to obtain a sixth mask layer with a sixth opening.

[0211] A portion of the initial insulating structure 400 is removed via the sixth opening to form a sixth trench. The dimension of the sixth trench in the second direction X is smaller than the dimension of the initial insulating structure 400 in the second direction X. Exemplarily, the removal of the initial insulating structure 400 can be achieved using any suitable etching process, such as dry etching or wet etching, and this embodiment of the present disclosure is not limited in this respect.

[0212] Using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, conductive and insulating materials are sequentially deposited in the sixth tank to form a thin film deposition process. Figure 22 The conductive structure 151 and the insulating structure 152 are shown. The conductive structure 151 and the insulating structure 152 form an isolation structure 150.

[0213] With this configuration, the conductive structure 151 can be used to improve the isolation effect of the isolation structure 150 between the first semiconductor body 111 and the second semiconductor body 121 of the two adjacent columns of first transistor structures 110 and second transistor structures 120.

[0214] The insulating structure 152 can surround the conductive structure 151 to isolate the conductive structure 151 from the adjacent first semiconductor body 111 and second semiconductor body 121, thereby improving the stability and reliability of the first transistor structure 110 and the second transistor structure 120.

[0215] For example, the conductive structure 151 may be made of a conductive material, such as W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The material of the insulating structure 152 may include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride) materials, and may be any suitable insulating material such as silicon oxide. In this embodiment, the conductive material of the conductive structure 151 may include W, and the insulating material of the insulating structure 152 may include silicon oxide; however, this embodiment of the present disclosure is not limiting in this respect.

[0216] Based on the semiconductor structure 100 provided in the above embodiments, this disclosure also provides an optimization method for the semiconductor structure 100, which is used to optimize the semiconductor structure 100.

[0217] Figure 23 A flowchart illustrating a method for optimizing a semiconductor structure 100 according to some embodiments of this disclosure.

[0218] like Figure 23 As shown, in some embodiments, the optimization method of the semiconductor structure 100 includes the following steps S10 to S30.

[0219] S10. A semiconductor structure is provided, including a first transistor structure. The first transistor structure includes a first semiconductor body, a first gate, and a first gate dielectric layer. The first semiconductor body extends along a first direction, the first gate is disposed on one side of the first semiconductor body along a second direction, and the first gate dielectric layer is disposed between the first gate and the first semiconductor body. The first direction and the second direction intersect. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, which are stacked along the first direction, and the first sub-gate dielectric layer is disposed near one end of the first gate in the first direction. The material of the first sub-gate dielectric layer includes a non-volatile material, and the material of the first sub-gate dielectric layer is different from the material of the second sub-gate dielectric layer.

[0220] In step S10, by forming a first sub-gate dielectric layer 1131 of non-volatile material on the side near the first gate 112, the non-volatility of the non-volatile material can be utilized to reduce the leakage current of the source or drain of the semiconductor structure in the first direction Z during the subsequent optimization process of the semiconductor structure. The specific optimization process will be described in subsequent steps S20 and S30, and will not be repeated here.

[0221] S20. An optimized voltage is applied to the first gate of the first transistor structure to form an optimized electric field within the first sub-gate dielectric layer of the first transistor structure.

[0222] Figure 24 To and Figure 23 The electric field diagram of a first transistor structure 110 corresponding to the optimization method in the diagram is shown below. Figure 25 To and Figure 23 The electric field diagram of another first transistor structure 110 corresponding to the optimization method in the figure.

[0223] like Figure 24 and Figure 25 As shown, in step S20, during the testing phase before the first transistor structure 110 is put into use, an optimized voltage can be applied to the first gate 112 to form an optimized electric field E1 on the first gate dielectric layer 113 and the first semiconductor body 111, and then the ferroelectric material of the first sub-gate dielectric layer 1131 is ferroelectrically polarized under the action of the optimized electric field E1.

[0224] Before the optimization voltage is applied, the ferroelectric domains in the ferroelectric material of the first sub-gate dielectric layer 1131 are arranged in a disordered manner. After the optimization voltage is applied, the ferroelectric domains in the ferroelectric material are polarized under the action of the optimization electric field E1, thereby forming the optimization electric field E1 on the first sub-gate dielectric layer 1131.

[0225] For example, in the scenario where the first transistor structure 110 needs to be turned off by negative voltage, the optimized voltage applied to the first gate 112 can be a positive voltage, such as any suitable voltage value such as 2V, 3V, 4V, 5V, etc.; or, in some other implementations, the optimized voltage can also be any achievable voltage value such as negative voltage, and this disclosure embodiment does not limit this.

[0226] S30. Stop applying the optimized voltage to the first gate, and store the optimized electric field within the first sub-gate dielectric layer. The optimized electric field is used to optimize the turn-off electric field at the location of the first sub-gate dielectric layer when the first transistor structure is in the off state.

[0227] Figure 26 To and Figure 23 The electric field diagram of another first transistor structure 110 corresponding to the optimization method in the figure.

[0228] In this step S30, after the optimized voltage applied to the first gate 112 is stopped, the optimized electric field E1 formed on the first sub-gate dielectric layer 1131 can be preserved in the first sub-gate dielectric layer 1131 due to the non-volatility of the ferroelectric material.

[0229] like Figure 26 As shown, after the first transistor structure 110 is put into use, since the optimized electric field E1 is stored in the first sub-gate dielectric layer 1131, when the first transistor structure 110 is turned off, the optimized electric field E1 stored on the first sub-gate dielectric layer 1131 can cancel the turn-off electric field E2 applied to the first gate 112, thereby weakening the turn-off electric field E2 of the source or drain of the first transistor structure 110 in the turn-off state, thereby reducing the leakage current of the source or drain of the first transistor structure 110, thereby improving the data retention time of the DRAM cell where the first transistor structure 110 is located.

[0230] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first transistor structure includes a first semiconductor body, a first gate, and a first gate dielectric layer. The first semiconductor body extends along a first direction, the first gate is disposed on one side of the first semiconductor body along a second direction, and the first gate dielectric layer is disposed between the first gate and the first semiconductor body. The first direction intersects the second direction. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, which are stacked along the first direction, and the first sub-gate dielectric layer is disposed near one end of the first gate in the first direction; wherein, the material of the first sub-gate dielectric layer includes a non-volatile material, and the material of the first sub-gate dielectric layer is different from that of the second sub-gate dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer further includes a third sub-gate dielectric layer, which is disposed on the side of the second sub-gate dielectric layer away from the first sub-gate dielectric layer, and is disposed near the other end of the first gate in the first direction; wherein, the material of the third sub-gate dielectric layer includes a non-volatile material.

3. The semiconductor structure according to claim 2, characterized in that, The first gate includes a first end and a second end in the first direction, a portion of the first sub-gate dielectric layer is disposed between the first end and the first semiconductor body, and a portion of the third sub-gate dielectric layer is disposed between the second end and the first semiconductor body.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The ratio of the size of the first sub-gate dielectric layer in the first direction to the size of the first gate in the first direction is greater than or equal to 0.02 and less than or equal to 0.

2.

5. The semiconductor structure according to claim 4, characterized in that, The non-volatile materials include ferroelectric materials.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second gate dielectric layer, which is disposed between the first semiconductor body and the first gate dielectric layer, and the material of the second gate dielectric layer is different from the material of the first sub-gate dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that, Both the second sub-gate dielectric layer and the second gate dielectric layer are made of oxide materials.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second transistor structure and an isolation structure; The second transistor structure and the first transistor structure are arranged at intervals along the second direction; the second transistor structure includes a second semiconductor body and a second gate, the second semiconductor body extends along the first direction, and the second gate is disposed on one side of the second semiconductor body along the second direction; wherein, the second gate and the first gate are both located between the first semiconductor body and the second semiconductor body; The isolation structure is located on the side of the second semiconductor body away from the second gate.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes bit lines; The bit line extends along the second direction and is connected to one end of the first semiconductor body and one end of the second semiconductor body.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: A capacitor structure layer is stacked on the side of the first semiconductor body away from the bit line. The capacitor structure layer includes a plurality of capacitor units, and one capacitor unit is connected to the other end of the first semiconductor body or the other end of the second semiconductor body.

11. A method for fabricating a semiconductor structure, characterized in that, include: A first semiconductor body is formed, and the first semiconductor body extends along a first direction; A first gate dielectric layer is formed on one side of the first semiconductor body along a second direction. The first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer. The first sub-gate dielectric layer and the second sub-gate dielectric layer are stacked along the second direction. The material of the first gate dielectric layer includes a non-volatile material. The material of the first sub-gate dielectric layer is different from the material of the second sub-gate dielectric layer. The first direction intersects the second direction. A first gate is formed on the side of the first gate dielectric layer away from the first semiconductor body to form a first transistor structure including the first semiconductor body, the first gate and the first gate dielectric layer, wherein one end of the first gate in the first direction is close to the first sub-gate dielectric layer.

12. The preparation method according to claim 11, characterized in that, The formation of a first gate dielectric layer along a second direction on one side of the first semiconductor body includes: On one side of the first semiconductor body, a first insulating layer and a first ferroelectric layer are stacked along the first direction to form a first insulating layer and a first ferroelectric layer. A portion of the first insulating layer and a portion of the first ferroelectric layer are removed to form a first trench and a first gate dielectric layer; the first trench extends along the first direction, penetrates the first ferroelectric layer and extends into the first insulating layer, and the size of the first trench in the second direction is smaller than the size of the first ferroelectric layer in the second direction; wherein the first ferroelectric layer exposed on the sidewall of the first trench is the first sub-gate dielectric layer, and the first insulating layer exposed on the sidewall of the first trench is the second sub-gate dielectric layer.

13. The preparation method according to claim 11, characterized in that, The formation of a first gate dielectric layer along a second direction on one side of the first semiconductor body includes: On one side of the first semiconductor body, a second insulating layer, a second ferroelectric layer, a third insulating layer, and a third ferroelectric layer are stacked along the first direction, with the second ferroelectric layer and the third insulating layer formed between the second insulating layer and the third ferroelectric layer, and the second ferroelectric layer being closer to the second insulating layer than the third insulating layer. A portion of the second ferroelectric layer, a portion of the third insulating layer, and a portion of the third ferroelectric layer are removed to form a second trench and a first gate dielectric layer; the second trench extends along the first direction, penetrating the second ferroelectric layer, the third insulating layer, and the third ferroelectric layer, and the size of the second trench in the second direction is smaller than the size of the second ferroelectric layer in the second direction; wherein, the second ferroelectric layer exposed on the sidewall of the second trench is the third sub-gate dielectric layer, the third insulating layer exposed on the sidewall of the second trench is the second sub-gate dielectric layer, and the third ferroelectric layer exposed on the sidewall of the second trench is the first sub-gate dielectric layer.

14. The preparation method according to claim 12 or 13, characterized in that, Before forming a first gate dielectric layer along a second direction on one side of the first semiconductor body, the fabrication method further includes: A second gate dielectric layer is formed on one side of the first semiconductor body along the second direction.

15. A method for optimizing a semiconductor structure, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a first transistor structure; the first transistor structure includes a first semiconductor body, a first gate, and a first gate dielectric layer, the first semiconductor body extending along a first direction, the first gate disposed on one side of the first semiconductor body along a second direction, and the first gate dielectric layer disposed between the first gate and the first semiconductor body, wherein the first direction intersects the second direction; the first gate dielectric layer includes a first sub-gate dielectric layer and a second sub-gate dielectric layer, the first sub-gate dielectric layer and the second sub-gate dielectric layer being stacked along the first direction, and the first sub-gate dielectric layer being disposed near one end of the first gate in the first direction; wherein the material of the first sub-gate dielectric layer includes a non-volatile material, and the material of the first sub-gate dielectric layer is different from the material of the second sub-gate dielectric layer; An optimized voltage is applied to the first gate of the first transistor structure to form an optimized electric field within the first sub-gate dielectric layer of the first transistor structure; The optimized voltage applied to the first gate is stopped, and the optimized electric field is stored within the first sub-gate dielectric layer; wherein the optimized electric field is used to optimize the turn-off electric field at the location of the first sub-gate dielectric layer when the first transistor structure is in the turn-off state.

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