Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate including a cell region and a connection region, a bit line extending in a first direction on the substrate across the cell region and the connection region, a word line extending on the cell region above the bit line and in a second direction, an active pattern on one side surface of the word line on the cell region, and a cell region isolation layer on the bit line on the connection region. The active pattern is an outermost active pattern, the cell region isolation layer includes a first insulating film on an outer side surface of the outermost active pattern and a second insulating film including a first portion and a second portion, wherein a lower surface of the second portion contacts an upper surface of the bit line.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices. Background Technology

[0002] Semiconductor devices are core components used in electronic devices to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, semiconductor memory devices are primarily used for storing and retrieving data. Semiconductor memory devices are core components of electronic devices that perform indispensable roles in various fields such as computers, communication equipment, and consumer electronics.

[0003] With industrial development, the performance and functional requirements of electronic devices are increasing. Therefore, to achieve high performance, the integration density of semiconductor memory devices is constantly increasing. During this development process, novel transistor structures, such as transistors with vertical channels or vertically stacked transistors, have been proposed.

[0004] The information provided herein is intended to help understand the context of this disclosure and may include information that does not correspond to the relevant art. Summary of the Invention

[0005] One of the objectives of this disclosure is to provide a semiconductor memory device with improved electrical characteristics and / or reliability.

[0006] According to some embodiments of this disclosure, a semiconductor memory device may include: a substrate having a cell region and a connection region on one side of the cell region; a bit line extending across the cell region and the connection region in a first direction on the substrate; a word line extending above the bit line in the cell region and in a second direction intersecting the first direction; a first active pattern disposed on a side surface of the word line in the cell region; and a cell region isolation layer on the bit line in the connection region. The first active pattern may be an outermost active pattern disposed at the outermost point of the cell region in the first direction, and the cell region isolation layer may include a first insulating film and a second insulating film. The first insulating film has a first side surface on the outer surface of the outermost active pattern and extends in the second direction, and the second insulating film includes a first portion on the second side surface of the first insulating film and a second portion extending from a first end of the first portion in the first direction at the second side surface of the first insulating film. The first side surface of the first insulating film is opposite to the second side surface of the first insulating film, and the lower surface of the second portion in a third direction may contact the upper surface of the bit line in a third direction, the third direction intersecting each of the first and second directions.

[0007] According to some embodiments of this disclosure, a semiconductor memory device may include: a substrate having a cell region and a connection region on one side of the cell region; a bit line on the substrate extending across the cell region and the connection region in a first direction; a plurality of word lines on the bit line in the cell region, each of the plurality of word lines being spaced apart from an adjacent word line in the first direction, the plurality of word lines including a first word line and a second word line, the first word line and the second word line each extending in a second direction intersecting the first direction; a plurality of active patterns on the cell region, the plurality of active patterns including a first active pattern on a first side surface of the first word line and a second active pattern on a second side surface of the second word line opposite to the first side surface of the second word line; and a cell region isolation layer on the bit line in the connection region. The cell region isolation layer may include a first insulating film and a second insulating film, which are sequentially located on the outer surface of a third active pattern. The third active pattern is the outermost active pattern in a first direction among a plurality of active patterns. The outermost active pattern defines the boundary between the cell region and the connection region. The lower surface of the second insulating film may contact the upper surface of the bit line in a third direction, which intersects with each of the first and second directions.

[0008] According to some embodiments of this disclosure, a semiconductor memory device may include: a substrate having a cell region and a connection region on one side of the cell region; a bit line extending across the cell region and the connection region in a first direction on the substrate; a plurality of word lines on the bit line in the cell region, each of the plurality of word lines being spaced apart from an adjacent word line in the first direction, the plurality of word lines including a first word line and a second word line, the first word line and the second word line each extending in a second direction intersecting the first direction; a plurality of active patterns on the cell region, the plurality of active patterns including a first active pattern on a first side surface of the first word line and a second active pattern on a second side surface of the second word line opposite to the first side surface of the second word line; and a cell region isolation layer on the bit line in the connection region. The cell region isolation layer may include a first insulating film, a second insulating film, and a third insulating film sequentially on an outer surface of a third active pattern, the third active pattern being the outermost active pattern among the plurality of active patterns, the outer surface of the outermost active pattern in the first direction defining a boundary between the cell region and the connection region. The first insulating film and the second insulating film can be made of different materials, and the first insulating film and the third insulating film can be made of the same material. The lower surface of the first insulating film and the lower surface of the second insulating film can contact the upper surface of the bit line, and the second insulating film can include a portion between the third insulating film and the bit line.

[0009] According to some embodiments of this disclosure, a method of manufacturing a semiconductor memory device may include: preparing an initial substrate including an initial cell region and an initial connection region disposed on one side of the initial cell region; forming a cell isolation trench in the initial connection region; sequentially forming a first initial insulating film, a second initial insulating film, and a third initial insulating film on the inner wall of the cell isolation trench and on the upper surface of the initial substrate in the initial cell region; forming a plurality of word lines in the initial cell region, the plurality of word lines being spaced apart from adjacent word lines in a first direction, each of the plurality of word lines extending in a second direction intersecting the first direction; forming a plurality of active patterns, each of the plurality of active patterns being disposed on one side of a corresponding word line in the plurality of word lines in the initial cell region; polishing the initial substrate in the initial cell region and the initial connection region downward to the lower surface of the first initial insulating film; and polishing the first initial insulating film downward in the initial connection region to the lower surface of the second initial insulating film to form a cell isolation insulating film including the first insulating film, the second insulating film, and the third insulating film sequentially disposed on the inner wall of the cell isolation trench.

[0010] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may further include: forming bit lines that contact the lower surface of an active pattern and the lower surface of a second insulating film and extend in a first direction.

[0011] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may further include: after forming an active pattern, forming a landing pad connected to the active pattern, and forming a capacitor structure connected to the landing pad.

[0012] According to some embodiments of the present disclosure, forming a unit isolation insulating film may include: forming a unit isolation insulating film including a first insulating film, a second insulating film and a third insulating film, wherein the first insulating film is disposed on the inner wall of a unit isolation trench, the second insulating film includes a first portion of the second insulating film disposed on a side surface of the first insulating film and a second portion of the second insulating film extending from the end of the first portion of the second insulating film in a direction parallel to the surface of the initial substrate, and the third insulating film is disposed on the first portion of the second insulating film and the second portion of the second insulating film.

[0013] According to some embodiments of the present disclosure, forming a unit isolation insulating film may include: forming a first insulating film and a second insulating film such that a first width of the first insulating film in a first direction, a second width of a first portion of the second insulating film in a first direction, and a third width of a second portion of the second insulating film in a third direction intersecting with each of the first and second directions are the same as each other.

[0014] According to some embodiments of the present disclosure, forming a unit isolation insulating film may include: forming a first insulating film and a second insulating film, such that a first width of the first insulating film in a first direction is greater than both the second width of a first portion of the second insulating film in the first direction and the third width of a second portion of the second insulating film in a third direction intersecting with each of the first and second directions.

[0015] According to some embodiments of this disclosure, forming a unit isolation insulating film may include: forming a first insulating film and a second insulating film, such that a first width of the first insulating film in a first direction is less than both the second width of a first portion of the second insulating film in the first direction and the third width of a second portion of the second insulating film in a third direction intersecting with each of the first and second directions.

[0016] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may further include: forming a gate capping layer disposed between a plurality of word lines and bit lines, wherein the lower surface of the gate capping layer may be disposed coplanarly with the lower surface of a second insulating film.

[0017] According to some embodiments of this disclosure, the multiple insulating films in the cell region isolation layer of the connection region can be used as CMP stop layers during the CMP process, thereby improving surface flatness and thickness uniformity. In this way, semiconductor memory devices with improved electrical characteristics and reliability can be provided. Attached Figure Description

[0018] Figure 1 This is a layout diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0019] Figure 2 This is a layout diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0020] Figure 3 yes Figure 2 A magnified view of region Q.

[0021] Figure 4 It is along Figure 3 The cross-sectional view taken from line AA.

[0022] Figure 5 yes Figure 4 A magnified view of region R1.

[0023] Figures 6 to 8 yes Figure 4 A magnified view of region R2.

[0024] Figure 9 This is a diagram illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure.

[0025] Figure 10 and Figure 11 This is a layout diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0026] Figures 12 to 19 This is an intermediate process diagram used to describe a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0027] Figure 20 This is a flowchart describing a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Detailed Implementation

[0028] In the following description, various embodiments of the present disclosure are described with reference to the accompanying drawings. Throughout the specification, the same reference numerals may denote the same parts.

[0029] As can be seen, for example, in the accompanying figures, items described in the singular herein may be provided in the plural. Therefore, unless the context otherwise requires, a description of a single item provided in the plural form should be understood to apply to the remaining multiple items.

[0030] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context otherwise requires. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0031] As used herein, when referring to orientation, layout, location, shape, size, composition, quantity, or other measures, terms such as “identical,” “equal,” “planar,” or “coplanar” do not necessarily refer to exactly the same orientation, layout, location, shape, size, composition, quantity, or other measures, but are intended to cover orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures that are substantially identical within typical variations that can be caused by conventional manufacturing processes. The term “substantially” may be used herein to emphasize this meaning unless the context or other statement otherwise indicates otherwise. For example, items described as “substantially identical” or “substantially constant” may be exactly the same or completely constant, or may be identical or constant within acceptable variations that may occur, for example, due to manufacturing processes.

[0032] It should be understood that when an element is referred to as being “connected” to another element or “on” another element, it can be directly connected to or directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “in contact” or “in contact with” another element (or using any form of the word “in contact”), there are no intermediate elements at the point of contact. As used herein, the terms “on,” “above,” or “cover” are intended to indicate that one element is above another element. Elements may be in contact or not in contact. For example, layers may exist between layers that are “on” each other. An element being “on” another element or “above,” “stacked,” or “covered” another element does not require covering the entire top surface of the element below it to be considered “on,” “above,” “stacked,” or “covered.” These terms are intended to cover an element being “on” or “above” the entire or any part of the element below it, or being “stacked” or “covered” the entire or any part of the element below it.

[0033] Ordinal numbers such as "first," "second," and "third" can be simply used as markers for certain elements, steps, etc., to distinguish them from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be referenced elsewhere without an ordinal number or with a different ordinal number (e.g., "second" in the specification or another claim).

[0034] For ease of description, spatial relative terms such as “down,” “above,” “up,” “inner,” “outer,” and “outermost” may be used to describe positional relationships as shown in the figure. It should be understood that spatial relative terms also cover different orientations of the device besides those shown in the figure.

[0035] In the accompanying drawings, the first direction D1 and the second direction D2 may represent the same plane. For example, the first direction D1 and the second direction D2 may represent directions parallel to the surface of the substrate 100. The third direction D3 may represent a direction perpendicular to each of the first direction D1 and the second direction D2. For example, the third direction D3 may represent a direction perpendicular to the surface of the substrate 100. The first direction D1 and the second direction D2 may intersect each other.

[0036] Figure 1 This is a layout diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure.

[0037] Reference Figure 1 Semiconductor memory devices may include cell structures (CELL) and peripheral circuit structures (PERI) arranged in a vertical direction (e.g., third direction D3).

[0038] A cell structure (CELL) may include multiple cell regions (MCAs) arranged in a matrix. The MCA may be a memory cell region of DRAM. For example, the MCA may include memory cell transistors and data storage elements. In some embodiments, the memory cell transistors may be vertical channel transistors (VCTs). The gates of the memory cell transistors may be connected to word lines (e.g., ...). Figure 3 The word line WL). Furthermore, the channel pattern of the memory cell transistor (e.g., active pattern (e.g., Figure 3 The active patterned AP can be connected to a bit line (e.g., Figure 3 The bit line (BL) and data storage elements. For example, the data storage element can be a capacitor structure (e.g., Figure 4 Capacitor structure (CAP).

[0039] The Peripheral Circuit Area (PERI) can be either the core area or the peripheral circuit area of ​​a DRAM. The Peripheral Circuit Area (PCA) can include peripheral circuit transistors for delivering signals and / or power to the cell transistors included in the Cell Area (MCA). In exemplary embodiments, the peripheral circuit transistors can form various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, or data input / output circuits.

[0040] Figure 2 This is a layout diagram illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, Figure 2 yes Figure 1 The diagram shows a schematic layout of the cell area (MCA) of a semiconductor memory device. Figure 2 In the text, elements other than capacitor structures (e.g., ...) are omitted. Figure 4 The structure of the capacitor (CAP) is other than the first electrode 312.

[0041] Reference Figure 2 The connection area INT can be arranged on one side of the cell region MCA. For example, the cell region MCA can be surrounded by the connection area INT. In some embodiments, the connection area INT may include an insulating pattern arranged to separate adjacent cell regions MCA from each other.

[0042] like Figure 2 As shown, multiple first electrodes 312 can be arranged on the cell region MCA. Although Figure 2 A planar arrangement of the first electrodes 312 in a matrix form is shown, but the arrangement and number of the first electrodes 312 are exemplary and the scope of this disclosure is not limited thereto.

[0043] Figure 3 yes Figure 2 A magnified view of region Q. Figure 4 It is along Figure 3 The cross-sectional view taken from line AA.

[0044] Reference Figure 3 and Figure 4 According to some embodiments of the present disclosure, a semiconductor memory device may include a substrate 100, a bit line BL, a word line WL, an active pattern AP, a gate capping layer 140, a gate isolation layer 150, a cell isolation layer CSP, a landing pad LP, and a capacitor structure CAP.

[0045] Substrate 100 may be, for example, a base substrate and may be formed of a crystalline semiconductor material. For example, substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In some embodiments, substrate 100 may comprise polysilicon (poly Si) or may be polysilicon (poly Si).

[0046] In some embodiments, the substrate 100 may be an insulating material. For example, the substrate 100 may be an insulating substrate. In some embodiments, the substrate 100 may be constituted by a wiring insulating layer, which includes a unit structure (e.g., Figure 1 The cell structure (CELL) and the peripheral circuit structure (e.g., Figure 1 The wiring structure of the peripheral circuit structure (PERI) is connected.

[0047] The substrate 100 may include a cell region MCA and a connection region INT.

[0048] A memory cell array comprising multiple memory cells can be formed in a cell region MCA. For example, the bit line BL, word line WL, and active pattern AP described herein can be arranged in a cell region MCA.

[0049] The connection area INT can be arranged around one or more sides of the cell area MCA. For example, the connection area INT can surround the cell area MCA. The cell area isolation layer CSP can be arranged within the connection area INT.

[0050] In some embodiments, the substrate 100 may include a plurality of cell regions MCA, and connection regions INT may be arranged between adjacent cell regions MCA. In one example, adjacent cell regions MCA may have a symmetrical structure, but the scope of this disclosure is not limited thereto.

[0051] Multiple bit lines BL can be arranged on the substrate 100. Adjacent bit lines BL can be spaced apart from each other in a second direction D2. Each bit line BL can extend across the cell region MCA and the connection region INT in a first direction D1 parallel to the surface of the substrate 100. In some embodiments, each bit line BL can be cut off at the connection region INT. Adjacent bit lines BL can be arranged with equal intervals relative to each other. The width of each bit line BL or the spacing between adjacent bit lines BL can be determined according to design rules.

[0052] In some embodiments, each bit line BL may include, or may be, a metal layer 122 and a polysilicon film 124 sequentially stacked along a third direction D3 on a substrate 100. The polysilicon film 124 may be doped polysilicon, and the metal layer 122 may include, or may be, a conductive material. The metal layer 122 may be a conductive metal nitride, such as titanium nitride or tantalum nitride, or a combination thereof. Furthermore, the metal layer 122 may be a metal silicide, such as titanium silicide, cobalt silicide, or nickel silicide. However, the materials included in the metal layer 122 are not limited thereto and may vary.

[0053] Multiple word lines WL can be arranged above the bit line BL. Specifically, the multiple word lines WL can be spaced apart from the surface of the bit line BL in a third direction D3. In addition, adjacent word lines WL can be spaced apart from adjacent word lines in a first direction D1. Each word line WL can extend in a second direction D2 that intersects the first direction D1.

[0054] An active pattern AP can be arranged on one side of a word line WL. In some embodiments, multiple word lines WL may include a first word line WL1 and a second word line WL2, and active patterns AP are arranged on different side surfaces of the word lines. The first word line WL1 and the second word line WL2 may be alternately spaced along a first direction D1. For example, a first active pattern AP1 may be arranged on a first side surface of the first word line WL1. A second active pattern AP2 may be arranged on a second side surface of the second word line WL2 opposite to the first side surface.

[0055] Each active patterned AP may include or may be a single-crystal semiconductor material. For example, an active patterned AP may include or may be single-crystal silicon.

[0056] A gate insulating film 130 may be disposed between a word line WL and an active pattern AP. The gate insulating film 130 may extend in a third direction D3 between the word line WL and the active pattern AP. For example, the gate insulating film 130 may be disposed between a first word line WL1 and a first active pattern AP1, and may extend along a first side surface profile of the first word line WL1. Furthermore, the gate insulating film 130 may be disposed between a second word line WL2 and a second active pattern AP2, and may extend along a second side surface profile of the second word line WL2.

[0057] The gate insulating film 130 may include or may be silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric material may include or may be a metal oxide or a metal oxynitride. For example, the high-k dielectric material that can be used for the gate insulating film 130 may include or may be HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, or a combination thereof, but is not limited thereto.

[0058] The gate capping layer 140 can be disposed between the word line WL and the bit line BL. For example, when adjacent first word lines WL1 and second word lines WL2 face each other, the gate capping layer 140 can be disposed between the lower surface of each of the first word lines WL1 and second word lines WL2 and the upper surface of the bit line BL.

[0059] The gate capping layer 140 may include or may be silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material having a dielectric constant lower than that of silicon oxide, or a combination thereof, but is not limited thereto.

[0060] A gate isolation layer 150 may be disposed between adjacent first word lines WL1 and second word lines WL2 that face each other. For example, the gate isolation layer 150 may be disposed on the side surface of each of the first word lines WL1 and second word lines WL2 and on the upper surface of the first word lines WL1 and second word lines WL2 to which these side surfaces are connected.

[0061] Specifically, the gate isolation layer 150 may include a vertical portion 152 extending along the second side surface of the first word line WL and the first side surface of the second word line WL in a third direction D3, and a horizontal portion 154 connected to the end of the vertical portion 152 and disposed on the upper surface of each of the first word lines WL1 and WL2. In an example embodiment, the second side surface of the first word line WL1 indicates a side surface opposite to the first side surface of the first word line WL1 on which the first active pattern AP1 is disposed, and the first side surface of the second word line WL2 indicates a side surface opposite to the second side surface of the second word line WL2 on which the second active pattern AP2 is disposed.

[0062] The gate isolation layer 150 may include, or may be, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low-k dielectric material having a dielectric constant lower than that of silicon oxide, or a combination thereof, but is not limited thereto.

[0063] According to some embodiments, the semiconductor memory device may further include a back gate electrode BG, a back gate capping layer 160, a back gate isolation layer 170, and a back gate insulating film 180.

[0064] A back gate electrode BG can be disposed between a first active pattern AP1 and a second active pattern AP2, wherein the first active pattern AP1 and the second active pattern AP2 face each other. The back gate electrode BG can be spaced apart from the surface of the bit line BL in a third direction D3. Furthermore, adjacent back gate electrodes BG among a plurality of back gate electrodes can be spaced apart from each other in a first direction D1. Each back gate electrode BG can extend in the same direction as each word line WL (e.g., a second direction D2). Although Figure 4 The height of the back gate electrode BG on the third direction D3 is shown to correspond to the height of the word line WL, but this disclosure is not limited thereto, and the height of the back gate electrode BG may be different from the height of the word line WL.

[0065] The back gate electrode (BG) may include or may be a conductive material. For example, the back gate electrode (BG) may include or may be doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material or metal, or a combination thereof.

[0066] In some embodiments, a negative voltage can be applied to the back gate electrode BG when the semiconductor memory device is operating, and the threshold voltage of the vertical channel transistor can be increased. For example, this can prevent degradation of leakage current characteristics, which may occur during miniaturization of the vertical channel transistor and reduction of the threshold voltage.

[0067] The back gate capping layer 160 can be disposed on the lower surface of the back gate electrode BG. For example, the back gate capping layer 160 can be disposed together with the gate capping layer 140 between the back gate electrode BG and the bit line BL.

[0068] The back gate cap 160 may include or may be an insulating material. For example, the back gate cap 160 may be silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof, but is not limited thereto.

[0069] A back-gate isolation layer 170 may be disposed on the upper surface of the back-gate electrode BG. For example, the back-gate isolation layer 170 may be disposed between the back-gate electrode BG and the contact interlayer insulating layer 190 described herein. Furthermore, the side surface of the back-gate isolation layer 170 may contact a portion of the side surface of each of the adjacent first active patterns AP1 and second active patterns AP2. For example, a portion of the side surface of each of the adjacent first active patterns AP1 and second active patterns AP2 may contact the side surface of the back-gate isolation layer 170.

[0070] The back gate isolation layer 170 may include or may be an insulating material. For example, the back gate isolation layer 170 may include or may be silicon oxide, silicon nitride, or silicon oxynitride, or a combination thereof, but is not limited thereto.

[0071] A back gate insulating film 180 may be disposed between the back gate electrode BG and the active pattern AP. The back gate insulating film 180 may extend in a third direction D3 between the back gate electrode BG and the active pattern AP. For example, the back gate insulating film 180 may extend in a third direction D3 along the side surface of each of the back gate capping layer 160 and the back gate electrode BG in a first direction D1.

[0072] The back gate insulating film 180 may include or may be silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric material may include or may be a metal oxide or a metal oxynitride. For example, the high-k dielectric material that can be used for the back gate insulating film 180 may include or may be HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, or a combination thereof, but is not limited thereto.

[0073] Cell isolation layer (CSP) can be placed on bit line BL in the link area (INT).

[0074] The cell region isolation layer (CSP) may include a first insulating film 210, a second insulating film 220, and a third insulating film 230 sequentially arranged on the outermost surface (OSF) of the outermost active pattern AP among a plurality of active pattern APs. Here, the outermost active pattern AP may refer to the active pattern AP arranged at the outermost position of the cell region MCA in a first direction, and may refer to the active pattern AP closest to the connection region INT among the plurality of active pattern APs. In some examples, the outermost surface (OSF) of the outermost active pattern AP may be a standard defining the boundary between the cell region MCA and the connection region INT.

[0075] The first insulating film 210 may have a first side surface disposed on the outer surface OSF of the outermost active pattern AP. Furthermore, referring to… Figure 3 On one side of the outermost word line WL among the multiple word lines WL (e.g., the side adjacent to the connection area INT), multiple outermost active patterns AP can be spaced apart from each other in the second direction D2. The first insulating film 210 can extend in the second direction D2 along a side surface of each active pattern among the multiple outermost active patterns AP (e.g., the side surface adjacent to the connection area INT).

[0076] The second insulating film 220 may include a first portion (or vertically extending portion) 222 disposed on a second side surface of the first insulating film 210 opposite to the first side surface (e.g., the inner side surface), and a second portion (or horizontally extending portion) 224 extending from the lower end of the first portion 222 in a horizontal direction (e.g., a first direction D1 and a second direction D2). For example, the second portion 224 may extend from the first end of the first portion 222 at the second side surface of the first insulating film 210. The second portion 224 may be disposed parallel to the upper surface of the substrate 100 or the upper surface of the bit line BL.

[0077] In some embodiments, the lower surface of the second portion 224 may contact the upper surface of the bit line BL. For example, the lower surface of the second portion 224 on the third direction D3 may include a portion that contacts the upper surface of the bit line BL. In embodiments where the bit line BL has a configuration that is cut off in the connection region INT, the lower surface of the second portion 224 may include a portion that does not contact the upper surface of the bit line BL.

[0078] The third insulating film 230 may be disposed on the first portion 222 and the second portion 224 of the second insulating film 220. For example, the first insulating film 210 may be disposed on the outer surface of the first portion 222. The third insulating film 230 may be disposed on the inner surface of the first portion 222 and the upper surface of the second portion 224. The third insulating film 230 may overlap with the second portion 224 in a third direction D3. The second insulating film 220 may include a portion disposed between the first insulating film 210 and the third insulating film 230 (e.g., the first portion 222), and the second insulating film 220 may include a portion disposed between the third insulating film 230 and the bit line BL (e.g., the second portion 224).

[0079] The third insulating film 230 may extend in a horizontal direction (e.g., a first direction D1 and a second direction D2). The third insulating film 230 may be arranged parallel to the upper surface of the substrate 100 or the upper surface of the bit line BL. The third insulating film 230 may be wrapped by the second insulating film 220 on multiple sides. For example, the two side surfaces of the third insulating film 230 in the first direction D1 and the lower surface of the third insulating film 230 may be surrounded by the second insulating film 220.

[0080] Reference Figure 3 The cell isolation layer CSP can have a symmetrical structure in the connection region INT. For example, the first insulating film 210 can be spaced apart from each other, for example, in a first direction D1 or a second direction D2. For example, each first insulating film 210 can be arranged in the edge region on a corresponding side of the connection region INT. The second insulating film 220 can be arranged inside the first insulating film 210. The second insulating film 220 can be U-shaped. For example, the second insulating film 220 can include a first portion 222 disposed inside each of the respective spaced first insulating films 210, and a second portion 224 connecting the lower ends of the spaced first portions 222 to each other in a third direction D3. The third insulating film 230 can be arranged on the inner surface of the first portion 222 and the upper surface of the second portion 224 of the second insulating film 220. For example, the third insulating film 230 can fill the space defined by the inner surface of the first portion 222 and the upper surface of the second portion 224 of the second insulating film 220.

[0081] In some embodiments, the first insulating film 210 and the second insulating film 220 may be made of different materials. The first insulating film 210 and the second insulating film 220 may be materials with different etching selectivity. For example, the first insulating film 210 may be silicon oxide and the second insulating film 220 may be silicon nitride, but the scope of this disclosure is not limited thereto. Alternatively, the first insulating film 210 and the third insulating film 230 may be made of the same material. However, the scope of this disclosure is not limited thereto.

[0082] The semiconductor memory device may also include an interlayer contact insulating layer 190. The interlayer contact insulating layer 190 may be disposed on an active pattern AP. Additionally, the interlayer contact insulating layer 190 may contact the gate isolation layer 150, the back gate isolation layer 170, and the cell region isolation layer CSP. The interlayer contact insulating layer 190 may include, or may be, an insulating material such as silicon oxide, silicon nitride, or combinations thereof, but is not limited thereto.

[0083] Landing pads (LPs) can be connected to active patterned pads (APs). For example, landing pads (LPs) can penetrate the interlayer insulation layer (ILD) 190. Multiple landing pads (LPs) can be separated from each other by the ILD 190. The ILD 190 can be arranged between multiple landing pads (LPs).

[0084] The landing pad (LP) may include or may be a conductive material. The conductive material may include, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material or metal, or a combination thereof.

[0085] In some embodiments, although not shown, buried contacts may be disposed between the landing pad LP and the active pattern AP. The buried contacts may be conductive materials. For example, the buried contacts may be doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional materials or metals, or combinations thereof, and may consist of a single film and / or multiple films.

[0086] The capacitor structure CAP may include a first electrode 312, a dielectric film 314, a conductive film 316, and a second electrode 318.

[0087] The first electrode 312 may be disposed on the landing pad LP. The first electrode 312 may be electrically connected to the landing pad LP. A portion of the first electrode 312 may be disposed in the etch stop film 320. For example, the first electrode 312 may penetrate the etch stop film 320 to connect to the landing pad LP.

[0088] In some embodiments, the first electrode 312 may be columnar and may extend in a third direction D3. Furthermore, the first electrode 312 may include or may be at least one of the following materials: conductive metal materials (such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), or molybdenum (Mo)), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or tungsten nitride (WN)), noble metal materials (such as platinum (Pt), ruthenium (Ru), or iridium (Ir)), conductive oxide films (such as PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), and metal silicide films. However, this disclosure is not limited thereto.

[0089] A dielectric film 314 may be disposed on the first electrode 312. The dielectric film 314 may extend along the contours of the side and top surfaces of the first electrode 312. Furthermore, the dielectric film 314 may be disposed on the etch stop film 320. Additionally, the dielectric film 314 may comprise or may be, for example, a high-k dielectric material containing silicon oxide, silicon nitride, silicon oxynitride, and a metal. Although the dielectric film 314 is shown as a single film for ease of illustration, it is not limited thereto. According to the example embodiment, the dielectric film 314 may be multiple films.

[0090] A conductive film 316 may be disposed on a dielectric film 314. The conductive film 316 may extend along the contour of the dielectric film 314. The conductive film 316 may contact the dielectric film 314. The conductive film 316 may include, or may be, at least one of, but is not limited to, doped semiconductor materials, conductive metal nitrides (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (such as ruthenium, iridium, titanium, or tantalum), and conductive metal oxides (such as iridium oxide or niobium oxide).

[0091] The second electrode 318 may be disposed on the conductive film 316. For example, the second electrode 318 may fill the empty space between a plurality of first electrodes 312. The second electrode 318 may fill the remaining space between the plurality of first electrodes 312 after the formation of the dielectric film 314 and the conductive film 316. The second electrode 318 may be electrically connected to the conductive film 316. The second electrode 318 may include or be at least one of, for example, elemental semiconductor films and compound semiconductor films. The second electrode 318 may include doped n-type or p-type impurities.

[0092] The semiconductor memory device may further include an upper interlayer insulating layer 330. The upper interlayer insulating layer 330 may be disposed on the cell region MCA and the interconnect region INT of the substrate 100. For example, the upper interlayer insulating layer 330 may contact the second electrode 318 in the cell region MCA. Furthermore, the upper interlayer insulating layer 330 may contact the contact interlayer insulating layer 190 disposed on the cell region isolation layer CSP in the interconnect region INT.

[0093] The upper interlayer insulation layer 330 may include or may be an insulating material such as silicon oxide, or silicon nitride, or a combination thereof, but is not limited thereto.

[0094] Figure 5 This is a diagram used to illustrate a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, Figure 5 yes Figure 4 A magnified view of region R1. For ease of explanation, the following description will focus on [the region R1]. Figures 1 to 4 The constructions described herein differ from those in the original text. The same reference numerals are used as described herein with respect to other embodiments.

[0095] In some embodiments, the lower surface of the active pattern AP may be disposed on a surface coplanar with the lower surface of the second insulating film 220. For example, the lower surface of the active pattern AP and the lower surface of the second insulating film 220 may be aligned along a first direction D1. The lower surface of the active pattern AP and the lower surface of the second insulating film 220 may contact the upper surface of the bit line BL.

[0096] In some embodiments, the lower surface of the gate capping layer 140 may be coplanar with the lower surface of the second insulating film 220. For example, the lower surfaces of the gate capping layer 140 and the second insulating film 220 may be aligned along a first direction D1. The lower surfaces of the gate capping layer 140 and the second insulating film 220 may contact the upper surface of the bit line BL. Furthermore, the gate capping layer 140 may overlap with the second insulating film 220 (e.g., the second portion 224 of the second insulating film 220) in the first direction D1.

[0097] In some embodiments, the lower surface of the back gate capping layer 160 may be coplanar with the lower surface of the second insulating film 220. For example, the lower surfaces of the back gate capping layer 160 and the second insulating film 220 may be aligned along a first direction D1. The lower surfaces of the back gate capping layer 160 and the second insulating film 220 may contact the upper surface of the bit line BL. Furthermore, the back gate capping layer 160 may overlap with the second insulating film 220 (e.g., the second portion 224 of the second insulating film 220) in the first direction D1.

[0098] In some embodiments, the first distance H1 from the upper surface to the lower surface of the active pattern AP can be the same as the second distance H2 from the upper surface to the lower surface of the first insulating film 210. For example, the vertical level of the upper surface of the active pattern AP can correspond to the vertical level of the upper surface of the first insulating film 210, and the vertical level of the lower surface of the active pattern AP can correspond to the vertical level of the lower surface of the first insulating film 210.

[0099] In this disclosure, the term "vertical level" can refer to a vertical level in a third direction D3. "Vertical level" can also refer to the distance along the third direction D3 from a reference level to a surface of a particular configuration. The reference level can be a vertical level corresponding to the upper or lower surface of any component (e.g., substrate 100 or bit line BL) having a flat surface.

[0100] In some embodiments, the first distance H1 from the upper surface to the lower surface of the active pattern AP can be the same as the third distance H3 from the upper surface to the lower surface of the first portion 222 of the second insulating film 220. For example, the vertical level of the upper surface of the active pattern AP can correspond to the vertical level of the upper surface of the first portion 222, and the vertical level of the lower surface of the active pattern AP can correspond to the vertical level of the lower surface of the first portion 222.

[0101] In some embodiments, the fourth distance H4 from the upper surface of the horizontal portion 154 of the gate isolation layer 150 to the lower surface of the gate capping layer 140 may be the same as the second distance H2 from the upper surface to the lower surface of the first insulating film 210. For example, the vertical level of the upper surface of the horizontal portion 154 of the gate isolation layer 150 may correspond to the vertical level of the upper surface of the first insulating film 210, and the vertical level of the lower surface of the gate capping layer 140 may correspond to the vertical level of the lower surface of the first insulating film 210.

[0102] In some embodiments, the fourth distance H4 from the upper surface of the horizontal portion 154 of the gate isolation layer 150 to the lower surface of the gate capping layer 140 may be the same as the third distance H3 from the upper surface to the lower surface of the first portion 222 of the second insulating film 220. For example, the vertical level of the upper surface of the horizontal portion 154 of the gate isolation layer 150 may correspond to the vertical level of the upper surface of the first portion 222, and the vertical level of the lower surface of the gate capping layer 140 may correspond to the vertical level of the lower surface of the first portion 222.

[0103] In some embodiments, the fifth distance H5 from the upper surface of the back gate isolation layer 170 to the lower surface of the back gate capping layer 160 may be the same as the second distance H2 from the upper surface to the lower surface of the first insulating film 210. For example, the vertical level of the upper surface of the back gate isolation layer 170 may correspond to the vertical level of the upper surface of the first insulating film 210, and the vertical level of the lower surface of the back gate capping layer 160 may correspond to the vertical level of the lower surface of the first insulating film 210.

[0104] In some embodiments, the fifth distance H5 from the upper surface of the back gate isolation layer 170 to the lower surface of the back gate capping layer 160 may be the same as the third distance H3 from the upper surface to the lower surface of the first portion 222 of the second insulating film 220. For example, the vertical level of the upper surface of the back gate isolation layer 170 may correspond to the vertical level of the upper surface of the first portion 222, and the vertical level of the lower surface of the back gate capping layer 160 may correspond to the vertical level of the lower surface of the first portion 222.

[0105] In some embodiments, the first insulating film 210 and the second insulating film 220 of the cell region isolation layer CSP can be used as an etch stop layer or a polishing stop layer. (Refer to...) Figure 5 The described embodiments can be based on the fact that the first insulating film 210 and the second insulating film 220 are used as CMP stop layers in the chemical mechanical polishing (CMP) process. This can improve the surface flatness produced during the CMP process, enhance thickness uniformity, and thus provide a semiconductor memory device with improved electrical properties and / or reliability.

[0106] Figures 6 to 8 This is a diagram illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Specifically, Figures 6 to 8 yes Figure 4 A magnified view of region R2. For ease of explanation, the following description will focus on [the region R2]. Figures 1 to 5 The descriptions describe different constructions.

[0107] Reference Figure 6 The first width W1 of the first insulating film 210 in the first direction D1, the second width W2 of the first portion 222 of the second insulating film 220 in the first direction D1, and the third width W3 of the second portion 224 of the second insulating film 220 in the third direction D3 can be the same as each other, and the third direction D3 intersects with each of the first direction D1 and the second direction D2.

[0108] Reference Figure 7The first width W1 of the first insulating film 210 in the first direction D1 can be greater than the second width W2 of the first portion 222 in the first direction D1 and the third width W3 of the second portion 224 in the third direction D3. For example, the second width W2 of the first portion 222 in the first direction D1 and the third width W3 of the second portion 224 in the third direction D3 can be less than the first width W1 of the first insulating film 210 in the first direction D1. In embodiments, the second width W2 and the third width W3 can be the same as each other, but this disclosure is not limited thereto. The second width W2 and the third width W3 can also be different from each other.

[0109] Reference Figure 8 The first width W1 of the first insulating film 210 in the first direction D1 may be smaller than the second width W2 of the first portion 222 in the first direction D1 and the third width W3 of the second portion 224 in the third direction D3. For example, the second width W2 of the first portion 222 in the first direction D1 and the third width W3 of the second portion 224 in the third direction D3 may be larger than the first width W1 of the first insulating film 210 in the first direction D1. In embodiments, the second width W2 and the third width W3 may be the same as each other, but this disclosure is not limited thereto. The second width W2 and the third width W3 may be different from each other.

[0110] Figure 9 This is a diagram illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Figure 9 Can correspond to along Figure 2 The cross-sectional view taken from line AA. Besides the shape of the cell isolation layer CSP, Figure 9 The semiconductor memory device in the reference can be used with Figures 1 to 8 The semiconductor memory devices described are essentially the same. For ease of explanation, the following description will focus on those... Figures 1 to 8 The constructions described in the text are different.

[0111] In some embodiments, the cell region isolation layer (CSP) may include a first insulating film 210 and a second insulating film 220 sequentially disposed on the outer surface (OSF) of the outermost active pattern AP among a plurality of active patterns AP. The first insulating film 210 may be disposed adjacent to the active pattern AP on the cell region MCA. Additionally, the second insulating film 220 may be disposed on a side surface of the first insulating film 210. In some embodiments, the lower surface of the second insulating film 220 may contact the upper surface of the bit line BL.

[0112] In some embodiments, the distance from the upper surface to the lower surface of the first insulating film 210 may be the same as the distance from the upper surface to the lower surface of the second insulating film 220. For example, the vertical level of the upper surface of the first insulating film 210 may correspond to the vertical level of the upper surface of the second insulating film 220, and the vertical level of the lower surface of the first insulating film 210 may correspond to the vertical level of the lower surface of the second insulating film 220.

[0113] In some embodiments, the height of the second insulating film 220 (e.g., the distance from the upper surface to the lower surface of the second insulating film 220) can be kept substantially constant within the connection region INT.

[0114] Figure 10 and Figure 11 This is a layout diagram illustrating a semiconductor memory device according to exemplary embodiments of the present disclosure. Except for the different arrangement shapes of the cell region MCA and the peripheral circuit region PCA, Figure 10 and Figure 11 The semiconductor memory device can be compared with a reference Figures 1 to 9 The semiconductor memory devices described are essentially the same. For ease of explanation, the following description will focus on those... Figures 1 to 9 The constructions described in the text are different from the constructions described in the text. (Refer to...) Figures 1 to 9 The described semiconductor memory device can correspond to along Figure 11 The cross-sectional view of line BB.

[0115] Reference Figure 10 and Figure 11 The semiconductor memory device may include a cell region MCA and a peripheral circuit region PCA arranged in a plane (e.g., in a first direction D1 and a second direction D2).

[0116] The peripheral circuit area (PCA) can be arranged around the cell area (MCA). For example, the peripheral circuit area (PCA) can surround the cell area (MCA). In an embodiment, the connection area (INT) can be arranged between the cell area (MCA) and the peripheral circuit area (PCA) surrounding the cell area (MCA). In some embodiments, the connection area (INT) can include an insulating pattern arranged to separate adjacent cell areas (MCAs) and peripheral circuit areas (PCAs) from each other.

[0117] Figures 12 to 19 This is an intermediate process diagram used to describe a method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Figures 12 to 19 Can correspond to along Figure 2 line AA or Figure 11 The following is a cross-sectional view taken along line BB. For ease of explanation, the following will be based on... Figure 2 Example description of a cross-section diagram taken from line AA.

[0118] Reference Figure 12 An initial substrate 300 may be provided, which includes an initial cell region PMCA and an initial interconnect region PINT disposed on one side of the initial cell region PMCA. An initial insulating layer 310, a first mask layer HM1, a second mask layer HM2, and a photoresist layer PR may be formed on the initial substrate 300.

[0119] The initial insulating layer 310 may be, for example, silicon nitride. The first mask layer HM1 may include a spin-on hard mask (SOH) pattern. The second mask layer HM2 may be, for example, silicon nitride. However, the scope of this disclosure is not limited thereto. The materials of the initial insulating layer 310, the first mask layer HM1, and the second mask layer HM2 are not limited thereto and may vary.

[0120] Reference Figure 13 and Figure 14 By patterning the initial connection region PINT, cell isolation trenches ST can be formed in the initial connection region PINT. Subsequently, a first initial insulating film 210P, a second initial insulating film 220P, and a third initial insulating film 230P can be sequentially formed on the inner wall TW of the cell isolation trench ST and on the upper surface of the initial insulating layer 310 of the initial cell region PMCA. In an embodiment, the third initial insulating film 230P can be formed such that the vertical horizontality of its upper surface remains constant in the initial cell region PMCA and the initial connection region PINT.

[0121] Reference Figure 15 The third initial insulating film 230P can be polished. For example, the third initial insulating film 230P can be polished downwards to the upper surface of the second initial insulating film 220P. Therefore, the second initial insulating film 220P can be exposed in the initial cell region PMCA, and the upper surface of the third initial insulating film 230P in the initial connection region PINT can be coplanar with the upper surface of the second initial insulating film 220P in the initial cell region PMCA. In some embodiments, the third initial insulating film 230P can be polished using a CMP process.

[0122] Reference Figure 16 The second initial insulating film 220P can be polished. For example, the second initial insulating film 220P can be polished down to the upper surface of the first initial insulating film 210P. Therefore, the first initial insulating film 210P can be exposed in the initial cell region PMCA, and the upper surfaces of each of the second initial insulating film 220P and the third initial insulating film 230P in the initial connection region PINT can be coplanar with the upper surface of the first initial insulating film 210P in the initial cell region PMCA. In some embodiments, the second initial insulating film 220P can be polished using a CMP process.

[0123] Reference Figure 17Multiple word lines can be formed in the initial substrate 300. For example, after patterning the initial substrate 300, an initial gate insulating film 132 can be formed in the patterned recesses, and then initial word lines WL_P spaced apart from adjacent initial word lines WL_P can be formed. An initial gate isolation layer can be formed between the spaced-apart initial word lines WL_P in the recesses.

[0124] Multiple back gate electrodes can be formed in the initial substrate 300. For example, after patterning the initial substrate 300, an initial back gate insulating film 182 can be formed in the patterned recesses, and then an initial back gate electrode BG_P can be formed on the initial back gate insulating film 182. Subsequently, a back gate isolation layer 170 can be formed on the initial back gate electrode BG_P.

[0125] Multiple active patterns can be formed in the initial substrate 300. The region between the recess for forming word lines and the recess for forming back gate electrodes in the initial substrate 300 can be defined as the initial active pattern AP_P.

[0126] Subsequently, an initial insulating layer 310 can be formed as a contact interlayer insulating layer 190, and a landing pad LP can be formed. A capacitor structure CAP including a first electrode 312, a dielectric film 314, a conductive film 316, and a second electrode 318 can be formed. Furthermore, the contact interlayer insulating layer 190 and an upper interlayer insulating layer 330 covering the capacitor structure CAP (e.g., the second electrode 318) can be formed.

[0127] Reference Figure 18 After flipping the initial substrate 300 so that its lower surface faces upward, the lower surface of the initial substrate 300 can be polished. For example, the initial substrate 300 can be polished downward to the lower surface BS1 of the first initial insulating film 210P in the initial cell region PMCA and the initial connection region PINT. In some embodiments, the initial substrate 300 can be polished using a CMP process.

[0128] Reference Figure 19 The first initial insulating film 210P can be polished downwards to the lower surface BS2 of the second initial insulating film 220P in the initial connection region PINT. In some embodiments, the first initial insulating film 210P can be polished using a CMP process. In this process, the initial word line WL_P, the initial back gate electrode BG_P, the initial active pattern AP_P, etc., can be polished together.

[0129] Subsequently, by further patterning the initial word line WL_P and the initial back gate electrode BG_P, and by forming the gate capping layer 140 and the back gate capping layer 160, multiple word lines WL, multiple back gate electrodes BG, and multiple active patterns AP can be formed.

[0130] Then, bit lines BL can be formed connecting multiple active pattern APs, wherein the multiple active pattern APs are electrically connected to landing pads LP, and the landing pads LP are electrically connected to capacitor structures CAP. This process can provide a reference. Figures 1 to 11 The semiconductor memory device described.

[0131] Figure 20 This is a flowchart describing a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0132] A method 2000 for manufacturing a semiconductor memory device may begin by preparing an initial substrate including an initial cell region and an initial connection region disposed on one side of the initial cell region (S2010). Cell isolation trenches may be formed in the initial connection region (S2020). A first initial insulating film, a second initial insulating film, and a third initial insulating film may be sequentially formed on the inner wall of the cell isolation trench and on the upper surface of the initial substrate of the initial cell region (S2030).

[0133] Multiple word lines can be formed in the initial cell area, the multiple word lines being spaced apart from adjacent word lines in a first direction and each of the multiple word lines extending in a second direction intersecting the first direction (S2040). Multiple active patterns can be formed on one side of each of the multiple word lines arranged in the initial cell area (S2050). After forming the active patterns, landing pads connected to the active patterns can be formed, and capacitor structures (CAPs) connected to the landing pads can be formed.

[0134] The initial substrate in the initial cell region and the initial connection region can be polished downwards to the lower surface of the first initial insulating film (S2060). Then, by polishing the first initial insulating film downwards in the initial connection region to the lower surface of the second initial insulating film (S2070), a cell isolation insulating film can be formed, which includes a first insulating film, a second insulating film, and a third insulating film arranged sequentially on the inner wall of the cell isolation trench.

[0135] For example, a cell isolation insulating film can be formed, comprising: a first insulating film disposed on the inner wall of a cell isolation trench; a second insulating film comprising a first portion disposed on a side surface of the first insulating film and a second portion extending from an end of the first portion in a direction parallel to the surface of the initial substrate (e.g., a first direction and a second direction); and a third insulating film disposed on the first portion and the second portion.

[0136] In some embodiments, the first insulating film and the second insulating film may be formed such that the first width of the first insulating film in the first direction, the second width of the first portion in the first direction, and the third width of the second portion in the third direction intersecting with each of the first and second directions are the same as each other.

[0137] In some embodiments, the first insulating film and the second insulating film may be formed such that a first width of the first insulating film in a first direction is greater than a second width of the first portion in the first direction and a third width of the second portion in a third direction.

[0138] In some embodiments, the first insulating film and the second insulating film may be formed such that a first width of the first insulating film in a first direction is smaller than a second width of the first portion in the first direction and a third width of the second portion in a third direction.

[0139] A bit line can be formed that contacts the lower surface of the active pattern and the lower surface of the second insulating film and extends in a first direction.

[0140] Although the invention has been described herein with reference to embodiments and accompanying drawings, the invention is not limited thereto, and various modifications and variations can be made by those skilled in the art within the spirit of the invention and the equivalents of the claims described herein.

[0141] Furthermore, the exemplary embodiments are not exclusive. For example, some exemplary embodiments may include features mentioned in one or more of the figures, and may additionally include one or more other features mentioned in other figures.

Claims

1. A semiconductor memory device, comprising: A substrate comprising a cell region and a connection region on one side of the cell region; Bit lines, which are on the substrate and extend across the cell region and the connection region in a first direction; A word line that extends above the bit line on the cell area and in a second direction intersecting the first direction; A first active pattern is located on one side surface of the word line in the cell area; as well as A cell isolation layer on the bit line of the connection region. The first active pattern is the outermost active pattern arranged at the outermost position of the cell region in the first direction. The unit area isolation layer includes: A first insulating film having a first side surface on the outer surface of the outermost active pattern and extending in the second direction; and The second insulating film comprises: The first part, which is on the second side surface of the first insulating film, wherein the first side surface of the first insulating film is opposite to the second side surface of the first insulating film, and The second portion extends from the first end of the first portion along the first direction at the second side surface of the first insulating film, wherein the second portion contacts the bit line on the upper surface of the third direction on the third direction, the third direction intersecting each of the first direction and the second direction.

2. The semiconductor memory device according to claim 1, wherein, The first insulating film and the second insulating film comprise different materials.

3. The semiconductor memory device according to claim 1, wherein, The unit area isolation layer further includes a third insulating film, which is located on the first portion of the second insulating film and on the second portion of the second insulating film.

4. The semiconductor memory device according to claim 3, wherein, The second portion of the second insulating film is located between the third insulating film and the bit line in the third direction.

5. The semiconductor memory device according to claim 3, wherein, The first portion of the second insulating film is located between the first insulating film and the third insulating film in the first direction.

6. The semiconductor memory device according to claim 1, wherein, The lower surface of the first active pattern is coplanar with the lower surface of the second insulating film.

7. The semiconductor memory device of claim 1, further comprising a gate capping layer between the word line and the bit line, wherein, The lower surface of the gate capping layer is coplanar with the lower surface of the second insulating film.

8. The semiconductor memory device according to claim 1, wherein, The first width of the first insulating film in the first direction, the second width of the first portion of the second insulating film in the first direction, and the third width of the second portion of the second insulating film in the third direction are the same as each other.

9. The semiconductor memory device according to claim 1, wherein, The first width of the first insulating film in the first direction is greater than each of the second width of the first portion of the second insulating film in the first direction and the third width of the second portion of the second insulating film in the third direction.

10. The semiconductor memory device according to claim 1, wherein, The first width of the first insulating film in the first direction is less than each of the second width of the first portion of the second insulating film in the first direction and the third width of the second portion of the second insulating film in the third direction.

11. The semiconductor memory device according to claim 1, wherein, The distance from the upper surface of the first active pattern to the lower surface of the first active pattern is the same as the distance from the upper surface of the first insulating film to the lower surface of the first insulating film.

12. The semiconductor memory device according to claim 1, wherein, The distance from the upper surface of the first active pattern to the lower surface of the first active pattern is the same as the distance from the upper surface of the first portion of the second insulating film to the lower surface of the first portion of the second insulating film.

13. The semiconductor memory device of claim 1, further comprising a second active pattern and a third active pattern, the second active pattern and the third active pattern being spaced apart from each other in the first direction such that the second active pattern and the third active pattern face each other. in, The semiconductor memory device further includes: A back gate electrode, which is located between the second active pattern and the third active pattern in the first direction; A back gate capping layer, which is located on the lower surface of the back gate electrode in the third direction; and A back gate isolation layer is located on the upper surface of the back gate electrode in the third direction.

14. The semiconductor memory device according to claim 13, wherein, The lower surface of the back grid cover layer is coplanar with the lower surface of the second insulating film.

15. The semiconductor memory device according to claim 13, wherein, The distance from the upper surface of the back gate isolation layer to the lower surface of the back gate capping layer is the same as the distance from the upper surface of the first insulating film to the lower surface of the first insulating film.

16. A semiconductor memory device, comprising: A substrate comprising a cell region and a connection region on one side of the cell region; Bit lines, which are on the substrate and extend across the cell region and the connection region in a first direction; Multiple word lines are provided on the bit line in the unit area. Each of the multiple word lines is spaced apart from adjacent word lines in the first direction. The multiple word lines include a first word line and a second word line, and the first word line and the second word line each extend in a second direction intersecting the first direction. Multiple active patterns are provided on the unit area, including a first active pattern on a first side surface of the first word line and a second active pattern on a second side surface of the second word line opposite to the first side surface of the second word line. as well as A cell isolation layer on the bit line of the connection region. The unit area isolation layer includes a first insulating film and a second insulating film, which are sequentially located on the outer surface of a third active pattern. The third active pattern is the outermost active pattern among the plurality of active patterns. The outermost active pattern defines the boundary between the unit area and the connection area on its outer surface in the first direction. The lower surface of the second insulating film contacts the upper surface of the bit line in a third direction, which intersects each of the first and second directions.

17. The semiconductor memory device of claim 16, further comprising: A gate capping layer that extends along the first direction on the lower surface of each of the first word line and the second word line; as well as A gate isolation layer is located between the first word line and the second word line. The gate isolation layer includes: The vertical portion extends upward along the second side surface of the first character line and the first side surface of the second character line on the third side; and The horizontal portion connects to the end of the vertical portion and extends along the first direction on the upper surface of each of the first and second letter lines.

18. The semiconductor memory device according to claim 17, wherein, The distance from the upper surface of the horizontal portion of the gate isolation layer to the lower surface of the gate capping layer is the same as the distance from the upper surface of the second insulating film to the lower surface of the second insulating film.

19. The semiconductor memory device of claim 16, wherein, The distance from the upper surface of the third active pattern to the lower surface of the third active pattern is the same as the distance from the upper surface of the second insulating film to the lower surface of the second insulating film.

20. A semiconductor memory device, comprising: A substrate comprising a cell region and a connection region on one side of the cell region; Bit lines, which are on the substrate and extend across the cell region and the connection region in a first direction; Multiple word lines are provided on the bit line in the unit area. Each of the multiple word lines is spaced apart from adjacent word lines in the first direction. The multiple word lines include a first word line and a second word line, and the first word line and the second word line each extend in a second direction intersecting the first direction. A plurality of active patterns are provided on the unit region, the plurality of active patterns including a first active pattern on a first side surface of the first word line and a second active pattern on a second side surface of the second word line opposite to the first side surface of the second word line; and A cell isolation layer on the bit line of the connection region. The unit area isolation layer includes a first insulating film, a second insulating film, and a third insulating film. The first insulating film, the second insulating film, and the third insulating film are sequentially located on the outer surface of a third active pattern. The third active pattern is the outermost active pattern among the plurality of active patterns. The outermost active pattern defines the boundary between the unit area and the connection area on its outer surface in the first direction. The first insulating film and the second insulating film are made of different materials. The first insulating film and the third insulating film are made of the same material. Wherein, the lower surfaces of the first insulating film and the lower surfaces of the second insulating film contact the upper surface of the bit line, and The second insulating film includes a portion located between the third insulating film and the bit line.

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