Integrated circuit structure with nanoribbon transistors and backside capacitor

Abstract

Disclosed herein are integrated circuit structures having nanoribbon transistors and backside capacitors, and related methods and apparatus. In one aspect, an IC structure includes a nanoribbon including a semiconductor material and a transistor including a channel portion and first and second source / drain (S / D) regions, where the channel portion includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side, and the first and second S / D regions are located at opposite ends of the channel portion. The IC structure also includes a contact structure in conductive contact with the first S / D region and a capacitor in conductive contact with the second S / D region, where the contact structure is located at the front side of the channel portion and the capacitor is located at the back side of the channel portion.

Description

Background Technology

[0001] Embedded memory is crucial to the performance of modern System-on-Chip (SoC) technology. Low-power and high-density embedded memory is used in many different computer products, and further improvements are always expected. Attached Figure Description

[0002] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. In the various figures of the drawings, embodiments are shown by way of example rather than limitation.

[0003] Figure 1 A perspective view of an exemplary integrated circuit (IC) structure having nanoribbon transistors according to some embodiments is provided.

[0004] Figure 2 This is a flowchart of an exemplary method for manufacturing an IC structure having nanoribbon transistors and a back-side capacitor according to some embodiments.

[0005] Figure 3A , Figure 3B and Figure 3C This illustrates, according to some embodiments, in Figure 2 Cross-sectional side view of an exemplary IC structure following various processes of the methods described.

[0006] Figure 3D This is a cross-sectional top view illustrating an exemplary shape of a via for a back-side capacitor in an IC structure having nanoribbon transistors and a back-side capacitor, according to some embodiments.

[0007] Figure 4 A top view is shown of a wafer and die that may include one or more IC structures having nanoribbon transistors and back-side capacitors according to some embodiments.

[0008] Figure 5 This is a side cross-sectional view of an IC device that may include one or more IC structures having nanoribbon transistors and back-side capacitors, according to some embodiments.

[0009] Figure 6 This is a side cross-sectional view of an IC package that may include one or more IC structures having nanoribbon transistors and back-side capacitors, according to some embodiments.

[0010] Figure 7 A cross-sectional side view of an IC device assembly, which may include one or more IC structures having nanoribbon transistors and back-side capacitors, is shown according to some embodiments.

[0011] Figure 8This is a block diagram of an exemplary computing device that may include one or more IC structures having nanoribbon transistors and back-side capacitors, according to some embodiments.

[0012] Figure 9 This is a block diagram of an exemplary processing device that may include one or more IC structures having nanoribbon transistors and back-side capacitors, according to some embodiments. Detailed Implementation

[0013] This document discloses an IC structure with nanoribbon transistors and a back-side capacitor, as well as related methods and apparatus. The systems, methods, and apparatuses disclosed herein each have several innovative aspects, wherein no single aspect individually determines all the desired properties disclosed herein. Details of one or more embodiments of the subject matter described herein are set forth in the following description and accompanying drawings.

[0014] For the purpose of illustrating the IC structure with nanoribbon transistors and back-side capacitors presented herein, it may be helpful to first understand the phenomena that may play a role in IC fabrication. The following basic information can be considered as the basis for a proper interpretation of this disclosure. Such information is provided for illustrative purposes only and therefore should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0015] Some memory devices can be considered "standalone" devices because they are contained within a chip that does not contain computational logic (wherein, as used herein, the term "computational logic device" or simply "computational logic" or "logic device" refers to a device for performing computational / processing operations, such as a transistor). Other memory devices can be contained within a chip along with computational logic and can be referred to as "embedded" memory devices. Using embedded memory to support computational logic can improve performance by bringing the memory and computational logic closer to each other and eliminating interfaces that increase latency. Various embodiments of this disclosure relate to embedded memory arrays and corresponding methods and apparatus.

[0016] Some embodiments of this disclosure may relate to dynamic random access memory (DRAM), particularly embedded DRAM (eDRAM), as this type of memory has been introduced in the past to address density and standby power limitations of some other types of memory devices. A DRAM memory cell may include: a capacitor for storing the bit value or memory state of the cell (e.g., logic "1" or "0"), and an access transistor for controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell," highlighting the fact that it uses one transistor (i.e., "1T" in the term "1T-1C memory cell") and one capacitor (i.e., "1C" in the term "1T-1C memory cell"). The access transistor of a 1T-1C memory cell may be a field-effect transistor (FET) having a source terminal, a drain terminal, and a gate terminal, such as a metal-oxide-semiconductor FET (MOSFET). An FET typically includes a semiconductor channel material, source and drain regions disposed in the channel material, and a gate comprising at least a gate electrode material and optionally also a gate insulator. In such a transistor, the gate is disposed on a portion of the channel material between the source and drain regions. The term "source terminal" typically refers to the source region or its contact with the source region, the term "drain terminal" typically refers to the drain region or its contact with the drain region, and the term "gate terminal" typically refers to the gate or its contact with the gate. Since the designations of "source" and "drain" are often interchangeable in the FET field, the source and drain regions / contacts / terminals of a transistor can be referred to as first and second source or drain (S / D) regions / contacts / terminals. In some embodiments, the first S / D region / contact / terminal is the source region / contact / terminal, and the second S / D region / contact / terminal is the drain region / contact / terminal; in other embodiments, this designation of source and drain can be interchanged. The capacitor of a 1T-1C memory cell can be coupled to one S / D terminal of the access transistor (e.g., coupled to the source terminal of the access transistor), while the other S / D terminal of the access transistor can be coupled to the bit line (BL), and the gate terminal of the transistor can be coupled to the word line (WL). Because such a memory cell can be fabricated with only a single access transistor, it can offer higher density and lower standby power compared to some other types of memory in the same process technology, such as static random access memory (SRAM).

[0017] Recently, FETs with non-planar architectures (such as nanoribbon transistors, sometimes also called "gate-all-around (GAA) transistors") have been extensively studied as an alternative to transistors with planar architectures. In a nanoribbon transistor, a gate stack can be provided around a portion of an elongated semiconductor structure called a "nanoribbon," thereby forming the gate on all sides of the nanoribbon. The "channel" or "channel portion" of a nanoribbon transistor is the portion of the nanoribbon surrounded by the gate stack. Such transistors are sometimes called "GAA transistors" because, in use, such transistors can form conductive channels on all "sides" of the channel portion of the nanoribbon. Source and drain regions are disposed in the nanoribbon located on either side of the gate stack, thereby forming the source and drain of the nanoribbon transistor, respectively. In some configurations, the terms "nanoribbon" or "nanosheet" have been used to describe elongated semiconductor structures having a substantially rectangular cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe similar structures, but with a substantially circular or square cross-section. In this disclosure, the term "nanoribbon" is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as elongated semiconductor structures having a cross-section with any geometry (e.g., an elliptical or polygonal cross-section with rounded corners) parallel to the longitudinal axis of the substrate. A transistor can be described as a "nanoribbon transistor" if the channel of a transistor is part of a nanoribbon (i.e., the portion around which the gate stack of the transistor may surround). The semiconductor material in the portion of the nanoribbon that forms the channel of the transistor can be referred to as the "channel material," wherein the S / D regions of the transistor are disposed on both sides of the channel material. In some embodiments, a nanoribbon transistor may include a nanoribbon stack comprising two or more nanoribbons stacked one on top of the other, wherein a single gate stack comprises a gate electrode material (which may include a work function material) that provides the entire stack.

[0018] The embodiments of this disclosure are based on the understanding that nanoribbon transistors can be used to implement access transistors for memory cells. The embodiments of this disclosure are also based on the understanding that implementing a capacitor for a memory cell on the back side of a substrate having a nanoribbon transistor may be particularly advantageous because, in this way, the process for manufacturing the capacitor will not interfere with the front-side processing and cause yield problems. In one aspect, an IC structure includes a nanoribbon and a transistor, the nanoribbon comprising a semiconductor material, the transistor including a channel portion and first and second source / drain (S / D) regions, wherein the channel portion includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side, and the first and second S / D regions are located at opposite ends of the channel portion. The IC structure also includes a contact structure electrically contacting the first S / D region and a capacitor electrically contacting the second S / D region, wherein the contact structure is located on the front side of the channel portion and the capacitor is located on the back side of the channel portion.

[0019] An IC structure having nanoribbon transistors and back-side capacitors can be included in one or more components associated with the IC and / or included among various such components. In various embodiments, components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with the IC can include components mounted on the IC or connected to the IC. The IC can be analog or digital and can be used in a wide range of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, the IC structure as described herein can be included in a radio frequency (RF) IC (RFIC), which can be included, for example, in any component associated with an IC of an RF receiver, RF transmitter, or RF transceiver (e.g., an RF receiver, RF transmitter, or RF transceiver used in a telecommunications device within a base station (BS) or user equipment (UE). Such components can include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including RF filter arrays or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structure described herein may be included in a memory device or circuitry. In some embodiments, the IC structure described herein may be used as part of a chipset to perform one or more related functions in a computer.

[0020] For illustrative purposes, specific quantities, materials, and configurations have been set forth to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that this disclosure may be practiced without these specific details, and / or may be practiced using only some of the aspects described. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrative embodiments.

[0021] In the following detailed description, various aspects of the illustrative embodiments will be described using terminology commonly used by those skilled in the art to convey the essence of the work to others skilled in the art. For example, in the context of an S / D contact of a transistor, the term "contact" may be used interchangeably with the term "terminal" of a transistor. In another example, as used herein, the term "connection" refers to a direct electrical or magnetic connection between connected things without any intermediate means, while the term "coupling" refers either to a direct electrical or magnetic connection between connected things or to an indirect connection via one or more passive or active intermediate means. The term "circuit" refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. When used, the terms "oxide," "carbide," "nitride," "sulfide," etc., refer to compounds containing oxygen, carbon, nitrogen, sulfur, etc., respectively; the term "high-k dielectric" refers to a material with a dielectric constant (k) higher than that of silicon oxide; and the term "low-k dielectric" refers to a material with a k value lower than that of silicon oxide. The terms “substantially,” “close to,” “approximately,” “nearly,” and “about” generally refer to a difference of + / -20% from a target value, for example, within + / -5% or + / -2%, depending on the context of the specific value as described herein or as known in the art. Similarly, terms indicating the orientation of various elements (e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements) generally refer to a difference of + / -20% from a target value, for example, within + / -5% or + / -2%, depending on the context of the specific value as described herein or as known in the art.

[0022] As used herein, the terms “above,” “below,” “between,” and “above” refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with both layers or may have one or more intermediate layers. Conversely, a first layer “above” a second layer is in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intermediate layers.

[0023] For the purposes of this disclosure, the phrases “A” and / or “B” represent (A), (B), or (A and B). For the purposes of this disclosure, the phrases “A, B, and / or C” represent (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When the term “between” is used with respect to a measurement range, the term “between” includes the endpoints of the measurement range. As used herein, the symbol “A / B / C” represents (A), (B), and / or (C).

[0024] Although certain elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials. Unless otherwise stated, the term "insulating" and its variations (e.g., "insulating" or "insulator") means "electrically insulating," and the term "conductive" and its variations (e.g., "conductive" or "conductor") means "electrically conductive." For example, the term "insulating material" may refer to a solid material (and / or a liquid material that solidifies after the treatments described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glasses, silicon, and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. For optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conductive / conductive" may also mean "optically conductive / conductive."

[0025] This specification may use the phrases "in embodiments" or "in multiple embodiments," each of which may refer to one or more embodiments in the same or different embodiments. Furthermore, as used with respect to embodiments of this disclosure, the terms "comprising," "including," "having," etc., are synonymous. This disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are for ease of discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise stated, the use of ordinal adjectives such as "first," "second," and "third" to describe common objects merely indicates different instances of similar objects being referenced and is not intended to imply that the objects so described must be in a given sequence in time, space, order, or any other way.

[0026] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, and embodiments that can be practiced are shown by way of example in the drawings. It should be understood that other embodiments may be adopted and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be interpreted in a limiting sense. In order not to confuse the drawings, if multiple instances of certain elements are shown, only some elements may be labeled with reference numerals. Multiple figures having the same numerals but different letters may be referred to without using letters.

[0027] In the accompanying drawings, some schematic diagrams of exemplary structures of the various devices and components described herein may be shown with precise right angles and straight lines. However, it should be understood that such schematic diagrams may not reflect actual process constraints, which may cause features to appear less “ideal” when examined using, for example, scanning electron microscopy (SEM) or transmission electron microscopy (TEM) images. Possible processing defects may also be visible in such images of actual structures, such as imperfectly straight edges of the material, tapered vias or other openings, unintended rounding of corners or variations in the thickness of different material layers, sporadic spiral dislocations within crystal regions, edge dislocations or combined dislocations, and / or sporadic dislocation defects of individual atoms or clusters of atoms. Other defects not listed herein but common in the field of device fabrication may also exist. Examining layout and mask data using, for example, optical microscopy, TEM, or SEM, and reverse engineering portions of the device for circuit reconstruction, and / or using, for example, physical fault analysis (PFA) to examine cross-sections of the device to detect the shape and location of the various device elements described herein, will allow the determination of the presence of an IC structure with nanoribbon transistors and back-side capacitors.

[0028] Figure 1 A perspective view of an exemplary IC structure 100 implementing a nanoribbon transistor 110 according to some embodiments is provided. Figure 1 It is a perspective view, and... Figure 1 An exemplary coordinate system 105 (xyz coordinate system) is shown to aid in explanation. Other figures showing various axes (e.g., ...) are also provided. Figures 3A-3D () refers to the axis of coordinate system 105.

[0029] Go to Figure 1 In detail, the IC structure 100 may include a semiconductor material, which may include one or more semiconductor materials, formed as a nanoribbon 104 extending substantially parallel to the substrate 102 (i.e., an elongated semiconductor structure). This can be achieved by providing a gate stack 112 that at least partially surrounds a portion referred to as a "channel portion" of the nanoribbon and by providing an S / D region (in...) on either side of the gate stack 112. Figure 1The transistor 110 is formed based on the nanoribbon 104, as shown in the diagram as a first S / D region 114 and a second S / D region 116. Figure 1 A first S / D contact 124 and a dummy second S / D contact 126' are also shown. The first S / D contact 124 can make conductive contact with the first S / D region 114 (i.e., electrically connected, for example, directly electrically connected). The dummy second S / D contact 126' is in... Figure 1 The object shown in the middle is indicated by a dashed line to indicate that it is a non-functional contact for the S / D region 116 (hence it is referred to as a "dummy" contact), because the actual functional contacts for the S / D region 116 are provided from the back side of the S / D region 116 via the back-side capacitor 382, ​​as shown in the reference. Figures 3A-3D As described above. For ease of manufacturing, in some embodiments, the dummy second S / D contact 126' may still be located on the same side as the first S / D contact 124, such as... Figure 1 As shown. In other embodiments, the dummy second S / D contact 126' may not be present in the IC structure 100. In some embodiments, an oxide material layer 130 may be provided between the substrate 102 and the gate stack 112 / nanoribbon 104; in other embodiments, the oxide material 130 may not be present in the IC structure 100. Although Figure 1 Only a single nanoribbon 104 is shown, but in some embodiments, the IC structure 100 may include a stack of nanoribbons 104, wherein the nanoribbons 104 are stacked perpendicularly to each other, as is known in the art. In such an embodiment, a gate stack 112 may at least partially surround portions of a plurality (e.g., all) of the nanoribbons 104 of the stack, and each of the first S / D region 114 and the second S / D region 116 may extend continuously through the entire stack to form a single transistor 110, wherein the channel portion is in the plurality of nanoribbons 104 of the stack. Figures 3A-3D An exemplary embodiment of a transistor including a nanoribbon stack is shown in the figure.

[0030] Figure 1 The IC structure 100 shown and the other accompanying drawings of this disclosure are intended to illustrate the relative arrangement of some of its components, and the IC structure / device or portions thereof shown herein may include other components not shown. For example, Figure 1 Additional layers, such as the spacer layer around the gate stack 112 of transistor 110, are not shown. In another example, although... Figure 1Not specifically shown, but dielectric spacers may be provided between the first S / D contact 124 and the gate stack 112, and optionally between the dummy second S / D contact 126' and the gate stack 112, to provide electrical isolation between the source contact, gate contact, and drain contact (such dielectric spacers in...). Figure 1 Not shown in the figure to avoid confusing the accompanying drawings, but in... Figures 3A-3D (Seen as gate spacer 348). Generally, the "contact" referred to herein may also be called an "electrode". In yet another example, although in Figure 1 Not specifically shown, but at least a portion of transistor 110 may be surrounded by an insulating material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulating material may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers (e.g., perfluorocyclobutane or polytetrafluoroethylene), fused silica glass (FSG), and organosilicones (e.g., silsesquioxanes, siloxanes, or organosilicon glasses). In other embodiments, the insulating material surrounding a portion of transistor 110 may be a high-k dielectric, including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for this purpose may include, but are not limited to, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0031] Embodiments of this disclosure can be formed or performed on any suitable substrate 102 (e.g., substrate, die, wafer, or chip). Substrate 102 can be, for example, the type discussed below. Figure 4 The wafer 2000 in the context can be a die or included within a die, such as those discussed below. Figure 4The diced die 2002 is shown in the image. The substrate 102 can be a semiconductor substrate composed of a semiconductor material system including, for example, N-type or P-type material systems. In one embodiment, the semiconductor substrate can be a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In other embodiments, alternative materials that may or may not be combined with silicon can be used to form the semiconductor substrate, including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic table), group II-VI materials (i.e., materials from groups II and IV of the periodic table), or group IV materials (i.e., materials from group IV of the periodic table). In some embodiments, the substrate can be amorphous. In some embodiments, the substrate 102 can be a printed circuit board (PCB) substrate. Although several examples of materials that can form substrate 102 are described herein, any material that can be used as the basis for building IC structures with nanoribbon transistors and back-side capacitors as described herein falls within the spirit and scope of this disclosure.

[0032] For example, nanoribbon 104 may take the form of nanowires or nanoribbons. In some embodiments, the area of ​​the cross-section of nanoribbon 104 (i.e., the area in the yz plane of coordinate system 105) may be between about 25 square nanometers and 10,000 square nanometers, including all values ​​and ranges therein (e.g., between about 25 square nanometers and 1,000 square nanometers, or between about 25 square nanometers and 500 square nanometers). The cross-section of nanoribbon 104 is a cross-section along a plane perpendicular to the longitudinal axis 120 of nanoribbon 104, wherein the longitudinal axis 120 may, for example, be along the x-axis of coordinate system 105, and Figure 1 The nanoribbon 104 is shown in dashed lines. In some embodiments, the width of the nanoribbon 104 (i.e., the dimension measured in a plane parallel to the substrate 102 and in a direction perpendicular to the longitudinal axis 120 (e.g., along the y-axis of coordinate system 105) may be at least about 3 times larger than the thickness (or “height”) of the nanoribbon 104 (i.e., the dimension measured in a plane perpendicular to the substrate 102 (e.g., along the z-axis of coordinate system 105) (inclusive of all values ​​and ranges therein), for example, at least about 4 times larger, or at least about 5 times larger.

[0033] although Figure 1The nanoribbon 104 shown is illustrated as having a square cross-section, or more generally a rectangular cross-section, but the nanoribbon 104 may alternatively have a cross-section that is rounded at the corners or otherwise irregularly shaped, and the gate stack 112 may conform to the shape of the nanoribbon 104. The terms “front side” and “back side” for nanoribbon may refer to the surface / face of the semiconductor material of the nanoribbon 104 that is substantially parallel to the substrate 102, the term “sidewall” (or “side” or simply “side”) for nanoribbon may refer to the opposite face of the nanoribbon 104 that is substantially perpendicular to the substrate 102 and extends in a direction that is substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104, and the term “end” for nanoribbon may refer to the opposite face of the nanoribbon 104 that is substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104.

[0034] The nanoribbon 104 may be formed of one or more semiconductor materials (collectively referred to as "channel materials"). Typically, the channel material of transistor 110 may consist of a semiconductor material system including, for example, an N-type or P-type material system. In some embodiments, the nanoribbon 104 may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a single-crystal semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb).

[0035] For some exemplary N-type transistor embodiments (i.e., embodiments where transistor 110 is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of nanoribbon 104 may include a III-V material with relatively high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In... x Ga 1-x As in the finned embodiment, the In content (x) can be between 0.6 and 0.9, and can advantageously be at least 0.7 (e.g., In 0.5%). 0.7 Ga 0.3As). For some exemplary P-type transistor embodiments (i.e., for the embodiment where transistor 110 is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of nanoribbon 104 may advantageously be a group IV material with high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the channel material of nanoribbon 104 may have a Ge content between 0.6 and 0.9, and may advantageously be at least 0.7.

[0036] In some embodiments, the channel material of the nanoribbon 104 can be a thin film material, such as a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, if the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 nanometers and 75 nanometers (inclusive of all values ​​and ranges therein). In some embodiments, thin-film channel material can be deposited at relatively low temperatures, which allows the channel material to be deposited within the thermal budget applied to the back-end manufacturing process to avoid damaging other components, such as front-end components of logic devices.

[0037] As described above, channel materials can include IGZO. IGZO-based devices possess several desirable electrical and fabrication characteristics. Compared to other semiconductors, IGZO exhibits high electron mobility, for example, in the range of 20-50 times that of amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high bandgap, low-temperature process compatibility, and low manufacturing costs compared to other semiconductors. IGZO can be deposited as a uniform amorphous phase while maintaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include varying ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another exemplary form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO can have a gallium-indium ratio of 1:1, a gallium-indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium-indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain a third dopant, such as aluminum or nitrogen.

[0038] As described above, in some embodiments, transistor 110 may be a TFT. A TFT is a special type of FET fabricated by depositing an active semiconductor material on a substrate (e.g., substrate 102 as described above), which may be a non-conductive substrate. Some such materials can be deposited at relatively low temperatures, which allows these materials to be deposited within the thermal budget imposed on back-end manufacturing to avoid damaging front-end components (e.g., logic devices of IC devices, which may include transistors). Therefore, in some embodiments, the channel material of transistor 110 may be a semiconductor material deposited at relatively low temperatures and may include any thin-film material, such as the high-mobility oxide semiconductor material described above.

[0039] In other embodiments, the channel material of transistor 110 may be epitaxially grown in a manner that typically involves relatively high-temperature processing, rather than being deposited at relatively low temperatures as described above for TFTs. In such embodiments, the channel material may include any of the semiconductor materials described above, including oxide semiconductor materials. In some such embodiments, the channel material may be epitaxially grown directly on a semiconductor layer of a substrate in a process called “monolithic integration,” on which the transistor will be fabricated. In other such embodiments, the channel material of transistor 110 may be epitaxially grown on a semiconductor layer of another substrate, and then the epitaxially grown layer of the channel material may be transferred in a process called “layer transfer” to the substrate on which the transistor will be disposed (e.g., substrate 102), in which case the latter substrate may not necessarily include a semiconductor layer prior to the layer transfer. Layer transfer advantageously allows the formation of non-planar transistors (e.g., in the back end of an IC device), such as nanoribbon transistors, on a substrate or in a layer that does not contain semiconductor material. Layer transfer also advantageously allows the formation of transistors of any architecture (e.g., non-planar or planar transistors) without negatively impacting the relatively high-temperature epitaxial growth process on devices that may already exist on the substrate.

[0040] Channel materials deposited at relatively low temperatures are typically polycrystalline, polymorphic, or amorphous semiconductors, or any combination thereof. Epitaxially grown channel materials are typically highly crystalline (e.g., monocrystalline or single-crystal) materials. Therefore, the channel material of transistor 110 can be identified as either deposited or epitaxially grown at a relatively low temperature by examining the grain size of the active portion of the channel material (e.g., the portion of the channel material that forms the channel of the transistor). An average grain size of the channel material of transistor 110 between about 0.5 mm and 1 mm (in which case the material may be polycrystalline) or less than about 0.5 mm (in which case the material may be polymorphic or amorphous) indicates that the channel material was deposited (e.g., in which case the transistor including such a channel material is a TFT). On the other hand, an average grain size of the channel material of transistor 110 equal to or greater than about 1 mm (in which case the material may be single-crystal) indicates that the channel material was grown epitaxially via monolithic integration or layer transfer and included in the final device.

[0041] In some embodiments, the channel material of transistor 110 may comprise a two-dimensional (2D) semiconductor material, i.e., a semiconductor material having a thickness of a few nanometers or less, wherein electrons in the material move freely in a 2D plane, but their restricted movement in a third direction is controlled by quantum mechanics. In some such embodiments, such a channel material may comprise a single atom monolayer of 2D semiconductor material, while in other such embodiments, such a channel material may comprise five or more atom monolayers of 2D semiconductor material. Examples of 2D materials that may be used to implement the channel material of any transistor described herein include, but are not limited to, graphene, hexagonal boron nitride, or transition metal chalcogenides.

[0042] like Figure 1 As shown, a gate stack 112, including gate electrode material 108 and optional gate insulator 106, can completely or almost completely surround a portion of the nanoribbon 104, wherein the channel portion of the transistor 110 is the active region (channel region) of the channel material, which is located in the portion of the nanoribbon 104 surrounded by the gate stack 112. Figure 1 As shown, the gate insulator 106 may surround the lateral portion / section of the nanoribbon 104, and the gate electrode material 108 may surround the gate insulator 106.

[0043] The gate electrode material 108 may include at least one P-type work function (PWF) metal or an N-type work function (NWF) metal, depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor. When the transistor 110 is a PMOS transistor, a PWF metal may be used as the gate electrode material 108, and when the transistor 110 is an NMOS transistor, an NWF metal may be used as the gate electrode material 108. For PMOS transistors, metals that can be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors, metals that can be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a filler metal layer. Other layers may be included alongside the gate electrode material 108 for other purposes, such as serving as a diffusion barrier layer or / and an adhesive layer.

[0044] In some embodiments, the gate insulator 106 may include one or more high-k dielectrics, comprising any materials discussed above for the ILD that may surround a portion of the transistor 110. In some embodiments, the high-k dielectric may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate insulator 106 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate insulator 106 during the manufacture of the transistor 110 to improve the quality of the gate insulator 106. In some embodiments, the gate insulator 106 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values ​​and ranges therein (e.g., between about 1 nanometer and 3 nanometers, or between about 1 nanometer and 2 nanometers), but in other embodiments, the thickness of the gate insulator 106 may be greater than 3 nanometers. In some embodiments, the gate stack 112 may be Figure 1 Gate spacers, not shown, surround the transistor 110. Such gate spacers will be configured to provide separation between the gate stack 112 and the first S / D contact 124 and the second S / D contact 126 of the transistor 110 (e.g., as described below). Figures 3A-3D The gate spacer (348) can be made of a low-k dielectric material, some examples of which have been provided above. The gate spacer may include holes or air gaps to further reduce its dielectric constant.

[0045] Turning to the S / D regions 114 and 116 of transistor 110, in some embodiments, the S / D regions may be highly doped, for example, having at least about 10 dopant. 20 Or at least about 10 21 cm -3 The dopant concentration is adjusted to form a favorable ohmic contact with the corresponding S / D contact portion, although these regions may also have a lower dopant concentration and may form a Schottky contact in some embodiments. Regardless of the specific doping level, the S / D region of the transistor can be a region with a higher dopant concentration than other regions (e.g., higher than the dopant concentration in the channel portion (i.e., in the channel material extending between the first S / D region 114 and the second S / D region 116)) and can therefore be referred to as a “highly doped” (HD) region. The channel portion of transistor 110 may include a doping concentration (e.g., a doping concentration below 10). 18 cm -3 or below 10 17 cm -3Semiconductor materials with significantly lower doping concentrations than those in the S / D regions 114 and 116.

[0046] The S / D regions 114 and 116 of transistor 110 can typically be formed using either an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into nanoribbon 104 to form source and drain regions. After the ion implantation process, an annealing process can be performed to activate the dopants and allow them to diffuse further into nanoribbon 104. In the latter process, a portion of nanoribbon 104 can be etched first to form a depression at the future location of S / D regions 114 and 116. An epitaxial deposition process can then be performed to fill the depression with the material used to fabricate the S / D regions 114 and 116. In some embodiments, silicon alloys (e.g., silicon-germanium or silicon carbide) can be used to fabricate the S / D regions 114 and 116. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped with dopants such as boron, arsenic, or phosphorus. In another embodiment, one or more alternative semiconductor materials (e.g., germanium or group III-V materials or alloys) may be used to form the S / D regions 114, 116. And in another embodiment, one or more layers of metal and / or metal alloys may be used to form the S / D regions 114, 116. In some embodiments, the distance between the first S / D region 114 and the second S / D region 116 (i.e., the dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 nanometers and 40 nanometers, including all values ​​and ranges therein (e.g., between about 22 nanometers and 35 nanometers, or between about 20 nanometers and 30 nanometers).

[0047] Figure 2 This is a flowchart of a method 200 for metallizing S / D contacts for manufacturing an IC structure having nanoribbon transistors and a back-side capacitor, according to some embodiments. Figures 3A-3D This illustrates, according to some embodiments, in Figure 2 Cross-sectional side and top views of exemplary IC structures following various processes of the methods described. Figures 3A-3C Each of these illustrates an IC structure including a nanoribbon transistor with nanoribbon stacks. For example, Figures 3A-3C Nanoribbon transistors with IC structures can be implemented as Figure 1 In transistor 110, where, Figures 3A-3C The illustration shows a cross-sectional side view along a plane substantially perpendicular to the substrate 102, and includes... Figure 1 The vertical axis 120 is shown (i.e., along the cross-section of the nanoribbon 104). Therefore, Figures 3A-3C Each of them shows along Figure 1 A cross-sectional side view of the xz plane in coordinate system 105. Although Figures 3A-3C A specific number of nanoribbons 334 (e.g., four) in the nanoribbon stack for the transistors shown in these figures are depicted, but this is merely for illustrative purposes, and the IC structure may include more or fewer nanoribbons 334 in the nanoribbon stack for a given transistor. Figure 3D A top view of a cross-section along a plane substantially parallel to substrate 102 is shown. Therefore, Figure 3D It shows along Figure 1 A top view of the cross-section in the xy plane of coordinate system 105. Although Figure 3D A specific number of vias (e.g., two) for the back-side capacitor is depicted, but this is merely for illustrative purposes, and the IC structure may include more or fewer vias for a given back-side capacitor. In this specification, Figures 3A-3D Some of the elements shown are designated by reference numerals with different patterns shown in these figures, wherein legends illustrating the correspondence between reference numerals and patterns are provided in Figures 3A-3D At the bottom of each drawing page.

[0048] although Figure 2 The operations of the manufacturing method shown are each illustrated once in a specific order, but these operations can be performed in any suitable order and repeated as needed. For example, Figure 2 The exemplary manufacturing method shown may include other operations not specifically shown in the drawings, such as various cleaning or planarization operations known in the art. For example, in some embodiments, it may be possible to... Figure 2 Before, after, or during any of the manufacturing methods illustrated, the substrate on which the IC structure is provided, as well as layers of various other materials subsequently deposited thereon, are cleaned, for example, to remove oxides, surface-bound organic and metallic contaminants, and subsurface contaminants. In some embodiments, cleaning may be performed using, for example, chemical solutions (e.g., peroxides) and / or ultraviolet (UV) radiation combined with ozone and / or surface oxidation (e.g., using thermal oxidation) followed by oxide removal (e.g., using hydrofluoric acid (HF)). In another example, the arrangement / apparatus described herein may be as described herein. Figure 2 Planarization is performed before, after, or during any of the processes in the manufacturing methods shown, for example, to remove overcoat or excess material. In some embodiments, planarization may be performed using wet or dry planarization processes, such as chemical mechanical planarization (CMP), which can be understood as a process that uses polished surfaces, abrasives, and slurries to remove overcoat material and planarize the surface.

[0049] Method 200 may begin with process 202, which includes providing a transistor on the positive side of a substrate. Figure 3AThe IC structure 302 depicted illustrates an exemplary result of process 202. (As shown...) Figure 3A As shown, IC structure 302 includes a transistor similar to transistor 110, but this transistor is based on a stack of multiple nanoribbons 334 instead of... Figure 1 The diagram shows a single nanoribbon 104 constructed, wherein each nanoribbon in the nanoribbon 334 can be implemented as nanoribbon 104. Although four nanoribbons 334 are shown as included in a nanoribbon stack of IC structure 302, in other embodiments, fewer or more nanoribbons 334 may be included.

[0050] Figure 3A Also shown is a sub-fin 336 of semiconductor material 338 beneath the stack of nanoribbons 334. In some embodiments, semiconductor material 338 may include any semiconductor material described with respect to nanoribbons 104, but in some embodiments, at least a portion of nanoribbons 334 and sub-fin 336 may include semiconductor materials of different material compositions.

[0051] like Figure 3A As shown, a gate stack 112 having a gate insulator 106 and a gate electrode material 108 can surround the channel portion of the nanoribbon 334. Figure 3A Also shown are a first S / D region 114 and a second S / D region 116 extending through a stack of nanoribbons 334, electrically insulated / separated from the gate electrode material 108 and the semiconductor material 338 of the sub-fins 336 by an insulating material 340. In some embodiments, as part of fabricating transistor 110, a so-called recess 342 may be formed to separate the S / D regions 114, 116 from the gate electrode material 108. Figure 3A As shown, the recess 342 may be filled with an insulating material 340, therefore, the insulating material 340 may be referred to as a "recess spacer". The insulating material 340 may include any insulating material described herein, such as any ILD material described above.

[0052] Above the stack of nanoribbons 334, Figure 3A A gate contact 344 is shown, along with a first S / D contact 124 and a dummy second S / D contact 126' on either side of the gate contact 344. The gate contact 344 may include a conductive material 346 in conductive contact with the gate electrode material 108. In various embodiments, the material composition of the conductive material 346 and the gate electrode material 108 may be substantially the same or different. Figure 3AAs further shown, the sidewalls of the first S / D contact 124 and the dummy second S / D contact 126' may be lined with a gate spacer 348. The gate spacer 348 can electrically isolate the conductive materials of the first S / D contact 124 and the dummy second S / D contact 126' from the gate electrode material 108 and the conductive material 346 of the gate contact 344. The gate spacer 348 may include one or more spacer materials, diffusion barrier materials, adhesive materials, etc., as known in the art, for forming contacts of various components to the IC structure. In some embodiments, the gate spacer 348 may include a low-k dielectric and / or any of the above-mentioned ILD materials.

[0053] In some embodiments, the first S / D contact 124 may include a conductive filler material 364, and the dummy second S / D contact 126' may include an insulating material 366, such as... Figure 3A As shown. In various embodiments, the conductive filler material 364 may include any suitable metal (e.g., tungsten, titanium, tantalum, copper, ruthenium, palladium, platinum, cobalt, nickel, etc.), metal alloy, or a carbide or nitride of one or more metals, while the insulating material 366 may include any insulating material described herein, such as any low-k dielectric material described herein. In other embodiments, the dummy second S / D contact 126' may include the conductive filler material 364 instead of the insulating material 366 ( Figure 3A (Not shown in the image). In such an embodiment, the conductive filler material 364 in the dummy second S / D contact 126' may be electrically floating (i.e., not electrically connected to any signal, power, or ground path).

[0054] For example Figure 3A As shown, in some embodiments, optionally, the first S / D contact 124 and the dummy second S / D contact 126' may include an interface liner 350 located on the bottom and possibly also on the sidewalls. The interface liner 350 may include any material that can improve the electrical contact between the S / D regions 114, 116 and the conductive filler material 364 of the first S / D contact 124 and the dummy second S / D contact 126'. In some embodiments, the interface liner 350 may include / may be a metal (e.g., titanium), which, once deposited, can be mixed with the material of the S / D regions 114, 116 (e.g., with silicon) to form an interface compound 352 (e.g., titanium silicide) that can help reduce the contact resistance of the S / D contact 124. Figure 3AAs shown, in some embodiments, the interface liner 350 may be recessed on the sidewalls of the first S / D contact 124 and the dummy second S / D contact 126'. In some embodiments, the thickness of the interface liner 350 may be between about 2 nanometers and about 20 nanometers, for example, between about 2 nanometers and 15 nanometers, or between about 2 nanometers and 10 nanometers. Although in Figure 3A Not specifically shown, but in some embodiments, the first S / D contact 124 and the dummy second S / D contact 126' may optionally be lined with one or more additional liner layers, which may include, but are not limited to, materials containing silicon and nitrogen (e.g., silicon nitride), materials containing silicon and oxygen (e.g., silicon oxide), materials containing silicon and carbon (e.g., silicon carbide), and / or composites thereof.

[0055] Method 200 can then proceed to process 204, which includes providing connections at the back side of IC structure 302 to the second S / D region 116 of transistor 110 and the first capacitor electrode. Figure 3B The IC structure 304 depicted illustrates an exemplary result of process 204. (As shown...) Figure 3B As shown, in some embodiments, process 204 may include substantially removing substrate 102, for example, by thinning substrate 102 starting from the back side of IC structure 100 and replacing it with a layer of insulating material 368. Insulating material 368 may include any of the insulating materials described herein, such as any of the low-k dielectric materials described herein. Figure 3B The structure of the conductive material 372, which forms the first capacitor electrode of the future capacitor, is also shown. (As shown) Figure 3B As shown, the conductive material 372 may have a portion 373-1 (e.g., a via portion) that makes a conductive contact with the S / D region 116, and may have an interface compound 374 formed at the interface between the portion 373-1 of the conductive material 372 and the S / D region 116. For example, if the S / D region 116 comprises silicon and the conductive material 372 comprises a metal, the interface compound 374 may comprise a silicide of the metal of the conductive material 372. Figure 3B As further shown, one or more vias 376 may be formed in the insulating material 368, starting from the back side of the IC structure 100 and extending upward toward a portion 373-1 of the conductive material 372. Figure 3BTwo such vias 376 are shown, but in other embodiments, any number or number of vias 376 can be implemented. The sidewalls and bottom of the via 376 may be lined with a layer of conductive material 372, thereby forming a portion 373-2 of conductive material 372. Finally, the portion 373-3 of conductive material 372 may be materially connected and electrically connected to the portion 373-1 of conductive material 372 and the portion 373-2 in the different vias 376. Thus, the conductive material 372 in portion 373-1, portion 373-3, and portion 373-2 of one or more vias 376 is materially continuous and electrically continuous with each other, thereby forming a single first capacitor electrode of the future capacitor.

[0056] In various embodiments, the conductive material 372 may comprise any suitable conductive material (e.g., a metal or combination of metals), such as any of the conductive materials described above. Vias 376 may be formed in process 204 using any suitable technique, such as any suitable etching technique, possibly combined with any suitable patterning technique. Insulating material 368 and conductive material 372 may be deposited in process 204 using any suitable deposition technique (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD)). In some embodiments, conductive material 372 may be deposited in one or more vias 376 and portions 373-3 using any suitable conformal deposition technique. In various embodiments, the thickness of the conductive material 372 in these portions may be between about 2 nanometers and about 20 nanometers, for example, between about 2 nanometers and 15 nanometers, or between about 2 nanometers and 10 nanometers. In some embodiments, the width of via 376 (e.g., a dimension measured along the x-axis of coordinate system 105) can be between about 15 nanometers and about 100 nanometers, for example, between about 20 and 75 nanometers, or between about 20 and 50 nanometers. In some embodiments, the depth of via 376 (e.g., a dimension measured along the z-axis of coordinate system 105) can be between about 25 nanometers and about 200 nanometers, for example, between about 30 nanometers and 150 nanometers, or between about 30 nanometers and 100 nanometers. Figure 3B As shown, individual vias in via 376 can be separated from each other by a portion of insulating material 368. In some embodiments, the width of the portion of insulating material 368 that separates adjacent vias 376 from each other can be between about 2 nanometers and about 20 nanometers, for example between about 2 nanometers and 15 nanometers, or between about 2 nanometers and 10 nanometers.

[0057] Next, method 200 may include process 206, which includes providing a capacitor insulator and a second capacitor electrode at the back side of IC structure 304. Figure 3CThe IC structure 306 depicted illustrates an exemplary result of process 206. (As shown...) Figure 3C As shown, IC structure 306 includes capacitor insulator 378, which is deposited as a liner lining the bottom and sidewalls of one or more vias 376. In some embodiments, the thickness of capacitor insulator 378 may be between about 1 nanometer and about 10 nanometers, for example, between about 1 nanometer and 8 nanometers, or between about 1 nanometer and 5 nanometers. Figure 3C A conductive material 380 is also shown, which is deposited to partially fill at least the remaining volume of one or more vias 376 lined with conductive material 372 and capacitor insulator 378. (See diagram below.) Figure 3C As shown, capacitor insulator 378 separates conductive material 372 from conductive material 380 and thus acts as capacitor insulator for capacitor 382, ​​while conductive material 380 can form the second capacitor electrode of capacitor 382. Because capacitor 382 is located on the back side of IC structure 306, it can be referred to as a back-side capacitor. Therefore, in IC structure 306 (which is an example of IC structure 100), S / D contact 124 is a contact structure that makes conductive contact (e.g., direct electrical connection) with S / D region 114 and is located on the positive side of the channel portion of nanoribbon 334, while capacitor 382 is a structure that makes conductive contact (e.g., direct electrical connection) with S / D region 116 and is located on the back side of the channel portion of nanoribbon 334. The transistor 110 and capacitor 382 of IC structure 306 can together form a memory cell, such as a 1T-1C memory cell. In various embodiments, IC structure 306 may include multiple such memory cells.

[0058] The capacitor insulator 378 and conductive material 380 can be deposited in process 206 using any suitable deposition technique (e.g., any of those described above). In various embodiments, the conductive material 380 may include any suitable conductive material (e.g., a metal or combination of metals), such as any of the conductive materials described above. In some embodiments, the capacitor insulator 378 may include any insulating material described herein, such as any high-k dielectric material described herein. In other embodiments, the capacitor insulator 378 may be provided as a layer of ferroelectric (FE) or antiferroelectric (AFE) material. Such FE / AFE materials may include one or more materials that are capable of exhibiting sufficient FE / AFE properties even at thin dimensions, such as at least about 5%, at least about 7%, or at least about 10% of insulating material, which is in an orthorhombic and / or tetragonal phase (e.g., as up to about 95-90% of the material, it may be an amorphous or monoclinic phase material). For example, such materials may be based on hafnium and oxygen (e.g., hafnium oxide), wherein various dopants are added to ensure a sufficient amount of orthorhombic or tetragonal phase. Some examples of such materials include: materials containing hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also known as HZO)); materials containing hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide); materials containing hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide); materials containing hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide); and materials containing hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other material exhibiting FE / AFE characteristics at a thin size can be used as capacitor insulator 378 and is within the scope of this disclosure.

[0059] Figure 3D Different embodiments of the shape of the via 376 of capacitor 382 are shown. For example... Figure 3D As shown, in various embodiments, each via in via 376 can be circular ( Figure 3D The topmost illustration in the image) or a rectangle (e.g., a square) Figure 3D The middle diagram in the middle) or hexagon ( Figure 3D (The bottom illustration in the image).

[0060] IC structures with nanoribbon transistors and back-side capacitors (e.g., according to reference) Figures 1-3D An IC structure having a nanoribbon transistor 110 and a back-side capacitor 382, ​​any of the embodiments described or any combination of such embodiments, may be included in any suitable electronic device. Figures 4-9Various examples of devices are shown that may include one or more IC structures having nanoribbon transistors and back-side capacitors (e.g., any embodiment of IC structure 100 or any embodiment of IC structure 306 described herein).

[0061] Figure 4 A top view is shown of a wafer and die that may include one or more IC structures having nanoribbon transistors and back-side capacitors according to some embodiments. The wafer 2000 may be made of semiconductor material and may include one or more dies 2002 having IC structures formed on the surface of the wafer 2000. Each die 2002 may include any suitable IC structure (e.g., reference...). Figures 1-3D A repeating unit of a semiconductor product (any IC structure described herein). After the semiconductor product is manufactured (e.g., after manufacturing one or more IC structures as described herein), the wafer 2000 may undergo a dicing process, wherein each die 2002 is separated from each other to provide a discrete “chip” of the semiconductor product. In particular, devices including one or more IC structures as disclosed herein may take the form of a wafer 2000 (e.g., undicated) or a die 2002 (e.g., diced). A die 2002 may include: one or more nanoribbon transistors and back-side capacitors as described herein, and / or support circuitry for transmitting electrical signals to transistors 110 and capacitors 382, ​​as well as any other IC components. In some embodiments, the wafer 2000 or die 2002 may include memory devices (e.g., memory devices having one or more nanoribbon transistors 110 and back-side capacitors 382), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices can be formed in conjunction with a processing device (e.g., Figure 9 The same die 2002 is configured to store information in a memory device or execute instructions stored in a memory array.

[0062] Figure 5 This is a side cross-sectional view of an IC device 2100 that may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein, according to some embodiments. For example, as described herein, any transistor 2140 of the IC device 2100 may be implemented as any transistor 110 coupled to a corresponding capacitor 382. In another example, one or more of the IC device 2100 may include... Figure 4 One or more dies 2002 are formed in the substrate 2102. The IC device 2100 may be formed on the substrate 2102 (e.g., Figure 4On the wafer 2000, and may be included on the die (e.g., Figure 4 In the die 2002). The substrate 2102 can be any form of the substrate 102 described above.

[0063] IC device 2100 may include one or more device layers 2104 disposed on substrate 2102. Device layer 2104 may include features of one or more transistors 2140 (e.g., MOSFETs) formed on substrate 2102. Device layer 2104 may include, for example, one or more S / D regions 2120, a gate 2122 for controlling the flow of current in transistor 2140 between S / D regions 2120, and one or more S / D contacts 2124 for transmitting electrical signals to and from S / D regions 2120. Transistor 2140 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. Transistor 2140 is not limited to... Figure 5 The types and configurations described herein may include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as dual-gate or tri-gate transistors, and all-around or GAA transistors, such as nanoribbon and nanowire transistors.

[0064] Each transistor 2140 may include a gate 2122 formed of at least two layers (gate insulator and gate electrode). The gate insulator of transistor 2140 may be implemented as the gate insulator 106 described above, and the gate electrode of transistor 2140 may be implemented as the gate electrode material 108 described above.

[0065] The S / D region 2120 may be formed adjacent to the gate 2122 of each transistor 2140 within the substrate 2102. The S / D region 2120 of the transistor 2140 may be implemented as the S / D regions 114 and 116 described above.

[0066] One or more interconnect layers disposed on device layer 2104 (in Figure 5The interconnect layers 2106, 2108, and 2110 (shown as interconnect layers 2106, 2108, and 2110) transmit electrical signals, such as power and / or input / output (I / O) signals, to and from devices (e.g., transistor 2140) on device layer 2104. For example, conductive features of device layer 2104 (e.g., gate 2122 and S / D contact 2124) may be electrically coupled to interconnect structures 2128 of interconnect layers 2106, 2108, and 2110. One or more interconnect layers 2106, 2108, and 2110 may form a metallized stack (also referred to as an "ILD stack") 2119 of IC device 2100.

[0067] Interconnection structure 2128 can be arranged within interconnect layers 2106, 2108, and 2110 to transmit electrical signals according to a variety of designs (in particular, the arrangement is not limited to...). Figure 5 The specific configuration of the interconnect structure 2128 depicted in the diagram). Although in Figure 5 The disclosure depicts a specific number of interconnect layers 2106, 2108, and 2110, but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those depicted.

[0068] In some embodiments, the interconnect structure 2128 may include conductive lines 2128a and / or conductive vias 2128b filled with a conductive material (e.g., metal). The conductive lines 2128a may be arranged to transmit electrical signals in a direction substantially parallel to a plane on the substrate 2102 on which the device layer 2104 is formed. For example, from... Figure 5 From the perspective of the page, conductive line 2128a can transmit electrical signals in the direction of entering and exiting the page. Conductive via 2128b can be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the surface of the substrate 2102 on which the device layer 2104 is formed. In some embodiments, conductive via 2128b can electrically couple conductive lines 2128a of different interconnect layers 2106, 2108, and 2110 together.

[0069] Interconnect layers 2106, 2108, and 2110 may include an insulating material 2126 disposed between interconnect structures 2128, such as... Figure 5 As shown. In some embodiments, the insulating material 2126 disposed between the interconnect structures 2128 in different interconnect layers 2106, 2108 and 2110 may have different compositions; in other embodiments, the composition of the insulating material 2126 between different interconnect layers 2106, 2108 and 2110 may be the same.

[0070] A first interconnect layer 2106 may be formed over a device layer 2104. In some embodiments, the first interconnect layer 2106 may include a conductive line 2128a and / or a conductive via 2128b, as shown in the figure. The conductive line 2128a of the first interconnect layer 2106 may be coupled to a contact portion (e.g., an S / D contact portion 2124) of the device layer 2104.

[0071] A second interconnect layer 2108 may be formed over a first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include a conductive via 2128b to couple a conductive line 2128a of the second interconnect layer 2108 to a conductive line 2128a of the first interconnect layer 2106. Although for clarity, the conductive line 2128a and the conductive via 2128b are structurally defined by lines within each interconnect layer (e.g., within the second interconnect layer 2108), in some embodiments, the conductive line 2128a and the conductive via 2128b may be structurally and / or materially continuous (e.g., the conductive line 2128a and the conductive via 2128b are simultaneously filled during a dual damascene process).

[0072] Based on similar techniques and configurations described in conjunction with the second interconnect layer 2108 or the first interconnect layer 2106, a third interconnect layer 2110 (and additional interconnect layers as needed) can be continuously formed on the second interconnect layer 2108. In some embodiments, the interconnect layers that are “higher” (i.e., further away from the device layer 2104) in the metallization stack 2119 of the IC device 2100 can be thicker.

[0073] IC device 2100 may include solder resist material 2134 (e.g., polyimide or similar material) and one or more conductive contacts 2136 formed on interconnect layers 2106, 2108, and 2110. Figure 5 In the diagram, conductive contact 2136 is shown in the form of a bonding pad. Conductive contact 2136 may be electrically coupled to interconnect structure 2128 and is configured to transmit electrical signals from one or more transistors 2140 to other external devices. For example, solder bonding portions may be formed on one or more conductive contacts 2136 to mechanically and / or electrically couple a chip including IC device 2100 to another component (e.g., a circuit board). IC device 2100 may include additional or alternative structures to transmit electrical signals from interconnect layers 2106, 2108, and 2110; for example, conductive contact 2136 may include other similar features (e.g., posts) for transmitting electrical signals to external components.

[0074] Figure 6This is a side cross-sectional view of an exemplary IC package 2200 according to some embodiments. The exemplary IC package 2200 may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein. For example, any die 2202 of the IC package 2200 may be implemented as... Figure 4 In another example, any die 2202 may include die 2002. Figure 5 Any embodiment of the IC device 2100. In embodiments where the IC package 2200 includes a plurality of dies 2202, the IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2202 may include circuitry for performing any desired function. For example, one or more dies in the die 2202 may be logic dies (e.g., silicon-based dies), and one or more dies in the die 2202 may be memory dies (e.g., high-bandwidth memory). In some embodiments, the IC package 2200 may be a system-in-package (SiP). In some embodiments, the IC package 2200 may include a photonic IC (PIC) co-packaged with the IC package. In some embodiments, the IC package 2200 may include a fully integrated electro-photonic IC (EPIC).

[0075] IC package 2200 may include package substrate 2204, which may be formed of a dielectric material (e.g., ceramic, deposited film, epoxy resin film having filler particles therein, glass, organic material, inorganic material, combination of organic and inorganic materials, embedded portion formed of different materials, etc.) and may have conductive pathways extending through the dielectric material between surfaces 2206 and 2208, or between different locations on surface 2206 and / or between different locations on surface 2208. These conductive pathways may take the form described above. Figure 5 The discussion covers any interconnect structure in the form of 2128.

[0076] The package substrate 2204 may include conductive contacts 2210 coupled to conductive pathways (not shown) passing through the package substrate 2204, thereby allowing circuitry within the die 2202 and / or the interposer 2212 to be electrically coupled to various conductive contacts in the conductive contacts 2214 (or electrically coupled to other devices (not shown) included in the package substrate 2204). The IC package 2200 may include an interposer 2212, which is coupled to the package substrate 2204 via conductive contacts 2216, first-level interconnects 2218, and conductive contacts 2210 of the package substrate 2204. Figure 6The first-level interconnect 2218 shown is a solder bump, but any suitable first-level interconnect 2218 can be used. In some embodiments, the interposer 2212 may not be included in the IC package 2200; instead, the die 2202 can be directly coupled to the conductive contact 2210 at the face 2206 via the first-level interconnect 2218. Typically, one or more dies 2202 can be coupled to the package substrate 2204 via any suitable structure (e.g., silicon bridge, organic bridge, one or more waveguides, one or more interposers, wire bonding, etc.).

[0077] IC package 2200 may include one or more dies 2202, which are coupled to interposer 2212 via conductive contacts 2220, first-level interconnects 2222, and conductive contacts 2224 of interposer 2212. The conductive contacts 2224 can be coupled to conductive paths (not shown) through interposer 2212, thereby allowing circuitry within die 2202 to be electrically coupled to individual conductive contacts in conductive contacts 2216 (or to other unshown devices included in interposer 2212). Figure 6 The first-level interconnect 2222 shown is a solder bump, but any suitable first-level interconnect 2222 can be used. For example, the first-level interconnect 2222 can include a hybrid bonding interconnect. As used herein, "conductive contact" can refer to a portion of an electrical material (e.g., a metal) that serves as an interface between different components; the conductive contact can be recessed into the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and can take any suitable form (e.g., conductive pad or socket).

[0078] In some embodiments, an underfill material 2226 may be disposed between the package substrate 2204 and the interposer 2212 around the first-level interconnect 2218, and a molding compound 2228 may be disposed around the die 2202 and the interposer 2212 and contact the package substrate 2204. In some embodiments, the underfill material 2226 may be the same as the molding compound 2228. Exemplary materials that can be used for the underfill material 2226 and the molding compound 2228, if appropriate, are epoxy molding materials. The second-level interconnect 2230 may be coupled to the conductive contact 2214. Figure 6 The second-level interconnect 2230 shown is a solder ball (e.g., for a ball grid array arrangement), but any suitable second-level interconnect 2230 can be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). The second-level interconnect 2230 can be used to couple IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and referenced below. Figure 7 The subject of discussion.

[0079] although Figure 6 The IC package 2200 shown is a flip-chip package, but other package architectures can be used. For example, IC package 2200 can be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although in Figure 6 Two dies 2202 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2202. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2206 or the second side 2208 of the package substrate 2204 or on either side of the interposer 2212. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0080] Figure 7 This is a side cross-sectional view of an IC device assembly 2300 according to some embodiments. The IC device assembly 2300 may include one or more IC packages or other electronic components (e.g., dies) comprising one or more IC structures having nanoribbon transistors and back-side capacitors as described herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and an opposing second surface 2342 of the circuit board 2302; typically, components may be disposed on one or both of surfaces 2340 and 2342. Any IC package discussed below with respect to the IC device assembly 2300 may take the form of the above reference. Figure 6 The form of any embodiment of the IC package 2200 discussed.

[0081] In some embodiments, circuit board 2302 may be a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 2302 (optionally combined with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0082] Figure 7 The illustrated IC device assembly 2300 includes an on-intermediate package (IP) structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling member 2316. The coupling member 2316 can electrically and mechanically couple the IP structure 2336 to the circuit board 2302 and may include solder balls (e.g., ...). Figure 7(as shown), the male and female parts of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0083] The on-intermediate package structure 2336 may include an IC package 2320 coupled to the package intermediate layer 2304 via a coupling member 2318. The coupling member 2318 may take any form suitable for the application, such as the form discussed above for coupling member 2316. Although Figure 7 A single IC package 2320 is shown, but multiple IC packages can be coupled to a package interposer 2304; in fact, additional interposers can be coupled to the package interposer 2304. The package interposer 2304 can provide an intermediary substrate for bridging the circuit board 2302 and the IC package 2320. The IC package 2320 can be, for example, a die (…). Figure 4 In the die 2002), IC device (e.g., Figure 5 IC device 2100 or any other suitable component, or including, for example, a die ( Figure 4 In the die 2002), IC device (e.g., Figure 5 This can be an IC device 2100 or any other suitable component. Typically, the package interposer 2304 can extend connections to wider spacing or rewire connections to different connections. For example, the package interposer 2304 can couple an IC package 2320 (e.g., a die) to a set of BGA conductive contacts on a coupling member 2316 to couple to a circuit board 2302. Figure 7 In the illustrated embodiment, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the package interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the package interposer 2304. In some embodiments, three or more components may be interconnected via the package interposer 2304. In some embodiments, the IC package 2320 may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein.

[0084] In some embodiments, the encapsulation interposer 2304 may be formed as a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the encapsulation interposer 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the encapsulation interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The encapsulation interposer 2304 may include metal lines 2310 and vias 2308, including but not limited to through-substrate vias (TSVs) 2306. The encapsulation interposer 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the package interposer 2304. The package-on-interposer structure 2336 can take the form of any package-on-interposer structure known in the art.

[0085] IC device assembly 2300 may include IC package 2324 coupled to a first side 2340 of circuit board 2302 via coupling member 2322. Coupling member 2322 may take the form of any of the embodiments discussed above with respect to coupling member 2316, and IC package 2324 may take the form of any of the embodiments discussed above with respect to IC package 2320.

[0086] Figure 7 The illustrated IC device assembly 2300 includes a stacked package structure 2334 coupled to a second side 2342 of a circuit board 2302 via a coupling member 2328. The stacked package structure 2334 may include IC packages 2326 and 2332 coupled together via a coupling member 2330, such that IC package 2326 is disposed between the circuit board 2302 and IC package 2332. The coupling members 2328 and 2330 may take the form of any embodiment of the coupling member 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 discussed above. The stacked package structure 2334 can be configured according to any stacked package structure known in the art.

[0087] Figure 8This is a block diagram of an exemplary computing device 2400 according to some embodiments. The exemplary computing device 2400 may include one or more components, which include one or more IC structures having nanostrip transistors and back-side capacitors as described herein. For example, any suitable component of the computing device 2400 may include a die (e.g., Figure 4 The die (2002) has one or more IC structures as described herein, including nanostrip transistors and back-side capacitors. Any one or more components of the computing device 2400 may include... Figure 5 IC device 2100 in Figure 6 IC package 2200 or Figure 7 IC device component 2300.

[0088] Multiple components Figure 8 The components are shown as included in computing device 2400, but any one or more of these components may be omitted or copied to suit an application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SoC die.

[0089] Additionally, in various embodiments, the computing device 2400 may not include... Figure 8 The computing device 2400 may include one or more components, but may include interface circuitry for coupling to said one or more components. For example, the computing device 2400 may not include the display device 2412, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2412 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2416 or the audio output device 2414, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 2416 or the audio output device 2414 may be coupled.

[0090] Computing device 2400 may include processing device 2402 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing means. In some embodiments, processing device 2402 may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein.

[0091] Computing device 2400 may include memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drive. In some embodiments, memory 2404 may include memory sharing a die with processing device 2402. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque MRAM. In some embodiments, memory 2404 may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein.

[0092] In some embodiments, computing device 2400 may include communication chip 2406 (e.g., one or more communication chips). For example, communication chip 2406 may be configured to manage wireless communication for the transmission of data to and from computing device 2400. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation that travels through a non-solid medium. This term does not imply that the associated apparatus does not contain any wiring, although in some embodiments they may not contain wiring.

[0093] The 2406 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision)), Long Term Evolution (LTE) projects, and any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks. WiMAX stands for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 2406 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2406 can operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocols designated 3G, 4G, 5G, and higher generations. In other embodiments, the communication chip 2406 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2408 to facilitate wireless communication and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0094] In some embodiments, communication chip 2406 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication chip 2406 may include multiple communication chips. For example, a first communication chip 2406 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2406 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2406 may be dedicated to wireless communications, and the second communication chip 2406 may be dedicated to wired communications.

[0095] The computing device 2400 may include a battery / power circuit 2410. The battery / power circuit 2410 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the computing device 2400 to an energy source (e.g., an AC line power supply) that is separate from the computing device 2400.

[0096] The computing device 2400 may include a display device 2412 (or a corresponding interface circuit as described above). The display device 2412 may include any visual indicator, such as, for example, a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0097] The computing device 2400 may include an audio output device 2414 (or a corresponding interface circuit as described above). The audio output device 2414 may include any means of generating audible indicators, such as, for example, a speaker, headphones, or earphones.

[0098] The computing device 2400 may include an audio input device 2416 (or a corresponding interface circuit as described above). The audio input device 2416 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0099] The computing device 2400 may include other output devices 2418 (or corresponding interface circuits as described above). Examples of other output devices 2418 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0100] The computing device 2400 may include other input devices 2420 (or corresponding interface circuits as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse, a stylus, a touchpad), a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0101] The computing device 2400 may include a GPS device 2422 (or a corresponding interface circuit as described above). As is known in the art, the GPS device 2422 can communicate with a satellite-based system and can receive the location of the computing device 2400.

[0102] Computing device 2400 may include a security interface device 2424. Security interface device 2424 may include any means of providing security features for computing device 2400 or any individual component therein (e.g., for processing device 2402 or for memory 2404). Examples of security features may include authorization, access permissions for digital certificates, access permissions for items in a keychain, etc. Examples of security interface device 2424 may include software firewalls, hardware firewalls, antivirus software, content filtering devices, or intrusion detection devices.

[0103] In some embodiments, the computing device 2400 may include a temperature detection device 2426 and a temperature regulation device 2428.

[0104] Temperature detection device 2426 may include any means capable of determining the temperature of computing device 2400 or the temperature of any individual component therein (e.g., the temperature of processing device 2402 or the temperature of memory 2404). In various embodiments, temperature detection device 2426 may be configured to determine the temperature of an object (e.g., computing device 2400, components of computing device 2400, means coupled to computing device 2400, etc.), the temperature of an environment (e.g., a data center that includes, is controlled by, or is otherwise associated with computing device 2400). Temperature detection device 2426 may include one or more temperature sensors. Different temperature sensors of temperature detection device 2426 may be located at different locations within and around computing device 2400. Temperature sensors may generate data (e.g., digital data) representing the detected temperature and provide that data to another means, such as temperature regulation device 2428, processing device 2402, memory 2404, etc. In some embodiments, the temperature sensor of the temperature detection device 2426 may be turned on or off, for example, by the processing device 2402 or an external system. The temperature sensor detects temperature when it is on and does not detect temperature when it is off. In other embodiments, the temperature sensor of the temperature detection device 2426 may detect temperature continuously and automatically, or detect temperature at a predetermined time or at a time triggered by an event associated with the computing device 2400 or any component thereof.

[0105] Temperature regulation device 2428 may include any means configured to change (e.g., decrease) a temperature, for example, based on one or more target temperatures and / or based on temperature measurements performed by temperature detection device 2426. The target temperature may be a preferred temperature. The target temperature may depend on the operating settings of computing device 2400. In some embodiments, the target temperature may be 200 degrees (Kelvin) or lower. In some embodiments, the target temperature may be 20 degrees (Kelvin) or lower, or 5 degrees (Kelvin) or lower. The target temperature may differ for different objects and environments associated with computing device 2400. In some embodiments, the cooling provided by temperature regulation device 2428 may be a multi-stage process with a temperature range from room temperature to 4K or lower.

[0106] In some embodiments, the temperature regulating device 2428 may include one or more cooling devices. Different cooling devices may be located at different locations within and around the computing device 2400. The cooling devices of the temperature regulating device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426 and may be configured to operate based on the temperature detected by the temperature sensors. For example, the cooling device may be configured to determine whether the detected ambient temperature is higher than a target temperature or whether the detected ambient temperature is higher than the target temperature by a predetermined value, or to determine whether any other temperature-related conditions associated with the temperature of the computing device 2400 are met. In response to determining that one or more temperature-related conditions associated with the temperature of the computing device 2400 are met (e.g., in response to determining that the detected ambient temperature is higher than the target temperature), the cooling device may trigger its cooling mechanism and begin to lower the ambient temperature. Otherwise, the cooling device does not trigger any cooling. The cooling devices of the temperature regulating device 2428 may operate with various cooling mechanisms, such as evaporative cooling, radiative cooling, conductive cooling, convection cooling, other cooling mechanisms, or any combination thereof. The cooling devices of the temperature regulating device 2428 may include a coolant, such as water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature control device 2428 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature control device 2428 or any part thereof (e.g., one or more separate cooling devices) may be connected to the computing device 2400 in close proximity (e.g., less than about 1 meter), or may be housed in a separate enclosure containing a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.).

[0107] By maintaining a target temperature, the energy consumption of the computing device 2400 (or its components) can be reduced, while computing efficiency can be improved. For example, when the computing device 2400 (or its components) operates at a lower temperature, energy dissipation (e.g., heat dissipation) can be reduced. Furthermore, the energy consumed by semiconductor components (e.g., the energy required for transistor switching of any component of the computing device 2400) can also be reduced. Various semiconductor materials can have lower resistivity and / or higher mobility at lower temperatures. Thus, the current per unit supply voltage can be increased by lowering the temperature. Conversely, for the same current that would be required, the supply voltage can be reduced by lowering the temperature. Since energy is related to the supply voltage, the energy consumption of semiconductor components can also be lower. In some embodiments, the energy savings achieved by reducing heat dissipation and reducing the energy consumed by the semiconductor components of the computing device or its components may outweigh (and sometimes significantly outweigh) the cost associated with the energy required for cooling.

[0108] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0109] Figure 9 This is a block diagram of an exemplary processing device 2500, which may include one or more IC structures having nanoribbon transistors and back-side capacitors as described herein. For example, any suitable component of the processing device 2500 may include a die (e.g., Figure 4 The die 2002 has one or more IC structures as described herein, including nanostrip transistors and back-side capacitors. Any one or more components of the processing device 2500 may include... Figure 5 IC device 2100 in Figure 6 IC package 2200 or Figure 7 The IC device assembly 2300 in the process device 2500 may include one or more components of the process device 2500. Figure 8 The computing device 2400 or included in Figure 8 In the computing device 2400; for example, the processing device 2500 may be the processing device 2402 of the computing device 2400.

[0110] Multiple components Figure 9 These components are shown as being included in processing device 2500, but any one or more of these components may be omitted or duplicated to suit an application. In some embodiments, some or all of the components included in processing device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single substrate, such as a single carrier substrate.

[0111] Additionally, in various embodiments, the processing device 2500 may not include... Figure 9 The processing device 2500 may include one or more components, but may also include interface circuitry for coupling to one or more components. For example, the processing device 2500 may not include the memory 2504, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the memory 2504 can be coupled.

[0112] The processing device 2500 may include logic circuitry 2502 (e.g., one or more circuits configured to perform logic / computation functions). Examples of such circuitry include ICs that perform one or more input / output (I / O) functions, arithmetic operations, data pipelines, etc.

[0113] In some embodiments, logic circuitry 2502 may include one or more circuits responsible for read / write operations on data stored in memory 2504. For this purpose, logic circuitry 2502 may include one or more I / O ICs configured to control access to data stored in memory 2504.

[0114] In some embodiments, logic circuitry 2502 may include one or more high-performance computing dies configured to perform various operations on data stored in memory 2504 (e.g., arithmetic and logical operations, pipelined operations on data from one or more memory dies of memory 2504, and possibly also arithmetic and logical operations, pipelined operations on data from external devices / chips). In some embodiments, logic circuitry 2502 may be configured to control I / O access to data without performing any operations on the data. In some embodiments, logic circuitry 2502 may implement an IC configured to perform I / O control on data stored in memory 2504, assemble data from memory 2504 for transfer (e.g., via a central bus) to devices / chips located inside or outside processing device 2500. In some embodiments, logic circuitry 2502 may be configured to perform any operations on data other than I / O and assembly to facilitate transfer to memory 2504.

[0115] Processing device 2500 may include memory 2504, which may include one or more ICs configured to implement memory circuitry (e.g., ICs implementing one or more of the following: memory devices, memory arrays, control logic configured to control memory devices and arrays, etc.). In some embodiments, memory 2404 may be substantially as described above. Figure 8 The memory 2504 is implemented as described in [the original text]. In some embodiments, the memory 2504 may be a designated means configured to provide storage functionality (e.g., local) to components of the processing device 2500, while the memory 2404 may be configured to provide system-level storage functionality (e.g., global) to the entire computing device 2400. In some embodiments, the memory 2504 may include a memory that shares a die with the logic circuitry 2502.

[0116] Processing device 2500 may include communication device 2506, which may be substantially as described above for communication chip 2406 ( Figure 8 The communication device 2506 is implemented as described in the description. In some embodiments, the communication device 2506 may be a designated device configured to provide communication functions (e.g., local) to components of the processing device 2500, while the communication chip 2406 may be configured to provide system-level communication functions (e.g., global) to the entire computing device 2400.

[0117] Processing device 2500 may include interconnects 2508, which may include any element or means containing conductive material for providing electrical connections to one or more components of processing device 2500, or to one or more components associated with processing device 2500, or / or for providing electrical connections between various such components. Examples of interconnects 2508 include conductive lines / wiring (sometimes also referred to as “wires” or “metallic wires” or “trenches”) and conductive vias (sometimes also referred to as “vias” or “metallic vias”). In some embodiments, interconnects 2508 may be implemented as described above. Figure 5 The interconnection structure in 2128.

[0118] The processing device 2500 may include a temperature detection device 2510, which can be substantially as described above for... Figure 8 Temperature detection device 2510 is implemented as described in temperature detection device 2426, but temperature detection device 2510 is configured to determine temperature, for example, with respect to a more local scale, of processing device 2500 or its components. In some embodiments, temperature detection device 2510 may be a designated device configured to provide temperature detection functionality (e.g., local) to components of processing device 2500, while temperature detection device 2426 may be configured to provide system-level temperature detection functionality (e.g., global) to the entire computing device 2400.

[0119] The processing device 2500 may include a temperature regulating device 2512, which can be substantially as described above for... Figure 8 Temperature regulation device 2512 is implemented as described in temperature regulation device 2428, but temperature regulation device 2512 is configured to regulate temperature at a more local scale, for example, with respect to processing device 2500 or its components. In some embodiments, temperature regulation device 2512 may be a designated device configured to provide temperature regulation functionality (e.g., local) to components of processing device 2500, while temperature regulation device 2428 may be configured to provide system-level temperature regulation functionality (e.g., global) to the entire computing device 2400.

[0120] Processing device 2500 may include battery / power circuitry 2514, which can be substantially as described above for... Figure 8 The battery / power circuit 2514 is implemented as described in the battery / power circuit 2410. In some embodiments, the battery / power circuit 2514 may be a designated device configured to provide battery / power functionality (e.g., local) to components of the processing device 2500, while the battery / power circuit 2410 may be configured to provide system-level battery / power functionality (e.g., global) to the entire computing device 2400.

[0121] Processing device 2500 may include hardware security device 2516, which can be substantially as described above for... Figure 8 The hardware security device 2516 is implemented as described in the secure interface device 2424. In some embodiments, the hardware security device 2516 may be a physical computing device configured to protect and manage digital keys, perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, the hardware security device 2516 may include one or more secure cryptographic processor chips.

[0122] The following paragraphs provide examples of the various embodiments disclosed herein.

[0123] Example 1 provides an IC structure comprising: a nanoribbon comprising a semiconductor material; a transistor comprising a channel portion, a first region, and a second region, wherein: the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon and has a positive side and a back side, the first region and the second region are at opposite ends of the channel portion, one of the first region and the second region is a source region of the transistor, and the other of the first region and the second region is a drain region of the transistor; a contact structure electrically contacts the first region (e.g., is directly electrically connected to the first region), the contact structure comprising a conductive material (e.g., a conductive filler material 364); and a capacitor electrically contacts the second region (e.g., is directly electrically connected to the second region), wherein the contact structure is located on the positive side of the channel portion, and the capacitor is located on the back side of the channel portion.

[0124] Example 2 provides an IC structure according to Example 1, wherein: the capacitor includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator, the first capacitor electrode is in conductive contact with a second region, and the capacitor insulator separates the first capacitor electrode and the second capacitor electrode.

[0125] Example 3 provides an IC structure according to Example 2, which also includes a region comprising metal and silicon (e.g., metal silicide) at the interface between the first capacitor electrode and the second region.

[0126] Example 4 provides an IC structure according to any one of Examples 2-3, further comprising a first insulating material at the back side of the channel portion; and two or more vias extending through the first insulating material, wherein: a first capacitor electrode comprises a first conductive material lining the sidewalls and bottom of the two or more vias; a capacitor insulator comprises a second insulating material lining the sidewalls and bottom of the two or more vias lining the first conductive material; and a second capacitor electrode comprises a second conductive material that at least partially fills the remaining space of the two or more vias lining the first conductive material and the second insulating material.

[0127] Example 5 provides an IC structure according to Example 4, further comprising: a portion of first conductive material between two or more vias, wherein the portion of first conductive material between two or more vias is materially continuous with the first conductive material lining the sidewalls and bottom of the two or more vias.

[0128] Example 6 provides an IC structure according to any one of Examples 4-5, wherein, in a top view of the IC structure, individual vias among two or more vias are substantially circular.

[0129] Example 7 provides an IC structure according to any of Examples 4-5, wherein, in a top view of the IC structure, individual vias among two or more vias are substantially rectangular.

[0130] Example 8 provides an IC structure according to any one of Examples 4-5, wherein, in a top view of the IC structure, individual vias of two or more vias are substantially hexagonal.

[0131] Example 9 provides an IC structure according to any one of Examples 1-8, further comprising: a region including metal and silicon (e.g., metal silicide) at the interface between the conductive material of the contact structure and the first region.

[0132] Example 10 provides an IC structure according to any one of Examples 1-9, wherein: the nanoribbon is one of a plurality of nanoribbons stacked one on top of the other, and the channel portion of the transistor includes portions of semiconductor material of the plurality of nanoribbons.

[0133] Example 11 provides an IC package including: an IC die including an IC structure; and another IC component coupled to the IC die, wherein the IC die includes: a nanoribbon including a semiconductor material; a transistor including a channel portion, a first region, and a second region, wherein: the channel portion of the transistor includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side, the channel portion being between the first region and the second region, one of the first region and the second region being a source region of the transistor, and the other of the first region and the second region being a drain region of the transistor; a contact structure electrically contacting (e.g., directly electrically connected to the first region), the contact structure including a conductive material (e.g., conductive filler material 364); and a capacitor electrically contacting (e.g., directly electrically connected to the second region), wherein the capacitor is located on the back side of the channel portion.

[0134] Example 12 provides an IC package according to Example 11, wherein the contact structure is on the positive side of the channel portion.

[0135] Example 13 provides an IC package according to any one of Examples 11-12, wherein: the capacitor includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator, the first capacitor electrode is in conductive contact with a second region, the capacitor insulator separates the first capacitor electrode and the second capacitor electrode, and the capacitor insulator includes FE or AFE material.

[0136] Example 14 provides an IC package according to Example 13, wherein the FE or AFE material comprises at least 5% of a material in an orthorhombic or tetragonal phase, the material comprising one or more of the following: a material comprising hafnium, zirconium and oxygen; a material comprising silicon, hafnium and oxygen; a material comprising germanium, hafnium and oxygen; a material comprising aluminum, hafnium and oxygen; a material comprising yttrium, hafnium and oxygen; a material comprising lanthanum, hafnium and oxygen; a material comprising gadolinium, hafnium and oxygen; and a material comprising niobium, hafnium and oxygen.

[0137] Example 15 provides an IC package according to any one of Examples 11-14, further comprising: an insulating material that at least partially surrounds the IC die and another IC component.

[0138] Example 16 provides an IC package according to any one of Examples 11-15, wherein another IC component includes a package substrate.

[0139] Example 17 provides an IC package according to any one of Examples 11-15, wherein another IC component includes an interposer layer.

[0140] Example 18 provides an IC package according to any one of Examples 11-15, wherein another IC component includes another IC die.

[0141] Example 19 provides a method for manufacturing an IC structure, the method comprising: fabricating a transistor on the front side of a substrate, the transistor comprising: a nanoribbon comprising a semiconductor material, wherein a channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon; a first region and a second region, wherein one of the first region and the second region is a source region of the transistor, and the other of the first region and the second region is a drain region of the transistor; fabricating a contact structure on the front side of the substrate, wherein a conductive material of the contact structure is in conductive contact with the first region (e.g., directly electrically connected to the first region); and fabricating a capacitor on the back side of the substrate, wherein the capacitor is in conductive contact with the second region (e.g., directly electrically connected to the second region).

[0142] Example 20 provides a method according to Example 19, further comprising: replacing at least a portion of the back side of the substrate with an insulating material prior to manufacturing the capacitor.

[0143] Example 21 provides a method according to any one of Examples 19-20, wherein the IC structure is an IC structure according to any one of Examples 1-10.

[0144] Example 22 provides a computing structure including: a carrier substrate and an IC structure coupled to the carrier substrate, wherein the IC structure is an IC structure according to any one of Examples 1-10, or the IC structure is included in an IC package according to any one of Examples 11-18.

[0145] Example 23 provides a computing architecture based on Example 22, wherein the computing architecture is a wearable or handheld computing architecture.

[0146] Example 24 provides a computing architecture based on Example 22 or 23, wherein the computing architecture also includes one or more communication chips.

[0147] Example 25 provides a computational structure based on any one of Examples 22-24, wherein the computational structure also includes an antenna.

[0148] Example 26 provides a computational structure based on any one of Examples 22-25, where the carrier substrate is a mother plate.

[0149] Example 27 provides an IC structure according to any one of Examples 1-10, wherein the IC structure includes a central processing unit or a part thereof.

[0150] Example 28 provides an IC structure according to any one of Examples 1-10 or Example 27, wherein the IC structure includes a memory structure or a part of a memory structure.

[0151] Example 29 provides an IC structure based on any one of Examples 1-10 or Examples 27-28, wherein the IC structure includes or is a part of a logic circuit.

[0152] Example 30 provides an IC structure according to any one of Examples 1-10 or Examples 27-29, wherein the IC structure includes input / output circuitry or a portion thereof.

[0153] Example 31 provides an IC structure according to any one of Examples 1-10 or Examples 27-30, wherein the IC structure includes a field-programmable gate array transceiver or a portion thereof.

[0154] Example 32 provides an IC structure according to any one of Examples 1-10 or any one of Examples 27-31, wherein the IC structure includes field-programmable gate array logic or a portion thereof.

[0155] Example 33 provides an IC structure according to any one of Examples 1-10 or any one of Examples 27-32, wherein the IC structure includes a power delivery circuit or a part of a power delivery circuit.

[0156] The above description of the embodiments shown in this disclosure (including the content described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the above detailed description.

Claims

1. An integrated circuit (IC) structure, comprising: Nanoribbons, wherein the nanoribbons comprise semiconductor materials; A transistor, the transistor comprising a channel portion, a first region, and a second region, wherein: The channel portion of the transistor includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side. The first region and the second region are located at opposite ends of the channel portion. One of the first region and the second region is the source region of the transistor, and The other of the first and second regions is the drain region of the transistor; A contact structure, wherein the contact structure is in conductive contact with the first region, the contact structure comprising a conductive material; and A capacitor that makes conductive contact with the second region, wherein the contact structure is located on the positive side of the channel portion and the capacitor is located on the back side of the channel portion.

2. The integrated circuit structure according to claim 1, wherein: The capacitor includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator. The first capacitor electrode is in conductive contact with the second region, and The capacitor insulator separates the first capacitor electrode and the second capacitor electrode.

3. The integrated circuit structure according to claim 2, further comprising: The region comprising metal and silicon at the interface between the first capacitor electrode and the second region.

4. The integrated circuit structure according to claim 2 or 3, further comprising: The first insulating material at the back side of the channel portion; as well as Extending through two or more vias in the first insulating material, in: The first capacitor electrode includes a first conductive material, which lines the sidewalls and bottom of the two or more vias. The capacitor insulator includes a second insulating material, the second insulating material lining the sidewalls and bottom of the two or more through-holes, and... The second capacitor electrode includes a second conductive material that at least partially fills the remaining space of the two or more vias lined with the first conductive material and the second insulating material.

5. The integrated circuit structure according to claim 4, further comprising: The portion of the first conductive material between the two or more vias, wherein the portion of the first conductive material between the two or more vias is continuous in material with the first conductive material lining the sidewalls and bottom of the two or more vias.

6. The integrated circuit structure according to claim 4, wherein, In a top view of the integrated circuit structure, each of the two or more vias is substantially circular.

7. The integrated circuit structure according to claim 4, wherein, In a top view of the integrated circuit structure, each of the two or more vias is substantially rectangular.

8. The integrated circuit structure according to claim 4, wherein, In a top view of the integrated circuit structure, each of the two or more vias is substantially hexagonal.

9. The integrated circuit structure according to any one of claims 1 to 3, further comprising: The region comprising metal and silicon at the interface between the conductive material of the contact structure and the first region.

10. The integrated circuit structure according to any one of claims 1 to 3, wherein: The nanoribbon is one of multiple nanoribbons stacked one on top of the other, and The channel portion of the transistor includes portions of the semiconductor material of the plurality of nanoribbons.

11. An integrated circuit (IC) package, comprising: Including IC chips with IC structure; as well as Another IC component coupled to the IC die, The IC die includes: Nanoribbons, the nanoribbons comprising semiconductor materials, A transistor, the transistor comprising a channel portion, a first region, and a second region, wherein: The channel portion of the transistor includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side. The channel portion is located between the first region and the second region. One of the first region and the second region is the source region of the transistor, and The other of the first and second regions is the drain region of the transistor. A contact structure, wherein the contact structure is in conductive contact with the first region, the contact structure comprising a conductive material, and A capacitor that is in conductive contact with the second region, wherein the capacitor is located on the back side of the channel portion.

12. The integrated circuit package according to claim 11, wherein, The contact structure is located on the positive side of the channel portion.

13. The integrated circuit package according to claim 11 or 12, wherein: The capacitor includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator. The first capacitor electrode is in conductive contact with the second region. The capacitor insulator separates the first capacitor electrode and the second capacitor electrode, and The capacitor insulator includes ferroelectric (FE) materials or antiferroelectric (AFE) materials.

14. The integrated circuit package according to claim 13, wherein, The ferroelectric (FE) material or the antiferroelectric (AFE) material comprises at least 5% of the material in the orthorhombic or tetragonal phase, and the material comprises one or more of the following: Materials including hafnium, zirconium, and oxygen, Materials including silicon, hafnium, and oxygen. Materials including germanium, hafnium, and oxygen, Materials including aluminum, hafnium, and oxygen. Materials including yttrium, hafnium, and oxygen, Materials including lanthanum, hafnium, and oxygen, Materials including gadolinium, hafnium, and oxygen, and Materials including niobium, hafnium, and oxygen.

15. The integrated circuit package according to claim 11 or 12, further comprising: Insulating material that at least partially surrounds the IC die and the other IC component.

16. The integrated circuit package according to claim 11 or 12, wherein, The other IC component includes a packaging substrate.

17. The integrated circuit package according to claim 11 or 12, wherein, The other IC component includes an interposer layer.

18. The integrated circuit package according to claim 11 or 12, wherein, The other IC component includes another IC die.

19. A method for manufacturing an integrated circuit (IC) structure, the method comprising: A transistor is fabricated on the positive side of a substrate, the transistor comprising: Nanoribbons comprising semiconductor material, wherein the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbons, and A first region and a second region, wherein one of the first region and the second region is the source region of the transistor, and the other of the first region and the second region is the drain region of the transistor; A contact structure is formed on the positive side of the substrate, wherein the conductive material of the contact structure is in conductive contact with the first region; and A capacitor is fabricated on the back side of the substrate, wherein the capacitor is in conductive contact with the second region.

20. The method of claim 19, further comprising: Before manufacturing the capacitor, at least a portion of the back side of the substrate is replaced with an insulating material.

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