Semiconductor memory device

Abstract

A semiconductor memory device includes a first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to the respective first local bit lines, first local bit line multiplexers connected to the respective first local bit lines, and first global bit lines connected to the respective first local bit line multiplexers; a second cell structure located above the first cell structure and including second local bit lines, second memory cells connected to the respective second local bit lines, second local bit line multiplexers connected to the respective second local bit lines, and second global bit lines connected to the second local bit line multiplexers; bit line contacts extending into the second cell structure and connecting the respective first global bit lines and the respective second global bit lines; and a peripheral circuit structure located above the second cell structure and including a sense amplifier connected to the bit line contacts, wherein the first global bit lines and the second global bit lines share the sense amplifier.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device. Background Technology

[0002] To meet consumer demand for superior performance at a lower cost, it may be desirable to increase the integration density of semiconductor memory devices. In the case of semiconductor memory devices, integration density can be a factor that determines product cost, making higher integration density particularly desirable. Summary of the Invention

[0003] For traditional two-dimensional (2D) or planar semiconductor memory devices, the integration density can be determined by the area occupied by a single memory cell, which is largely influenced by the level of fine patterning technology. However, achieving finer patterns may require the use of expensive equipment, which could increase the integration density of 2D semiconductor memory devices, but the achievable integration density remains limited. Therefore, three-dimensional (3D) semiconductor memory devices incorporating memory cells arranged in three dimensions have been proposed.

[0004] This disclosure provides a semiconductor memory device including cell structures, each cell structure including a local bit line multiplexer and sharing a sense amplifier.

[0005] The purposes of this disclosure are not limited to those mentioned herein, and other purposes not expressly stated will be clearly understood by those skilled in the art based on the following description.

[0006] One aspect of this disclosure provides a semiconductor memory device, the semiconductor memory device comprising: a first cell structure, the first cell structure including first local bit lines extending in a vertical direction, first memory cells connected to each of the first local bit lines and arranged in a vertical direction, first local bit line multiplexers electrically connected to each of the first local bit lines, and first global bit lines electrically connected to each of the first local bit line multiplexers; a second cell structure, the second cell structure located on the first cell structure, the second cell structure including second local bit lines extending in a vertical direction, second memory cells connected to each of the second local bit lines and arranged in a vertical direction, second local bit line multiplexers electrically connected to each of the second local bit lines, and second global bit lines electrically connected to the second local bit line multiplexers; bit line contacts penetrating the second cell structure and electrically connecting each of the first global bit lines and each of the second global bit lines; and a peripheral circuit structure located on the second cell structure, the peripheral circuit structure including a sense amplifier electrically connected to the bit line contacts, wherein the first global bit lines and the second global bit lines share the sense amplifier.

[0007] Another aspect of this disclosure provides a semiconductor memory device, the semiconductor memory device comprising: a first cell structure, the first cell structure including a first local bit line extending in a vertical direction on a first insulating layer; a first cell semiconductor pattern disposed in the vertical direction and each having a first end connected to the first local bit line; a first data storage device connected to a second end of the first cell semiconductor pattern; a first cell gate electrode located on the first cell semiconductor pattern; a first logic semiconductor pattern spaced apart from the first cell semiconductor pattern in the vertical direction; a first logic transistor located on the first logic semiconductor pattern and electrically connected to the first local bit line; and a first global bit line electrically connected to the first logic transistor; and a second cell structure, the second cell structure including a second local bit line extending in a vertical direction on a second insulating layer; The system comprises: a second cell semiconductor pattern arranged vertically and each having a second cell semiconductor pattern connected to a first end of a second local bit line; a second data storage device connected to a second end of the second cell semiconductor pattern; a second cell gate electrode located on the second cell semiconductor pattern; a second logic semiconductor pattern spaced vertically from the second cell semiconductor pattern; a second logic transistor located on the second logic semiconductor pattern and electrically connected to the second local bit line; and a second global bit line electrically connected to the second logic transistor; a bit line contact penetrating the second cell structure and electrically connecting the first global bit line and the second global bit line; and a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit transistor located on the peripheral circuit substrate and electrically connected to the first global bit line and the second global bit line.

[0008] Another aspect of this disclosure provides a semiconductor memory device comprising: a first cell structure including a first local bit line extending in a vertical direction, a first memory cell arranged in the vertical direction and connected to each of the first local bit lines, a first global bit line located on the first memory cell, a first local bit line multiplexer electrically connected to the first global bit line and the first local bit line, and a first global bit line multiplexer electrically connected to the first global bit line; a second cell structure including a second local bit line extending in a vertical direction, a second memory cell arranged in the vertical direction and connected to each of the second local bit lines, a second global bit line located on the second memory cell, a second local bit line multiplexer electrically connected to the second global bit line and the second local bit line, and a second global bit line multiplexer electrically connected to the second global bit line; and a peripheral circuit structure located on the second cell structure and including a sense amplifier electrically connected to the first global bit line and the second global bit line.

[0009] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be readily understood from the following description. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more readily understood by referring to the accompanying drawings, which describe exemplary embodiments thereof in detail, in which:

[0011] Figure 1 This is a top view of an example of a semiconductor storage device; Figure 2 It is along Figure 1 A cross-sectional view taken from I-I'; Figure 3 It is along Figure 1 The cross-sectional view taken from section II-II'; Figure 4 This is a cross-sectional view of an example of a semiconductor memory device; Figure 5 This is a cross-sectional view of an example of a semiconductor memory device; Figure 6 It is along Figure 5 A cross-sectional view taken from I-I'; Figure 7 yes Figure 6 Enlarged cross-sectional views of regions A1 and A2 in the middle; Figure 8 It is along Figure 5 A cross-sectional view taken from I-I'; Figure 9 and Figure 10 This is a cross-sectional view of an example of a semiconductor memory device; Figures 11 to 13 This is a top view of an example of a semiconductor storage device; Figures 14 to 37 This is a diagram illustrating an intermediate step in an example method for manufacturing a semiconductor memory device. Detailed Implementation

[0012] Figure 1 This is a top view of a semiconductor memory device according to some embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from I-I'. Figure 3 It is along Figure 1 The cross-sectional view taken from section II-II'.

[0013] The first direction DR1 and the second direction DR2 may be parallel to the front surface of the first insulating layer 140, which will be described later, and may intersect each other (e.g., perpendicularly). The third direction DR3 may be perpendicular to the front surface of the first insulating layer 140, and may be perpendicular to the first direction DR1 and the second direction DR2. The third direction DR3 may be referred to as the vertical direction, the first direction DR1 may be referred to as the first horizontal direction, and the second direction DR2 may be referred to as the second horizontal direction. The front surface of the first insulating layer 140 may refer to the surface of the first insulating layer 140 on which the first memory cell MC1, which will be described later, is arranged.

[0014] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor memory device may include a cell region 1, a word line pad region WPR, and a bit line pad region BPR.

[0015] Cell region 1 may include one or more bit line regions BR, one or more semiconductor regions SR, one or more word line regions WR, one or more capacitor regions CR, and a board region PR. The word line region WR may be located between the bit line region BR and the capacitor region CR. For example, the bit line region BR, the word line region WR, and the capacitor region CR may be arranged along a first direction DR1. The board region PR may be located on one side of each capacitor region in the capacitor region CR. At least a portion of the semiconductor region SR may overlap with the capacitor region CR. At least a portion of the semiconductor region SR may overlap with the word line region WR.

[0016] Word line pad regions WPR can be located on at least one side of cell region 1. For example, cell region 1 can be adjacent to word line pad regions WPR in the second direction DR2. Word line pad regions WPR are illustrated as being spaced apart from word line regions WR only for the purpose of distinguishing these regions, and they can be connected to word line regions WR. In some embodiments, the semiconductor device may include multiple word line pad regions WPR. For example, multiple word line pad regions WPR can be located on both sides of cell region 1 in the second direction DR2.

[0017] A semiconductor memory device according to some embodiments may include multiple bit line regions BR, multiple word line regions WR, and multiple capacitor regions CR. The bit line regions BR, word line regions WR, semiconductor regions SR, and capacitor regions CR may be arranged symmetrically relative to a board region PR. In some embodiments, the semiconductor memory device may include multiple board regions PR. In this case, on both sides of each of the multiple board regions PR, the bit line regions BR, semiconductor regions SR, word line regions WR, and capacitor regions CR may be arranged symmetrically relative to the corresponding board region PR. The capacitor regions CR are illustrated as being spaced apart from the board regions PR only for the purpose of distinguishing these regions, and the board regions PR may be connected to the capacitor regions CR located on either side thereof.

[0018] According to some embodiments, a semiconductor memory device may include a first cell structure CS1, a second cell structure CS2, and a peripheral circuit structure PR.

[0019] The first unit structure CS1 may include a first insulating layer 140, a first local bit line LBL1, a first memory cell MC1, a first wiring insulating layer 180, a first wiring 182, a first path 186, a first global bit line GBL1, and a first logic transistor LTR1.

[0020] The first local bit line LBL1 can be located in each bit line region BR. The first local bit lines LBL1 can be spaced apart from each other in the second direction DR2 within each bit line region BR. The first local bit lines LBL1 can each extend in the third direction DR3.

[0021] The first memory cell MC1 arranged on the third direction DR3 can be connected to each of the first local bit lines LBL1. The first memory cells MC1 arranged on the third direction DR3 can be collectively connected to the first local bit line LBL1. The first memory cells MC1 can be spaced apart from each other in a single layer on the first direction DR1 and the second direction DR2. The first memory cells MC1 adjacent on the first direction DR1 can have a symmetrical structure with respect to the vertical portion of the second conductive layer 176b extending on the third direction DR3. Conversely, in some embodiments, the first memory cells MC1 adjacent on the first direction DR1 and having a symmetrical structure with respect to the vertical portion of the second conductive layer 176b can also be spaced apart from each other on the first direction DR1.

[0022] Each of the first storage cells MC1 may include a first cell transistor CTR1 and a first data storage device 170 connected to each other.

[0023] The first unit transistor CTR1 may each include a first unit semiconductor pattern SP1, a first unit gate electrode GE1, and a first unit gate insulating film GI1.

[0024] First unit semiconductor patterns SP1 can be stacked on a third-direction DR3 while being spaced apart from each other on the first insulating layer 140. First local bit lines LBL1 can each be connected to the stack of the first unit semiconductor patterns SP1 on the third-direction DR3. Each of the first unit semiconductor patterns SP1 can extend in a first direction DR1. The stack of the first unit semiconductor patterns SP1 on the third-direction DR3 can be arranged on the first direction DR1 and the second direction DR2.

[0025] The first unit semiconductor pattern SP1 may each include a first source / drain region, a second source / drain region, and a channel region located between the first source / drain region and the second source / drain region. A first end of the first unit semiconductor pattern SP1 on the first direction DR1 may correspond to the first source / drain region, and a second end of the first unit semiconductor pattern SP1 on the first direction DR1 may correspond to the second source / drain region. The first source / drain region and the second source / drain region may be regions doped with n-type or p-type impurities. The first end of the first unit semiconductor pattern SP1 on the first direction DR1 may be connected to the first local bit line LBL1, and the second end of the first unit semiconductor pattern SP1 on the first direction DR1 may be connected to the first data storage device 170.

[0026] The first cell gate electrode GE1 may be located in each word line region WR. The first cell gate electrodes GE1 may be stacked on a third direction DR3 while being spaced apart from each other. The first cell gate electrodes GE1 may be located on at least a portion of the outer peripheral surface of each first cell semiconductor pattern SP1. The first cell gate electrodes GE1 may each extend in a second direction DR2. The first cell gate electrodes GE1 may extend in the second direction DR2 while passing through the first semiconductor pattern SP1 within a single layer.

[0027] The first unit gate insulating film GI1 can be located between the first unit gate electrode GE1 and the first unit semiconductor pattern SP1. The first unit gate electrode GE1 can be spaced apart from the first unit semiconductor pattern SP1 by the first unit gate insulating film GI1.

[0028] The first unit insulating layer 132 may be located on the first insulating layer 140. The first unit insulating layer 132 may be located between the first unit semiconductor patterns SP1 and between the first unit gate electrodes GE1.

[0029] The first data storage device 170 can be disposed in the capacitor region CR and the plate region PR. The first data storage device 170 can be located on the first cell semiconductor pattern SP1 and the first cell insulating layer 132. The first data storage device 170 and the first local bit line LBL1 can be located at opposite ends of the first cell semiconductor pattern SP1 in the first direction DR1.

[0030] The first data storage device 170 and the second data storage device 270, which will be described later, can be capacitors or variable resistors. The first data storage device 170 and the second data storage device 270 will be described below using a capacitor as an example. The first data storage device 170 may each include a first storage electrode 172, a first plate electrode 176, and a first dielectric layer 174 located between the first storage electrode 172 and the first plate electrode 176. Each of the first data storage devices 170 may be defined by a respective first storage electrode 172.

[0031] The first storage electrode 172 may contact the end of the first unit semiconductor pattern SP1. For example, the length of the first storage electrode 172 in the second direction DR2 and the third direction DR3 may be the same as the length of the first unit semiconductor pattern SP1 in the second direction DR2 and the third direction DR3, respectively.

[0032] The first dielectric layer 174 may cover the entire surface of the first storage electrode 172 except for the portion that contacts the first cell semiconductor pattern SP1. The first dielectric layer 174 may extend along the upper and lower surfaces of the first storage electrode 172, and along the side surface of the first storage electrode 172 facing the first plate electrode 176. The first dielectric layer 174 may extend along the upper surface of the first insulating layer 140 and the side surface of the first cell insulating layer 132 between adjacent first storage electrodes 172 on the third-direction DR3.

[0033] Each of the first plate electrodes 176 may include a first conductive layer 176a and a second conductive layer 176b. The first conductive layer 176a may be located on each of the first dielectric layers 174. The first conductive layer 176a may extend along the first dielectric layer 174. The second conductive layer 176b may be located on the first conductive layer 176a. Each of the second conductive layers 176b may include a vertical portion perpendicular to the upper surface of the first insulating layer 140 and a horizontal portion parallel to the upper surface of the first insulating layer 140. The horizontal portion of the second conductive layer 176b may protrude from the vertical portion of the second conductive layer 176b in a first direction DR1 and may be surrounded by the first dielectric layer 174 and the first conductive layer 176a. The vertical portion of the second conductive layer 176b may be arranged in the plate region PR.

[0034] The first logic transistor LTR1 may be located on the first memory cell MC1. In some embodiments, the first logic transistor LTR1 may be formed on the first cell insulating layer 132. Each of the first logic transistors LTR1 may include a first logic semiconductor pattern LSP1, a first logic gate electrode LGE1, a first logic gate insulating film LGI1, and a first logic gate spacer LGS1.

[0035] The first logic semiconductor pattern LSP1 can be arranged in each semiconductor region SR. The first logic semiconductor pattern LSP1 and the first insulating pattern 133 can be located on the first unit insulating layer 132. The first logic semiconductor pattern LSP1 can be defined by the first insulating pattern 133. The first logic semiconductor patterns LSP1 can be spaced apart from each other by the first insulating pattern 133.

[0036] The first logic semiconductor pattern LSP1 may include the same material as the first cell semiconductor pattern SP1. On the third-party DR3, the thickness of the first logic semiconductor pattern LSP1 may be greater than the thickness of the first cell semiconductor pattern SP1.

[0037] The first logic gate electrode LGE1 may be located on the first logic semiconductor pattern LSP1. The first logic gate insulating film LGI1 may be located between the first logic semiconductor pattern LSP1 and the first logic gate electrode LGE1. The first logic gate spacer LGS1 may be located on the sidewall of the first logic gate electrode LGE1 and the sidewall of the first logic gate insulating film LGI1. The first source / drain region and the second source / drain region may be disposed adjacent to both sides of the first logic gate electrode LGE1 in the first logic semiconductor pattern LSP1.

[0038] The first interlayer insulating layer 134 may be located on the first logic semiconductor pattern LSP1 and the first insulating pattern 133. The first interlayer insulating layer 134 may cover the first logic transistor LTR1.

[0039] The first logic gate contact 166 can penetrate the first interlayer insulating layer 134 to contact the first logic gate electrode LGE1. The first source / drain contact 168 can contact the first source / drain region and the second source / drain region in the first logic semiconductor pattern LSP1 that are adjacent to both sides of the first logic gate electrode LGE1.

[0040] The first local access line LBL1 can penetrate the first unit insulating layer 132, the first insulating pattern 133, and the first interlayer insulating layer 134. The first plate electrode 176 and the first dielectric layer 174 can extend into the first insulating pattern 133 and the first interlayer insulating layer 134.

[0041] The first wiring insulating layer 180 may be located on the first interlayer insulating layer 134. The first wiring 182 and the first path 186 may be arranged in the first interlayer insulating layer 134. The first wiring 182 and the first path 186 may be electrically connected to the first logic gate contact 166 and the first source / drain contact 168. The number, arrangement, and interconnection of the first wiring 182 and the first path 186 may vary.

[0042] A first global bit line GBL1 may be disposed within a first wiring insulation layer 180. The first global bit lines GBL1 may be spaced apart in a second direction DR2. Each of the first global bit lines GBL1 may be electrically connected to a plurality of first local bit lines LBL1. Each of the first global bit lines GBL1 may extend in a first direction DR1 and be electrically connected to a plurality of first local bit lines LBL1 spaced apart in the first direction DR1. The first global bit lines GBL1 are illustrated as being located in the uppermost layer of the first wiring insulation layer 180. In some embodiments, the first wiring 182 and the first passage 186 may be located above the first global bit lines GBL1.

[0043] The first local bit line LBL1 can be directly connected to the first memory cell MC1, and the first global bit line GBL1 can be connected to the first local bit line LBL1 through the first wiring 182, the first path 186 and the first logic transistor LTR1.

[0044] One or more first logic transistors LTR1 can be connected between a first global bit line GBL1 and a first local bit line LBL1. For example, the first source / drain region of the first logic transistor LTR1 can be connected to the first local bit line LBL1 through a first source / drain contact 168, a first path 186, and a first wiring 182, while the second source / drain region of the first logic transistor LTR1 can be connected to the first global bit line GBL1 through the first source / drain contact 168, the first path 186, and the first wiring 182. The first logic transistor LTR1 can be configured to connect one or more selected first local bit lines LBL1 to the first global bit line GBL1. The first logic transistor LTR1 can form a first local bit line multiplexer. The first logic transistor LTR1 can be referred to as a first local bit line multiplexer.

[0045] The second cell structure CS2 can be located on the first cell structure CS1. The second cell structure CS2 may include a second insulating layer 240, a second local bit line LBL2, a second memory cell MC2, a second wiring insulating layer 280, a second wiring 282, a second path 286, a second global bit line GBL2, a second logic transistor LTR2, a first bonding insulating layer 290, and a first bonding pad 292.

[0046] The second insulating layer 240 may be located on the first unit structure CS1. The second insulating layer 240 may be located on the first wiring insulating layer 180. The first insulating layer 140 and the second insulating layer 240 may each comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0047] The second local bit line LBL2 can be located within the bit line region BR. Within the bit line region BR, the second local bit lines LBL2 can be spaced apart from each other in the second direction DR2. Each of the second local bit lines LBL2 can extend in the third direction DR3. The second local bit lines LBL2 can overlap with the first local bit line LBL1 in the third direction DR3.

[0048] In some examples, the first local bit line LBL1 and the second local bit line LBL2 may each include at least one conductive material, such as a doped semiconductor material (e.g., doped silicon, doped silicon germanium, doped germanium), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a metal (e.g., tungsten, titanium, tantalum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide).

[0049] Second memory cells MC2 arranged along the third direction DR3 can be connected to individual second local bit lines LBL2. Second memory cells MC2 arranged along the third direction DR3 can also be collectively connected to the second local bit lines LBL2. Second memory cells MC2 can be spaced apart within a single layer along the first direction DR1 and the second direction DR2. Adjacent second memory cells MC2 along the first direction DR1 can have a symmetrical structure relative to the vertical portion of the fourth conductive layer 276b. Conversely, in some embodiments, second memory cells MC2 adjacent along the first direction DR1 and having a symmetrical structure relative to the vertical portion of the fourth conductive layer 276b can be spaced apart from each other along the first direction DR1.

[0050] The second storage unit MC2 may each include a second unit transistor CTR2 and a second data storage device 270, and the second unit transistor CTR2 and the second data storage device 270 are connected to each other.

[0051] The second unit transistor CTR2 may each include a second unit semiconductor pattern SP2, a second unit gate electrode GE2, and a second unit gate insulating film GI2.

[0052] The second unit semiconductor patterns SP2 can be stacked along a third direction DR3 while being spaced apart from each other on the second insulating layer 240. Second local bit lines LBL2 can each be connected to the stack of the second unit semiconductor patterns SP2 on the third direction DR3. The second unit semiconductor patterns SP2 can extend on a first direction DR1. The stack of the second unit semiconductor patterns SP2 on the third direction DR3 can be arranged on the first direction DR1 and the second direction DR2. The second unit semiconductor patterns SP2 can overlap with the first unit semiconductor pattern SP1 on the third direction DR3.

[0053] The second semiconductor pattern SP2 may each include a first source / drain region, a second source / drain region, and a channel region located between the first and second source / drain regions. A first end of the second semiconductor pattern SP2 on the first direction DR1 may correspond to the first source / drain region, and a second end of the second semiconductor pattern SP2 on the first direction DR1 may correspond to the second source / drain region. The first and second source / drain regions may be regions doped with n-type or p-type impurities. The first end of the second semiconductor pattern SP2 on the first direction DR1 may be connected to the second local bit line LBL2, and the second end of the second semiconductor pattern SP2 on the first direction DR1 may be connected to the second data storage device 270.

[0054] The first unit semiconductor pattern SP1 and the second unit semiconductor pattern SP2 may each include at least one of single-crystal semiconductors, polycrystalline semiconductors, oxide semiconductors, and two-dimensional materials. For example, the single-crystal semiconductor may be single-crystal silicon. The polycrystalline semiconductor may be polycrystalline silicon. In some examples, the oxide semiconductor may be selected from InGaZnO (IGZO), Sn-IGZO, InWO (IWO), InZnO (IZO), ZnSnO (ZTO), ZnO, yttrium-doped zinc oxide (YZO), InGaSiO (IGSO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, or ZrZnSnO. In some embodiments, the two-dimensional semiconductor may include a transition metal chalcogenide compound or a bipolar semiconductor material that utilizes electrons and holes as driving charges. In some examples, the two-dimensional semiconductor material may be selected from MoS2, MoSe2, WS2, NbS2, TaS2, ZrS2, HfS2, TcS2, ReS2, CuS2, GaS2, InS2, SnS2, GeS2, PbS2, WSe2, NbSe2, TaSe2, ZrSe2, HfSe2, TcSe2, ReSe2, CuSe2, GaSe2, InSe2, SnSe2, GeSe2, PbSe2, MoTe2, WTe2, NbTe2, TaTe2, ZrTe2, HfTe2, TcTe2, ReTe2, CuTe2, GaTe2, InTe2, SnTe2, GeTe2, or PbTe2.

[0055] In some embodiments, the first unit transistor CTR1 and the second unit transistor CTR2 may be gate-all-around transistors (GAA transistors). The first unit gate electrode GE1 may surround the channel region of the first unit semiconductor pattern SP1, and the second unit gate electrode GE2 may surround the channel region of the second unit semiconductor pattern SP2. The first unit gate electrode GE1 may surround the outer peripheral surface of the channel region of the first unit semiconductor pattern SP1, and the second unit gate electrode GE2 may surround the outer peripheral surface of the channel region of the second unit semiconductor pattern SP2. The first unit gate electrode GE1 may extend in the second direction DR2 and surround the channel regions of the first unit semiconductor pattern SP1 spaced apart along the second direction DR2 at the same height. The second unit gate electrode GE2 may extend in the second direction DR2 and surround the channel regions of the second unit semiconductor pattern SP2 spaced apart along the second direction DR2 at the same height.

[0056] Contrary to the illustration, in some embodiments, the first unit transistor CTR1 and the second unit transistor CTR2 may each have a dual-gate transistor structure. The first unit gate electrode GE1 may be located on opposite sidewalls of the channel region of the first unit semiconductor pattern SP1 (e.g., on opposite sidewalls of the third-direction DR3) spaced apart from each other, and the second unit gate electrode GE2 may be located on opposite sidewalls of the channel region of the second unit semiconductor pattern SP2 (e.g., on opposite sidewalls of the third-direction DR3) spaced apart from each other.

[0057] In some embodiments, the first unit gate electrode GE1 may be located on a sidewall of the corresponding first unit semiconductor pattern SP1, and the second unit gate electrode GE2 may be located on a sidewall of the corresponding second unit semiconductor pattern SP2.

[0058] In some examples, the first unit gate electrode GE1 and the second unit gate electrode GE2 may each comprise at least one conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0059] The cell gate contact can be arranged in the word line pad area WPR. The cell gate contact can contact the first cell gate electrode GE1 or the second cell gate electrode GE2.

[0060] The second unit gate insulating film GI2 may be located between the second unit gate electrode GE2 and the second unit semiconductor pattern SP2. The second unit gate electrode GE2 may be spaced apart from the second unit semiconductor pattern SP2 by the second unit gate insulating film GI2. The first unit gate insulating film GI1 and the second unit gate insulating film GI2 may each include at least one of, for example, a high-k insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0061] The second unit insulating layer 232 may be located on the second insulating layer 240. The second unit insulating layer 232 may be located between the second unit semiconductor patterns SP2 and between the second unit gate electrodes GE2. The first unit insulating layer 132 and the second unit insulating layer 232 may each include an insulating material, such as at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a carbon-containing silicon oxide film, a silicon carbonitride film, or a silicon carbonitride film. For example, the first unit insulating layer 132 and the second unit insulating layer 232 may each include a silicon oxide film.

[0062] The second data storage device 270 can be disposed in the capacitor region CR and the plate region PR. The second data storage device 270 can be located on the second cell semiconductor pattern SP2 and the second cell insulating layer 232. The second data storage device 270 and the second local bit line LBL2 can be located at opposite ends of the second cell semiconductor pattern SP2 in the first direction DR1. Each of the second data storage devices 270 can include a second storage electrode 272, a second plate electrode 276, and a second dielectric layer 274 located between the second storage electrode 272 and the second plate electrode 276. Each of the second data storage devices 270 can be defined by a respective second storage electrode 272.

[0063] The second storage electrode 272 can contact the second end of the second unit semiconductor pattern SP2. For example, the length of the second storage electrode 272 in the second direction DR2 and the third direction DR3 can be the same as the length of the second unit semiconductor pattern SP2 in the second direction DR2 and the third direction DR3, respectively.

[0064] The second dielectric layer 274 may cover the entire surface of the second storage electrode 272 except for the portion that contacts the second cell semiconductor pattern SP2. The second dielectric layer 274 may extend along the upper and lower surfaces of the second storage electrode 272, and along the side surface of the second storage electrode 272 facing the second plate electrode 276. The second dielectric layer 274 may extend along the upper surface of the second insulating layer 240 and the side surface of the second cell insulating layer 232 between adjacent second storage electrodes 272 on the third-direction DR3.

[0065] The second plate electrode 276 may each include a third conductive layer 276a and a fourth conductive layer 276b. The third conductive layer 276a may extend along the second dielectric layer 274. The fourth conductive layer 276b may be located on each of the third conductive layers 276a. The fourth conductive layer 276b may each include a vertical portion perpendicular to the upper surface of the second insulating layer 240 (e.g., along a third direction DR3) and a horizontal portion parallel to the upper surface of the second insulating layer 240 (e.g., along a first direction DR1). The horizontal portion of the fourth conductive layer 276b may protrude from the vertical portion of the fourth conductive layer 276b in the first direction DR1 and may be surrounded by the second dielectric layer 274 and the third conductive layer 276a. The vertical portion of the fourth conductive layer 276b may be located in the plate region PR.

[0066] The first storage electrode 172, the second storage electrode 272, the first plate electrode 176, and the second plate electrode 276 may each comprise a conductive material. In some cases, the first storage electrode 172, the second storage electrode 272, the first plate electrode 176, and the second plate electrode 276 may each comprise at least one of, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide). For example, the first conductive layer 176a and the third conductive layer 276a may each comprise the same material as the first storage electrode 172 and the second storage electrode 272, while the second conductive layer 176b and the fourth conductive layer 276b may comprise materials different from the first conductive layer 176a, the third conductive layer 276a, the first storage electrode 172, and the second storage electrode 272. In one example, the first storage electrode 172, the second storage electrode 272, and the first conductive layer 176a and the third conductive layer 276a may include titanium nitride, while the second conductive layer 176b and the fourth conductive layer 276b may include doped silicon germanium.

[0067] The first dielectric layer 174 and the second dielectric layer 274 may each comprise, for example, a high-k material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, or combinations thereof). In a semiconductor memory device according to some embodiments, the first dielectric layer 174 may have a stacked structure of zirconium oxide, aluminum oxide, and zirconium oxide stacked sequentially. In some embodiments, the first dielectric layer 174 and the second dielectric layer 274 may each comprise hafnium (Hf).

[0068] The second logic transistor LTR2 may be located on the second memory cell MC2. In some embodiments, the second logic transistor LTR2 may be formed on the second cell insulating layer 232. Each of the second logic transistors LTR2 may include a second logic semiconductor pattern LSP2, a second logic gate electrode LGE2, and a second logic gate insulating film LGI2.

[0069] The second logic semiconductor pattern LSP2 can be located in each semiconductor region SR. The second logic semiconductor pattern LSP2 and the second insulating pattern 233 can be located on the second unit insulating layer 232. The second logic semiconductor pattern LSP2 can be defined by the second insulating pattern 233. The second logic semiconductor patterns LSP2 can be spaced apart from each other by the second insulating pattern 233. The second logic semiconductor pattern LSP2 can overlap with the first logic semiconductor pattern LSP1 on the third direction DR3.

[0070] The second logic semiconductor pattern LSP2 may include the same material as the second cell semiconductor pattern SP2. On the third-party DR3, the thickness of the second logic semiconductor pattern LSP2 may be greater than the thickness of the second cell semiconductor pattern SP2.

[0071] The second logic gate electrode LGE2 can be located on the second logic semiconductor pattern LSP2. The second logic gate insulating film LGI2 can be located between the second logic semiconductor pattern LSP2 and the second logic gate electrode LGE2. The second logic gate spacer LGS2 can be located on the sidewalls of the second logic gate electrode LGE2 and the sidewalls of the second logic gate insulating film LGI2. The first source / drain region and the second source / drain region can be located adjacent to both sides of the second logic gate electrode LGE2 in the second logic semiconductor pattern LSP2.

[0072] In some examples, the first logic gate electrode LGE1 and the second logic gate electrode LGE2 may each comprise at least one conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. The first logic gate insulating film LGI1 and the second logic gate insulating film LGI2 may each comprise at least one of, for example, a high-k insulating film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first logic gate spacer LGS1 and the second logic gate spacer LGS2 may each comprise at least one of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0073] The second interlayer insulating layer 234 may be located on the second logic semiconductor pattern LSP2 and the second insulating pattern 233. The second interlayer insulating layer 234 may cover the second logic transistor LTR2.

[0074] The second logic gate contact 266 can penetrate the second interlayer insulating layer 234 and contact the second logic gate electrode LGE2. The second source / drain contact 268 can contact the source / drain regions in the second logic semiconductor pattern LSP2 that are adjacent to both sides of the second logic gate electrode LGE2.

[0075] The second local bit line LBL2 can penetrate the second unit insulating layer 232, the second insulating pattern 233, and the second interlayer insulating layer 234. The second plate electrode 276 and the second dielectric layer 274 can extend into the second insulating pattern 233 and the second interlayer insulating layer 234.

[0076] The second wiring insulating layer 280 may be located on the second unit insulating layer 232. The second wiring 282 and the second path 286 may be located within the second unit insulating layer 232. The second wiring 282 and the second path 286 may be electrically connected to the second logic gate contact 266 and the second source / drain contact 268. The number, arrangement, and interconnection of the second wiring 282 and the second path 286 may vary.

[0077] The second global bit line GBL2 may be located within the second wiring insulation layer 280. The second global bit lines GBL2 may be spaced apart in the second direction DR2. Each of the second global bit lines GBL2 may be electrically connected to a plurality of second local bit lines LBL2. Each of the second global bit lines GBL2 may extend in the first direction DR1 and be electrically connected to a plurality of second local bit lines LBL2 spaced apart in the first direction DR1. The second global bit lines GBL2 are illustrated as being located in the uppermost layer of the second wiring insulation layer 280. In some embodiments, the second wiring 282 and the second path 286 may be located above the second global bit lines GBL2.

[0078] The second local bit line LBL2 can be directly connected to the second memory cell MC2, and the second global bit line GBL2 can be connected to the second local bit line LBL2 via the second wiring 282, the second path 286, and the second logic transistor LTR2.

[0079] In some examples, the first global bit line GBL1 and the second global bit line GBL2 may each include a conductive material, such as a doped semiconductor material (e.g., doped silicon, doped silicon germanium, doped germanium), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), a metal (e.g., tungsten, titanium, tantalum), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide).

[0080] One or more second logic transistors LTR2 can be connected between a second global bit line GBL2 and a second local bit line LBL2. For example, the first source / drain region of the second logic transistor LTR2 can be connected to the second local bit line LBL2 via a second source / drain contact 268, a second path 286, and a second wiring 282, while the second source / drain region of the second logic transistor LTR2 can be connected to the second global bit line GBL2 via the second source / drain contact 268, the second path 286, and the second wiring 282. The second logic transistor LTR2 can be configured to connect one or more selected second local bit lines LBL2 to the second global bit line GBL2. The second logic transistor LTR2 can form a second local bit line multiplexer and can be referred to as a second local bit line multiplexer.

[0081] The bit line pad region BPR can be located on at least one side of the cell region 1. In some embodiments, the bit line pad region BPR can be located on one side of the cell region 1 in the first direction DR1. The cell region 1 and the bit line pad region BPR can be adjacent in the first direction DR1. The bit line contact BLC can be located in the bit line pad region BPR.

[0082] In some implementations, the bit line contact BLC can be arranged in a zigzag pattern along the second direction DR2 in the bit line pad region BPR. In some examples, each bit line contact BLC can be alternately offset from the adjacent bit line contact along the second direction DR2 in the bit line pad region BPR.

[0083] The bit line contact BLC can extend on the third-direction DR3. The bit line contact BLC can extend on the third-direction DR3 through the second wiring insulation layer 280, the second interlayer insulation layer 234, the second insulation pattern 233, the second unit insulation layer 232, the second insulation layer 240, and the first wiring insulation layer 180. The bit line contact BLC can electrically connect the first global bit line GBL1 and the second global bit line GBL2.

[0084] A first bonding insulating film 290 may be located on a second wiring insulating layer 280. A first bonding pad 292 may be located within the first bonding insulating film 290. The first bonding pad 292 may be connected to a second path 286. The first bonding pad 292 may be electrically connected to the second wiring 282 and the second path 286. The first bonding pad 292 may be electrically connected to a second global bit line GBL2.

[0085] In some embodiments, the first cell structure CS1 and the second cell structure CS2 can be joined together by bonding the first insulating layer 140 and the second insulating layer 240. The first insulating layer 140 and the second insulating layer 240 can be in contact with each other. In some embodiments, the bit line contact BLC can be in contact with the corresponding first global bit line GBL1 and the corresponding second global bit line GBL2. The first logic transistor LTR1 and the first global bit line GBL1 can be located between the first memory cell MC1 and the second cell structure CS2, while the second logic transistor LTR2 and the second global bit line GBL2 can be located between the second memory cell MC2 and the first cell structure CS1.

[0086] The peripheral circuit structure PR can be located on the second unit structure CS2. The peripheral circuit structure PR may include a substrate 300, peripheral circuit transistors (PTR1 and PTR2), a front insulating layer 380, a front wiring 382, ​​a front pass 386, a second bonding insulating film 390, a second bonding pad 392, a rear insulating layer 320, a rear wiring 322, a rear pass 326, an external connection pad 340, and a through pass 330.

[0087] The substrate 300 may include a front side and a back side on the third-direction DR3. The substrate 300 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate 300 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0088] Device isolation pattern 302 can be formed in substrate 300. Device isolation pattern 302 can be embedded in the front side of substrate 300. Peripheral circuit transistors (PTR1 and PTR2) can be located on the front side of substrate 300. Peripheral circuit transistors (PTR1 and PTR2) can be located on the active region defined by device isolation pattern 302.

[0089] The first peripheral circuit transistor PTR1 can form a sense amplifier and can be referred to as such. The first peripheral circuit transistor PTR1 can be configured to detect and amplify data from the first local bit line LBL1 and the second local bit line LBL2. The second peripheral circuit transistor PTR2 can be a transistor forming various circuits for controlling the first memory cell MC1 and the second memory cell MC2. For example, the second peripheral circuit transistor PTR2 can be a transistor forming a sub-word line driver that provides voltage to the first cell gate electrode GE1 and the second cell gate electrode GE2.

[0090] A front insulating layer 380 may be located on the front side of the substrate 300. Front wiring 382 and front access 386 may be located within the front insulating layer 380. Front access 386 may connect front wiring 382 at different heights. The number, arrangement, and interconnection of front wiring 382 and front access 386 may vary. Front wiring 382 and front access 386 may be electrically connected to peripheral circuit transistors (PTR1 and PTR2). Front access 386 may include pathways connecting to the source / drain regions and gate electrodes of the peripheral circuit transistors (PTR1 and PTR2).

[0091] The second bonding insulating film 390 may be located on the front insulating layer 380. The second bonding pad 392 may be located in the second bonding insulating film 390. The second bonding pad 392 may be connected to the front pass 386. The second bonding pad 392 may be electrically connected to the front wiring 382 and the front pass 386.

[0092] In some embodiments, the second cell structure CS2 and the peripheral circuit structure PR can have a chip-to-chip structure. After fabricating the second cell structure CS2 and the peripheral circuit structure PR, they can be joined together to fabricate a semiconductor memory device according to some embodiments.

[0093] The first bonding pad 292 and the second bonding pad 392 can be bonded together. As a result of the bonding, the second unit structure CS2 and the peripheral circuit structure PR can be electrically connected. The first bonding pad 292 and the second bonding pad 392 can each comprise various metals, such as copper (Cu), aluminum (Al), or tungsten (W). The first bonding insulating film 290 and the second bonding insulating film 390 can be bonded together. The first bonding insulating film 290 and the second bonding insulating film 390 can each comprise an insulating material such as silicon oxide.

[0094] The rear insulating layer 320 may be located on the rear side of the substrate 300. The rear wiring 322 and the rear passage 326 may be located in the rear insulating layer 320. The rear passage 326 may connect the rear wiring 322 located at different heights. The number, arrangement and interconnection of the rear wiring 322 and the rear passage 326 may vary.

[0095] The through-path 330 can penetrate the rear insulating layer 320, the substrate 300, and the front insulating layer 380 to connect the rear wiring 322 and the front wiring 382. The through-path 330 can contact the rear wiring 322 and the front wiring 382. The insulating spacer 332 can surround the sidewall of the through-path 330.

[0096] External connection pad 340 may be located on the back insulating layer 320. External connection pad 340 may be connected to the back wiring 322 and the back path 326.

[0097] In some implementations, the first unit structure CS1 and the second unit structure CS2 can share a sense amplifier, namely the first peripheral transistor PTR1. The first global bit line GBL1 and the second global bit line GBL2 can also share a sense amplifier. Therefore, multiple global bit lines (GBL1 and GBL2) can be sensed simultaneously using a single sense amplifier.

[0098] Specifically, the first local bit line LBL1 can be electrically connected to the first peripheral transistor PTR1 via the first logic transistor LTR1, the first global bit line GBL1, and the bit line contact BLC. The second local bit line LBL2 can be electrically connected to the first peripheral transistor PTR1 via the second logic transistor LTR2 and the second global bit line GBL2. The first local bit line LBL1 and the second local bit line LBL2 can be selected by the first logic transistor LTR1 and the second logic transistor LTR2 to be connected to a sense amplifier. Therefore, compared to the case where the first cell structure CS1 and the second cell structure CS2 include separate grouped sense amplifiers, the size of the semiconductor memory device according to some embodiments can be reduced. Furthermore, it is possible to facilitate the manufacture of semiconductor memory devices including multiple cell structures.

[0099] Figure 4 This is a cross-sectional view of a semiconductor memory device according to some implementation methods. Figure 4 It is along Figure 1 The cross-sectional view taken from I-I'.

[0100] refer to Figure 1 and Figure 4 In some embodiments, the first unit structure CS1 may further include a third logic transistor LTR3, and the second unit structure CS2 may further include a fourth logic transistor LTR4.

[0101] The third logic transistor LTR3 and the fourth logic transistor LTR4 can be located in the bit line pad region BPR. For example, the fourth logic transistor LTR4 can be located between the adjacent second local bit line LBL2 and the bit line contact BLC, and the third logic transistor LTR3 can be located below the fourth logic transistor LTR4 so as to overlap with the fourth logic transistor LTR4 on the third-direction DR3.

[0102] In some implementations, the third logic transistor LTR3 may be formed at the same height as the first logic transistor LTR1, and the fourth logic transistor LTR4 may be formed at the same height as the second logic transistor LTR2.

[0103] The third logic transistor LTR3 can be formed on the first cell insulating layer 132. Each of the third logic transistors LTR3 may include a third logic semiconductor pattern LSP3, a third logic gate electrode LGE3, a third logic gate insulating film LGI3, and a third logic gate spacer LGS3.

[0104] The third logic semiconductor pattern LSP3 may be defined by the first insulating pattern 133. The third logic semiconductor pattern LSP3 may be insulated from the first logic semiconductor pattern LSP1 by the first insulating pattern 133.

[0105] The third logic semiconductor pattern LSP3 may include the same material as the first unit semiconductor pattern SP1. On the third-direction DR3, the thickness of the third logic semiconductor pattern LSP3 may be substantially the same as the thickness of the first logic semiconductor pattern LSP1, and may be greater than the thickness of the first unit semiconductor pattern SP1.

[0106] The third logic gate electrode LGE3 may be located on the third logic semiconductor pattern LSP3. The third logic gate insulating film LGI3 may be located between the third logic semiconductor pattern LSP3 and the third logic gate electrode LGE3. The third logic gate spacer LGS3 may be located on the sidewalls of the third logic gate electrode LGE3 and the sidewalls of the third logic gate insulating film LGI3. The first source / drain region and the second source / drain region may be located adjacent to both sides of the third logic gate electrode LGE3 in the third logic semiconductor pattern LSP3.

[0107] The first interlayer insulating layer 134 can cover the third logic transistor LTR3. The first logic gate contact 166 can contact the third logic gate electrode LGE3, and the first source / drain contact 168 can contact the first source / drain region and the second source / drain region in the third logic semiconductor pattern LSP3 that are adjacent to both sides of the third logic gate electrode LGE3.

[0108] One or more third logic transistors LTR3 can be connected between the first global bit line GBL1 and the bit line contact BLC. For example, the first source / drain region of the third logic transistor LTR3 can be connected to the first global bit line GBL1 via the first source / drain contact 168, the first pass 186, and the first wiring 182, while the second source / drain region of the third logic transistor LTR3 can be connected to the bit line contact BLC via the first source / drain contact 168, the first pass 186, and the first wiring 188 at the same height as the first global bit line GBL1. The third logic transistor LTR3 can be configured to connect one or more selected first global bit lines GBL1 to the bit line contact BLC. The third logic transistor LTR3 can form a first global bit line multiplexer and can be referred to as a first global bit line multiplexer.

[0109] In some implementations, the first global bit line multiplexer does not overlap with the first memory cell MC1 in the vertical direction. For example, the first global bit line multiplexer is offset from the first memory cell MC1 in the vertical direction.

[0110] One or more fourth logic transistors LTR4 can be connected between the second global bit line GBL2 and the bit line contact BLC. For example, the first source / drain region of the fourth logic transistor LTR4 can be connected to the second global bit line GBL2 via the second source / drain contact 268, the second path 286, and the second wiring 282, while the second source / drain region of the fourth logic transistor LTR4 can be connected to the bit line contact BLC via the second source / drain contact 268, the second path 286, and the second wiring 288 at the same height as the second global bit line GBL2. The fourth logic transistor LTR4 can be configured to connect one or more selected second global bit lines GBL2 to the bit line contact BLC. The fourth logic transistor LTR4 can form a second global bit line multiplexer and can be referred to as a second global bit line multiplexer.

[0111] In some implementations, the second global bit line multiplexer does not overlap with the second memory cell MC2 in the vertical direction. For example, the second global bit line multiplexer is offset from the second memory cell MC2 in the vertical direction.

[0112] The bit line contact BLC can contact the first wiring 188 and the second wiring 288.

[0113] In a semiconductor memory device according to some embodiments, a sense amplifier can sense the global bit lines (GBL1 and GBL2) of a selected cell structure CS1 or CS2 via a first global bit line multiplexer and a second global bit line multiplexer.

[0114] Figure 5 This is a cross-sectional view of a semiconductor memory device according to some implementation methods. Figure 6 and Figure 8 It is along Figure 5 The cross-sectional view taken from I-I'. Figure 7 yes Figure 6 Enlarged cross-sectional views of regions A1 and A2 in the middle. For convenience, a brief description will be provided. Figures 1 to 4 The descriptions overlap, while focusing on the differences.

[0115] refer to Figures 5 to 8 In some embodiments, a first unit transistor CTR1 included in some first memory cells MC1 can be provided as a first logic transistor LTR1, and a second unit transistor CTR2 included in some second memory cells MC2 can be provided as a second logic transistor LTR2. The semiconductor region SR can overlap with the word line region WR.

[0116] The topmost first unit transistor CTR1 can be provided as a first logic transistor LTR1. The topmost first unit semiconductor pattern SP1 can be provided as a first logic semiconductor pattern LSP1, and the first unit gate electrode GE1 and the first unit gate insulating film GI1 located on the topmost first unit semiconductor pattern SP1 can be provided as the first logic gate electrode LGE1 and the first logic gate insulating film LGI1, respectively. The first terminal of the first logic semiconductor pattern LSP1 on the first direction DR1 can be connected to the first local bit line LBL1.

[0117] The second unit transistor CTR2 of the uppermost second memory cell MC2 can be provided as the second logic transistor LTR2. The uppermost second unit semiconductor pattern SP2 can be provided as the second logic semiconductor pattern LSP2, and the second unit gate electrode GE2 and the second unit gate insulating film GI2 located on the uppermost second unit semiconductor pattern SP2 can be provided as the second logic gate electrode LGE2 and the second logic gate insulating film LGI2, respectively. The first end of the second logic semiconductor pattern LSP2 on the first direction DR1 can be connected to the second local bit line LBL2.

[0118] The first source / drain contact 164 can penetrate the first interlayer insulating layer 134 and the first cell insulating layer 132 to contact the second source / drain region of the first logic semiconductor pattern LSP1. The second source / drain contact 268 can penetrate the second interlayer insulating layer 234 and the second cell insulating layer 232 to contact the second source / drain region of the second logic semiconductor pattern LSP2. Although not shown, the logic gate contact can be located in the word line pad region WPR. The logic gate contact can contact the corresponding first logic gate electrode LGE1 or second logic gate electrode LGE2.

[0119] In some embodiments, the second end of the first logic semiconductor pattern LSP1 on the first direction DR1 and the second end of the second logic semiconductor pattern LSP2 on the first direction DR1 can be connected to the first data storage device 170 and the second data storage device 270, respectively. The first storage electrode 172 and the second storage electrode 272 can contact the second end of the first logic semiconductor pattern LSP1 and the second end of the second logic semiconductor pattern LSP2, respectively. The first end of the first logic semiconductor pattern LSP1 on the first direction DR1 and the first end of the second logic semiconductor pattern LSP2 on the first direction DR2 can contact the first local bit line LBL1 and the second local bit line LBL2, respectively.

[0120] refer to Figure 7 In some embodiments, the insulating pattern 150 may be located between the first logic semiconductor pattern LSP1 and the first data storage device 170, and between the second logic semiconductor pattern LSP2 and the second data storage device 270. The second end of the first logic semiconductor pattern LSP1 in the first direction DR1 may be spaced apart from the first data storage device 170, and the second end of the second logic semiconductor pattern LSP2 in the first direction DR1 may be spaced apart from the second data storage device 270. For example, the insulating pattern 150 may be located between the first logic semiconductor pattern LSP1 and the first storage electrode 172, and between the second logic semiconductor pattern LSP2 and the second storage electrode 272.

[0121] refer to Figure 8 In some embodiments, the first unit structure CS1 may further include a third logic transistor LTR3, and the second unit structure CS2 may further include a fourth logic transistor LTR4.

[0122] In some embodiments, the third logic transistor LTR3 may be formed at a different height than the first logic transistor LTR1, and the fourth logic transistor LTR4 may be formed at a different height than the second logic transistor LTR2. For example, the third logic transistor LTR3 may be formed above the first logic transistor LTR1 relative to the front side of the first insulating layer 140 on which the first memory cell MC1 is formed, and the fourth logic transistor LTR4 may be formed above the second logic transistor LTR2 relative to the front side of the second insulating layer 240 on which the second memory cell MC2 is formed.

[0123] Figure 9 and Figure 10 This is a cross-sectional view of a semiconductor memory device according to some embodiments. For convenience, a brief description will be provided. Figures 1 to 8 The descriptions overlap, while focusing on the differences.

[0124] refer to Figure 9 According to some embodiments, a semiconductor memory device may include a plurality of first cell structures CS1 to nth cell structures CSn (where n is a natural number equal to or greater than 3) stacked along a third direction DR3. The first cell structure CS1 may have a reference... Figures 1 to 8 The first unit structure CS1 described is identical in structure. Second unit structures CS2 through nth unit structures CSn can have the same structure as the reference. Figures 1 to 8 The second unit structure CS2 described is identical in structure. Each of the second unit structures CS2 through the nth unit structure CSn may include a bit line contact BLC.

[0125] The first unit structure CS1 to the nth unit structure CSn can share the first peripheral transistor PTR1. The global bit lines (GBL1 and GBL2) of each of the first unit structures CS1 to the nth unit structure CSn can be electrically connected to the first peripheral transistor PTR1 via bit line contact BLC.

[0126] refer to Figure 10 In a semiconductor memory device according to some embodiments, the first cell structure CS1 and the second cell structure CS2 may have a chip-to-chip structure. After manufacturing the first cell structure CS1 and the second cell structure CS2, the first cell structure CS1 and the second cell structure CS2 may be joined together to manufacture a semiconductor memory device according to some embodiments.

[0127] The first unit structure CS1 may include a third bonding insulating film 490 and a third bonding pad 492 located within the third bonding insulating film 490. The third bonding insulating film 490 may be located on the first wiring insulating layer 180. The third bonding pad 492 may be electrically connected to the first wiring (182 and 188) and the first path 186.

[0128] The second unit structure CS2 may include a fourth bonding insulating film 590 and a fourth bonding pad 592 located within the fourth bonding insulating film 590. The fourth bonding insulating film 590 may be located on the second wiring insulating layer 280. The fourth bonding pad 592 may be electrically connected to the second wiring (282 and 288) and the second path 286.

[0129] The third bonding pad 492 and the fourth bonding pad 592 can be bonded together. As a result of the bonding, the first unit structure CS1 and the second unit structure CS2 can be electrically connected. The third bonding pad 492 and the fourth bonding pad 592 can each comprise various metals such as copper (Cu), aluminum (Al), or tungsten (W). The third bonding insulating film 490 and the fourth bonding insulating film 590 can also be bonded together. The third bonding insulating film 490 and the fourth bonding insulating film 590 can each comprise an insulating material such as silicon oxide.

[0130] The first logic transistor LTR1 and the first global bit line GBL1 can be located between the first memory cell MC1 and the second cell structure CS2, and the second logic transistor LTR2 and the second global bit line GBL2 can be located between the second memory cell MC2 and the peripheral circuit structure PR.

[0131] The first unit structure CS1 and the second unit structure CS2 can have the same Figures 1 to 8 The corresponding structures in the text are identical.

[0132] Figures 11 to 13 This is a schematic top view of a semiconductor memory device according to some embodiments. For convenience, a brief description will be provided. Figures 1 to 10 The descriptions overlap, while focusing on the differences.

[0133] refer to Figure 11 In a semiconductor memory device according to some embodiments, the first bit pad region BPR1 and the second bit pad region BPR2 can be located on either side of the cell region 1.

[0134] For example, the first bit pad region BPR1, cell region 1, and second bit pad region BPR2 can be arranged along the first direction DR1. The first bit pad region BPR1 may include a first bit contact BLC1, and the second bit pad region BPR2 may include a second bit contact BLC2. Adjacent first global bit lines GBL1 and GBL2 on the second direction DR2 can be connected to the first bit contact BLC1 and the second bit contact BLC2, respectively. The first bit contact BLC1 can be arranged within the first bit pad region BPR1 along the second direction DR2, and the second bit contact BLC2 can be arranged within the second bit pad region BPR2 along the second direction DR2. For example, adjacent first global bit lines GBL1 on the second direction DR2 can be electrically connected to the first bit contact BLC1 and the second bit contact BLC2, respectively.

[0135] Figure 11 Shown as an example Figure 1 Cell region 1 in the image. In some embodiments, the semiconductor memory device according to some embodiments may include... Figure 5 Cell region 1 in the text.

[0136] refer to Figure 12 and Figure 13 According to some embodiments, a semiconductor memory device may each include a first memory block BLK1 to an nth memory block BLKn (where n is a natural number and i is a natural number less than n). For example, the first memory blocks BLK1 to the nth memory block BLKn may be arranged along a first direction DR1. Each of the first memory blocks BLK1 to the nth memory block BLKn may include a reference... Figures 1 to 10 The first unit structure CS1, the second unit structure CS2, and the peripheral circuit structure PR are described.

[0137] exist Figure 12 and Figure 13 In the diagram, the first storage block BLK1 to the nth storage block BLKn are illustrated as including... Figure 1 Cell region 1 in the memory. In some implementations, the first storage block BLK1 to the nth storage block BLKn may include Figure 5 Cell region 1 in the text.

[0138] The first global bit line GBL1 and the second global bit line GBL2 of each of the first memory blocks BLK1 to the nth memory block BLKn can be connected to each other. The first global bit line GBL1 and the second global bit line GBL2 can extend through the first memory block BLK1 to the nth memory block BLKn in the first direction DR1. The bit line contact BLC can be located in the bit line pad area BPR. The first global bit line GBL1 and the second global bit line GBL2 can be electrically connected via the bit line contact BLC.

[0139] refer to Figure 12 Bit line pad regions (BPRs) can be located between adjacent memory blocks (BLK1 to BLKn). Bit line contacts (BLCs) can also be located between adjacent memory blocks (BLK1 to BLKn). For example, a bit line pad region (BPR) can be located between the i-th memory block BLKi and the (i+1)-th memory block BLK(i+1).

[0140] refer to Figure 13 The bit line pad region BPR can be located at at least one end of the array of the first memory block BLK1 to the nth memory block BLKn.

[0141] For example, a bit line pad region BPR can be located on one side of the nth memory block BLKn in the first direction DR1. The bit line pad region BPR can be adjacent to the nth memory block BLKn in the first direction DR1. In another example, the bit line pad region BPR can be located on one side of the first memory block BLK1 in the first direction DR1. The first memory block BLK1 can be adjacent to the bit line pad region BPR in the first direction DR1. In yet another example, the bit line pad region BPR can be located on either side of the array of first memory blocks BLK1 to the nth memory block BLKn in the first direction DR1. That is, the array of first memory blocks BLK1 to the nth memory block BLKn can be located between two bit line pad regions BPR. Some bit line contacts BLC can be located in the bit line pad region BPR adjacent to the nth memory block BLKn, while the remaining bit line contacts BLC can be located in the bit line pad region BPR adjacent to the first memory block BLK1.

[0142] Figures 14 to 37 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments. Figure 15 , Figure 17 , Figure 21 , Figure 25 , Figure 29 , Figure 33 and Figure 37 They are along Figure 14 , Figure 16 , Figure 20 , Figure 24 , Figure 28 , Figure 32 and Figure 36 The cross-sectional view taken from A-A'. Figure 18 , Figure 22 , Figure 26 , Figure 31 and Figure 34 They are along Figure 16 , Figure 20 , Figure 24 , Figure 30 and Figure 32The cross-sectional view taken from B-B'. Figure 19 , Figure 23 , Figure 27 and Figure 35 They are along Figure 16 , Figure 20 , Figure 24 and Figure 32 The cross-sectional view taken from C-C'.

[0143] Figure 14 , Figure 16 , Figure 20 , Figure 24 , Figure 28 , Figure 30 , Figure 32 and Figure 36 The bit line region BR, word line region WR, semiconductor region SR, capacitor region CR, board region PR, and word line pad region WPR shown represent the planar regions that will form the first local bit line LBL1, the first cell gate electrode GE1, the first logic semiconductor pattern LSP1, the first data storage device 170, the first board electrode 176, and the first cell gate connection pad WLP1 in subsequent processes. Figure 14 , Figure 16 , Figure 20 , Figure 24 , Figure 28 , Figure 30 , Figure 32 and Figure 36 A-A' in the middle can correspond to Figure 1 The I-I' in the middle. Figure 14 , Figure 16 , Figure 20 , Figure 24 , Figure 28 , Figure 30 , Figure 32 and Figure 36 B-B' in the middle can correspond to Figure 1 II-II' in the middle.

[0144] refer to Figure 14 and Figure 15 A molded structure MS is formed, which includes a plurality of sacrificial layers 110 and a plurality of semiconductor layers 120 alternately stacked on a substrate 10.

[0145] Substrate 10 may include bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 10 may be a silicon substrate, or may include other materials such as silicon germanium, gallium arsenide, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Substrate 10 may also be an epitaxial layer formed on a base substrate, ceramic substrate, quartz substrate, or display glass substrate.

[0146] The sacrificial layer 110 may include a material that is etch-selective relative to the semiconductor layer 120. For example, the sacrificial layer 110 may include at least one of silicon germanium, silicon oxide, silicon nitride, or silicon oxynitride. The semiconductor layer 120 may include silicon, germanium, silicon germanium, or indium gallium zinc oxide (IGZO). In one example, the semiconductor layer 120 may include silicon, and the sacrificial layer 110 may include carbon-doped silicon germanium.

[0147] Subsequently, a molded insulating layer 130 is formed on the molded structure MS. The molded insulating layer 130 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0148] refer to Figures 14 to 19 All sacrificial layers 110 except the bottommost sacrificial layer 110a can be removed, and all semiconductor layers 120 except the bottommost semiconductor layer 120a can be patterned to form the first unit semiconductor pattern SP1.

[0149] For example, by selective etching, all semiconductor layers 120 except the bottommost semiconductor layer 120a can be removed. As a result, the upper and lower surfaces of all sacrificial layers 110 except the bottommost sacrificial layer 110a can be exposed. Subsequently, by thinning, the thickness of all semiconductor layers 120 except the bottommost semiconductor layer 120a can be reduced.

[0150] Subsequently, all sacrificial layers 110 except the bottommost sacrificial layer 110a can be removed, and the remaining space can be filled with insulating material to form the first unit insulating layer 132.

[0151] Subsequently, the molded insulating layer 130 can be patterned to form a first insulating pattern. Using the first insulating pattern as an etching mask, all semiconductor layers 120 except the bottommost semiconductor layer 120a can be patterned. Using the first insulating pattern as an etching mask, a first trench can be formed along the first direction DR1 separating all semiconductor layers 120 except the bottommost semiconductor layer 120a. At this time, the bottommost semiconductor layer 120a can be used as an etch stop layer. The first trench can extend in the third direction DR3, penetrating the bottommost sacrificial layer 110a and all semiconductor layers except the bottommost semiconductor layer 120a.

[0152] Subsequently, the first insulating pattern can be removed, and an insulating layer covering the first interlayer insulating layer 134 can be formed. The insulating layer can be patterned to form a second insulating pattern. Using the second insulating pattern as an etch mask, all semiconductor layers 120 except the bottommost semiconductor layer 120a can be patterned. Using the second insulating pattern as an etch mask, a second trench separating the semiconductor layers 120 except the bottommost semiconductor layer 120a along the second direction DR2 can be formed. At this time, the bottommost semiconductor layer 120a can be used as an etch stop layer. The second trench can extend in the third direction DR3, penetrating the bottommost sacrificial layer 110a and all semiconductor layers except the bottommost semiconductor layer 120a. Subsequently, the second insulating pattern can be removed.

[0153] Therefore, multiple first cell semiconductor patterns SP1 spaced apart on the first direction DR1 and the second direction DR2 and stacked on the third direction DR3 can be formed. The remaining portion 120P of the semiconductor layer 120, excluding the first cell semiconductor patterns SP1 and the bottommost semiconductor layer 120a, can be later replaced with first cell gate connection pads WLP1 in a subsequent process. The remaining portion 120P can be located on the extension line of the first cell semiconductor pattern SP1 on the second direction DR2. The remaining portion 120P can be located in the word line pad region WPR.

[0154] Subsequently, the first unit insulating layer 132 surrounding the first unit semiconductor pattern SP1 can be partially removed by a selective etching process. Then, a first unit gate insulating film GI1 surrounding a portion of the first unit semiconductor pattern SP1 can be formed by a deposition process. The first unit gate insulating film GI1 can be formed using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

[0155] Subsequently, a first unit gate electrode GE1 can be formed covering the first unit gate insulating film GI1. For example, the first unit gate electrode GE1 can be formed by a CVD process to fill the space remaining after the first interlayer insulating layer 134 has been removed by a selective etching process. Thus, a first unit transistor CTR1 including the first unit gate electrode GE1 and the first unit semiconductor pattern SP1 can be formed.

[0156] The first cell gate electrode GE1 may have a linear shape extending in the second direction DR2. The first cell gate electrode GE1 may surround a first cell semiconductor pattern SP1 arranged along the second direction DR2. The first cell gate electrodes GE1 may be spaced apart from each other by a first cell gate insulating film GI1. The first cell gate electrode GE1 may be located in the word line region WR.

[0157] refer to Figures 20 to 23A first insulating layer 140 can be formed on the molded structure MS. A carrier substrate 20 can be attached to the first insulating layer 140. The carrier substrate 20, the molded structure MS, and the substrate 10 can be flipped and inverted. That is, the substrate 10 can be on top, and the carrier substrate 20 can be on the bottom. Thereafter, the substrate 10 and the bottommost sacrificial layer 110a can be removed.

[0158] Subsequently, the bottommost semiconductor layer 120a can be patterned to form a first logic semiconductor pattern LSP1. For example, a photoresist pattern can be formed on the bottommost semiconductor layer 120a through an exposure and development process, and the photoresist pattern can be used as an etching mask to perform an etching process, thereby forming a third trench penetrating the bottommost semiconductor layer 120a on the third-direction DR3. An insulating material can be filled into the third trench to form a first insulating pattern 133. The first insulating pattern 133 can be used as a device isolation pattern. The first insulating pattern 133 can define the first logic semiconductor pattern LSP1. The first logic semiconductor pattern LSP1 can be located in the semiconductor region SR.

[0159] Subsequently, a first logic gate electrode LGE1, a first logic gate insulating film LGI1, and a first gate spacer LGS1 can be formed on the first logic semiconductor pattern LSP1. The first logic gate insulating film LGI1 can be formed on the first logic semiconductor pattern LSP1. The first logic gate electrode LGE1 can be formed on the first logic gate insulating film LGI1. The first gate spacer LGS1 can be formed on both side surfaces of the first logic gate electrode LGE1 and the two side surfaces of the first logic gate insulating film LGI1. Impurities can be doped into the first logic semiconductor pattern LSP1 on both sides of the first logic gate electrode LGE1, thereby forming a first source / drain region and a second source / drain region. Therefore, a first logic transistor LTR1 including the first logic gate insulating film LGI1, the first logic semiconductor pattern LSP1, the first logic gate electrode LGE1, the first gate spacer LGS1, and the first source / drain region and the second source / drain region can be formed.

[0160] refer to Figures 24 to 27 A first interlayer insulating layer 134 can be formed to cover the first logic gate electrode LGE1, the first logic semiconductor pattern LSP1, and the first insulating pattern 133. The first interlayer insulating layer 134 can cover the first logic gate electrode LGE1, the first gate spacer LGS1, the first logic semiconductor pattern LSP1, and the first insulating pattern 133.

[0161] Subsequently, a first logic gate contact 162 and a first source / drain contact 164 penetrating the first interlayer insulating layer 134 can be formed. For example, a contact hole penetrating the first interlayer insulating layer 134 can be formed, and a metallic material can be filled into the contact hole to form the first logic gate contact 162 and the first source / drain contact 164. The first logic gate contact 162 can penetrate the first interlayer insulating layer 134 to contact the upper surface of the first logic gate electrode LGE1. The first source / drain contact 164 can penetrate the first interlayer insulating layer 134 to contact the upper surface of the first logic semiconductor pattern LSP1 on both sides of the first logic gate electrode LGE1. The first source / drain contact 164 can be connected to the first source / drain region and the second source / drain region.

[0162] Subsequently, a fourth trench can be formed to penetrate the first interlayer insulating layer 134, the first insulating pattern 133, and the first unit insulating layer 132. The fourth trench can be formed on the third direction DR3 by an etching process, and during the etching process, the first insulating layer 140 can be used as an etch stop layer. With the formation of the fourth trench, the first end of the first unit semiconductor pattern SP1 can be exposed. For example, the first end of the first unit semiconductor pattern SP1 on the first direction DR1 can be exposed. Impurities can be doped into the surface of the first end of the first unit semiconductor pattern SP1 exposed on the first direction DR1.

[0163] Subsequently, conductive material can be filled into the fourth trench to form a first local bit line LBL1. The first local bit line LBL1 can contact a first end of the first cell semiconductor pattern SP1. The first local bit line LBL1 can have a columnar shape extending on the third-direction DR3. Multiple first cell semiconductor patterns SP1 stacked on the third-direction DR3 can be connected to a single first local bit line LBL1.

[0164] The first local location line LBL1 can be formed in Figure 24 In the bit line region BR, the first local bit line LBL1 is illustrated as having a rectangular planar shape. In some embodiments, the planar shape of the first local bit line LBL1 can be circular, elliptical, or another polygon.

[0165] Subsequently, the remaining portion 120P of the semiconductor layer 120, located in the same layer as the first unit semiconductor pattern SP1, can be replaced with a conductive material to form a plurality of first unit gate connection pads WLP1 connected to the respective first unit gate electrodes GE1. The first unit gate connection pads WLP1 can be connected to the first unit gate electrodes GE1 in the second direction DR2. The first unit gate connection pads WLP1 can be located at... Figure 24 In the word line pad area WPR.

[0166] The first cell gate connection pad WLP1 can have a stepped structure. For example, the length of the first cell gate connection pad WLP1 in the second direction DR2 can be increased in the direction toward the first insulating layer 140.

[0167] refer to Figure 28 and Figure 29 A fifth trench can be formed, penetrating the first interlayer insulating layer 134, the first insulating pattern 133, and the first unit insulating layer 132, and multiple data storage devices 170 can be formed through the fifth trench. The fifth trench can be formed by etching the first interlayer insulating layer 134, the first insulating pattern 133, and the first unit insulating layer 132 on the third-direction DR3. At this time, the first insulating layer 140 can be used as an etch stop layer. The bottom surface of the fifth trench can be defined by the upper surface of the first insulating layer 140. The sidewalls of the fifth trench can be defined by the side surfaces of the first interlayer insulating layer 134, the first insulating pattern 133, the first unit insulating layer 132, and the first unit semiconductor pattern SP1. The first unit semiconductor pattern SP1 can be exposed through the fifth trench.

[0168] Subsequently, a portion of the first unit semiconductor pattern SP1 exposed through the fifth trench can be etched to form a plurality of first grooves. The first grooves can be formed by etching the first unit semiconductor pattern SP1 on the first direction DR1. With the formation of the first grooves, the second end of the first unit semiconductor pattern SP1 in the first direction DR1 can be exposed. Impurities can be doped into the surface of the second end of the first unit semiconductor pattern SP1 exposed through the first grooves.

[0169] Subsequently, conductive material can be filled into the first groove to form a plurality of first electrodes 172. The first electrodes 172 can contact the opposite ends of each first unit semiconductor pattern SP1. The first electrodes 172 can be connected to each first unit semiconductor pattern SP1 in the first direction DR1.

[0170] Subsequently, portions of the first cell insulating layer 132 exposed through the fifth trench can be etched to form a plurality of second grooves. Some of the second grooves may each have sidewalls defined by opposing surfaces of the first electrodes 172 adjacent to each other on the third direction DR3 and a bottom surface defined by the side surface of the first cell insulating layer 132. Other second grooves may each have sidewalls defined by the upper surface of the first electrode 172, the lower surface of the first logic semiconductor pattern LSP1, and the lower surface of the first insulating pattern 133, and a bottom surface defined by the side surface of the first cell insulating layer 132. Still other second grooves may each have sidewalls defined by the lower surface of the first electrode 172 and the upper surface of the first insulating layer 140, and a bottom surface defined by the side surface of the first cell insulating layer 132. The second grooves can be formed by etching the first cell insulating layer 132 located on the first direction DR1 at positions between the first cell semiconductor patterns SP1, between the uppermost first cell semiconductor pattern SP1 and the first logic semiconductor pattern LSP1, and between the lowermost first cell semiconductor pattern SP1 and the first insulating layer 140.

[0171] Subsequently, a first dielectric layer 174 and a first conductive layer 176a can be formed to cover the sidewalls and bottom surface of the second trench and the sidewalls and bottom surface of the fifth trench. The first dielectric layer 174 can extend along the fifth trench and the second trench. The first conductive layer 176a can be formed along the first dielectric layer 174.

[0172] Subsequently, the remaining spaces in the second groove and the fifth trench can be filled with conductive material to form a second conductive layer 176b. Therefore, a first plate electrode 176 including a first conductive layer 176a and a second conductive layer 176b can be formed. Multiple data storage devices 170 including a first electrode 172, a first dielectric layer 174, and a first plate electrode 176 can be formed. The first plate electrode 176 can be located in the plate region PR. The portions of the first electrode 172, the first dielectric layer 174, and the first plate electrode 176 located between adjacent first electrodes 172 can be located in the capacitor region CR.

[0173] refer to Figure 30 and Figure 31 Multiple sixth trenches can be formed that penetrate the first interlayer insulating layer 134, the first insulating pattern 133, and the first unit insulating layer 132. These sixth trenches can be formed by an etching process that penetrates the first interlayer insulating layer 134, the first insulating pattern 133, and the first unit insulating layer 132 on the third-direction DR3. In this case, the first unit gate connection pad WLP1 can be used as an etch stop layer.

[0174] Subsequently, conductive material can be filled into the sixth trench to form a plurality of first unit gate contacts WLC1. The first unit gate contacts WLC1 can contact the upper surface of each first unit gate connection pad WLP1. The first unit gate connection pads WLP1 can be connected to each first unit gate electrode GE1 stacked on the third-direction DR3. The first unit gate contacts WLC1 can have a columnar shape extending on the third-direction DR3.

[0175] The first cell gate contact WLC1 may be located in the word line pad region WPR. The first cell gate contact WLC1 is illustrated as having a rectangular planar shape. In some embodiments, the planar shape of the first cell gate contact WLC1 may be circular, elliptical, or another polygon.

[0176] refer to Figures 32 to 35 First wiring 182 and first global bit line GBL1 can be formed on the first interlayer insulating layer 134. For example, a first wiring insulating layer 180 can be formed on the first interlayer insulating layer 134, and the first wiring insulating layer 180 can be patterned and then filled with a conductive material to form multiple first wirings 182, multiple first paths 186, and the first global bit line GBL1. Each of the first wirings 182 can include multiple layers, and the first paths 186 can connect the first wirings 182 located at different heights. The first wirings 182 and the first paths 186 can be electrically connected to the first global bit line GBL1, the first local bit line LBL1, the first cell gate contact WLC1, the first plate electrode 176 of the data storage device 170, the first logic gate contact 166, and the first source / drain contact 168.

[0177] The first wiring 182 can connect the first global bit line GBL1 and the first local transistor LTR1, and can also connect the first local bit line LBL1 and the first local transistor LTR1. The first wiring 182 can connect one of the paired first source / drain contacts 168 connected to the paired source / drain regions of the first local transistor LTR1 to a first global bit line GBL1, and can connect the other first source / drain contact 168 to a first local bit line LBL1. That is, the first local transistor LTR1 can be connected between the first global bit line GBL1 and the first local bit line LBL1.

[0178] refer to Figure 36 and Figure 37 The second unit structure CS2 can be joined to the first unit structure CS1.

[0179] For example, according to the reference Figures 14 to 35The described method allows for the formation of a second cell structure CS2 on a carrier substrate 20, comprising a second insulating layer 240, a second local bit line LBL2, a second memory cell MC2, a second logic transistor LTR2, a second logic gate contact 266, a second source / drain contact 268, a second wiring insulating layer 280, and a second wiring 282. Specifically, a portion of the second cell structure CS2 can be formed on the carrier substrate 20. The carrier substrate 20 can then be removed, and this portion of the second cell structure CS2 can be bonded. The second insulating layer 240 can contact the first wiring insulating layer 180. Therefore, the second cell structure CS2 can be bonded to the first cell structure CS1. Subsequently, bit line contacts BLC, a second global bit line GBL2, a second channel 286, a second wiring insulating layer 280, a first bonding insulating film 290, and a first bonding pad 292 can be formed. Thus, the second cell structure CS2 can be formed.

[0180] After that, refer to again Figure 1 and Figure 2 The peripheral circuit structure PR can be bonded to the second unit structure CS2. The first bonding insulating film 290 and the first bonding pad 292 of the second unit structure CS2 can be bonded to the second bonding insulating film 390 and the second bonding pad 392 of the peripheral circuit structure PR, respectively.

[0181] Although this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of specific features of a particular embodiment of a particular invention. Some features described in this specification within the context of individual embodiments can also be implemented in combination within a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases it is possible to remove one or more features from the combination, and the combination may be for sub-combinations or variations thereof.

[0182] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be made in various other forms. Those skilled in the art will understand that the technical scope or essential features of the present disclosure can be modified and implemented in other specific forms without departing from the spirit of the present disclosure. Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first unit structure, comprising: (i) a plurality of first local bit lines extending in a vertical direction; (ii) a plurality of first memory cells respectively connected to the plurality of first local bit lines and arranged in the vertical direction; (iii) a plurality of first local bit line multiplexers respectively connected to the plurality of first local bit lines; and (iv) a plurality of first global bit lines respectively connected to the plurality of first local bit line multiplexers. A second unit structure, located on the first unit structure, includes: (i) a plurality of second local bit lines extending in the vertical direction; (ii) a plurality of second memory cells respectively connected to the plurality of second local bit lines and arranged in the vertical direction; (iii) a plurality of second local bit line multiplexers respectively connected to the plurality of second local bit lines; and (iv) a plurality of second global bit lines respectively connected to the plurality of second local bit line multiplexers. Multiple bit line contacts extend into the second cell structure and respectively connect the multiple first global bit lines to the multiple second global bit lines; and The peripheral circuit structure is located on the second unit structure and includes a sense amplifier connected to the plurality of bit line contacts. The plurality of first global bit lines and the plurality of second global bit lines are connected to the sense amplifier.

2. The semiconductor memory device according to claim 1, wherein, The first unit structure includes multiple first global bit line multiplexers respectively connected to the multiple first global bit lines. The second unit structure includes multiple second global bit line multiplexers respectively connected to the multiple second global bit lines, and The plurality of bit line contacts respectively connect the plurality of first global bit line multiplexers to the plurality of second global bit line multiplexers.

3. The semiconductor memory device according to claim 1, wherein, The first unit structure and the second unit structure define a unit region and a bit line pad region adjacent to the unit region in a first horizontal direction. Wherein, the first global bit line and the second global bit line extend in the first horizontal direction in the cell region and the bit line pad region, and Each of the plurality of bit line contacts is alternately offset from the adjacent bit line contact along a second horizontal direction in the bit line pad region.

4. The semiconductor memory device according to claim 1, wherein, The first unit structure and the second unit structure include a plurality of storage blocks arranged in a horizontal direction. Each storage block includes the plurality of first local bit lines, at least one first local bit line multiplexer among the plurality of first local bit line multiplexers, the plurality of first global bit lines, the plurality of second local bit lines, at least one second local bit line multiplexer among the plurality of second local bit line multiplexers, and the plurality of second global bit lines. The plurality of first global bit lines and the plurality of second global bit lines extend through the plurality of memory blocks in the horizontal direction, and The plurality of bit line contacts are located between adjacent memory blocks.

5. The semiconductor memory device according to claim 1, wherein, The first unit structure and the second unit structure define a first bit line pad area, a unit area, and a second bit line pad area arranged sequentially along the horizontal direction. The plurality of first global bit lines and the plurality of second global bit lines extend horizontally through the first bit line pad region, the cell region, and the second bit line pad region, and The plurality of bit line contacts include a plurality of first bit line contacts located in the first bit line pad region and a plurality of second bit line contacts located in the second bit line pad region.

6. The semiconductor memory device according to claim 1, wherein, The first unit structure and the second unit structure include storage blocks arranged in a horizontal direction, and The plurality of bit line contacts are located between adjacent memory blocks.

7. A semiconductor memory device, the semiconductor memory device comprising: A first cell structure, comprising: (i) a first local bit line extending in a vertical direction on a first insulating layer; (ii) a plurality of first cell semiconductor patterns arranged in the vertical direction, each first cell semiconductor pattern having a first end connected to the first local bit line; (iii) a plurality of first data storage devices connected to a second end of the plurality of first cell semiconductor patterns; (iv) a plurality of first cell gate electrodes located on the plurality of first cell semiconductor patterns; (v) a first logic semiconductor pattern spaced apart from the plurality of first cell semiconductor patterns in the vertical direction; (vi) a first logic transistor located on the first logic semiconductor pattern and connected to the first local bit line; and (vii) a first global bit line connected to the first logic transistor. The second unit structure includes: (i) a second local bit line extending in the vertical direction on a second insulating layer; (ii) a plurality of second unit semiconductor patterns arranged in the vertical direction, each second unit semiconductor pattern having a first end connected to the second local bit line; (iii) a plurality of second data storage devices connected to the second ends of the plurality of second unit semiconductor patterns; (iv) a plurality of second unit gate electrodes located on the plurality of second unit semiconductor patterns; (v) a second logic semiconductor pattern spaced apart from the plurality of second unit semiconductor patterns in the vertical direction; (vi) a second logic transistor located on the second logic semiconductor pattern and connected to the second local bit line; and (vii) a second global bit line connected to the second logic transistor. Bit line contacts, the bit line contacts extending into the second cell structure and connecting to the first global bit line and the second global bit line; and A peripheral circuit structure, the peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit transistor located on the peripheral circuit substrate, the peripheral circuit transistor being connected to a first global bit line and a second global bit line.

8. The semiconductor memory device according to claim 7, wherein, The first unit structure includes a first unit insulating layer located between the plurality of first unit semiconductor patterns. The second unit structure includes a second unit insulating layer located between adjacent second unit semiconductor patterns. Wherein, the first logic semiconductor pattern is located on the first unit insulating layer, and The second logic semiconductor pattern and the second logic transistor are located on the second insulating layer.

9. The semiconductor memory device according to claim 8, wherein, The first unit structure includes a third logic semiconductor pattern located on the insulating layer of the first unit and a third logic transistor located on the third logic semiconductor pattern. The second unit structure includes a fourth logic semiconductor pattern located on the second insulating layer and a fourth logic transistor located on the fourth logic semiconductor pattern. The third logic transistor is connected to the first global bit line and the bit line contact, and The fourth logic transistor is connected to the second global bit line and the bit line contact.

10. The semiconductor memory device according to claim 9, wherein, The fourth logic semiconductor pattern and the fourth logic transistor are located between the second local bit line and the bit line contact.

11. The semiconductor memory device according to claim 7, wherein, The first end of the first logic semiconductor pattern is connected to the first local bit line. The second end of the first logic semiconductor pattern is connected to the plurality of first data storage devices. Wherein, the first end of the second logic semiconductor pattern is connected to the second local bit line, and The second end of the second logic semiconductor pattern is connected to the plurality of second data storage devices.

12. The semiconductor memory device according to claim 7, wherein, The first end of the first logic semiconductor pattern is connected to the first local bit line. The second end of the first logic semiconductor pattern is spaced apart from the plurality of first data storage devices. Wherein, the first end of the second logic semiconductor pattern is connected to the second local bit line, and The second end of the second logic semiconductor pattern is spaced apart from the plurality of second data storage devices.

13. The semiconductor memory device according to claim 7, wherein, The first cell structure includes: (i) a first cell insulating layer located on the first insulating layer and between adjacent first cell semiconductor patterns, and (ii) another first cell insulating layer located on the first cell insulating layer and covering the first global bit line. The second cell structure includes: (i) a second cell insulating layer located on the second insulating layer and between adjacent second cell semiconductor patterns; (ii) another second cell insulating layer located on the second cell insulating layer and covering the second global bit line; (iii) a first bonding insulating film located on the second cell insulating layer; and (iv) a first bonding pad located within the first bonding insulating film. The peripheral circuit structure includes a second bonding insulating film and a second bonding pad located within the second bonding insulating film. The first unit insulating layer is in contact with the second insulating layer. Wherein, the first bonding insulating film is in contact with the second bonding insulating film, and The first bonding pad is in contact with the second bonding pad.

14. The semiconductor memory device according to claim 7, wherein, The first cell structure includes: (i) a first cell insulating layer located on the first insulating layer and between adjacent first cell semiconductor patterns; (ii) another first cell insulating layer located on the first cell insulating layer and covering the first global bit line; (iii) a first bonding insulating film located on the first cell insulating layer; and (iv) a first bonding pad located within the first bonding insulating film. The second cell structure includes: (i) a second cell insulating layer located on the second insulating layer and between adjacent second cell semiconductor patterns; (ii) another second cell insulating layer located on the second cell insulating layer and covering the second global bit line; (iii) a second bonding insulating film located on the second cell insulating layer; (iv) a second bonding pad located within the second bonding insulating film; (v) a third bonding insulating film located on the second insulating layer; and (vi) a third bonding pad located within the third bonding insulating film. The peripheral circuit structure includes a fourth bonding insulating film and a fourth bonding pad located within the fourth bonding insulating film. The first bonding insulating film is in contact with the second bonding insulating film. The first bonding pad is in contact with the second bonding pad. Wherein, the third bonding insulating film is in contact with the fourth bonding insulating film, and The third bonding pad is in contact with the fourth bonding pad.

15. A semiconductor memory device, the semiconductor memory device comprising: A first unit structure, comprising: (i) a plurality of first local bit lines extending in a vertical direction; (ii) a plurality of first memory cells arranged in the vertical direction and respectively connected to the plurality of first local bit lines; (iii) a plurality of first global bit lines located on the plurality of first memory cells; (iv) a plurality of first local bit line multiplexers respectively connected to the plurality of first global bit lines and the plurality of first local bit lines; and (v) a plurality of first global bit line multiplexers respectively connected to the plurality of first global bit lines. A second unit structure, comprising: (i) a plurality of second local bit lines extending in the vertical direction; (ii) a plurality of second memory cells arranged in the vertical direction and respectively connected to the plurality of second local bit lines; (iii) a plurality of second global bit lines located on the plurality of second memory cells; (iv) a plurality of second local bit line multiplexers respectively connected to the plurality of second global bit lines and the plurality of second local bit lines; and (v) a plurality of second global bit line multiplexers respectively connected to the plurality of second global bit lines; and The peripheral circuit structure is located on the second unit structure and includes a sense amplifier connected to the plurality of first global bit lines and the plurality of second global bit lines.

16. The semiconductor memory device according to claim 15, wherein, The plurality of first local bit line multiplexers overlap with the plurality of first memory cells in the vertical direction. The plurality of second local bit line multiplexers overlap with the plurality of second memory cells in the vertical direction. The plurality of first global bit line multiplexers are offset from the plurality of first memory cells in the vertical direction, and The plurality of second global bit line multiplexers are offset from the plurality of second memory cells in the vertical direction.

17. The semiconductor memory device according to claim 15, wherein, The plurality of first global bit line multiplexers are located at different heights than the plurality of first local bit line multiplexers, and The plurality of second global bit line multiplexers are located at different heights than the plurality of second local bit line multiplexers.

18. The semiconductor memory device according to claim 15, wherein, The plurality of first global bit line multiplexers are located at the same height as the plurality of first local bit line multiplexers, and The plurality of second global bit line multiplexers are located at the same height as the plurality of second local bit line multiplexers.

19. The semiconductor memory device according to claim 15, wherein, The plurality of first local bit line multiplexers and the plurality of first global bit line multiplexers are located between (i) the plurality of first memory cells and (ii) the second cell structure, and The plurality of second local bit line multiplexers and the plurality of second global bit line multiplexers are located between (i) the plurality of second memory cells and (ii) the peripheral circuit structure.

20. The semiconductor memory device according to claim 15, wherein, The plurality of first local bit line multiplexers and the plurality of first global bit line multiplexers are located between (i) the plurality of first memory cells and (ii) the second cell structure, and The plurality of second local bit line multiplexers and the plurality of second global bit line multiplexers are located between (i) the first cell structure and (ii) the plurality of second memory cells.

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