Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a stack structure, a channel structure, a gate structure and a capacitor structure. The channel structure and the capacitor structure penetrate the stack structure along a stacking direction. The gate structure extends along a first direction and at least surrounds a part of the sidewall of the channel structure. The capacitor structure is connected with another part of the sidewall of the channel structure. Since the insulating layer and the dielectric layer can naturally realize the insulating separation between the adjacent channel structures and the bit line structures, a special isolation structure does not need to be additionally arranged, so that the chip area is saved, and the storage density is improved. Meanwhile, the plurality of capacitor structures and the plurality of channel structures are arranged in the first direction. The capacitor structure and the channel structure connected along a second direction form a storage unit. The plurality of storage units are arranged in the first direction. The second direction is perpendicular to the stacking direction and intersects with the first direction. The arrangement mode can further save the area and improve the storage density.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] 3D Dynamic Random Access Memory (3D DRAM), as a high-density memory device, represents an important development direction in the semiconductor memory field. In existing 3D DRAM structures, insulating layers are typically used as isolation structures between channel structures and bit line structures. These isolation structures occupy a large amount of chip area, making it difficult to further increase the density of memory cells and limiting the improvement of storage density in 3D DRAM devices. Summary of the Invention

[0003] This application provides a semiconductor device and a method for forming the same, in order to improve the storage density of the semiconductor device.

[0004] This application provides a semiconductor device, including: a stacked structure including alternately stacked insulating and dielectric layers; a channel structure extending through the stacked structure along its stacking direction; a gate structure extending along a first direction perpendicular to the stacking direction, the gate structure at least surrounding a portion of the sidewall of the channel structure; and a capacitor structure extending through the stacked structure along the stacking direction, the capacitor structure being connected to another portion of the sidewall of the channel structure; wherein a plurality of capacitor structures and a plurality of channel structures are arranged at intervals along the first direction; the capacitor structures and the channel structures connected along a second direction constitute a memory cell, a plurality of memory cells being arranged at intervals along the first direction, the second direction being perpendicular to the stacking direction and intersecting the first direction.

[0005] In some embodiments, the angle between the second direction and the first direction is an acute angle.

[0006] In some embodiments, a plurality of memory cells arranged at intervals along the first direction constitute a memory cell group, and a plurality of gate structures are arranged at intervals along a third direction, the third direction being perpendicular to the first direction and the stacking direction, and two memory cell groups are disposed between two adjacent gate structures.

[0007] In some embodiments, along the first direction, the storage cells in the two groups of storage cells are misaligned.

[0008] In some embodiments, the gate structure includes a connected body portion and an extension portion, the body portion extending along the first direction, and the extension portion including a plurality of extension structures spaced apart along the first direction, the extension structures surrounding a portion of the sidewall of the channel structure.

[0009] In some embodiments, the protruding structure includes a connecting conductive layer having a first opening, and the channel structure is connected to the capacitor structure through the first opening.

[0010] In some embodiments, the channel structure includes an annular portion and an outwardly protruding portion, the outwardly protruding portion being connected between the capacitor structure and the annular portion.

[0011] In some embodiments, the semiconductor device further includes: a gate insulating layer located between the gate structure and the channel structure, the gate insulating layer having a second opening, and the protrusion being connected to the capacitor structure through the second opening.

[0012] In some embodiments, the semiconductor device further includes: a bit line structure extending through the stacked structure along the stacking direction; wherein the channel structure is disposed around the bit line structure.

[0013] This application also provides a method for forming a semiconductor device, comprising: forming a stacked structure, the stacked structure including alternately stacked insulating layers and dielectric layers; forming a gate structure between two adjacent insulating layers, the gate structure extending along a first direction, the first direction being perpendicular to the stacking direction of the stacked structure; forming a capacitor structure and a channel structure extending through the stacked structure along the stacking direction, the gate structure at least surrounding a portion of the sidewall of the channel structure, another portion of the sidewall of the channel structure being connected to the capacitor structure, a plurality of capacitor structures and a plurality of channel structures being spaced apart along the first direction, the capacitor structures and the channel structures connected along a second direction constituting a memory cell, a plurality of memory cells being spaced apart along the first direction, the second direction being perpendicular to the stacking direction and intersecting the first direction.

[0014] In some embodiments, a plurality of gate structures are spaced apart along a third direction, the third direction being perpendicular to the first direction and the stacking direction, and two memory cell groups are formed between two adjacent gate structures, each memory cell group including a plurality of memory cells spaced apart along the first direction.

[0015] In some embodiments, the method of forming the capacitor structure includes: forming an initial capacitor hole that penetrates the stacked structure along the stacking direction; partially etching a dielectric layer through the initial capacitor hole to form a first groove located between two adjacent insulating layers; forming a second electrode on the inner wall of the first groove; forming a dielectric layer on the surface of the second electrode and the inner wall of the initial capacitor hole; and forming a first electrode on the surface of the dielectric layer.

[0016] In some embodiments, the method of forming the channel structure includes: forming an initial channel hole that penetrates the stacked structure along the stacking direction; partially etching the dielectric layer through the channel hole to form a second groove, the second groove communicating with the initial channel hole to form a channel hole; and forming a channel layer on the inner wall of the channel hole.

[0017] In some embodiments, the method of forming the gate structure includes: after forming the channel hole, forming a connecting conductive layer on the inner wall of the second groove and filling the channel hole with a second sacrificial layer; forming a trench penetrating the stacked structure, the trench extending along a first direction; removing the dielectric layer located between the second sacrificial layer and the trench to form a gate line groove extending along the first direction; and filling the gate line groove with a conductive structure, the conductive structure and the connecting conductive layer constituting the gate structure.

[0018] In some embodiments, the method further includes: after forming a first groove, removing a portion of the conductive layer through the first groove to form a first opening exposing the second sacrificial layer; after forming a third sacrificial layer in the capacitor hole, removing the second sacrificial layer; partially etching the third sacrificial layer through the channel hole to form an outward protrusion communicating with the channel hole; forming a gate insulating layer on the inner wall of the channel hole and the outward protrusion, and forming a fourth sacrificial layer on the surface of the gate insulating layer; removing the third sacrificial layer, removing a portion of the gate insulating layer through the capacitor hole to form a second opening exposing the fourth sacrificial layer, and forming a second electrode covering the second opening.

[0019] In some embodiments, the method further includes: after forming the capacitor structure, removing the fourth sacrificial layer; and forming the channel layer in the channel hole and the protruding hole.

[0020] In the semiconductor device of this application embodiment, the gate structure extends along a first direction and at least surrounds a portion of the sidewalls of the channel structure, while the capacitor structure is connected to another portion of the sidewalls of the channel structure, thereby realizing the basic storage function of the semiconductor device. Since the stacked structure uses alternating layers of insulating and dielectric layers, and the channel structure penetrates the stacked structure, both the insulating and dielectric layers can naturally achieve insulation separation between adjacent channel structures and bit line structures, eliminating the need for additional dedicated isolation structures, thus saving chip area and increasing storage density. Simultaneously, multiple capacitor structures and multiple channel structures are arranged at intervals along the first direction, and capacitor structures and channel structures connected along a second direction constitute a storage cell. Multiple storage cells are arranged at intervals along the first direction, the second direction is perpendicular to the stacking direction, and the second direction intersects the first direction. This arrangement further saves area and increases storage density.

[0021] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application; Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device in the XY1 direction; Figure 3 yes Figure 2 A schematic cross-sectional view of the semiconductor device at point A-A1; Figure 4 yes Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1; Figure 5 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 6 to 41 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0025] Explanation of reference numerals in the attached figures: 100. Semiconductor devices; 10. Stacked structure; 11. Insulating layer; 12. Dielectric layer; 13. Protective layer; 20. Channel structure; 21. Annular portion; 22. Outwardly convex portion; 23. Channel layer; 23a. Initial channel layer; 24. Channel hole; 241. Initial channel hole; 242. Second groove; 25. Outer protrusion hole; 30. Gate structure; 30a. Main body; 31. Inner sidewall; 32. Groove; 30b. Protrusion; 301. Protrusion structure; 302. Connecting conductive layer; 303. First opening; 33. First conductive layer; 33a. First initial conductive layer; 34. Second conductive layer; 34a. Second initial conductive layer; 35. Trench; 36. Gate line groove; 351. Isolation structure; 40. Capacitor structure; 41. First electrode; 411. Fifth conductive layer; 412. Sixth conductive layer; 42. Second electrode; 42a. Initial second electrode; 421. First sidewall; 422. Second sidewall; 43. Dielectric layer; 44. Capacitor hole; 441. Initial capacitor hole; 442. First groove; MC, storage unit; 60. Gate insulating layer; 61. Second opening; 70. Bit line structure; 71. Third conductive layer; 71a. Third initial conductive layer; 72. Fourth conductive layer; 72a. Fourth initial conductive layer; 80. Substrate; 91. First sacrificial layer; 92. Second sacrificial layer; 93. Third sacrificial layer; 94. Fourth sacrificial layer; M, mask layer; X, first direction; Y1, third direction; Y2, second direction; Z, stacking direction. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0027] In one embodiment, the stacked structure is formed by alternating layers of silicon and silicon-germanium, with silicon subsequently serving as the channel structure. Therefore, it is necessary to cut the silicon to form isolation structures to separate adjacent channel structures. Furthermore, separate isolation structures are often required between adjacent bit line structures. However, these isolation structures occupy a significant amount of chip area, making it difficult to further increase the density of memory cells and limiting the improvement of memory density in 3D DRAM devices.

[0028] Based on this, embodiments of this application provide a semiconductor device, including: a stacked structure including alternately stacked insulating layers and dielectric layers; a channel structure extending through the stacked structure along its stacking direction; a gate structure extending along a first direction perpendicular to the stacking direction, the gate structure at least surrounding a portion of the sidewall of the channel structure; a capacitor structure extending through the stacked structure along the stacking direction, the capacitor structure being connected to another portion of the sidewall of the channel structure; wherein, a plurality of capacitor structures and a plurality of channel structures are arranged at intervals along the first direction; the capacitor structures and the channel structures connected along a second direction constitute a memory cell, a plurality of memory cells being arranged at intervals along the first direction, the second direction being perpendicular to the stacking direction and intersecting the first direction.

[0029] In the semiconductor device of this application embodiment, the gate structure extends along a first direction and at least surrounds a portion of the sidewalls of the channel structure, while the capacitor structure is connected to another portion of the sidewalls of the channel structure, thereby realizing the basic storage function of the semiconductor device. Since the stacked structure uses alternating layers of insulating and dielectric layers, and the channel structure penetrates the stacked structure, both the insulating and dielectric layers can naturally achieve insulation separation between adjacent channel structures and bit line structures, eliminating the need for additional dedicated isolation structures, thus saving chip area and increasing storage density. Simultaneously, multiple capacitor structures and multiple channel structures are arranged at intervals along the first direction, and capacitor structures and channel structures connected along a second direction constitute a storage cell. Multiple storage cells are arranged at intervals along the first direction, the second direction is perpendicular to the stacking direction, and the second direction intersects the first direction. This arrangement further saves area and increases storage density.

[0030] The structure of the semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0031] Please see Figures 1 to 4 , Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in some embodiments of this application. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device in the XY1 direction. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 4 yes Figure 2 A schematic cross-sectional view of the semiconductor device at point B-B1. It should be noted that... Figure 1 Only the overall structure of the semiconductor device 100 is shown, while the structure inside the stacked structure 10 is omitted. The internal structure can be found in [reference needed]. Figures 2 to 4 .

[0032] The semiconductor device 100 includes a stacked structure 10, a channel structure 20, a gate structure 30, and a capacitor structure 40. The stacked structure 10 includes alternately stacked insulating layers 11 and dielectric layers 12. The channel structure 20 penetrates the stacked structure 10 along the stacking direction Z. The gate structure 30 extends along a first direction X, which is perpendicular to the stacking direction Z, and at least surrounds a portion of the sidewall of the channel structure 20. The capacitor structure 40 penetrates the stacked structure 10 along the stacking direction Z and is connected to another portion of the sidewall of the channel structure 20. Multiple capacitor structures 40 and multiple channel structures 20 are arranged at intervals along the first direction X. The capacitor structures 40 and channel structures 20 connected along a second direction Y2 constitute memory cells MC. Multiple memory cells MC are arranged at intervals along the first direction X. The second direction Y2 is perpendicular to the stacking direction Z and intersects the first direction X.

[0033] It should be noted that in this paper, the Z direction is used to represent the stacking direction of the insulating layer 11 and the dielectric layer 12, the X direction is used to represent the first direction X of the extension of the gate structure 30, Y1 is used to represent the third direction Y1 perpendicular to X and Z, and Y2 is used to represent the second direction Y2 perpendicular to Z and forming an acute angle with X. θ is used to represent the angle between Y2 and Y1.

[0034] The stacked structure 10 consists of alternating insulating layers 11 and dielectric layers 12. The insulating layer 11 may be made of silicon oxide, and the dielectric layer 12 may be made of silicon nitride. The number of stacked layers is determined according to the storage capacity requirements of the 3D DRAM and is not specifically limited. This stacked structure 10 provides support and a foundation for the various functional structures of the device.

[0035] The storage principle of the semiconductor device 100 in this embodiment is as follows.

[0036] The capacitor structure 40 is the core of data storage, recording binary data (0 / 1) through "charge storage". The gate structure 30 surrounds a portion of the sidewall of the channel structure 20, and the conduction state of the channel structure 20 is adjusted by applying a control voltage. The capacitor structure 40 is connected to another portion of the sidewall of the channel structure 20. When a positive voltage is applied to the gate, the channel is turned on, providing a charge transfer path for the capacitor. Charge flows through the channel structure 20 into the capacitor structure 40 for storage. When the gate voltage is removed, the channel is turned off, and the capacitor retains its existing charge state (data retention).

[0037] It is understandable that "a portion of the sidewall" of the channel structure 20 and "another portion of the sidewall" of the channel structure 20 are not at the same location in the channel structure 20. Among them, "a portion of the sidewall" is the part opposite to the gate structure 30, and "another portion of the sidewall" is the part connected to the capacitor structure 40.

[0038] The semiconductor device 100 may further include a bit line structure 70 that extends through the stacked structure 10 along the stacking direction Z, wherein the channel structure 20 is disposed around the bit line structure 70. That is, the bit line structure 70 is located within and surrounded by the channel structure 20. Thus, during a storage operation, charge is transferred from the bit line structure 70 through the channel structure 20 to the capacitor for storage.

[0039] The bitline structure 70 may include a third conductive layer 71 and a fourth conductive layer 72, the fourth conductive layer 72 being disposed around the surface of the third conductive layer 71, an exemplary material of the fourth conductive layer 72 including titanium nitride, and an exemplary material of the third conductive layer 71 including tungsten.

[0040] In some embodiments, see Figure 2 The capacitor structure 40 and the channel structure 20 are arranged along the second direction Y2. The angle between the second direction Y2 and the first direction X is an acute angle, indicating that the capacitor structure 40 and the channel structure 20 are not aligned in the third direction Y1. That is, each capacitor structure 40 is arranged obliquely relative to the channel structure 20 it is connected to. This oblique arrangement can compress the size occupied by the channel structure 20 and the capacitor structure 40 in the third direction Y1, thus saving chip area and increasing storage density.

[0041] In some embodiments, the acute angle between the second direction Y2 and the first direction X is 55° to 65°. This limited angle range allows for a closer arrangement of the capacitor structure 40 and the channel structure 20, maximizing the advantages of the oblique arrangement in saving chip area and increasing storage density. If the angle is too small, the distance between the capacitor structure 40 and the gate structure 30 will be too close; if the angle is too large, the arrangement will not be close enough.

[0042] In some embodiments, the acute angle between the second direction Y2 and the first direction X is 60°. 60° is the optimal angle for oblique arrangement, which can optimize the spacing between adjacent unit groups, save chip area to the maximum extent, and further improve storage density.

[0043] In other embodiments, the second direction Y2 and the first direction X can also be perpendicular to each other, that is, the angle between them is a right angle.

[0044] In some embodiments, a plurality of storage cells MC arranged at intervals along the first direction X constitute a storage cell group, i.e. Figure 2 A row of memory cells MC constitutes a memory cell group. Multiple gate structures 30 are arranged along a third direction Y1, which is perpendicular to the first direction X and the stacking direction Z. Two memory cell groups are disposed between two adjacent gate structures 30.

[0045] The first direction X can be referred to as the row direction. In each memory cell group, the channel structure 20 is positioned closer to the gate structure 30 than the capacitor structure 40. Therefore, the two rows of capacitor structures 40 are located between the two rows of channel structures 20. Each gate structure 30 surrounds a portion of the sidewall of a row of channel structures 20, so that one gate structure 30 controls one row of channel structures 20, and two gate structures 30 can control both rows of channel structures 20.

[0046] See Figure 3 The gate structure 30 is located between two adjacent insulating layers 11 and connected to the dielectric layer 12, meaning that a portion of the dielectric layer 12 is replaced by the gate structure 30. Each gate structure 30 can drive the memory cell MC on the same layer.

[0047] In some embodiments, such as Figure 2 As shown, along the first direction X, the memory cells MC in the two memory cell groups are staggered. This allows for full utilization of the gaps between adjacent memory cells MC to increase the density of the arrangement, thereby improving storage density.

[0048] In some embodiments, the gate structure 30 includes a main body portion 30a and an extension portion 30b connected to each other. The main body portion 30a extends along the first direction X, and the extension portion 30b includes a plurality of extension structures 301 arranged at intervals along the first direction X. The extension structures 301 surround a portion of the sidewall of the channel structure 20. That is, each extension structure 301 is provided corresponding to one channel structure 20, and the main body portion 30a connects the plurality of extension structures 301 together.

[0049] In some embodiments, the protruding structure 301 includes a connecting conductive layer 302 disposed around the sidewall of the channel structure 20, and at least a portion of the connecting conductive layer 302 is located between the channel structure 20 and the gate structure 30. The connecting conductive layer 302 has a first opening 303 (see...). Figure 24 The channel structure 20 is connected to the capacitor structure 40 through the first opening 303.

[0050] The conductive layer 302 contacts the gate structure 30, achieving electrical connection with it. Therefore, the conductive layer 302 also functions as a gate control mechanism for the channel structure 20. Furthermore, by surrounding the sidewall of the channel structure 20 with the conductive layer 302, the facing area between the gate and the channel structure 20 is increased, enhancing the gate's control effect. The first opening 303 of the conductive layer 302 is used to achieve electrical connection between the channel structure 20 and the capacitor structure 40, preventing isolation between them.

[0051] In some embodiments, a portion of the sidewall of the channel structure 20 surrounded by the conductive layer 302 is convex. Therefore, the corresponding main body portion 30a has an inner sidewall 31 facing the channel structure 20 (i.e., the sidewall closest to the channel structure 20). The main body portion 30a has a plurality of recesses 32 recessed inward relative to the inner sidewall 31. Each recess 32 is fitted into one channel structure 20, meaning the channel structure 20 is embedded within the main body portion 30a. This fitted structure increases the relative area between the main body portion 30a and the channel structure 20, improving the control capability of the gate structure 30 over the channel structure 20. Simultaneously, the fitted arrangement increases the connection stability between the two, preventing misalignment during fabrication and improving the structural consistency and yield rate of the device.

[0052] In some embodiments, the gate structure 30 includes a first conductive layer 33 and a second conductive layer 34, the first conductive layer 33 extending along the first direction X, the second conductive layer 34 surrounding the surface of the first conductive layer 33, and the second conductive layer 34 being in contact with the connecting conductive layer 302.

[0053] The second conductive layer 34 is located on the surface of the first conductive layer 33 and extends along the first direction X together with the first conductive layer 33. Grooves 32 are formed on the surfaces of both the first conductive layer 33 and the second conductive layer 34, so that the inner sidewall 31 of the gate structure 30 has grooves 32. The second conductive layer 34 can block metal diffusion in the material of the first conductive layer 33, wherein the material of the first conductive layer 33 may include tungsten, and the material of the second conductive layer 34 may include titanium nitride.

[0054] In some embodiments, see Figure 2 The channel structure 20 includes an annular portion 21 and an outwardly protruding portion 22, the outwardly protruding portion 22 connecting the capacitor structure 40 and the annular portion 21. Figure 3 As shown, the protruding portion 22 is located between two adjacent insulating layers 11, and at least part of the annular portion 21 is also located between adjacent insulating layers 11.

[0055] It should be noted that, as Figure 2As shown, the distance from each edge of the annular portion 21 to the center of the channel structure 20 is the same. The portion that extends further into the adjacent insulating layer 11 relative to the annular portion 21 is the outward protrusion 22, thereby defining the boundary between the annular portion 21 and the outward protrusion 22.

[0056] In some embodiments, the semiconductor device 100 further includes a gate insulating layer 60 located between the gate structure 30 and the channel structure 20. The gate insulating layer 60 can achieve insulation isolation between the gate structure 30 and the channel structure 20, ensuring the normal operation of the device. At the same time, the gate insulating layer 60 is disposed around the channel structure 20, which can protect the channel structure 20 and reduce damage to the channel structure 20 from external factors.

[0057] The gate insulating layer 60 has a second opening 61 (see Figure 32 The protrusion 22 is connected to the capacitor structure 40 through the second opening 61. The second opening 61 ensures that the electrical connection between the channel structure 20 and the capacitor structure 40 is not affected by the gate insulating layer 60, achieving the dual requirements of insulation isolation and signal conduction, eliminating the need for an additional conduction structure and saving chip area.

[0058] That is, the first opening 303 and the second opening 61 are respectively used to allow the protrusion 22 to extend from the conductive layer 302 and the gate insulating layer 60 to connect the capacitor structure 40. The protrusion 22 passes through the first opening 303 and the second opening 61 along the second direction Y2.

[0059] In some embodiments, the capacitor structure 40 includes a first electrode 41, a second electrode 42, and a dielectric layer 43. The first electrode 41 extends along the stacking direction Z, and the second electrode 42 is located between two adjacent insulating layers 11 and is disposed around the first electrode 41, contacting the sidewall of the channel structure 20. The dielectric layer 43 is located between the first electrode 41 and the second electrode 42 to isolate the first electrode 41 and the second electrode 42.

[0060] In this configuration, the first electrode 41 serves as a common electrode, and the second electrode 42 of each layer forms a capacitor with the first electrode 41. Since the second electrode 42 is located between two adjacent insulating layers 11, the second electrodes 42 of different layers are isolated by the insulating layer 11, that is, the capacitors of different layers are isolated by the insulating layer 11.

[0061] In one example, see Figure 3 The dielectric layer 12 has a first surface that contacts the second electrode 42, and the insulating layer 11 has a second surface that contacts the dielectric layer 43. The first surface is recessed inward relative to the second surface to form a first groove 442 (see...). Figure 23The first groove 442 is located between two adjacent insulating layers 11, the second electrode 42 is located on the inner wall of the first groove 442, and at least part of the dielectric layer 43 is located within the groove 32.

[0062] The material of the first electrode 41 may include at least one of a metal and a metal nitride, and the material of the second electrode 42 may include at least one of a metal and a metal nitride. The materials of the first electrode 41 and the second electrode 42 may be the same or different. Figure 2 and Figure 3 In this embodiment, the first electrode 41 includes a fifth conductive layer 411 and a sixth conductive layer 412, the sixth conductive layer 412 being disposed around the surface of the fifth conductive layer 411. An exemplary material for the fifth conductive layer 411 includes titanium nitride, and an exemplary material for the sixth conductive layer 412 includes tungsten. The dielectric layer 43 may be made of a high dielectric constant material, such as at least one of alumina, zirconium oxide, and hafnium oxide.

[0063] In some embodiments, see Figure 2 The second electrode 42 includes a first sidewall 421 and a second sidewall 422. The first sidewall 421 surrounds a portion of the sidewall of the dielectric layer 43 and is connected to the outward protrusion 22. The second sidewall 422 surrounds the remaining sidewall of the dielectric layer 43, and the distance from the second sidewall 422 to the first electrode 41 is greater than the distance from the second sidewall 422 to the first electrode 41. That is, the first sidewall 421, which contacts the outward protrusion 22, is recessed inward relative to the second sidewall 422 to achieve a mating contact between the second electrode 42 and the outward protrusion 22.

[0064] The protruding portion 22 of the channel structure 20 enables precise docking with the second electrode 42, ensuring a stable electrical connection between the two. The recessed sidewall design of the second electrode 42 increases the contact area between the second electrode 42 and the channel structure 20 without increasing the area occupied by the capacitor structure 40, further optimizing the energy storage performance of the capacitor. Simultaneously, the recessed design of the second electrode 42 and the protruding design of the channel structure 20 prevent interference between the second electrode 42 and other structures (such as the conductive layer 302), ensuring the rationality of the structural layout and reducing short circuits.

[0065] See Figure 2 The conductive layer 302 and the gate insulating layer 60 are both disposed around the channel structure 20, but their specific positions on the surface of the channel structure 20 may differ. See also Figure 3The annular portion 21 of the channel structure 20 includes a first portion and a second portion connected together. The first portion extends along the stacking direction Z, and the second portion is located between adjacent insulating layers 11 and connected to the outward protrusion 22. A connecting conductive layer 302 is located on the surface of the first portion, and a first opening 303 of the connecting conductive layer 302 exposes the sidewall of the outward protrusion 22 that contacts the second electrode 42. The gate insulating layer 60 is located on the outer surface of the entire channel structure 20.

[0066] The semiconductor device 100 may further include a substrate 80, and both the channel structure 20 and the capacitor structure 40 may extend into the substrate 80. In one example, see [reference needed]. Figure 3 and Figure 4 The gate insulating layer 60 is also located on the bottom surface of the channel structure 20 to isolate the bottom of the channel structure 20 from the substrate 80, thereby enhancing the isolation effect between the bottoms of adjacent channel structures 20.

[0067] Accordingly, this application also provides a method for forming a semiconductor device, for forming the above-mentioned semiconductor device 100.

[0068] Please see Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: Step S1: Form a stacked structure, the stacked structure comprising alternately stacked insulating layers and dielectric layers; Step S2: A gate structure is formed between two adjacent insulating layers, the gate structure extending along a first direction, the first direction being perpendicular to the stacking direction of the stacked structure; Step S3: Form a capacitor structure and a channel structure that run through the stacked structure along the stacking direction. The gate structure surrounds at least a portion of the sidewall of the channel structure. Another portion of the sidewall of the channel structure is connected to the capacitor structure. Multiple capacitor structures and multiple channel structures are arranged at intervals along the first direction. The capacitor structures and channel structures connected along the second direction constitute a memory cell. Multiple memory cells are arranged at intervals along the first direction. The second direction is perpendicular to the stacking direction and intersects the first direction.

[0069] In the semiconductor device formation method of this application embodiment, the gate structure extends along a first direction and at least surrounds a portion of the sidewalls of the channel structure, while the capacitor structure is connected to another portion of the sidewalls of the channel structure, thereby realizing the basic storage function of the semiconductor device. Since the stacked structure uses alternating layers of insulating and dielectric layers, and the channel structure penetrates the stacked structure, both the insulating and dielectric layers can naturally achieve insulation separation between adjacent channel structures and bit line structures, eliminating the need for additional dedicated isolation structures, thus saving chip area and increasing storage density. Simultaneously, multiple capacitor structures and multiple channel structures are arranged at intervals along the first direction, and capacitor structures and channel structures connected along a second direction constitute a storage cell. Multiple storage cells are arranged at intervals along the first direction, the second direction is perpendicular to the stacking direction, and the second direction intersects the first direction. This arrangement further saves area and increases storage density.

[0070] The method for forming a semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0071] Please see Figures 6 to 41 , Figures 6 to 41 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0072] Step S1: Form a stacked structure 10, which includes alternately stacked insulating layers 11 and dielectric layers 12. See also Figure 6 and Figure 7 .

[0073] In some embodiments, a substrate 80 is provided first, and then a stacked structure 10 is formed on the substrate 80.

[0074] See Figure 6 An insulating layer 11 and a dielectric layer 12 are sequentially and alternately formed on a substrate 80 to form multiple stacked layer pairs. Each stacked layer pair consists of one insulating layer 11 and one dielectric layer 12, with the insulating layer 11 positioned below the dielectric layer 12. Therefore, the insulating layer 11 is in contact with the substrate 80 to isolate the subsequently formed memory cells from the substrate 80.

[0075] See Figure 7 An additional insulating layer is formed on the stacked layers as a protective layer 13.

[0076] It is understandable that the number of layers in the stacked structure 10 determines the number of memory cells it contains in the stacking direction Z. The more layers the stacked structure 10 has, the higher the integration of the corresponding three-dimensional memory.

[0077] The substrate 80 can be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including semiconductors of other elements or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0078] The insulating layer 11 and the dielectric layer 12 have different etching selectivity. An exemplary material for the insulating layer 11 is silicon oxide, and an exemplary material for the dielectric layer 12 is silicon nitride. The formation process of the insulating layer 11 and the dielectric layer 12 includes a deposition process, which can employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0079] Step S2: A gate structure 30 is formed between two adjacent insulating layers 11. The gate structure 30 is connected to the dielectric layer 12. The gate structure 30 extends along a first direction X, which is perpendicular to the stacking direction Z of the stacked structure 10.

[0080] In order to combine with the formation process of other structures, the method of forming the gate structure 30 will be described below, because in some embodiments of this application, the formation process of the gate structure 30 can be aided by part of the processes of the capacitor structure 40 and the channel structure 20.

[0081] Step S3: Form a capacitor structure 40 and a channel structure 20 that extend through the stacked structure 10 along the stacking direction Z. The gate structure 30 surrounds a portion of the sidewall of the channel structure 20, and the other portion of the sidewall of the channel structure 20 is connected to the capacitor structure 40. The capacitor structure 40 and the channel structure 20 are respectively arranged along the first direction X. The connected capacitor structure 40 and channel structure 20 are arranged along the second direction Y2. The second direction Y2 is perpendicular to the stacking direction Z, and the angle between the second direction Y2 and the first direction X is an acute angle.

[0082] like Figure 2 As shown, multiple gate structures 30 are arranged along a third direction Y1, which is perpendicular to the first direction X and the stacking direction Z. Two memory cell groups are formed between two adjacent gate structures 30. Each memory cell group includes multiple memory cells MC arranged at intervals along the first direction X.

[0083] In some embodiments, see Figures 8 to 11 , Figure 39 and Figure 41 The method for forming the channel structure 20 includes the following steps.

[0084] See Figure 8 and Figure 9 An initial channel hole 241 is formed that penetrates the stacked structure 10 along the stacking direction Z.

[0085] In some embodiments, the initial channel hole 241 can be formed in the same etching process as the initial capacitor hole 441 during the formation of the capacitor structure 40 described below, to prevent alignment problems caused by step etching and to simplify the process. The etching process may include anisotropic etching processes, such as dry etching processes, which can precisely control the etching direction and etching depth. Therefore, the initial capacitor hole 441 has the same depth as the initial channel hole 241.

[0086] in, Figure 9 Show Figure 8 The cross-sectional structure of the semiconductor device 100 at C-C1 is shown to illustrate the arrangement relationship between the initial capacitor hole 441 and the initial channel hole 241. The arrangement relationship can be determined based on the positional relationship between the final capacitor structure 40 and the channel structure 20.

[0087] See Figure 10 A first sacrificial layer 91 is formed within the initial capacitor hole 441.

[0088] The material of the first sacrificial layer 91 may include polysilicon, and the formation process of the first sacrificial layer 91 may include a deposition process. For example, a mask or a shielding layer may be used to shield the initial channel hole 241 so that the first sacrificial layer 91 is deposited in the initial capacitor hole 441.

[0089] See Figure 11 After the first sacrificial layer 91 is formed, the dielectric layer 12 is partially etched through the channel hole 24 to form a second groove 242. The second groove 242 is connected to the initial channel hole 241 to form the channel hole 24.

[0090] In other words, the first sacrificial layer 91 is formed before the second groove 242 is formed. The etching process for forming the second groove 242 may include a wet etching process, in which the dielectric layer 12 is etched at a higher rate than the insulating layer 11. The step of forming the second groove 242 can bring the distance between the channel hole 24 and the initial capacitor hole 441 closer, facilitating the subsequent electrical connection between the channel structure 20 and the capacitor structure 40.

[0091] See Figure 39 and Figure 41 A channel layer 23 is formed on the inner wall of the channel hole 24.

[0092] like Figure 39 As shown, an initial channel layer 23a is formed on the inner wall of the channel hole 24 and on the surface of the stacked structure 10; as Figure 41 As shown, the initial channel layer 23a is planarized until the surface of the stacked structure 10 is exposed to form the channel layer 23.

[0093] The formation process of the initial channel layer 23a may include a deposition process, and the planarization process may include a chemical mechanical polishing process.

[0094] The material of the initial channel layer 23a may include semiconductor materials, such as indium gallium zinc oxide (IGZO). The formation process of the initial channel layer 23a may include any of the deposition processes described above. It should be noted that the initial channel layer 23a does not completely fill the channel via 24, reserving space for the subsequent formation of the bit line structure 70.

[0095] In some embodiments, see Figure 40 and Figure 41 The method of forming the semiconductor device 100 further includes forming a fourth conductive layer 72 and a third conductive layer 71 on the surface of the channel layer 23, wherein the fourth conductive layer 72 is disposed around the outer surface of the third conductive layer 71 to form a bit line structure 70.

[0096] See Figure 40 A fourth initial conductive layer 72a is formed on the surface of the initial channel layer 23a; a third initial conductive layer 71a is formed on the surface of the fourth initial conductive layer 72a.

[0097] An exemplary material for the fourth initial conductive layer 72a includes titanium nitride, and an exemplary material for the third initial conductive layer 71a includes tungsten. The formation processes of the third initial conductive layer 71a and the fourth initial conductive layer 72a include any of the deposition processes described above.

[0098] See Figure 41 The fourth initial conductive layer 72a, the third initial conductive layer 71a, and the initial channel layer 23a are planarized until the surface of the stacked structure 10 is exposed, forming the fourth conductive layer 72, the third conductive layer 71, and the channel layer 23 located within the channel hole 24 and the external protrusion hole 25. Among them, the fourth conductive layer 72 and the third conductive layer 71 constitute the bit line structure 70.

[0099] The planarization process may include a chemical mechanical polishing process. That is, the planarization of the initial channel layer 23a can be performed together with the fourth initial conductive layer 72a and the third initial conductive layer 71a.

[0100] In some embodiments, see Figure 8 and Figure 9 , Figure 22 and Figure 23 , Figures 33 to 37 The method for forming the capacitor structure 40 includes the following steps.

[0101] See Figure 8 and Figure 9 An initial capacitor hole 441 is formed that penetrates the stacked structure 10 along the stacking direction Z.

[0102] See Figure 22 Remove the first sacrificial layer 91.

[0103] The method for removing the first sacrificial layer 91 includes: forming a mask layer M on the surface of the stacked structure 10, wherein the opening of the mask layer M exposes the initial capacitor hole 441; and performing an etching process on the first sacrificial layer 91 through the opening to remove the first sacrificial layer 91.

[0104] The etching process for the first sacrificial layer 91 may include a wet etching process, in which the etching selectivity of the first sacrificial layer 91 is relatively large relative to that of the insulating layer 11 and the dielectric layer 12.

[0105] See Figure 23 After removing the first sacrificial layer 91, the dielectric layer 12 is partially etched through the initial capacitor hole 441 to form a first groove 442 located between two adjacent insulating layers 11.

[0106] The etching process for the dielectric layer 12 may include an isotropic wet etching process, in which the etching selection of the dielectric layer 12 is relatively large compared to that of the insulating layer 11.

[0107] See Figure 33 and Figure 34 A second electrode 42 is formed on the inner wall of the first groove 442.

[0108] like Figure 33 As shown, the inner walls of the initial capacitor hole 441 and the first groove 442 form the initial second electrode 42a; as Figure 34 As shown, the initial second electrode 42a is etched to remove a portion of the initial second electrode 42a located on the inner wall of the initial capacitor hole 441, forming a second electrode 42 located on the inner wall of the first groove 442.

[0109] The formation process of the initial second electrode 42a includes any of the above deposition processes, and the etching process of the initial second electrode 42a may include anisotropic dry etching processes.

[0110] See Figure 35 A dielectric layer 43 is formed on the surface of the second electrode 42 layer and the inner wall of the initial capacitor hole 441.

[0111] In some embodiments, a portion of the dielectric layer 43 is filled within the first groove 442.

[0112] The material of the dielectric layer 43 may include any of the high dielectric constant materials described above, and the formation process of the dielectric layer 43 includes any of the deposition processes described above.

[0113] See Figure 36 and Figure 37 A first electrode 41 is formed on the surface of the dielectric layer 43.

[0114] in, Figure 37 Show Figure 36 Cross-sectional structure of semiconductor device 100 at E-E1.

[0115] The method of forming the first electrode 41 may include: forming a sixth conductive layer 412 on the surface of the dielectric layer 43; forming a fifth conductive layer 411 on the surface of the fifth conductive layer 411, wherein the fifth conductive layer 411 fills the initial capacitor hole 441.

[0116] In some embodiments, see Figures 12 to 21 The method for forming the gate structure 30 includes the following steps.

[0117] See Figure 12 A conductive layer 302 is formed on the inner wall of the second groove 242.

[0118] The method for forming the conductive connection layer 302 may include: forming an initial connection layer on the inner wall of the channel hole 24; removing a portion of the initial connection layer located outside the second groove 242 to form the conductive connection layer 302 located on the inner wall of the second groove 242. It should be noted that this conductive connection layer 302 needs to be formed before forming the channel layer 23, so that the conductive connection layer 302 can subsequently be disposed around the sidewall of the channel layer 23.

[0119] In some embodiments, Figure 11 After the second groove 242 is formed, the conductive layer 302 is immediately formed. Part of the conductive layer 302 can be removed using the first groove 442 formed during the subsequent formation of the capacitor structure 40. Therefore, Figure 13The step of filling the second sacrificial layer 92 into the channel hole 24 is performed after the conductive layer 302 is formed.

[0120] See Figure 13 A second sacrificial layer 92 is filled into the channel hole 24.

[0121] After the second sacrificial layer 92 is formed, a chemical mechanical polishing process is performed until the surface of the stacked structure 10 is exposed. The chemical mechanical polishing process removes a portion of the conductive layer 302 and a portion of the second sacrificial layer 92 located on the stacked structure 10.

[0122] See Figure 14 After the second sacrificial layer 92 is formed, a trench 35 is formed through the stacked structure 10, the trench 35 extending along the first direction X.

[0123] It should be noted that the formation process of the trench 35 may include anisotropic etching processes, such as dry etching processes. A second sacrificial layer 92 is formed before forming the trench 35, so that the second sacrificial layer 92 can protect the channel hole 24 and prevent the products of the etching process for forming the trench 35 from affecting the channel hole 24.

[0124] See Figure 15 The dielectric layer 12 is partially etched through the trench 35 to remove the dielectric layer 12 located between the second sacrificial layer 92 and the trench 35, forming a gate line groove 36 extending along the first direction X.

[0125] The process of forming the gate groove 36 may include a wet etching process, in which the etching selectivity of the dielectric layer 12 relative to the insulating layer 11 is relatively large, so as to selectively etch the dielectric layer 12.

[0126] It should be noted that, in order to form a gate structure 30 and a channel structure 20 that are interlocked, the position of the channel hole 24 is first defined, and then the shape of the gate structure 30 surrounding the partial channel structure 20 is defined by etching a portion of the dielectric layer 12. Therefore, the second sacrificial layer 92 also serves as an etching stop layer for the etching process that forms the gate line groove 36. That is, the dielectric layer 12 removed by the trench 35 is located between the second sacrificial layer 92 and the trench 35.

[0127] In other embodiments, the gate groove 36 may be formed after the channel layer 23 is formed in the channel hole 24, that is, the etching process of the gate groove 36 may use the channel layer 23 as the stop layer.

[0128] See Figures 16 to 21A conductive structure is filled in the gate groove 36, and the conductive structure and the connecting conductive layer 302 constitute the gate structure 30.

[0129] like Figure 16 As shown, a second initial conductive layer 34a is formed in the gate groove 36, and the material of the second initial conductive layer 34a includes titanium nitride.

[0130] like Figure 17 As shown, a first initial conductive layer 33a is formed on the surface of the second initial conductive layer 34a, and the material of the first initial conductive layer 33a includes tungsten. The second initial conductive layer 34a and the first initial conductive layer 33a fill the gate groove 36 and are located on the surface of the trench 35.

[0131] See Figure 18 , Figure 19 and Figure 20 The first initial conductive layer 33a and the second initial conductive layer are etched back to remove portions of the first initial conductive layer 33a and the second initial conductive layer 34a located within the trench 35, forming a first conductive layer 33 and a second conductive layer 34 located within the gate line groove 36. The first conductive layer 33 and the second conductive layer 34 constitute the conductive structure.

[0132] It should be noted that, Figure 19 Show Figure 18 A cross-sectional view at position D-D1, i.e., a top view of the structure at position 12 of the dielectric layer. Figure 20 Show Figure 19 The schematic diagram of the three-dimensional structure omits the structure formed in the stacked structure 10, mainly showing the position of the groove 35.

[0133] See Figure 21 Insulating material is filled into the trench 35 to form an isolation structure 351.

[0134] The insulating material may include oxides or nitrides, such as silicon oxide and silicon nitride.

[0135] It should be noted that the embodiments of this application only show two adjacent gate structures 30 and the structure located in between, but this application is not limited to this. For example, the semiconductor device 100 may also include four gate structures 30 and four rows of cell groups, wherein there are two rows of cell groups between two adjacent gate structures 30, and two rows of cell groups between the other two gate structures 30. The isolation structure 351 can be used to isolate two gate structures 30 that are close to each other.

[0136] In some embodiments, see Figure 24The method of forming the semiconductor device 100 further includes: after forming the first groove 442, removing a portion of the connecting conductive layer 302 through the first groove 442 to form a first opening 303 exposing the second sacrificial layer 92.

[0137] In this embodiment of the application, in order to ensure the connection between the channel layer 23 and the second electrode 42, a first opening 303 is formed by removing part of the conductive layer 302 through the first groove 442. This not only enhances the control effect of the gate, but also ensures the subsequent contact between the second electrode 42 and the channel layer 23.

[0138] In some embodiments, Figure 13 The conductive connecting layer 302 is formed before the second sacrificial layer 92. This results in a relatively large distance between the conductive connecting layer 302 and the second electrode 42, reducing the risk of short circuits between them. Since there is a subsequent process to form the external protrusion hole 25, forming the conductive connecting layer 302 after the external protrusion hole 25 would result in a smaller distance between the conductive connecting layer 302 and the second electrode 42, potentially causing a short circuit (described in detail later).

[0139] In some embodiments, the first groove 442 communicates with the initial capacitor hole 441 to form a capacitor hole 44.

[0140] See Figures 25 to 32 The method for forming the semiconductor device 100 further includes the following steps, the purpose of which is to form an external protrusion 25 and a gate insulating layer 60.

[0141] See Figure 25 After the first opening 303 is formed, a third sacrificial layer 93 is formed inside the capacitor hole 44.

[0142] See Figure 26 After the third sacrificial layer 93 is formed, the second sacrificial layer 92 is removed.

[0143] The process for removing the second sacrificial layer 92 includes a wet etching process, in which the etching selection of the second sacrificial layer 92 is greater than that of the third sacrificial layer 93. The material of the third sacrificial layer 93 may be different from that of the second sacrificial layer 92. For example, the material of the third sacrificial layer 93 may be either polysilicon or a spin-coated carbon layer, while the material of the second sacrificial layer 92 may be either polysilicon or a spin-coated carbon layer.

[0144] See Figure 27 The third sacrificial layer 93 is partially etched through the channel hole 24 to form an external protrusion hole 25 that communicates with the channel hole 24.

[0145] It should be noted that although the etching selection of the second sacrificial layer 92 is larger than that of the third sacrificial layer 93, some of the top of the third sacrificial layer 93 is consumed during the etching process of removing the second sacrificial layer 92.

[0146] See Figure 28 After the external protrusion hole 25 is formed, the inner wall of the channel hole 24 and the external protrusion hole 25 forms a gate insulating layer 60.

[0147] See Figure 29 A fourth sacrificial layer 94 is formed on the surface of the gate insulating layer 60.

[0148] The formation process of the gate insulating layer 60 and the fourth sacrificial layer 94 includes any of the above deposition processes.

[0149] See Figure 30 The fourth sacrificial layer 94 and the gate insulating layer 60 are planarized until the surface of the third sacrificial layer 93 is exposed.

[0150] The planarization process may include a chemical mechanical polishing (CMP) process. The CMP process is used to remove a portion of the fourth sacrificial layer 94 and a portion of the gate insulating layer 60 located on top of the third sacrificial layer 93, with the third sacrificial layer 93 serving as the stop layer.

[0151] It should be noted that in the chemical mechanical polishing process, the protective layer 13 is partially removed to avoid damage to the dielectric layer 12.

[0152] See Figure 31 Remove the third sacrificial layer 93.

[0153] The removal process of the third sacrificial layer 93 includes a wet etching process, in which the third sacrificial layer 93 has a larger etching selectivity than the fourth sacrificial layer 94.

[0154] See Figure 32 A portion of the gate insulating layer 60 is removed through the capacitor hole 44, forming a second opening 61 that exposes the fourth sacrificial layer 94.

[0155] In some embodiments, the second electrode 42 is formed after the second opening 61, so the second electrode 42 covers the second opening 61, thus the capacitor hole 44 can be used to form an opening to ensure the subsequent contact between the second electrode 42 and the channel layer 23.

[0156] In other embodiments, the conductive layer 302 may be formed before the gate insulating layer 60, and the second opening 61 may be formed before the first opening 303. That is, in Figure 28In the process, a conductive layer 302 is first formed, followed by a gate insulating layer 60; Figure 32 In this process, a portion of the gate insulating layer 60 is first removed to form the second opening 61, and then a portion of the conductive layer 302 is removed to form the first opening 303. However, this would result in the conductive layer 302 being closer to the second electrode 42 (as described above).

[0157] In some embodiments, see Figure 38 and Figure 41 The method for forming the channel structure 20 further includes the following steps.

[0158] See Figure 38 After the capacitor structure 40 is formed (i.e., after the first electrode 41 is formed), the fourth sacrificial layer 94 is removed.

[0159] See Figure 41 The channel layer 23 is formed within the channel hole 24 and the external protrusion hole 25.

[0160] In other embodiments, it is possible to Figure 28 Based on this, after forming the external convex hole 25, a channel layer 23 and a bit line structure 70 are first formed within the external convex hole 25 and the channel hole 24. Then, a portion of the gate insulating layer 60 is removed through the capacitor hole 44 to form a second opening 61, and finally, the capacitor structure 40 is formed. However, this method can easily damage the channel layer 23 during the etching process of forming the second opening 61. Therefore, Figure 38 In this embodiment, the channel layer 23 is formed after the gate insulating layer 60 and the capacitor structure 40 are formed. The gate insulating layer 60 can protect the channel layer 23 and reduce the damage to the channel layer 23 caused by the etching process.

[0161] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0162] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0163] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0164] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, comprising alternating layers of insulating and dielectric; A channel structure that penetrates the stacked structure along the stacking direction of the stacked structure; A gate structure extending along a first direction perpendicular to the stacking direction, the gate structure at least surrounding a portion of the sidewall of the channel structure; A capacitor structure extends through the stacking structure along the stacking direction, and the capacitor structure is connected to another part of the sidewall of the channel structure; Among them, the plurality of capacitor structures and the plurality of channel structures are arranged at intervals along the first direction; The capacitor structure and the channel structure connected along the second direction constitute a memory cell. A plurality of memory cells are arranged at intervals along the first direction. The second direction is perpendicular to the stacking direction and intersects the first direction.

2. The semiconductor device according to claim 1, characterized in that, The angle between the second direction and the first direction is an acute angle.

3. The semiconductor device according to claim 1, characterized in that, Multiple memory cells arranged at intervals along the first direction constitute a memory cell group. Multiple gate structures are arranged at intervals along a third direction, which is perpendicular to the first direction and the stacking direction. Two memory cell groups are arranged between two adjacent gate structures.

4. The semiconductor device according to claim 3, characterized in that, Along the first direction, the storage cells in the two storage cell groups are staggered.

5. The semiconductor device according to claim 1, characterized in that, The gate structure includes a connected main body and an extension, the main body extending along the first direction, and the extension including a plurality of extension structures spaced apart along the first direction, the extension structures surrounding a portion of the sidewall of the channel structure.

6. The semiconductor device according to claim 5, characterized in that, The protruding structure includes a connecting conductive layer having a first opening, and the channel structure is connected to the capacitor structure through the first opening.

7. The semiconductor device according to claim 6, characterized in that, The channel structure includes an annular portion and an outwardly protruding portion, with the outwardly protruding portion connecting the capacitor structure and the annular portion.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a gate insulating layer located between the gate structure and the channel structure, the gate insulating layer having a second opening, and the protrusion being connected to the capacitor structure through the second opening.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The semiconductor device further includes: Bit line structure, penetrating the stacking structure along the stacking direction; The channel structure is arranged around the bit line structure.

10. A method for forming a semiconductor device, characterized in that, include: A stacked structure is formed, the stacked structure comprising alternately stacked insulating layers and dielectric layers; A gate structure is formed between two adjacent insulating layers, the gate structure extending along a first direction perpendicular to the stacking direction of the stacked structure; A capacitor structure and a channel structure are formed that extend through the stacked structure along the stacking direction. The gate structure surrounds at least a portion of the sidewall of the channel structure, and another portion of the sidewall of the channel structure is connected to the capacitor structure. A plurality of capacitor structures and a plurality of channel structures are arranged at intervals along the first direction. The capacitor structures and the channel structures connected along the second direction constitute a memory cell. A plurality of memory cells are arranged at intervals along the first direction. The second direction is perpendicular to the stacking direction and intersects the first direction.

11. The method for forming a semiconductor device according to claim 10, characterized in that, Multiple gate structures are spaced apart along a third direction, which is perpendicular to the first direction and the stacking direction. Two memory cell groups are formed between two adjacent gate structures, and each memory cell group includes multiple memory cells spaced apart along the first direction.

12. The method for forming a semiconductor device according to claim 10 or 11, characterized in that, The method for forming the capacitor structure includes: An initial capacitor hole is formed that penetrates the stacked structure along the stacking direction; The dielectric layer is partially etched through the initial capacitor hole to form a first groove located between two adjacent insulating layers. A second electrode is formed on the inner wall of the first groove; A dielectric layer is formed on the surface of the second electrode and on the inner wall of the initial capacitor hole; A first electrode is formed on the surface of the dielectric layer.

13. The method for forming a semiconductor device according to claim 12, characterized in that, The method for forming the channel structure includes: Forming initial channel holes that penetrate the stacked structure along the stacking direction; The dielectric layer is partially etched through the channel hole to form a second groove, and the second groove communicates with the initial channel hole to form a channel hole. A channel layer is formed on the inner wall of the channel hole.

14. The method for forming a semiconductor device according to claim 13, characterized in that, The method for forming the gate structure includes: After the channel hole is formed, a connecting conductive layer is formed on the inner wall of the second groove, and a second sacrificial layer is filled in the channel hole; A trench is formed that penetrates the stacked structure and extends along the first direction; Remove the dielectric layer located between the second sacrificial layer and the trench to form a gate line groove extending along the first direction; A conductive structure is filled within the gate line groove, and the conductive structure and the connecting conductive layer constitute the gate structure.

15. The method for forming a semiconductor device according to claim 14, characterized in that, The method further includes: After the first groove is formed, a portion of the conductive layer is removed through the first groove to form a first opening that exposes the second sacrificial layer; After forming the third sacrificial layer in the capacitor hole, the second sacrificial layer is removed; The third sacrificial layer is partially etched through the channel hole to form an outwardly protruding hole communicating with the channel hole; A gate insulating layer is formed on the inner wall of the channel hole and the external protrusion hole, and a fourth sacrificial layer is formed on the surface of the gate insulating layer; The third sacrificial layer is removed, and a portion of the gate insulating layer is removed through the capacitor hole to form a second opening that exposes the fourth sacrificial layer.

16. The method for forming a semiconductor device according to claim 15, characterized in that, The method further includes: after forming the capacitor structure, removing the fourth sacrificial layer; and forming the channel layer in the channel hole and the protruding hole.

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