Memory device and electronic system

Abstract

The application provides a memory device and an electronic system, the memory device comprising: a memory array and a peripheral circuit stacked in a first direction; a plurality of bonding contacts between the memory array and the peripheral circuit, the peripheral circuit and the memory array being coupled at least through the bonding contacts; the memory array comprising: bit lines extending in the first direction, the bit lines being coupled with corresponding bonding contacts; a plurality of word lines extending in a second direction and stacked in the first direction, a plurality of the word lines constituting a stepped structure on one side of the second direction, the second direction intersecting the first direction; a plurality of first connection structures extending in the first direction, the word lines being coupled with corresponding bonding contacts through the first connection structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a storage device and electronic system. Background Technology

[0002] Memory devices are storage equipment used to store information in modern information technology. Some memory devices, including some non-volatile and volatile memories, have become mainstream products in the storage market due to their high storage density, controllable production costs, suitable erasure speeds, and retention characteristics. With the increasing demand for memory devices with high storage density, high storage capacity, and high storage bandwidth, there is still much room for improvement in memory devices. Summary of the Invention

[0003] According to some aspects of embodiments of this application, a storage device is provided, including: a storage array and peripheral circuitry stacked in a first direction; a plurality of bonding contacts located between the storage array and the peripheral circuitry, the peripheral circuitry and the storage array being coupled at least through the bonding contacts; the storage array including: bit lines extending along the first direction, the bit lines being coupled to corresponding bonding contacts; a plurality of word lines extending along a second direction and stacked along the first direction, the plurality of word lines forming a stepped structure on one side of the second direction, the second direction intersecting the first direction; and a plurality of first connection structures extending along the first direction, the word lines being coupled to corresponding bonding contacts through the first connection structures.

[0004] In some embodiments, the stepped surface of the stepped structure faces the peripheral circuit along the first direction.

[0005] In some embodiments, the first connection structure is located between the step surface of the stepped structure and the peripheral circuit, and the first connection structure lands on the corresponding word line.

[0006] In some embodiments, the step surface of the stepped structure is away from the peripheral circuit along the first direction.

[0007] In some embodiments, the memory array further includes: a first interconnect layer located on the side of the stepped surface of the stepped structure facing away from the peripheral circuit; the first interconnect layer includes a plurality of first interconnect lines, the first interconnect lines being coupled to corresponding first connection structures; a second interconnect layer located between the stepped structure and the peripheral circuit; the first interconnect layer includes a plurality of second interconnect lines, the second interconnect lines being coupled to corresponding bonding contacts; a plurality of second connection structures located between the first interconnect layer and the second interconnect layer and extending along the first direction; the second connection structures being coupled to corresponding first interconnect lines and corresponding second interconnect lines.

[0008] In some embodiments, the first connection structure extends through a plurality of word lines along the first direction, the first connection structure is coupled to a corresponding word line, and the first connection structure passes through other word lines and is isolated by a dielectric material.

[0009] In some embodiments, the memory array further includes: a conductive pad located at one end of the word line along the second direction and on the step surface of the stepped structure; the conductive pad is coupled to the word line, and the first connection structure passes through the conductive pad and is coupled to the conductive pad.

[0010] In some embodiments, the storage array further includes: a plurality of sub-storage arrays, each sub-storage array having the stepped structure at one end along the second direction; and the stepped structures of two adjacent sub-storage arrays arranged in the second direction are arranged back-to-back along the second direction.

[0011] In some embodiments, the memory array further includes: a semiconductor body having a first active terminal and a second active terminal; a portion of the word line covering at least a portion of the sidewalls of the semiconductor body; the first active terminal being coupled to the bit line; and a capacitor structure being coupled to the second active terminal.

[0012] In some embodiments, the memory array includes: a first memory array and a second memory array disposed opposite to each other on both sides of the peripheral circuit along the first direction; the bonding contact includes: a first bonding contact located between the first memory array and the peripheral circuit, wherein the peripheral circuit is coupled to the first memory array at least through the first bonding contact; and a second bonding contact located between the second memory array and the peripheral circuit, wherein the peripheral circuit is coupled to the second memory array at least through the second bonding contact.

[0013] In some embodiments, the peripheral circuitry includes a first sub-circuit and a second sub-circuit stacked along the first direction, wherein the first sub-circuit is coupled to the first memory array and the second sub-circuit is coupled to the second memory array.

[0014] In some embodiments, the first sub-circuit and the second sub-circuit are located in different semiconductor structures, and the peripheral circuit further includes a third bonding contact located between the first sub-circuit and the second sub-circuit, wherein the first sub-circuit and the second sub-circuit are coupled at least through the third bonding contact.

[0015] In some embodiments, the first sub-circuit includes: a first word line driving circuit coupled to a first connection structure of the first memory array; and a first sensing amplification circuit coupled to the bit lines of the first memory array; the second sub-circuit includes: a second word line driving circuit coupled to the first connection structure of the second memory array; and a second sensing amplification circuit coupled to the bit lines of the second memory array.

[0016] In some embodiments, the storage device includes: a plurality of memory arrays sequentially bonded on a peripheral circuit; each of the plurality of memory arrays is coupled to the peripheral circuit, and the first connection structure and bit line of each memory array are coupled to the peripheral circuit; wherein the first connection structures coupled to the word lines of the same layer of each memory array are coupled to each other through bonding contacts.

[0017] In some embodiments, the memory array further includes: a plurality of third connection structures, the third connection structures extending at least through the stacked region of the word lines along the first direction; the bit lines of the current layer memory array are bonded to the third connection structures of the lower layer memory array, and coupled to peripheral circuitry through at least one third connection structure.

[0018] According to some aspects of embodiments of this application, an electronic system is provided, including the aforementioned storage device.

[0019] This application provides a storage device, including: a memory array and peripheral circuitry stacked in a first direction; a plurality of bonding contacts located between the memory array and the peripheral circuitry; the peripheral circuitry and the memory array being coupled at least through the bonding contacts; the memory array including bit lines extending along the first direction and coupled to corresponding bonding contacts; bit lines extending along a second direction and coupled to corresponding bonding contacts; and a plurality of word lines extending along the second direction and stacked along the first direction, with one bit line corresponding to one of the plurality of word lines stacked along the first direction, and the plurality of word lines corresponding to one bit line forming a single word line on one side of the second direction. A stepped structure; a plurality of first connection structures extending along a first direction, the plurality of first connection structures being arranged along the stepped surface of the stepped structure, at least a portion of the first connection structure being located on one side of the stepped structure along the first direction, the first connection structure being coupled to a word line, and the first connection structure being coupled to a corresponding bonding contact; by setting the first connection structure at different heights at the ends of the word lines with stepped surfaces, the electrical signals of each word line are led out and coupled to the peripheral circuit through bonding contacts, thereby realizing the power path of the word lines and bit lines in the bonding direction, which improves the storage density while optimizing the distribution of bonding contacts and the power path of the bonding contacts. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an exemplary storage array provided in an embodiment of this application; Figures 2 to 9This is a schematic diagram of the structure of the storage device provided in the embodiments of this application. Detailed Implementation

[0021] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0024] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0027] The memory devices provided in this application's embodiments may include memory structures and other semiconductor structures, and may serve as Dynamic Random Access Memory (DRAM), or at least as a portion of DRAM. The memory devices provided in this application's embodiments may be memory devices or at least a portion of memory devices. The memory devices may be DRAM, or at least a portion of DRAM, or the memory device may include DRAM, and the DRAM may include the memory devices of this application. They are applicable to DDR4 memory specifications, DDR5 memory specifications, Double Data Rate Synchronous Dynamic Random Access Memory, and LPDDR5 memory specifications, and are low-power Double Data Rate Synchronous Dynamic Random Access Memory. The examples of memory devices, semiconductor structures, semiconductor devices, memory devices, and memory systems described in this application's embodiments are merely illustrative, representing a hierarchical logical division of inclusion relationships for ease of explanation. In actual implementation, other division methods may exist, and this application does not limit these. In some other embodiments, multiple structures, chips, units, or components may be combined or integrated into another system, or some features may be ignored or not included.

[0028] In some embodiments, in DRAM, the memory array can be arranged in rows and columns, allowing memory cells to be addressed by specifying the rows and columns of the array. The memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting a memory cell at the intersection of a selected word line and a selected bit line selects it for read, write, or refresh operations. Figure 1 As exemplified, the memory array may include multiple word lines (WL) and multiple bit lines (BL), which intersect but are not connected. Memory cells in the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. Word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is connected to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is connected to the bit line. The other electrode of the capacitor may be grounded or have another voltage (such as Vcc / 2) applied to it. The row and column directions mentioned in this disclosed embodiment are not necessarily horizontal, and the extension directions of the bit lines and word lines are not necessarily horizontal; for example, bit lines may extend vertically, and word lines may extend horizontally; or bit lines may extend horizontally, and word lines may extend vertically.

[0029] Figure 1 The example shown is merely a circuit diagram of a DRAM memory array, where a DRAM memory cell includes a transistor and a capacitor coupled to it. The transistor, capacitor, word line, and bit line are integrated into the circuit. Figure 1Based on the electrical connection, the transistors can have any physical structure and relative position, and this embodiment does not impose specific limitations on the specific structure and position. For example, transistors and capacitors can be arranged in a horizontal direction, or transistors and capacitors can be stacked in a vertical direction (the thickness direction of the wafer or semiconductor structure). Transistors may include, but are not limited to, planar transistors, in which the source, channel, and drain of the transistor are arranged horizontally in a doped semiconductor film manner; or transistors may include, but are not limited to, three-dimensional transistors, in which the source, channel, and drain of the transistor are arranged in one direction on a semiconductor body; word lines may cover at least one side of the channel of the semiconductor body, or surround the channel. For example, transistors and capacitors may be arranged in a first lateral direction, bit lines may extend in a vertical direction, and word lines may extend in a second lateral direction intersecting or perpendicular to the first lateral direction; or transistors and capacitors may be arranged in a first lateral direction, bit lines may extend in a second lateral direction, and word lines may extend in a vertical direction.

[0030] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0031] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0032] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1Peripheral circuitry connected to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to, sense amplifier circuitry, row decoding circuitry, column decoding circuitry, and voltage generation circuitry. The sense amplifier circuitry is connected to the bit lines and is configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sense amplifier circuitry may include latches to latch the reconstructed capacitor voltage value, allowing information stored in the memory cell to be transferred from the capacitor to the amplifier circuitry. The sense amplifier circuitry may include differential sense amplifier circuitry connected to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuitry is configured to address the memory array and apply operating voltages to the word lines. The column decoding circuitry is configured to address the memory array by column, applying or receiving bit line voltages. The voltage generation circuitry generates the required high and low voltages for each device.

[0033] In some embodiments, the peripheral circuitry may include a CMOS structure or CMOS circuitry, including digital or analog circuitry composed of transistors, for controlling or powering the memory array. Increasing the device integration density of the peripheral circuitry is beneficial to improving the overall integration density of the memory device, and improving the device stability of the peripheral circuitry is beneficial to improving the operational stability of the memory device. The peripheral circuitry and the memory array may be disposed in the same semiconductor structure, or the peripheral circuitry and the memory array may be located in different semiconductor structures. The memory array and the peripheral circuitry are coupled through bonding contacts and an interconnect layer (or redistribution layer) under the co-bonding contacts for electrical signal interconnection. The bonding may include, but is not limited to, hybrid bonding.

[0034] According to some aspects of the embodiments of this application, Figure 2 A storage device 10 is provided. The first direction mentioned in the embodiments of this application may include the z direction in the figure. The z direction may be a vertical direction or a thickness direction. The second direction may be the x direction in the figure. The third direction may be the y direction in the figure. The x and y directions intersect or are perpendicular to the z direction. The second direction and the third direction may be interchanged. Other figures will not be described in detail.

[0035] Figure 2The storage device 10 may include: a storage array 100 and peripheral circuitry 200 stacked in a first direction (z direction); a plurality of bonding contacts 141 located between the storage array 100 and the peripheral circuitry 200, wherein the peripheral circuitry 200 and the storage array 100 are coupled at least through the bonding contacts 141; the storage array 100 includes: a bit line 110 extending along the z direction, wherein the bit line 110 is coupled to a corresponding bonding contact 141; a plurality of word lines 120 extending along a second direction (x direction) and stacked along the z direction, wherein the plurality of word lines 120 form a stepped structure on one side of the x direction, wherein the x direction intersects or is perpendicular to the z direction; and a plurality of first connection structures 131 extending along the z direction, wherein the word lines 120 are coupled to the corresponding bonding contacts 141 through the first connection structures 131.

[0036] In some embodiments, Figure 2 For example, a bit line 110 may correspond to multiple word lines 120 stacked along the z direction, and the multiple word lines 120 corresponding to a bit line 110 form a stepped structure on one side in the x direction; multiple first connection structures 131 may be arranged sequentially along the stepped surface of the stepped structure, at least a portion of the first connection structure 131 is located on one side of the stepped structure along the z direction, the first connection structure 131 is coupled to the word line 120, and the first connection structure 131 is coupled to the corresponding bonding contact 141.

[0037] Figure 2 The memory device 10 can be bonded together in the z-direction by different semiconductor structures. Bonding may include hybrid bonding. Devices in different semiconductor structures are telecommunication interconnected through bonding contacts 141. The memory device 10 may include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a memory array 100, and the second semiconductor structure may include peripheral circuitry 200. The first and second semiconductor structures can be wafer structures, or they can be die structures cut from a wafer along dicing lines. This application... Figure 2 The bonding method is not specifically limited to bonding between chips, bonding between chips and wafers, or bonding between wafers. The storage device 10 can be a stacked structure of chips cut off after wafer bonding.

[0038] For example, before bonding the first semiconductor structure to the second semiconductor structure, a first sub-bonding layer with multiple first sub-bonding contacts can be formed on the surface of the first semiconductor structure to be bonded. The first sub-bonding contacts can be... Figure 2The first connection structure 131 is coupled to the word line 120, and the first sub-bonding contact is coupled to the bit line 110. A second sub-bonding layer with multiple second sub-bonding contacts can be formed on the surface of the second semiconductor structure to be bonded. After the dielectric materials of the first and second sub-bonding layers are bonded, a bonding layer without physical boundaries can be formed. The first and second sub-bonding contacts can be bonded to form a bonding contact 141 without physical boundaries. An interconnect layer can also be provided between the first connection structure 131, the bit line 110, and the bonding layer to redistribute and optimize the power path of the word line 120 and the bit line 110, and then contact and couple with the bonding contact 141 through the topmost interconnect layer. A conductive plug or other connection structure can be provided to couple with the bit line 110 to lead the electrical signal of the bit line 110 to the bonding layer, or the length of the bit line 110 can be increased so that the first sub-bonding contact can be directly connected to the bit line 110. The second sub-bonding contact of the peripheral circuit 200 can land on the topmost interconnect layer of the peripheral circuit 200 to lead out the electrical signals of each part of the circuit or device of the peripheral circuit 200 to the bonding interface to interact with the memory array 100.

[0039] Figure 2 As shown, multiple word lines 120 are stacked at intervals along the z-direction, and adjacent word lines 120 are separated by a dielectric material. The lengths of word lines 120 in different layers along the x-direction can be different. Multiple word lines 120 are staggered at one end in the x-direction to form a stepped structure. The end of each layer of word lines 120 can be exposed along the x-direction without being blocked by the upper layer of word lines 120, thereby forming stepped surfaces of different heights. The stepped surfaces are located at the ends of the word lines 120 and extend along the x-direction for coupling the first connection structure 131. Multiple first connection structures 131 are distributed in the area where the step structure of the word line 120 is located. The first connection structure 131 can land on a step surface and be coupled to the word line 120. The first connection structure 131 does not penetrate the current step surface; or the first connection structure 131 passes through the current step surface and is coupled to the current step surface. The first connection structure 131 also passes through the remaining word lines 120 below the current step surface and is isolated from the remaining or non-target word lines 120 by a dielectric material. The dielectric material can surround a portion of the sidewall of the first connection structure 131 extending in the z direction. Figure 2 The memory array 100 also includes other device structures not shown and interconnect structures coupled to and powered by the device structures, including memory cells, interconnect layers that power the memory cells, and conductive plugs, etc. The memory cells may include, but are not limited to, transistors and capacitor structures coupled to the transistors.

[0040] Figure 2The positions of word lines 120 and bit lines 110 shown are for illustrative purposes only. Bit lines 110 and word lines 120 may intersect but not touch. Multiple bit lines 110 may be arranged along the x-direction, and each bit line 110 may correspond to multiple stacked word lines 120. There is no limitation on the number of bit lines 110 and word lines 120. More word lines 120 and more bit lines 110 arranged along the y-direction may also be present. Alternatively, bit lines 110 may be located at one end of a word line 120 along the y-direction, with one bit line 110 corresponding to multiple stacked word lines 120, and multiple bit lines 110 arranged in the y-direction (not shown). Figure 2 The memory array 100 bonded by the peripheral circuitry 200 is for illustrative purposes only and may be implemented elsewhere. Figure 2 The memory array 100 is bonded to both the top and bottom sides of the peripheral circuit 200, or multiple memory arrays 100 are bonded to one side of the peripheral circuit 200.

[0041] In some embodiments, the memory array 100 further includes: a semiconductor body having a first active terminal and a second active terminal; a portion of a word line 120 covering at least a portion of the sidewalls of the semiconductor body; the first active terminal being coupled to a bit line 110; and a capacitor structure being coupled to the second active terminal.

[0042] The memory array 100 includes transistors, each comprising a semiconductor body. The semiconductor body can be a columnar structure or a film structure. The semiconductor body has a first active terminal and a second active terminal, and a channel located between the first and second active terminals. The first and second active terminals serve as the source and drain, respectively, and their positions are interchangeable. The first and second active terminals can be doped, and the channel can be inversely doped with respect to the first active terminal. The transistor also includes a gate, which covers the channel region, or partially or fully surrounds the sidewalls of the semiconductor body, and includes a gate dielectric layer located between the gate and the semiconductor body. Multiple gates are coupled to word lines 120, or the gates constitute a portion of word lines 120. The first active terminal can be coupled to a bit line 110, and the second active terminal can be coupled to a capacitor structure. The capacitor structure may include a first electrode, a second electrode, and a dielectric layer located between them. The first and second electrodes have overlapping regions to form a capacitor. The second active terminal of the semiconductor body is coupled to the first electrode. The second electrode can serve as a common electrode for multiple capacitors, and it overlaps with multiple first electrodes. The second electrode can be connected to a common voltage, such as ground or other operating voltages like Vcc / 2. The second electrode can be bonded to the peripheral circuit 200 via an interconnect layer and connection structures extending along the z-direction, such as conductive plugs, conductive pillars, or conductive channels, and connected to the interconnect layer in the peripheral circuit 200 that provides ground or other common voltages. The first and second electrodes can be film structures, columnar structures, cup-shaped structures, or other regular or irregular structures. This application does not impose specific limitations on the specific physical structure and positional relationship of the transistor and capacitor structures.

[0043] In some embodiments, Figure 2 The word line 120 has more bit lines 110 arranged along the x-direction, and these bit lines 110 overlap and intersect with the word lines 120 in the y-direction but do not touch. Each bit line 110 corresponds to multiple word lines 120 stacked along the z-direction, and one word line 120 corresponds to multiple bit lines 110 arranged along the x-direction. Figure 2The word line 120 can extend to the right along the x-direction. The example bit line 110 in the figure has more bit lines 110 on its left and right sides (not shown); there are also more stacked word lines 120 arranged along the y-direction, and the arrangement of bit lines 110 is not shown. The bit line 110 can be located on one side of the word line in the y-direction, and the semiconductor body can be located on one side of the word line 120 in the z-direction. The semiconductor body can extend along the y-direction and has two ends opposite each other along the y-direction that are homo-doped as a first active terminal and a second active terminal. A channel is formed between the first active terminal and the second active terminal, and the channel can be inversely doped with the first active terminal. The first active terminals of multiple semiconductor bodies are coupled to the bit line 110, either through direct contact or through contact portions. The contact portions can include, but are not limited to, metal silicides such as titanium silicide and tungsten silicide to increase adhesion and reduce contact resistance. The word line 120 may include a gate layer disposed on one or both sides of the semiconductor body in the z direction, or the overlapping area of ​​the word line 120 and the semiconductor body may surround the sidewall of the semiconductor body, and the word line 120 or the gate layer may be spaced from the semiconductor body through a gate dielectric layer.

[0044] The capacitor structure can be disposed along the y-direction on one side of the semiconductor body away from the bit line 110. The capacitor structure can extend along the y-direction, and one capacitor structure can correspond to one semiconductor body. The capacitor structure has an independent first electrode and a second electrode; or the second electrode serves as a common electrode for multiple capacitors, the first electrode extends along the y-direction and corresponds to a semiconductor body, the second electrode extends along the z-direction and overlaps with multiple first electrodes, or the second electrode serves as a common electrode surrounding multiple first electrodes or filling the gap region between the first electrodes; a dielectric layer is located between the first electrode and the second electrode as electrical isolation. For example, the gate dielectric layer and dielectric layer may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may also include high dielectric materials such as aluminum oxide and hafnium oxide to reduce leakage current and reduce film thickness.

[0045] For example, the semiconductor substrate may include, but is not limited to: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. Materials such as indium gallium zinc oxide (IGZO) may also be included, where IGZO materials may be composed of oxides of elements such as indium, gallium, and zinc, exhibiting superior semiconductor properties. The addition of indium and gallium can improve the electron mobility of the semiconductor material, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps improve the stability of the semiconductor material.

[0046] In some embodiments, a bit line 110 may be located at one end of a word line 120 along the x-direction, and a plurality of stacked word lines 120 may be arranged in the y-direction. The semiconductor body and capacitor structure are both located between two word lines 120 in the z-direction and are stacked along the z-direction. The capacitor structure extends along the x-direction between adjacent word lines 120. The electrodes and dielectric layers of the capacitor structure may both be film structures; for example, a first electrode and a second electrode may be stacked in the z-direction and have overlapping regions. In other embodiments, the bit line 110 extending along the z-direction may pass through the word line 120, and the bit line 110 may be surrounded by the word line 120.

[0047] For example, word line 120, bit line 110, the first electrode, and the second electrode may include, but are not limited to, conductive materials such as tungsten, aluminum, copper, cobalt, gold, silver, platinum, titanium, nickel, titanium nitride, tungsten nitride, titanium nitride, polycrystalline silicon (or doped), titanium nitride, and tantalum nitride. The first electrode and the second electrode may be made of the same or different materials.

[0048] In some embodiments, refer to Figure 2 As shown, the first connection structure 131 is located between the stepped surface of the stepped structure and the peripheral circuit 200, and the first connection structure 131 lands on the corresponding word line 120. In some embodiments, refer to Figure 2 As shown, the stepped surface of the stepped structure faces the peripheral circuit 200 along the z-direction. A first connection structure 131 is located between the stepped surface and the peripheral circuit 200. One end of the first connection structure 131 is located on the stepped surface of the word line 120, or extends into the word line 120 but does not pass through it. The other end of the first connection structure 131 is coupled to the peripheral circuit 200 via a bonding contact 141. In other embodiments, as described below... Figure 5 , Figure 6 The first connection structure 131 of the memory array 100 lands on the step surface of the corresponding word line 120 without penetrating the word line 120, and is bonded with the step surface facing the peripheral circuit 200, which will not be described in detail below.

[0049] In some embodiments, refer to Figure 3 As shown, the storage array 100 further includes: a first interconnect layer 151 located on the side of the stepped surface of the stepped structure facing away from the peripheral circuit 200; the first interconnect layer 151 includes a plurality of first interconnect lines, the first interconnect lines being coupled to corresponding first connection structures 131; a second interconnect layer 152 located between the stepped structure and the peripheral circuit 200; the first interconnect layer 151 includes a plurality of second interconnect lines, the second interconnect lines being coupled to corresponding bonding contacts 141; a plurality of second connection structures 132 located between the first interconnect layer 151 and the second interconnect layer 152 and extending along a first direction; the second connection structures 132 being coupled to corresponding first interconnect lines and corresponding second interconnect lines.

[0050] Figure 3 In this configuration, the first interconnect structure 131 of the memory array 100 lands on the stepped surface of the corresponding word line 120 without penetrating the word line 120. The first interconnect layer 151 is located on the front side of the stepped surface and covers the stepped surface. A first interconnect line of the first interconnect layer 151 is coupled to the first interconnect structure 131 on a word line 120. The first interconnect layer 151 leads the electrical signals of multiple word lines 120 in parallel to the front side of the stepped surface. The first interconnect line passes through the second interconnect structure 132, which passes through the stacked area of ​​the word lines 120, and is coupled to a second interconnect line below the stepped structure. The second interconnect line is redistributed to align and uniformly distribute the bonding contacts of the memory array 100 portion with the bonding contacts of the peripheral circuit 200 portion. The height of the second interconnect structure 132 along the z-direction is greater than the thickness of the stacked word lines 120. The second interconnect structure 132 may be located at one end or edge of the word line 120 along the x-direction.

[0051] Both the first interconnect layer 151 and the second interconnect layer 152 may include multiple wiring layers. Adjacent wiring layers are coupled through conductive plugs. There are no specific restrictions on the distribution and shape of the interconnects in each wiring layer. The first interconnect layer 151, multiple second interconnect structures, and the second interconnect layer 152 enable front-side power delivery for each word line 120 and redistribute electrical signals to the back side of the word line 120 to achieve alignment of the bonding contacts of the peripheral circuit 200 or to achieve uniform distribution of the bonding contacts, thereby reducing crosstalk between the bonding contacts.

[0052] In some embodiments, refer to Figure 4 As shown, the first connection structure 131 passes through multiple word lines 120 along the z-direction. The first connection structure 131 is coupled to a corresponding word line 120. The first connection structure 131 passes through other word lines 120 and is isolated by a dielectric material. Figure 4 The first connection structure 131 lands on the stepped surface of the corresponding word line 120 from top to bottom along the z-direction and continues to extend downwards, penetrating all remaining word lines 120, coupling with the corresponding target word line 120, and is isolated from other word lines 120 by a dielectric material. For example Figure 4 A first connection structure 131 is aligned with a certain step surface and lands on the step surface. It continues to extend downwards, penetrating the first word line 120 that lands and all word lines 120 below the first word line 120. The first connection structure 131 is coupled to the first word line 120 it passes through and is electrically isolated from the remaining word lines 120.

[0053] In some embodiments, refer to Figure 4As shown, the storage array 100 further includes: a conductive pad 121 located at one end of the word line 120 along the x direction and located on the step surface of the stepped structure; the conductive pad 121 is coupled to the word line 120, and the first connection structure 131 passes through the conductive pad 121 and is coupled to the conductive pad 121.

[0054] At least a portion of the conductive pad 121 is located on, protrudes from, or is embedded within and surrounded by the word line 120. The conductive pad 121 may be annular. A first connecting structure 131 passes through and is coupled to the conductive pad 121. The portion of the first connecting structure 131 that does not overlap with the conductive pad 121 is surrounded by a dielectric material, isolating other unnecessary word lines 120. The cross-sectional shape of the conductive pad 121 in the xoy plane may include, but is not limited to, rectangles, circles, ellipses, or other regular or irregular polygons and arcs. The conductive pad 121 may be located above the word line 120 and connected to the first connecting structure 131. The first connecting structure 131 passes through the conductive pad 121, and its sidewalls are coupled to the conductive pad 121. Dielectric material is surrounding the sidewalls of the first connecting structure 131 in all word lines 120.

[0055] For example, an isolation pillar can be formed that runs through all word lines 120. The top surface of the isolation pillar is flush with the top surface of the step surface. A conductive pad 121 is formed on the step surface, covering the top surface of the isolation pillar. The bottom of the conductive pad 121 is in contact with and coupled to the step surface of the word line 120. The central region of the conductive pad 121 is a sacrificial material, and conductive material or annular sidewalls surround the sacrificial material. An opening is formed that passes through the sacrificial material in the conductive pad 121 and through the isolation pillar along the z-direction. An etchant with a high selectivity for etching the sacrificial material and a low selectivity for etching the isolation pillar is used to etch and clean the inside of the opening, so that the inner wall of the conductive pad 121 is exposed from the opening. The opening is then filled with conductive material to form the... Figure 4 The first connection structure 131 shown has its sidewalls contacted and coupled to the inner wall of the conductive pad 121. The sidewalls of the first connection structure 131 in all word lines 120 are surrounded and isolated by a dielectric material. The first connection structure 131 may be made of the same or different material as the conductive pad 121, and may also be formed by other methods. Figure 4 The first connection structure 131 and the conductive pad 121 are not other examples in this application.

[0056] The first connecting structure 131 penetrates the word line 120, which can reduce the possibility of the word line 120 being over-etched or even etched through due to different etching amounts when landing on word lines 120 of different layers. For example Figure 4The first connection structure 131 on the word line 120 of the middle and top layers has a small amount of etched openings, making it easy to be etched through and cause short circuits with the lower word line 120. The first connection structure 131 penetrates the word line 120, which can expand the manufacturing process window of the first connection structure 131 and allow the memory array 100 to be bonded to the peripheral circuit 200 from both the front and back sides. For example, after bonding, the stepped surface of the stepped structure can be either away from or facing the peripheral circuit 200 along the z-direction.

[0057] In some embodiments, refer to Figure 4 As shown, the stepped surface of the stepped structure is 200° away from the peripheral circuit along the z-direction. (See attached text.) Figure 7 , Figure 8 , Figure 9 All provide a first connection structure 131 running through all word lines 120, and are stacked in a manner where the stepped surfaces of the stepped structure are bonded away from the peripheral circuitry 200 in the z-direction. In some other embodiments, Figure 4 The storage array 100 can also adopt a stepped structure, with the stepped surface facing the peripheral circuit 200 along the z-direction and bonded to the peripheral circuit 200.

[0058] In some embodiments, refer to Figures 2 to 4 As shown, the storage array 100 further includes: a plurality of sub-storage arrays, one end of which has a stepped structure along the x-direction; the stepped structures of two adjacent sub-storage arrays arranged in the x-direction are arranged back-to-back along the x-direction.

[0059] Some areas in the storage array 100 can be treated as a separately addressed storage unit, such as the first sub-storage array 101 or the second sub-storage array 102. The sub-storage array can be configured as a bank for independent addressing. There are no specific restrictions on the number of word lines 120, bit lines 110, and storage cells in the sub-storage array.

[0060] In some embodiments, refer to Figures 5 to 8 As shown, the storage array 100 includes: a first storage array 100a and a second storage array 100b disposed opposite each other on both sides of the peripheral circuit 200 along the z-direction; the bonding contact 141 includes: a first bonding contact 141a located between the first storage array 100a and the peripheral circuit 200, wherein the peripheral circuit 200 is coupled to the first storage array 100a at least through the first bonding contact 141a; and a second bonding contact 141b located between the second storage array 100b and the peripheral circuit 200, wherein the peripheral circuit 200 is coupled to the second storage array 100b at least through the second bonding contact 141b. Figure 5 and Figure 6 In the middle, the first connection structure 131 lands on the corresponding word line 120 but does not penetrate it, and the stepped surface of the stepped structure is bonded to the peripheral circuit 200. Figure 7 and Figure 8 In the first connection structure 131, all word lines 120 are passed through, coupled to the word lines 120 of the corresponding layer, and isolated from other word lines 120 by a dielectric material. The stepped surface of the stepped structure is bonded to the peripheral circuit 200 with its back to the external circuit. In other embodiments... Figure 7 and Figure 8 Alternatively, directional bonding with the stepped surface facing the peripheral circuit 200 can be adopted. Two memory arrays can share a single peripheral circuit 200, which controls both arrays. It interconnects with an external host using a single control logic, power supply network, command decoding circuit, and I / O interface. Alternatively, the peripheral circuit 200 includes a first peripheral circuit and a second peripheral circuit. The first peripheral circuit controls the first memory array 100a, and the second peripheral circuit controls the second memory array 100b. Each peripheral circuit 200 has its own control logic, power supply network, command decoding circuit, and I / O interface, interacting with the external host independently and in parallel.

[0061] In some embodiments, the peripheral circuitry 200 includes a first sub-circuit 211 and a second sub-circuit 212 stacked along the z-direction. The first sub-circuit 211 is coupled to a first memory array 100a, and the second sub-circuit 212 is coupled to a second memory array 100b. The first sub-circuit 211 and the second sub-circuit 212 may be two independent complete peripheral portions, or may include portions of the peripheral circuitry 200, such as a word line driving circuit coupled to word line 120 and a sensing amplification circuit and column selection circuit coupled to bit line 110.

[0062] In some embodiments, Figure 5 and Figure 7 As shown, the first sub-circuit 211 and the second sub-circuit 212 are located in a semiconductor structure and are stacked in the z-direction.

[0063] In some embodiments, Figure 6 and Figure 8 As shown, the first sub-circuit 211 and the second sub-circuit 212 are located in different semiconductor structures. The peripheral circuit 200 also includes a third bonding contact 201 located between the first sub-circuit 211 and the second sub-circuit 212. The first sub-circuit 211 and the second sub-circuit 212 are coupled at least through the third bonding contact 201.

[0064] In some embodiments, the first sub-circuit 211 includes: a first word line driving circuit coupled to a first connection structure 131 of the first memory array 100a; and a first sensing amplification circuit coupled to a bit line 110 of the first memory array 100a. The second sub-circuit 212 includes: a second word line driving circuit coupled to the first connection structure 131 of the second memory array 100b; and a second sensing amplification circuit coupled to a bit line 110 of the second memory array 100b. The first sub-circuit 211 may further include: a first column decoding circuit coupled to a bit line 110 of the first memory array 100a; the second sub-circuit 212 further includes: a second column decoding circuit coupled to a bit line 110 of the second memory array 100b.

[0065] The first memory array 100a and the second memory array 100b share a complete peripheral circuit 200. The peripheral circuit 200 includes parallel first word line driver circuits and second word line driver circuits, respectively coupled to the word lines 120 of the first memory array 100a and the second memory array 100b via bonding. It also includes parallel first and second sensing amplifier circuits, respectively coupled to the bit lines 110 of the first memory array 100a and the second memory array 100b via bonding. Furthermore, it includes parallel first and second column decoding circuits, respectively coupled to the bit lines 110 of the first memory array 100a and the second memory array 100b via bonding. Each word line 120 and bit line 110 is coupled to its corresponding node via interconnection distribution through the interconnection layer of the peripheral circuit 200 after passing through various bonding contacts. This improves the area utilization of the peripheral circuit 200 and increases the integration density of the memory cells.

[0066] The peripheral circuit 200 may also include, but is not limited to, control logic, command decoding circuit, registers, address buffer circuit, data input / output circuit, voltage generation circuit, power supply circuit, and local or global power lines, data lines, and control communication lines. The first sub-circuit 211 and the second sub-circuit 212 may share the control logic, command decoding circuit, registers, address buffer circuit, data input / output circuit, voltage generation circuit, and power supply circuit; this part of the circuit may be arranged along the z-direction between the first sub-circuit 211 and the second sub-circuit 212. When the two parts of the first sub-circuit 211 and the second sub-circuit 212 are located in different semiconductor structures, the shared peripheral circuit 200 part may be arranged on one of the semiconductor structures and led out from the other side through bonding contacts 141. The bonding contacts of the shared peripheral circuit 200 part and the word line driving circuit (and the bonding contacts of the sensing amplification circuit) are located on opposite sides of the semiconductor structure in the z-direction.

[0067] For example, the control logic can be coupled to the individual component circuits of each of the aforementioned peripheral circuits 200 and configured to control the operation of each part of the peripheral circuit 200.

[0068] The sensing amplifier circuit can be implemented using a cross-coupled amplifier connected between the bit lines and complementary bit lines included in the memory array. The data input / output circuit can write input data to the memory array based on address signals (ADDs) and read output data from the memory array based on address information (ADDs), and output the data to the outside of the memory device 10. An address buffer circuit can temporarily store address signals (ADDs). A word line driver circuit can decode the row address in the address signals (ADDs) output from the address buffer circuit to specify the word line connected to the memory cell for writing or reading data. For example, during a write or read operation, the word line driver circuit can decode the row address output from the address buffer circuit to enable the word line corresponding to the row address. Similarly, during a refresh operation, the word line driver circuit can decode the row address generated by the address counter to enable the word line corresponding to the row address. A column decoding circuit can decode the column address in the address signals (ADDs) output from the address buffer circuit to specify the bit line connected to the memory cell for writing or reading data. The command decoding circuit can receive command signals (CMD) from the host or memory controller and can internally generate decoded command signals by decoding these signals.

[0069] In some embodiments, refer to Figure 9 As shown, the storage device 10 includes: a plurality of memory arrays sequentially bonded on the peripheral circuit 200; the plurality of memory arrays are all coupled to the peripheral circuit 200, and the first connection structure 131 and bit line 110 of each memory array are coupled to the peripheral circuit 200; wherein, the first connection structure 131 coupled to the word line 120 of each memory array are mutually coupled through bonding contacts. Figure 9 In the process, the first connecting structures 131 adjacent in the z direction can be aligned or substantially aligned along the z direction, or the first connecting structures 131 of two adjacent layers can be offset along the x or y direction. Figure 9 Two memory arrays are stacked on the peripheral circuit 200, such as the first memory array 100a and the second memory array 100b as an example. There may also be stacks of more memory arrays.

[0070] In some embodiments, the memory array further includes: a plurality of third connection structures 133, the third connection structures 133 extending at least along the z-direction through the stacked region of the word line 120; the bit line 110 of the current layer memory array is bonded to the third connection structure 133 of the lower layer memory array, and coupled to the peripheral circuitry 200 through at least one third connection structure 133.

[0071] Figure 9The bit lines 110 of adjacent memory arrays may not be coupled or aligned. In the figure, only part of the bit lines 110a and part of the third connection structure 133 of the bottom first memory array 100a are shown in the cross section. The third connection structure 133 of the upper second memory array 100b is not shown. Or, when the second memory array 100b is the topmost stack, the second memory array 100b may not have a third connection structure 133 that penetrates the memory array 100. The third connection structure 133 in the first memory array 100a extends through the memory array region along the z-direction, or passes through the stacking region of the word line 120 along the z-direction. The third connection structure 133 is aligned with the bit line 110b in the upper second memory array 100b and coupled through the bonding contact 141d. The third connection structure 133 leads the electrical signal of the upper bit line 110b to the bonding contact 141c and couples it with the peripheral circuit 200. The bit line 110a of the lower first memory array 100a is coupled to the peripheral circuit 200 through the bonding contact 141c. In the first memory array 100a, the third connection structure 133 may be located on one side of the bit line 110a along the y-direction or the x-direction.

[0072] In some embodiments, Figure 9 The third connection structure 133 of the middle and lower layers may not be aligned with the upper bit line 110b. The upper and lower bit lines 110a and 110b may be aligned but not coupled. An interconnection layer may be set to connect with the third connection structure 133 to redistribute the power path, and then coupled with the upper bit line 110 through the bonding contact 141a.

[0073] In some embodiments, with Figure 9 For example, the peripheral circuit 200 has n memory arrays 100 stacked on top of each other, where n is a positive integer greater than or equal to 2. Each memory array has a third connection structure 133 extending along the z direction. The top layer memory array may not have a third connection structure 133. The bit lines 110 of the nth layer memory array are connected to the peripheral circuit 200 layer by layer through the (n-1)th layer third connection structures 133 and bonding contacts. The bit lines 110 of the first layer memory array do not need to pass through the third connection structure 133, but are coupled to the peripheral circuit 200 through the bottom layer bonding contacts 141c. Figure 9 In the storage device 10 shown, the word lines 120 of the same layer of each storage array can be coupled to the peripheral circuit 200 in series, while each bit line is individually connected to the peripheral circuit 200 in parallel. When the peripheral circuit 200 addresses a storage cell, it selects the target word line 120 in each storage array, or selects the word line 120 of the same layer in each storage array, and then selects the target bit line of the target storage array through the third connection structure 133. Other non-target bit lines will not be selected. In this way, the target storage cell in the target storage array can be selected for read, write, or erase operations, thereby improving the operation speed.

[0074] According to some aspects of embodiments of this application, an electronic system is provided, including... Figures 2 to 9 Any of the example storage devices 10.

[0075] This application provides an electronic system or device including a host computer. The electronic system may be a mobile phone, graphics processing device, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0076] In some embodiments, the electronic system may include a host computer and a memory device coupled to the host computer, the memory device including... Figures 2 to 9 Any of the example storage devices 10 may include DRAM memory cells. The electronic system may consist only of a host computer and the memory devices coupled thereto. A controller controlling the memory devices may be located within the host computer, such as a memory controller integrated within a central processing unit (CPU), or integrated into a processor chip such as a graphics processing unit (GPU), neural processor, or other SOC chip; or integrated into the southbridge or northbridge chip of the system 300 motherboard. The memory device 304 may include, but is not limited to: DDR4 memory, DDR5 memory, Double Data Rate Synchronous Dynamic Random Access Memory, and Low Power Double Data Rate Synchronous Dynamic Random Access Memory using LPDDR5 memory specifications.

[0077] In some embodiments, the memory device may be adapted to a high-speed memory package. The memory device may include a logic chip and a plurality of memory devices 10 stacked on the logic chip. The logic chip and the memory devices 10 are electrically interconnected through through-silicon vias (TSVs) penetrating the memory devices 10. The logic chip is coupled to a processor chip such as a GPU, CPU, or SOC chip, and a memory controller may be integrated within the processor chip.

[0078] In some embodiments, the electronic system may include a host computer and a memory controller coupled to both the host computer and the memory devices, which may constitute a memory system. The memory controller controls the memory devices. The memory controller may be integrated into the host computer or a processor such as a GPU, or a logic chip of high-speed memory may serve as the memory controller.

[0079] In some embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the components shown or discussed may be directly or indirectly coupled to each other.

[0080] In some embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the components shown or discussed may be directly or indirectly coupled to each other.

[0081] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A storage device, characterized in that, include: A storage array and peripheral circuitry are stacked in the first direction; Multiple bonding contacts are located between the memory array and the peripheral circuitry, and the peripheral circuitry and the memory array are coupled at least through the bonding contacts. The storage array includes: A bit line extending along a first direction, the bit line being coupled to a corresponding bonding contact; A plurality of character lines extending along a second direction and stacked along the first direction, wherein the plurality of character lines form a stepped structure on one side of the second direction, and the second direction intersects the first direction; A plurality of first connection structures extending along a first direction are used to couple the word lines to the corresponding bonding contacts.

2. The storage device according to claim 1, characterized in that, The stepped surface of the stepped structure faces the peripheral circuit along the first direction.

3. The storage device according to claim 2, characterized in that, The first connection structure is located between the step surface of the stepped structure and the peripheral circuit, and the first connection structure lands on the corresponding word line.

4. The storage device according to claim 1, characterized in that, The stepped surface of the stepped structure is away from the peripheral circuit along the first direction.

5. The storage device according to claim 4, characterized in that, The storage array also includes: The first interconnect layer is located on the side of the stepped surface of the stepped structure that faces away from the peripheral circuit; the first interconnect layer includes a plurality of first interconnect lines, and the first interconnect lines are coupled to the corresponding first connection structures; The second interconnect layer is located between the stepped structure and the peripheral circuit; the first interconnect layer includes a plurality of second interconnect lines, and the second interconnect lines are coupled to the corresponding bonding contacts. Multiple second connection structures are located between the first interconnect layer and the second interconnect layer and extend along the first direction; the second connection structures are coupled to the corresponding first interconnect line and the corresponding second interconnect line.

6. The storage device according to claim 4, characterized in that, The first connection structure extends through a plurality of word lines along the first direction, the first connection structure is coupled to a corresponding word line, and the first connection structure passes through other word lines and is isolated by a dielectric material.

7. The storage device according to claim 6, characterized in that, The storage array also includes: A conductive pad is located at one end of the word line along the second direction and on the step surface of the stepped structure; the conductive pad is coupled to the word line, and the first connecting structure passes through the conductive pad and is coupled to the conductive pad.

8. The storage device according to any one of claims 1 to 7, characterized in that, The storage array also includes: Multiple sub-storage arrays, wherein one end of each sub-storage array along the second direction has the stepped structure; The stepped structures of the two sub-storage arrays arranged adjacent to each other in the second direction are arranged back-to-back along the second direction.

9. The storage device according to any one of claims 1 to 7, characterized in that, The storage array also includes: A semiconductor body has a first active terminal and a second active terminal; a portion of the word line covers at least a portion of the sidewalls of the semiconductor body; The first active terminal is coupled to the bit line; A capacitor structure is coupled to the second active terminal.

10. The storage device according to any one of claims 1 to 7, characterized in that, The storage array includes: a first storage array and a second storage array disposed opposite to each other on both sides of the peripheral circuit along the first direction; The bonding contacts include: A first bonding contact is located between the first memory array and the peripheral circuit, and the peripheral circuit is coupled to the first memory array at least through the first bonding contact; A second bonding contact is located between the second memory array and the peripheral circuit, and the peripheral circuit is coupled to the second memory array at least through the second bonding contact.

11. The storage device according to claim 10, characterized in that, The peripheral circuit includes: A first sub-circuit and a second sub-circuit are stacked along the first direction, the first sub-circuit being coupled to the first memory array and the second sub-circuit being coupled to the second memory array.

12. The storage device according to claim 11, characterized in that, The first sub-circuit and the second sub-circuit are located in different semiconductor structures, and the peripheral circuit further includes: A third bonding contact is located between the first sub-circuit and the second sub-circuit, and the first sub-circuit and the second sub-circuit are coupled at least through the third bonding contact.

13. The storage device according to claim 11, characterized in that, The first sub-circuit includes: The first word line driving circuit is coupled to the first connection structure of the first memory array; The first sensing amplifier circuit is coupled to the bit line of the first storage array; The second sub-circuit includes: The second word line driving circuit is coupled to the first connection structure of the second memory array; The second sensing amplifier circuit is coupled to the bit lines of the second storage array.

14. The storage device according to claim 6 or 7, characterized in that, The storage device includes: A plurality of memory arrays are sequentially bonded to the peripheral circuitry; each of the memory arrays is coupled to the peripheral circuitry. The first connection structure and bit lines of each of the memory arrays are coupled to the peripheral circuit; wherein the first connection structures coupled to the word lines of the same layer of each memory array are coupled to each other through bonding contacts.

15. The storage device according to claim 14, characterized in that, The storage array also includes: Multiple third connection structures, wherein the third connection structures penetrate at least the stacked area of ​​the word lines along the first direction; The bit lines of the current layer's memory array are bonded to the third connection structure of the lower layer's memory array and coupled to the peripheral circuitry through at least one third connection structure.

16. An electronic system, characterized in that, include: The storage device as described in any one of claims 1 to 15.

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