Dynamic random access memory with self-aligned shared bit lines and forming method

Abstract

The application provides a dynamic random access memory with self-aligned shared bit lines and a forming method, comprising: providing a substrate and a stack structure; forming a first trench and a plurality of spaced first silicon pillars; removing a second germanium-silicon epitaxial layer to form a cavity, a pair of bit lines are formed in the cavity, the bit lines have a gap therebetween, the gap has a cross-sectional shape of wide at the top and narrow at the bottom; filling a non-doped germanium-silicon layer in the gap; preparing an upper device part; turning over the substrate, removing the substrate and the first germanium-silicon epitaxial layer; forming a second trench and a plurality of spaced second silicon pillars, the second silicon pillars are aligned with the first silicon pillars; removing the non-doped germanium-silicon layer, reopening the gap between the bit lines, filling oxide into the gap to form an air gap between the pair of bit lines, and filling oxide into the second trench; and preparing a lower device part to form a dynamic random access memory with shared bit lines of the upper and lower devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a dynamic random access memory (DRAM) with self-aligned shared bit lines and a method for forming it, particularly to a 4F DRAM with self-aligned shared bit lines and bit line air structure. 2 Dual vertical channel transistors and semiconductor memory devices containing them. Background Technology

[0002] 4F 2 DRAM is a high-density dynamic random access memory, with a single memory cell having an area of ​​4F. 2 (i.e., 2F×2F), using a 1T1C structure (i.e., a structure of 1 transistor and 1 capacitor), a planar layout compressed dynamic random access memory is realized through vertical channel transistors.

[0003] As DRAM capacity continues to increase, 4F 2 Columnar transistors require more columnar structures to be added to a single bit line (BL), which not only increases the bit line capacitance (Cbl) and causes a decrease in sensing performance, but also has the disadvantage of extended process time because additional processes are required to control this problem.

[0004] To address the aforementioned issues, existing technologies typically employ a second wafer (WF) with a process identical to the original, followed by bonding to interconnect the two wafers. However, due to the additional process, wafer loss, and increased area from interconnect pads (PADs), devices cannot be integrated within the same area as the original chip, requiring additional chip area planning. Therefore, existing technologies not only increase costs due to the use of additional wafers but also introduce additional problems such as extended process time and increased process complexity. Furthermore, since the existing method is equivalent to using two bit lines, it still cannot avoid the problem of increased bit line capacitance (Cbl).

[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a dynamic random access memory with self-aligned shared bit lines and a method for forming it, which can reduce the use of wafers, reduce costs, and reduce bit line capacitance.

[0007] To achieve the above objectives, the present invention provides a method for forming a dynamic random access memory with self-aligned shared bit lines, comprising:

[0008] A substrate is provided, and a plurality of stacked structures spaced apart along the X direction and extending along the Y direction on the substrate, the stacked structures comprising a first germanium-silicon epitaxial layer, a first silicon epitaxial layer, a second germanium-silicon epitaxial layer and a second silicon epitaxial layer stacked sequentially on the substrate along the Z direction, the stacked structures being separated by oxides, wherein the X direction, the Y direction and the Z direction are perpendicular to each other;

[0009] The second silicon epitaxial layer is etched with the second germanium-silicon epitaxial layer as a stop layer to form a first trench in the second silicon epitaxial layer of each of the stacked structures. The etched second silicon epitaxial layer includes a plurality of spaced first silicon pillars.

[0010] The second germanium-silicon epitaxial layer is removed to form a cavity, and a pair of bit lines are formed in the cavity of each stacked structure. The pair of bit lines have a gap communicating with the first trench, and the gap has a cross-sectional shape that is wider at the top and narrower at the bottom.

[0011] An undoped germanium-silicon layer is filled into the gap, and then an oxide layer is filled into the first trench.

[0012] Fabrication of the upper-layer device;

[0013] The substrate is flipped over, and the substrate and the first germanium-silicon epitaxial layer are removed to expose the first silicon epitaxial layer;

[0014] The first silicon epitaxial layer is etched with an undoped germanium silicon layer as a stop layer to form a second trench in the first silicon epitaxial layer of each stacked structure. The etched first silicon epitaxial layer includes a plurality of spaced second silicon pillars, each second silicon pillar being aligned with a corresponding first silicon pillar.

[0015] Remove the undoped germanium silicon layer to reopen the gap between a pair of bit lines in each of the stacked structures, fill the gap with oxide to form an air gap between the pair of bit lines, and then fill the second trench with oxide.

[0016] The lower-level device portion is fabricated to form a dynamic random access memory with shared bit lines for both upper and lower-level devices.

[0017] Optionally, in the method for forming the dynamic random access memory, one side of the bit line is an air gap and the other side is an oxide layer.

[0018] Optionally, in the method for forming the dynamic random access memory, after flipping the substrate and removing the substrate and the first germanium-silicon epitaxial layer to expose the first silicon epitaxial layer, the oxide protruding from the surface of the first silicon epitaxial layer forms an oxide fence. The method further includes:

[0019] A mask layer is filled between the oxide fences, such that the morphology of the mask layer is substantially the same as that of the first germanium-silicon epitaxial layer that has been removed.

[0020] Remove oxide fencing;

[0021] Pull back the mask layer; and

[0022] The first silicon epitaxial layer is etched using the pulled-back mask layer as a mask to form the second trench.

[0023] Optionally, in the method for forming the dynamic random access memory, the thickness of the first germanium-silicon epitaxial layer is set such that each second silicon pillar obtained by etching the first silicon epitaxial layer using the pulled-back mask layer as a mask is aligned with the corresponding first silicon pillar.

[0024] Optionally, in the method for forming the dynamic random access memory, the thickness of the second germanium-silicon epitaxial layer is set according to the requirements of the bit line resistance.

[0025] Optionally, in the method for forming the dynamic random access memory, the gap that is reopened between a pair of bit lines in each of the stacked structures has a cross-sectional shape that is narrow at the top and wide at the bottom. The reopened gap is filled with oxide using a CVD filling process to form an air gap between the bit lines.

[0026] The present invention also provides a dynamic random access memory (DRAM) prepared using the above-described method for forming a DRAM.

[0027] The present invention also provides a dynamic random access memory, comprising:

[0028] An upper-layer device structure comprising multiple spaced-apart first silicon pillars;

[0029] A lower-level device structure comprising a plurality of spaced-apart second silicon pillars, wherein the plurality of second silicon pillars are aligned with a plurality of first silicon pillars; and

[0030] Multiple bit lines located between the first and second silicon pillars and shared by the upper and lower device structures.

[0031] Each bit line has an air gap on one side and an oxide on the other side. The sidewall of each bit line near the air gap is inclined relative to the vertical direction, while the sidewall near the oxide extends vertically.

[0032] Among them, the inclination direction of the opposite sidewalls of the two characters located on both sides of the same air gap is symmetrical about the vertical direction.

[0033] Optionally, in the dynamic random access memory, the upper-layer device structure includes a first pillar transistor and a first capacitor, and the lower-layer device structure includes a second pillar transistor and a second capacitor.

[0034] The first pillar-type transistor includes the first silicon pillar, and the second pillar-type transistor includes the second silicon pillar.

[0035] The first pillar transistor and the second pillar transistor share the bit line.

[0036] In the dynamic random access memory (DRAM) with self-aligned shared bit lines and its formation method provided by this invention, bit lines are formed between two silicon epitaxial layers on the same substrate, and upper and lower transistors are formed in the two silicon epitaxial layers respectively, sharing the bit lines. This avoids the use of additional wafers and reduces costs and processes. Simultaneously, this invention employs forming an air gap on the left or right side of a single bit line, and placing pillar transistors and capacitors above and below the bit line, respectively, forming a fully self-aligned shared bit line type 4F DRAM with an air gap structure. 2 DRAM array structure. This structure reduces bit line capacitance through air gaps, thereby reducing the required memory cell capacitance and improving sensing margin. Furthermore, the number of storage bits (cells) can be more than doubled by extending the length of the bit lines. Attached Figure Description

[0037] Figure 1 This is a flowchart of a method for forming a dynamic random access memory with self-aligned shared bit lines according to an embodiment of the present invention;

[0038] Figure 2 This is a cross-sectional view of an embodiment of the present invention after a silicon nitride layer has been formed on top of the stacked structure;

[0039] Figure 3 This is a top view of an embodiment of the present invention after a silicon nitride layer has been formed on top of the stacked structure;

[0040] Figure 4 This is a cross-sectional view of the third trench after it has been formed according to an embodiment of the present invention;

[0041] Figure 5 This is a top view of an embodiment of the present invention after the formation of the third trench;

[0042] Figure 6 This is a cross-sectional view of the third trench after filling it with oxide, according to an embodiment of the present invention.

[0043] Figure 7 This is a top view of the third trench after filling it with oxide, according to an embodiment of the present invention;

[0044] Figure 8 This is a cross-sectional view of the gaps between silicon nitride layers after filling with oxide according to an embodiment of the present invention;

[0045] Figure 9 This is a top view of an embodiment of the present invention after filling the gaps between silicon nitride layers with oxide;

[0046] Figure 10 This is a cross-sectional view of the second silicon epitaxial layer after etching to form the first trench according to an embodiment of the present invention;

[0047] Figure 11 This is a top view of the second silicon epitaxial layer after etching to form the first trench according to an embodiment of the present invention;

[0048] Figure 12 This is a cross-sectional view of the first sidewall formed in the first trench according to an embodiment of the present invention;

[0049] Figure 13 This is a top view of an embodiment of the present invention after the first sidewall has been formed in the first trench;

[0050] Figure 14 This is a cross-sectional view of an embodiment of the present invention after removing the second germanium-silicon epitaxial layer;

[0051] Figure 15 This is a top view of an embodiment of the present invention after the second germanium-silicon epitaxial layer has been removed;

[0052] Figure 16 This is a cross-sectional view of the bit line formed according to an embodiment of the present invention;

[0053] Figure 17 This is a top view of an embodiment of the present invention after the bit line has been formed;

[0054] Figure 18 This is a cross-sectional view of the first trench after filling it with oxide, according to an embodiment of the present invention;

[0055] Figure 19 This is a top view of the first trench after filling it with oxide, according to an embodiment of the present invention;

[0056] Figure 20 This is a cross-sectional view of the character line grid formed according to an embodiment of the present invention;

[0057] Figure 21 yes Figure 20 Cross-sectional view along AA1;

[0058] Figure 22 This is a cross-sectional view of the first character line after it is formed according to an embodiment of the present invention;

[0059] Figure 23 yes Figure 22 Cross-sectional view along AA1;

[0060] Figure 24 This is a cross-sectional view of the first capacitor after its formation according to an embodiment of the present invention;

[0061] Figure 25 This is a top view of the first capacitor after it has been formed according to an embodiment of the present invention;

[0062] Figure 26 This is a cross-sectional view of the substrate after flipping and removing the first germanium-silicon epitaxial layer according to an embodiment of the present invention;

[0063] Figure 27 This is a cross-sectional view of the silicon nitride mask formed according to an embodiment of the present invention;

[0064] Figure 28 This is a top view of the silicon nitride mask formed according to an embodiment of the present invention;

[0065] Figure 29 This is a cross-sectional view of the gaps between the mask silicon nitride after filling with oxide according to an embodiment of the present invention;

[0066] Figure 30 This is a top view of an embodiment of the present invention after filling the gaps between the mask silicon nitride with oxide;

[0067] Figure 31 This is a cross-sectional view of the first silicon epitaxial layer after etching to form the second trench according to an embodiment of the present invention;

[0068] Figure 32 This is a top view of the first silicon epitaxial layer after etching to form the second trench according to an embodiment of the present invention;

[0069] Figure 33 This is a cross-sectional view of an embodiment of the present invention after the removal of the undoped germanium-silicon layer;

[0070] Figure 34 This is a top view of an embodiment of the present invention after the undoped germanium-silicon layer has been removed;

[0071] Figure 35 This is a cross-sectional view of the second character line after it is formed according to an embodiment of the present invention;

[0072] Figure 36 yes Figure 35 Cross-sectional view along AA1;

[0073] Figure 37 This is a cross-sectional view of the dynamic random access memory after the second capacitor is formed according to an embodiment of the present invention;

[0074] Figure 38 This is a top view of the dynamic random access memory after the second capacitor is formed according to an embodiment of the present invention;

[0075] In the diagram: 101-Substrate, 102-First germanium-silicon epitaxial layer, 103-First silicon epitaxial layer, 104-Second germanium-silicon epitaxial layer, 105-Second silicon epitaxial layer, 106-Silicon dioxide layer, 107-Silicon nitride layer, 108-Third trench, 109-Oxide, 110-Oxide, 111-First trench, 112-First sidewall, 113-Cavity, 114-Bit line, 115-Undoped germanium-silicon layer, 116-Oxide layer, 117-Word line grid, 120-First barrier metal layer, 121 - First pad, 122 - Oxide, 123 - First capacitor barrier layer, 124 - First capacitor mold layer oxide layer, 125 - First capacitor layer, 126 - Pad oxide layer, 127 - Mask silicon nitride, 128 - Oxide, 129 - Second trench, 130 - Second sidewall, 131 - Oxide, 132 - Air gap, 136 - Second barrier metal layer, 137 - Second pad, 138 - Oxide layer, 139 - Second capacitor barrier layer, 140 - Second capacitor mold layer oxide layer, 141 - Second capacitor layer. Detailed Implementation

[0076] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0077] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be substituted where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0078] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0079] Please refer to Figure 1 The present invention provides a method for forming a dynamic random access memory with self-aligned shared bit lines, comprising:

[0080] S1: Provide a substrate, and a plurality of stacked structures spaced apart along the X direction and extending along the Y direction on the substrate, the stacked structures including a first germanium-silicon epitaxial layer, a first silicon epitaxial layer, a second germanium-silicon epitaxial layer and a second silicon epitaxial layer stacked sequentially on the substrate along the Z direction, the stacked structures being separated by oxides, wherein the X direction, Y direction and Z direction are perpendicular to each other;

[0081] S2: The second silicon epitaxial layer is etched with the second germanium-silicon epitaxial layer as the stop layer to form a first trench in the second silicon epitaxial layer of each stacked structure. The etched second silicon epitaxial layer includes a plurality of spaced first silicon pillars.

[0082] S3: Remove the second germanium-silicon epitaxial layer to form a cavity, and form a pair of bit lines in the cavity of each stacked structure. There is a gap between the pair of bit lines that communicates with the first trench. The gap has a cross-sectional shape that is wider at the top and narrower at the bottom.

[0083] S4: Fill the gap with an undoped germanium-silicon layer, and then fill the first trench with oxide;

[0084] S5: Fabrication of upper-layer devices;

[0085] S6: Flip the substrate and remove the substrate and the first germanium-silicon epitaxial layer to expose the first silicon epitaxial layer;

[0086] S7: Etch the first silicon epitaxial layer with the undoped germanium silicon layer as the stop layer to form a second trench in the first silicon epitaxial layer of each stacked structure. The etched first silicon epitaxial layer includes a plurality of spaced second silicon pillars, each second silicon pillar being aligned with the corresponding first silicon pillar.

[0087] S8: Remove the undoped germanium silicon layer to reopen the gap between a pair of bit lines in each stacked structure, fill the gap with oxide to form an air gap between a pair of bit lines, and then fill the second trench with oxide.

[0088] S9: Fabricate the lower-level device section to form a dynamic random access memory with shared bit lines for upper and lower-level devices.

[0089] The following will combine Figures 2 to 38 The process steps are described in detail.

[0090] Please refer to Figure 2 and Figure 3First, a substrate (Sub-Si) 101 is provided, which can be a wafer. A first germanium-silicon (SiGe) epitaxial layer 102, a first silicon epitaxial layer (EPI Si) 103, a second germanium-silicon (SiGe) epitaxial layer 104, a second silicon epitaxial layer (EPI Si) 105, a silicon dioxide layer (SiO2) 106, and a silicon nitride layer (SiN) 107 are sequentially grown on the substrate 101. The first germanium-silicon (SiGe) epitaxial layer 102 will subsequently be used as a stop layer in back-side thinning, chemical mechanical polishing, or lift-off processes. The first silicon epitaxial layer (EPI Si) 103 is used to fabricate the lower-layer device and can be custom-grown according to the doping concentration of the device channel. The second germanium-silicon (SiGe) epitaxial layer 104 serves as the substrate for bit lines (BL), and the second silicon epitaxial layer 105 (Si EPI Layer) serves as the substrate for the upper-layer device. A bilayer film consisting of silicon dioxide layer 106 and silicon nitride layer 107 is used as the mask layer for the next step.

[0091] To fabricate the bit lines (BLs) of the upper and lower layer devices, a 2-pitched bit line (BL) patterning process is performed. Please refer to [reference needed]. Figure 4 and Figure 5 The silicon nitride layer 107 and the silicon dioxide layer 106 are patterned to form a mask layer, which can be achieved by methods such as quad patterning technique (QPT), dual patterning technique (DPT), and self-aligned dual patterning technique (SET).

[0092] Next, dry etching is performed to form bit lines (BLs). Starting perpendicular to the surface of the second silicon epitaxial layer 105 and moving downwards, the second silicon-germanium-silicon epitaxial layer 104, the first silicon epitaxial layer 103, and the first silicon-germanium-silicon epitaxial layer 102 are sequentially dry etched to form several parallel third trenches 108 that penetrate the first silicon-germanium-silicon epitaxial layer 102, the first silicon epitaxial layer 103, the second silicon-germanium-silicon epitaxial layer 104, the second silicon epitaxial layer 105, the silicon dioxide layer 106, and the silicon nitride layer 107. The substrate 101 is exposed within the third trenches 108. During etching, the second silicon-germanium-silicon epitaxial layer 104 is etched without selection, while the first silicon-germanium-silicon epitaxial layer 102 is etched selectively. After etching stops, etching of the first silicon-germanium-silicon epitaxial layer 102 continues until the substrate 101 is exposed. If the stacking direction of the substrate 101, the first germanium-silicon epitaxial layer 102, the first silicon epitaxial layer 103, the second germanium-silicon epitaxial layer 104, the second silicon epitaxial layer 105, the silicon dioxide layer 106, and the silicon nitride layer 107 is defined as the Z direction, then a plurality of third trenches 108 are spaced apart along the X direction, and each third trench 108 extends along the Y direction, with the X, Y, and Z directions perpendicular to each other. At this time, a plurality of spaced-apart stacked structures are formed from the etched first germanium-silicon epitaxial layer 102 to the second silicon epitaxial layer 105, with the stacking direction along the Z direction.

[0093] The gap between the two-pitched BLs (in an open state) is filled with oxide. Please refer to [reference needed]. Figure 6 and Figure 7 The third trench 108 is filled with oxide 109. The oxide deposition process is carried out using atomic layer deposition (ALD). The oxide 109 separates the stacked structure.

[0094] Next, a chemical mechanical polishing (CMP) process is performed, using silicon nitride layer 107 (SiN) as the CMP stop layer to planarize oxide 109. Oxide 109 is etched using a dry etching process or a wet etching process to expose the surface and sides of silicon nitride layer 107, with the remaining oxide 109 flush with the surface of silicon dioxide layer 106.

[0095] Please refer to Figure 8 and Figure 9 The silicon nitride layer 107 is partially etched, reducing its width in the X direction. A reverse etching process (wet or dry etching) can then be used to perform isotropic etching on the open 2-pitch bit line mask silicon nitride layer 107. This process can also be referred to as pulling back the silicon nitride layer 107.

[0096] Then, an oxide 110 is grown using atomic layer deposition (ALD) to fill the gaps between the silicon nitride layers 107, followed by a chemical mechanical polishing (CMP) process to planarize the oxide 110. Here, the oxide 110 is preferably made of the same material as the aforementioned oxide 109.

[0097] Please refer to Figure 10 and Figure 11 The mask silicon nitride layer 107 is wet-etched or dry-etched to form an opening pattern within the oxide 110. Then, using the oxide 110 as a mask, the silicon dioxide layer 106 and the second silicon epitaxial layer 105 for fabricating the upper-layer device are etched, stopping at the second germanium-silicon epitaxial layer 104 to form a first trench 111, exposing the second germanium-silicon epitaxial layer 104 within the first trench 111. The first trench 111 is spaced apart along the X-direction and extends along the Y-direction. The first trench 111 divides the second silicon epitaxial layer 105 into several first silicon pillars. In this step, when performing dry etching of the second silicon epitaxial layer 105 required for upper-layer bit line (BL) fabrication, selective etching is performed on the second germanium-silicon epitaxial layer 104 to stop the etching.

[0098] Please refer to Figure 12 and Figure 13A first sidewall 112 is formed on the sidewall of the first trench 111. The method of forming the first sidewall 112 can be to etch the spacer layer ALD oxide after deposition and then etch it back to expose the bottom second germanium silicon epitaxial layer 104. In other embodiments of the present invention, the first sidewall 112 can also be prepared by an oxidation process.

[0099] Please refer to Figure 14 and Figure 15 The second germanium-silicon epitaxial layer 104 is etched using atomic layer etch (ALE dry etch) to remove it, thereby forming a cavity 113 below the second silicon epitaxial layer 105 and the first sidewall 112. The location of the cavity 113 is used for subsequent bit line formation. A P-type gas phase doping (P-GPD) process is performed to dope the first silicon epitaxial layer 103 and the second silicon epitaxial layer 105 near the cavity 113 (bit line). The doping locations are schematically indicated by dots in the figure, corresponding to the source side positions of the upper and lower layer bit lines. After depositing a barrier metal layer, a rapid thermal annealing (RTP) process is used to diffuse and activate impurities, thereby forming source regions for the upper and lower layer devices, respectively, in the first silicon epitaxial layer 103 and the second silicon epitaxial layer 105 near the cavity 113.

[0100] Please refer to Figure 16 and Figure 17 After depositing bit line metal (BL Metal) within cavity 113, a back etching process is performed. This can be achieved through multiple metal deposition-etching processes or by adding different types of metal. Subsequently, the bit line metal is vertically etched to form bit line 114, and a gap is formed within the etched bit line 114. This gap can have a cross-sectional shape that is wider at the top and narrower at the bottom; in other words, the etched bit line 114 has a positive slope structure.

[0101] Please refer to Figure 18 and Figure 19 Undoped germanium-silicon material is deposited to fill the gaps between bit lines 114, and the undoped germanium-silicon is etched back to form an undoped germanium-silicon layer 115 within the gaps of bit lines 114, thereby filling the open gaps of bit lines 114. The undoped germanium-silicon layer 115 is flush with the surface of bit lines 114. Utilizing the positive slope of bit lines 114, the bottom filling of the gaps can be accelerated by adjusting the thickness. Subsequently, the first trench 111 above the undoped germanium-silicon layer 115 is filled with oxide 116 using methods with relatively weak gap-filling capabilities, such as CVD oxide layers, and then the oxide 116 is planarized using a CMP polishing process.

[0102] Subsequently, the upper-layer device was fabricated. Cross-sectional structural diagrams of some steps are omitted here. Figure 22 and Figure 23 This shows the structure after word lines are formed in the upper-layer device. Figure 18 after, Figure 22 The previous preparation process included the following steps: Please refer to Figure 20 and Figure 21 Deposit a word line mask layer, which can be an oxide layer or a silicon nitride layer, and perform a word line patterning process. See details. Figure 21 The dashed box in the image; after word line etching, an oxide interlayer and a silicon nitride isolation layer are deposited; after silicon nitride etch-back, the exposed oxide layer is etched, and a word line mesh 117 (WL Mesh) can be formed at the top of the exposed upper first silicon pillar. The word line mesh 117 is epitaxial silicon / oxide / silicon carbide; please refer to... Figure 22 and Figure 23 The oxide layer is etched between the gaps of the already opened word line grid 117. After the oxide layer is etched, the word line (WL) is formed by gate oxidation / gate metal deposition / gate metal etchback / cover oxide layer deposition in sequence.

[0103] Please refer to Figure 24 and Figure 25 A barrier metal layer and node contact area metal are deposited, and the node contact area is patterned and etched to form a first barrier metal layer 120 and a first pad 121. An oxide 122 is formed by filling the area between the first pads 121. A first capacitor barrier layer 123 and a first capacitor mold oxide layer 124 are then formed on the first pads 121. A grid-like first capacitor layer 125 is formed within the first capacitor barrier layer 123 and the first capacitor mold oxide layer 124. The first capacitor layer 125 is bonded to the first pads 121, thus completing the fabrication of the first capacitor. After completing the device routing or pad fabrication process using an upper metal layer, a carrier wafer (not shown) is fused and bonded on top of the upper device.

[0104] Please refer to Figure 26 After flipping the wafer, with the substrate 101 on top, a grinding or chemical mechanical polishing (CMP) process is performed to remove the substrate 101. In this step, the first germanium-silicon epitaxial layer 102 is used as a stop layer when removing the substrate 101. After removing the substrate 101, the first germanium-silicon epitaxial layer 102 is etched back to remove it, exposing the first silicon epitaxial layer 103. After removing the first germanium-silicon epitaxial layer 102, the surface of the oxide 109 is higher than the surface of the first silicon epitaxial layer 103, forming a protrusion (e.g., ...). Figure 26 As shown in the red circle, an oxide fence is formed by oxides protruding from the surface of the first silicon epitaxial layer.

[0105] Please refer to Figure 27 and Figure 28 A pad oxide layer 126 and a mask silicon nitride layer 127 are deposited between the oxide fences as a mask layer. After chemical mechanical polishing of the mask silicon nitride 127, the oxide fences are etched away, leaving only the mask silicon nitride region exposed. Here, in contrast... Figure 24 and Figure 27 The morphology of the silicon nitride mask 127 is basically the same as that of the removed first germanium-silicon epitaxial layer 102, which is equivalent to replacing the first germanium-silicon epitaxial layer 102 with the silicon nitride mask 127. Therefore, the thickness of the first germanium-silicon epitaxial layer 102 is set to be the thickness of the self-aligned silicon nitride mask 127 that enables the etching of columnar structures in the underlying device. The thickness of the second germanium-silicon epitaxial layer 104 takes into account the bit line resistance and can be set according to the requirements of the bit line resistance. Therefore, the thickness of the second germanium-silicon epitaxial layer 104 can be different from the thickness of the first germanium-silicon epitaxial layer 102.

[0106] Please refer to Figure 29 and Figure 30 , adopt and Figures 6 to 8 Using the same process as the upper-layer device mask, a silicon nitride pull-back process is performed to reduce the width of the silicon nitride mask 127 in the X direction. An oxide 128 is deposited to fill the gaps between the silicon nitride mask 127, followed by an oxide chemical mechanical polishing (CMP) process to planarize the oxide 128.

[0107] Please refer to Figure 31 and Figure 32 The silicon nitride mask 127 is pulled back, and the pulled-back silicon nitride mask 127 is used as a mask to etch the underlying pad oxide layer 126 and the first silicon epitaxial layer 103. Etching stops at the undoped germanium silicon layer 115, thereby forming a plurality of second trenches 129, exposing the undoped germanium silicon layer 115 within the second trenches 129. The plurality of second trenches 129 are spaced apart along the X direction and extend along the Y direction. The second trenches 129 divide the etched first silicon epitaxial layer 103 into a plurality of second silicon pillars, that is, the etched first silicon epitaxial layer includes a plurality of spaced second silicon pillars, each second silicon pillar being aligned one-to-one with a corresponding first silicon pillar. The second silicon pillars are used to fabricate the underlying devices.

[0108] Please refer to Figure 33 and Figure 34A second sidewall 130 is formed on the sidewall of the second trench 129. The second sidewall 130 can be formed by etching after depositing the spacer layer ALD oxide, followed by an etch-back process to expose the undoped germanium-silicon layer 115. Next, the undoped germanium-silicon layer 115 is removed, allowing a new gap with a narrow top and wide bottom cross-sectional shape to be formed between the bit lines 114 of the same stacked structure. A gap is opened between each pair of bit lines in each stacked structure, such as... Figure 33 As shown, each bit line 114 has a gap on one side and oxide 109 on the other side.

[0109] Please refer to Figure 35 and Figure 36 After opening the gap, oxide 131 is filled into the second trench 129. Because the bit lines 114 formed in the preceding steps have a positive slope, after flipping the wafer, the gaps reopened between the bit lines 114 become a cross-sectional shape that is narrower at the top and wider at the bottom. That is, when fabricating the lower-layer device, the bit lines 114 exhibit a negative slope. Using oxides with relatively weak gap-filling capabilities, such as CVD oxides, for bit line gap filling and performing chemical mechanical polishing (CMP) planarization, due to the negative slope effect of the bit lines 114, air gaps 132 are formed between the bit lines 114 in the same stacked structure when filling the oxide. Figure 35 As shown, an air gap 132 is formed on one side (left or right) of each bit line 114, and an oxide 109 is formed on the other side. The inclination direction of the opposite sidewalls of the two word lines 114 located on both sides of the same air gap 132 is symmetrical about the vertical direction. Therefore, the present invention achieves the purpose of sharing bit lines 114 without additional wafers by setting up a stacked structure. Furthermore, by controlling the shape of the bit lines 114, an air gap 132 is obtained between the bit lines 114 to solve the problem of increased bit line capacitance. In other embodiments, it is not necessary to first form a gap that is wider at the top and narrower at the bottom, fill it with an undoped germanium-silicon layer 115, flip the wafer, and then remove the undoped germanium-silicon layer 115 to obtain a gap that is narrower at the top and wider at the bottom, and then fill the gap to form an air gap. Instead, a low dielectric constant material or a porous oxide material or a combination thereof can be directly filled into the gap without special shape requirements to reduce bit line capacitance, which can achieve a similar effect to an air gap.

[0110] Please continue to refer to Figure 35 and Figure 36 The word lines of the lower-level devices are formed using the same method that forms the word lines of the upper-level devices.

[0111] Please refer to Figure 37 and Figure 38A second barrier metal layer 136 and a second pad 137 are formed using the same method as the first capacitor, and an oxide layer 138 is formed by filling the area between the second pads 137. A second capacitor barrier layer 139 and a second capacitor mold oxide layer 140 are then formed on the second pads 137, and a second capacitor layer 141 is formed within the second capacitor barrier layer 139 and the second capacitor mold oxide layer 140. The second capacitor layer 141 is bonded to the second pads 137, thereby completing the fabrication of the second capacitor.

[0112] A second word line is formed on the upper sidewall of the second silicon pillar, thus forming an upper transistor. A second word line is formed on the lower sidewall of the first silicon pillar, thus forming a lower transistor. The two transistors share a bit line, thus forming a 4F type with fully self-aligned shared bit line (BL) with a capacitor configured on the upper and lower parts of the bit line. 2 DRAM array structure. There is an air gap on one side of bit line 114. This structure reduces the common bit line capacitance (Cbl) through the air gap, thereby reducing the required memory cell capacitance and improving the sensing margin. Extending the bit line length can also more than double the number of storage bits (cells).

[0113] Please continue to refer to Figure 37This invention also provides a dynamic random access memory (DRAM) with self-aligned shared bit lines, which can be formed using a method for DRAM with self-aligned shared bit lines. The DRAM with self-aligned shared bit lines includes: an upper device structure comprising a plurality of spaced first silicon pillars; a lower device structure comprising a plurality of spaced second silicon pillars, wherein the plurality of second silicon pillars are aligned with the plurality of first silicon pillars; and a plurality of bit lines 114 located between the first and second silicon pillars and shared by the upper and lower device structures. Each bit line 114 has an air gap 132 formed on one side and an oxide layer on the other side. The sidewall of each bit line 114 near the air gap 132 is inclined relative to the vertical direction, and the sidewall near the oxide layer extends vertically. The inclination directions of the opposing sidewalls of two word lines 114 located on opposite sides of the same air gap 132 are symmetrical about the vertical direction. In the dynamic random access memory (DRAM), the upper-layer device structure includes a first pillar transistor and a first capacitor, and the lower-layer device structure includes a second pillar transistor and a second capacitor. The first pillar transistor includes a first silicon pillar, and the second pillar transistor includes a second silicon pillar. The first pillar transistor and the second pillar transistor share a bit line 114. The sidewalls of the first silicon pillar are covered by a first sidewall 112; the sidewalls of the second silicon pillar are covered by a second sidewall 130. The first capacitor includes a first barrier metal layer 120, a first pad 121, a first capacitor blocking layer 123, a first capacitor oxide layer 124, and a first capacitor layer 125. The second capacitor includes a second barrier metal layer 136, a second pad 137, a second capacitor blocking layer 139, a second capacitor oxide layer 140, and a second capacitor layer 141.

[0114] The directions above and below in this embodiment of the invention are both set with reference to Figure 37 , Figure 37 This is a cross-sectional view along the Z direction. If the device is rotated, the corresponding first and second silicon pillars above and below may change; similarly, the names of the two corresponding vertical transistors may also change. The two transistors aligned with the bit line and air gap have a symmetrical structure.

[0115] In summary, in the self-aligned shared bit line dynamic random access memory and its formation method provided in this embodiment of the invention, a stacked structure of a first germanium-silicon epitaxial layer, a first silicon epitaxial layer, a second germanium-silicon epitaxial layer, and a second silicon epitaxial layer is formed on the same substrate. Upper transistors and lower transistors are then formed in the first silicon epitaxial layer and the second silicon epitaxial layer, respectively. By forming a bit line between the two silicon epitaxial layers on the same substrate, and then forming upper and lower transistors in the two silicon epitaxial layers respectively to share the bit line, the use of additional wafers is avoided, reducing costs and process complexity. Furthermore, this invention employs an air gap formed on the left or right side of a single bit line, and columnar transistors and capacitors are respectively arranged above and below the bit line. This forms a fully self-aligned shared bit line 4F² DRAM array structure with an air gap structure. This structure reduces the bit line capacitance through the air gap, thereby reducing the required memory cell capacitance and improving the sensing margin. Further, this embodiment of the invention can also increase the number of storage bits (cells) by more than doubling the length of the bit line.

[0116] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for forming a dynamic random access memory, characterized in that, include: A substrate is provided, and a plurality of stacked structures spaced apart along the X direction and extending along the Y direction on the substrate, the stacked structures comprising a first germanium-silicon epitaxial layer, a first silicon epitaxial layer, a second germanium-silicon epitaxial layer and a second silicon epitaxial layer stacked sequentially on the substrate along the Z direction, the stacked structures being separated by oxides, wherein the X direction, the Y direction and the Z direction are perpendicular to each other; The second silicon epitaxial layer is etched with the second germanium-silicon epitaxial layer as a stop layer to form a first trench in the second silicon epitaxial layer of each of the stacked structures. The etched second silicon epitaxial layer includes a plurality of spaced first silicon pillars. The second germanium-silicon epitaxial layer is removed to form a cavity, and a pair of bit lines are formed in the cavity of each stacked structure. The pair of bit lines have a gap communicating with the first trench, and the gap has a cross-sectional shape that is wider at the top and narrower at the bottom. An undoped germanium-silicon layer is filled into the gap, and then an oxide layer is filled into the first trench. Fabrication of the upper-layer device; The substrate is flipped over, and the substrate and the first germanium-silicon epitaxial layer are removed to expose the first silicon epitaxial layer; The first silicon epitaxial layer is etched with an undoped germanium silicon layer as a stop layer to form a second trench in the first silicon epitaxial layer of each stacked structure. The etched first silicon epitaxial layer includes a plurality of spaced second silicon pillars, each second silicon pillar being aligned with a corresponding first silicon pillar. Remove the undoped germanium silicon layer to reopen the gap between a pair of bit lines in each of the stacked structures, fill the gap with oxide to form an air gap between the pair of bit lines, and then fill the second trench with oxide. The lower-level device portion is fabricated to form a dynamic random access memory with shared bit lines for both upper and lower-level devices.

2. The method for forming a dynamic random access memory as described in claim 1, characterized in that, One side of the bit line is an air gap, and the other side is an oxide.

3. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The method further includes flipping the substrate and removing the substrate and the first germanium-silicon epitaxial layer to expose the first silicon epitaxial layer, and then forming an oxide fence with oxide protruding from the surface of the first silicon epitaxial layer. A mask layer is filled between the oxide fences, such that the morphology of the mask layer is substantially the same as that of the first germanium-silicon epitaxial layer that has been removed. Remove oxide fencing; Pull back the mask layer; and The first silicon epitaxial layer is etched using the pulled-back mask layer as a mask to form the second trench.

4. The method for forming a dynamic random access memory as described in claim 3, characterized in that, The thickness of the first germanium-silicon epitaxial layer is set such that each second silicon pillar obtained by etching the first silicon epitaxial layer with the pull-back mask layer as a mask is aligned with the corresponding first silicon pillar.

5. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The thickness of the second germanium-silicon epitaxial layer is set according to the requirements of the bit line resistance.

6. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The gap that reopens between a pair of bit lines in each of the stacked structures has a cross-sectional shape that is narrower at the top and wider at the bottom. The reopened gap is filled with oxide using a CVD filling process to form an air gap between the bit lines.

7. A dynamic random access memory (DRAM) prepared using the method for forming a DRAM according to any one of claims 1 to 6.

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