Semiconductor structure, method of manufacturing the same, and electronic device

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and an electronic device, wherein the semiconductor comprises: a substrate, and an active layer on the substrate, the active layer comprising a channel region and source / drain doped regions on both sides of the channel region; a word line structure electrically connected with the channel region; a bit line structure electrically connected with the source / drain doped region on one side of the channel region; an insulating layer between adjacent bit line structures; a capacitor contact structure in the insulating layer and electrically connected with the source / drain doped region on the other side of the channel region; and a capacitor structure electrically connected with the capacitor contact structure. The reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] As semiconductor manufacturing processes continue to advance, the size of semiconductor memories is becoming smaller and smaller. This leads to a reduction in the spacing between different conductive structures, especially capacitive contact structures. As device size decreases, the probability of short circuits in capacitive contact structures increases, resulting in a decrease in the reliability of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, as well as an electronic device, which can at least improve the reliability of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, comprising: a substrate, and an active layer on the substrate, the active layer including a channel region and source / drain doped regions located on both sides of the channel region; a word line structure electrically connected to the channel region; a bit line structure electrically connected to the source / drain doped region on one side of the channel region; an insulating layer located between adjacent bit line structures; a capacitor contact structure located within the insulating layer and electrically connected to the source / drain doped region on the other side of the channel region; and a capacitor structure electrically connected to the capacitor contact structure.

[0006] Optionally, the capacitor contact structure includes: a first part and a second part connected to each other, the first part being connected to the active layer, the second part being located on the side of the first part away from the active layer, and the spacing between the second part and the bit line structure being smaller than the spacing between the first part and the bit line structure.

[0007] Optionally, the second part includes: a first sub-part, one end of which is connected to the first part; and a second sub-part, which is connected to the other end of the first sub-part, and extends above the bit line structure.

[0008] Optionally, the extension direction of the first sub-part forms an angle with the extension direction of the first part.

[0009] Optionally, the angle between the extending direction of the first sub-part and the extending direction of the first part is 5° to 10°.

[0010] Optionally, the orthographic projection of the second sub-part onto the substrate is elliptical or circular.

[0011] Optionally, part of the capacitor structure is also located within the second sub-section.

[0012] Optionally, the capacitor structure located in the second sub-section is stepped, hemispherical, or cylindrical.

[0013] Optionally, the thickness of the capacitor structure located within the second sub-section is 4~6 nm.

[0014] Optionally, the capacitive contact structure further includes a transition portion located between the first portion and the second portion.

[0015] Optionally, it may also include an adhesive layer located between the capacitor contact structure and the capacitor structure.

[0016] Optionally, it may also include: a bit line protection layer, which covers the surface of the bit line structure, and the bit line protection layer and the insulating layer are an integral structure.

[0017] Optionally, it may also include: a second insulating layer, the second insulating layer covering the top surface of the capacitor contact structure and the sidewalls of the capacitor structure.

[0018] This disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate and an active layer on the substrate, the active layer including a channel region and source / drain doped regions located on both sides of the channel region; forming a word line structure electrically connected to the channel region; forming a bit line structure electrically connected to the source / drain doped regions on one side of the channel region; forming an insulating layer between adjacent bit line structures; forming a capacitor contact structure located within the insulating layer and electrically connected to the source / drain doped regions on the other side of the channel region; and forming a capacitor structure electrically connected to the capacitor contact structure.

[0019] In another aspect, this disclosure provides an electronic device, comprising: a semiconductor structure as described above, or a semiconductor structure formed by a method for fabricating a semiconductor structure as described above.

[0020] The technical solution provided in this disclosure has at least the following advantages: by setting the capacitor contact structure in the insulating layer located between adjacent bit line structures, the insulating layer can separate the bit line structures while simultaneously separating the capacitor contact structure, thereby reducing the risk of short circuit between adjacent capacitor contact structures during the formation of the capacitor contact structure, and thus improving the reliability of the semiconductor structure. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a partially enlarged schematic diagram of an active layer provided in an embodiment of the present disclosure; Figure 4 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure; Figure 5 This is a partially enlarged view of the capacitor contact structure and the contact position of the capacitor structure provided in an embodiment of this disclosure; Figure 6 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present disclosure.

[0023] Explanation of reference numerals in the attached figures: 100. Substrate; 101. Active layer; 111. Channel region; 121. Source / drain doped region; 102. Word line structure; 103. Bit line structure; 104. Insulating layer; 105. Capacitor contact structure; 106. Capacitor structure; 109. Isolation structure; 115. First part; 125. Second part; 1251. First sub-part; 1252. Second sub-part; 135. Transition part; 107. Adhesion layer; 108. Second insulating layer; 500. Processor; 501. Semiconductor structure. Detailed Implementation

[0024] As is known from the background technology, in order to improve the arrangement density of semiconductor structures, capacitor contact structures are usually placed on an insulating layer. The capacitor contact structure is used to change the capacitor structure to a hexagonal density arrangement. However, because the capacitor contact structure is placed on an insulating layer, it can cause short circuits between adjacent capacitor contact structures during the formation of the capacitor contact structure.

[0025] The technical solution provided in this disclosure has at least the following advantages: by setting the capacitor contact structure in the insulating layer located between adjacent bit line structures, the insulating layer can separate the bit line structures while simultaneously separating the capacitor contact structure, thereby reducing the risk of short circuit between adjacent capacitor contact structures during the formation of the capacitor contact structure, and thus improving the reliability of the semiconductor structure.

[0026] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0030] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0031] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0032] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0033] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0034] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and claims of the various embodiments described, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0035] In the description of the embodiments disclosed herein, electrical connection actually refers to the fact that one component and another component are both made of conductive materials, and the two components are in direct contact or connected via other conductive materials. Therefore, when in a power generation state, there is an electrical connection between the two components.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] refer to Figures 1 to 3 , Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 This is a partially enlarged schematic diagram of an active layer provided in an embodiment of this disclosure.

[0038] In some embodiments, the semiconductor structure may include: a substrate 100, and an active layer 101 located on the substrate 100, the active layer 101 including a channel region 111 and source / drain doped regions 121 located on both sides of the channel region 111.

[0039] The semiconductor structure may also include: word line structure 102, which is located on channel region 111.

[0040] The semiconductor structure may also include a bit line structure 103, which is electrically connected to the source / drain doped region 121 on one side of the channel region 111.

[0041] The semiconductor structure may also include an insulating layer 104, which is located between adjacent bit line structures 103.

[0042] The semiconductor structure may also include a capacitor contact structure 105, which is located within the insulating layer 104 and is electrically connected to the source / drain doped region 121 on the other side of the channel region 111.

[0043] The semiconductor structure may also include a capacitor structure 106, which is electrically connected to the capacitor contact structure 105.

[0044] In this embodiment of the present disclosure, the capacitor contact structure 105 is disposed within the insulating layer 104 located between adjacent bit line structures 103. Thus, the insulating layer 104 separates the bit line structures 103 while simultaneously separating the capacitor contact structures 105, thereby reducing the risk of short circuit between adjacent capacitor contact structures 105 during the formation of the capacitor contact structure 105, thereby improving the reliability of the semiconductor structure.

[0045] In some embodiments, the material of substrate 100 may include semiconductor materials, such as, but not limited to, silicon. In some embodiments, substrate 100 may include: basic semiconductors, compound semiconductors, or alloy semiconductors. For example, basic semiconductors include silicon; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; alloy semiconductors include gallium arsenide phosphide, gallium indium phosphide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator structure.

[0046] The active layer 101 is a junction-type doped layer. The dopant ions in the portion of the active layer 101 near the bit line structure 103 and near the capacitor structure 106 (i.e., the source / drain doped regions 121) can be either N-type or P-type, serving as the source and drain, respectively. The dopant ions in the portion covered by the word line structure 102 (i.e., the channel region 111) are either N-type or P-type, serving as the channel. Here, "junction-type" means that different regions within the active layer 101 have different dopant ion types to form a PN junction. In other embodiments, the active layer 101 is a junctionless layer (where "junction" refers to a PN junction), meaning that the dopant ion type of the entire active layer 101 is the same, which can all be N-type or all P-type. However, the doping concentration in the portion covered by the word line structure 102 should be lower than the doping concentration in the portion near the bit line structure 103 and the portion near the capacitor structure 106.

[0047] It should be noted that the source / drain doped region 121 and the channel region 111 are two artificially divided regions for ease of explanation. In the actual structure, there is no clear boundary between the source / drain doped region 121 and the channel region 111.

[0048] An isolation structure 109 is also spaced between adjacent active layers. The isolation structure 109 can serve as an STI (Shallow Trench Isolation) structure.

[0049] The word line structure 102 may include: a word line dielectric layer and a word line conductive layer located on the surface of the word line dielectric layer. The material of the word line dielectric layer may include silicon oxide or a high dielectric constant material, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, etc. The material of the word line conductive layer may include tungsten, titanium nitride, titanium aluminum nitride, or copper, etc.

[0050] The bit line structure 103 may include a first bit line conductive layer (not shown), a bit line blocking layer (not shown), a second bit line conductive layer (not shown), and a bit line capping layer (not shown) stacked together. By setting the bit line structure 103 to include the first bit line conductive layer, the bit line blocking layer, and the second bit line conductive layer stacked together, the reliability of the bit line structure 103 in transmitting data information can be improved.

[0051] In some embodiments, the material of the first bit line conductive layer can be a semiconductor material such as polysilicon, the material of the bit line blocking layer can be titanium nitride, and the material of the second bit line conductive layer can be a metal such as tungsten. By setting the material of the first bit line conductive layer to a semiconductor material such as polysilicon, the interface states at the contact surface between the bit line structure 103 and the source / drain doped region 121 can be reduced, thereby reducing the possibility of anomalies when transmitting data information between the active layer and the bit line structure 103. By setting the bit line blocking layer, metal ions in the second bit line conductive layer can be prevented from diffusing into the first bit line conductive layer, thus avoiding affecting the performance of the first bit line conductive layer. By setting the material of the second bit line conductive layer to a metal material, the transmission rate of data information transmitted by the bit line structure 103 can be improved.

[0052] In some embodiments, the first bit line conductive layer may also consist of only a single film layer, such as only polycrystalline silicon or only tungsten metal, and the material of the bit line capping layer may be silicon nitride.

[0053] In some embodiments, the semiconductor structure further includes a bit line protection layer covering the surface of the bit line structure 103. The bit line protection layer can be a NON (nitride-oxide-nitride) structure. By providing an oxide layer between two nitride layers, the insulation performance of the bit line protection layer can be improved, and the parasitic capacitance between adjacent bit line structures 103 can be reduced. Furthermore, the nitride layer is relatively hard, and providing two nitride layers can improve the morphology of the bit line protection layer. The bit line protection layer can also be a single-layer structure, such as a single-layer nitride layer or a single-layer oxide layer, etc.

[0054] The bit line protection layer can be integrated with the insulating layer 104. In other words, a portion of the bit line protection layer can be used as the insulating layer 104, and the capacitor contact structure 105 can be disposed within the bit line protection layer. This allows the bit line protection layer to isolate adjacent capacitor contact structures 105, thereby improving the reliability of the semiconductor structure and reducing the number of process steps. There is no need to form an additional insulating layer 104 for isolating the capacitor contact structure 105, which can reduce the process cost of the semiconductor structure.

[0055] The capacitor contact structure 105 is used to bring out the signal from the source and drain doped regions 121. On the one hand, it provides a larger process window for forming the capacitor structure 106. On the other hand, it avoids the spacing between the capacitor structure 106 and the bit line structure 103 being too small, thereby avoiding short circuits between the capacitor structure 106 and the bit line structure 103.

[0056] refer to Figure 4 , Figure 4 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0057] In some embodiments, the capacitor contact structure 105 may include a first portion 115 and a second portion 125 interconnected with each other. The first portion 115 is connected to the active layer 101, and the second portion 125 is located on the side of the first portion 115 away from the active layer 101. The spacing between the second portion 125 and the bit line structure 103 is smaller than the spacing between the first portion 115 and the bit line structure 103. The first portion 115 is used to lead out the capacitor contact structure 105, and the second portion 125 is used to increase the arrangement density of the subsequently formed capacitor contact structures 105. Therefore, by setting the spacing between the second portion 125 and the bit line structure 103 to be smaller, the spacing of the formed capacitor structures 106 can be reduced, thereby increasing the arrangement density of the capacitor structures 106.

[0058] In some embodiments, the second portion 125 may include: a first sub-portion 1251, one end of which is connected to the first portion 115; and a second sub-portion 1252, the other end of which is connected to the first sub-portion 1251, and extending above the bit line structure 103. By extending the second sub-portion 1252 above the bit line structure 103, the position of the bit line structure 103 does not need to be considered when forming the capacitor structure 106, thus increasing the process window for forming the capacitor structure 106. Simultaneously, the extension of the second sub-portion 1252 above the bit line structure 103 provides a larger accommodating space for forming the capacitor structure 106, facilitating an increase in the arrangement density of the capacitor structure 106.

[0059] In other embodiments, the second sub-part 1252 may also be located between adjacent bit line structures 103, and the top surface of the first sub-part 1251 may be flush with or higher than the bit line structure 103, so that when forming the second sub-part 1252, the interval between the second sub-part 1252 and the bit line structure 103 does not need to be considered, thereby facilitating the formation of the second sub-part 1252.

[0060] In some embodiments, the extending direction of the first sub-part 1251 forms an angle with the extending direction of the first part 115. By adjusting the extending direction of the first sub-part 1251, the position of the second part 125 can be adjusted, thereby providing a process basis for increasing the arrangement density of the second part 125.

[0061] The extension direction of the first part 115 can be the same as the extension direction of the bit line structure 103.

[0062] In some embodiments, the angle between the extending direction of the first sub-part 1251 and the extending direction of the first part 115 is 5° to 10°, for example, it can be 5° to 8° or 8° to 10°, or it can be 5°, 6°, 7°, 8°, 9° or 10°, etc. For the angle between the extending direction of the first sub-part 1251 and the extending direction of the first part 115, a larger angle is more conducive to increasing the arrangement density of the second sub-part 1252. However, an excessively large angle will reduce the spacing between the first sub-part 1251 and the bit line structure 103, increasing the risk of short circuit between the capacitor contact structure 105 and the bit line structure 103. Therefore, setting the angle between the extending direction of the first sub-part 1251 and the extending direction of the first part 115 to 5° to facilitate increasing the arrangement density of the capacitor contact structure 105 while avoiding affecting the reliability of the semiconductor structure.

[0063] Understandably, during the formation of the first sub-part 1251, the larger the angle between the extension direction of the first sub-part 1251 and the extension direction of the first part 115, the deeper the etching of the first sub-part 1251. Etching too much of the first sub-part 1251 will reduce the reliability of the capacitor contact structure 105. Therefore, controlling the angle between the extension direction of the first sub-part 1251 and the extension direction of the first part 115 to be less than or equal to 10° will also avoid reducing the reliability of the capacitor contact structure 105.

[0064] In some embodiments, the width of the second sub-part 1252 is greater than the width of the first sub-part 1251. Setting the width of the second sub-part 1252 to be larger can increase the contact area between the second sub-part 1252 and the capacitor structure 106, and at the same time can increase the process window for forming the capacitor structure 106, thereby improving the performance of the semiconductor structure.

[0065] It should be noted that the width here refers to the width along the arrangement direction of the bit line structure 103.

[0066] In some embodiments, the orthographic projection of the second sub-part 1252 onto the substrate 100 is elliptical or circular. In other words, setting the second sub-part 1252 as cylindrical reduces the edge morphology of the second sub-part 1252 compared to setting it as cubic, suppresses the selective growth of the second sub-part 1252 at the edge positions, and further reduces the risk of short circuits between adjacent capacitor contact structures 105.

[0067] It is understandable that if the second sub-part 1252 is cubic, material accumulation will occur at the edges and corners of the cube. Taking tungsten as an example, tungsten grows faster at the edges and corners, resulting in additional tungsten growth at the edges and corners between adjacent second sub-parts 1252, causing overlap between adjacent second sub-parts 1252. Therefore, setting the second sub-part 1252 as cylindrical can reduce the risk of overlap between adjacent capacitor contact structures 105.

[0068] When the orthographic projection of the second sub-part 1252 onto the substrate 100 is circular, its diameter can be 20nm~40nm, for example, 20nm~30nm or 30nm~40nm. When the orthographic projection of the second sub-part 1252 onto the substrate 100 is elliptical, its major axis can be 20nm~40nm, for example, 20nm~30nm or 30nm~40nm, and its minor axis can be 10nm~30nm, for example, 10nm~20nm or 20nm~30nm.

[0069] refer to Figure 5 , Figure 5 This is a partially enlarged view of the capacitor contact structure and the contact position of the capacitor structure provided in an embodiment of this disclosure.

[0070] In some embodiments, a portion of the capacitor structure 106 is also located within the second sub-part 1252. In other words, a groove is provided within the second sub-part 1252, and the capacitor structure 106 also covers the surface of the groove in the second sub-part 1252. On the one hand, this increases the contact area between the capacitor structure 106 and the capacitor contact structure 105; on the other hand, it increases the size of the capacitor structure 106, thereby improving the performance of the capacitor structure 106.

[0071] In some embodiments, the capacitor structure 106 located within the second sub-part 1252 is stepped, hemispherical, or cylindrical. In other words, the groove of the second sub-part 1252 has a stepped, hemispherical, or cylindrical shape. By adjusting the shape of the groove within the second sub-part 1252, the contact area between the capacitor structure 106 and the capacitor contact structure 105 is increased, while the size of the capacitor structure 106 is also increased, thereby improving the performance of the capacitor structure 106.

[0072] When the capacitor structure 106 within the second sub-part 1252 is stepped, the sidewall of the groove within the second sub-part 1252 can have at least one step, and the number of steps can be 1 to 3. The stepped structure increases the contact area between the capacitor structure 106 and the capacitor contact structure 105, and simultaneously increases the effective area of ​​the capacitor structure 106, thereby improving the capacitance of the capacitor structure 106. When the capacitor structure 106 within the second sub-part 1252 is hemispherical, the bottom of the groove within the second sub-part 1252 can be hemispherical. The hemispherical structure maximizes the surface area of ​​the capacitor structure 106 within a limited planar area, which is beneficial for improving the capacitance of the capacitor structure 106. When the capacitor structure 106 within the second sub-part 1252 is cylindrical, the groove within the second sub-part 1252 can be cylindrical. The cylindrical structure is simple to manufacture, easy to implement, and can increase the effective area of ​​the capacitor structure 106 to a certain extent.

[0073] It is understandable that after the capacitor structure 106 is formed, the groove in the second sub-part 1252 is filled. Therefore, there is no corresponding groove in the actual structure of the semiconductor structure. The shape of the capacitor structure 106 located in the second sub-part 1252 corresponds to the shape of the groove.

[0074] In some embodiments, the thickness of the capacitor structure 106 located in the second sub-part 1252 is 4nm to 6nm, for example, 4nm to 5nm or 5nm to 6nm, etc., and can be 4nm, 4.2nm, 4.5nm, 5nm, 5.3nm, 5.8nm or 6nm, etc. It is understandable that the thicker the capacitor structure 106 located in the second sub-part 1252, that is, the deeper the groove in the second sub-part 1252, the more reliable the second sub-part 1252 will be. If the thickness of the capacitor structure 106 located in the second sub-part 1252 is too thick, that is, the groove depth of the second sub-part 1252 is too deep, it will affect the reliability of the second sub-part 1252. If the thickness of the capacitor structure 106 located in the second sub-part 1252 is too shallow, it will result in a weaker effect on improving the contact capability between the capacitor structure 106 and the capacitor contact structure 105. Therefore, the thickness of the capacitor structure 106 located in the second sub-part 1252 is set to 4nm~6nm to reduce the contact resistance between the capacitor structure 106 and the capacitor contact structure 105 while avoiding affecting the reliability of the second sub-part 1252.

[0075] In some embodiments, the thickness of the portion of the second sub-part 1252 facing the capacitor structure 106 can be 15nm to 20nm, for example, 15nm to 18nm or 18nm to 20nm, or even 15nm, 16nm, 17nm, 18nm, 19nm, or 20nm, etc. If the thickness of the portion of the second sub-part 1252 facing the capacitor structure 106 is too thin, the reliability of the portion supporting the capacitor structure 106 will decrease. If the thickness of the portion of the second sub-part 1252 facing the capacitor structure 106 is too thick, the ability to improve the contact resistance between the capacitor structure 106 and the capacitor contact structure 105 will decrease. Therefore, setting the thickness of the portion of the second sub-part 1252 facing the capacitor structure 106 to 15nm and 20nm reduces the contact resistance between the capacitor structure 106 and the capacitor contact structure 105 while avoiding affecting the reliability of the second sub-part 1252 is achieved.

[0076] In some embodiments, the thickness of the portion of the second sub-part 1252 adjacent to the capacitor structure 106 can be 25nm~30nm, for example, 25nm~28nm or 28nm~30nm, or even 25nm, 26nm, 27nm, 28nm, 29nm or 30nm, etc. The thicker the portion of the second sub-part 1252 adjacent to the capacitor structure 106, the deeper the second sub-part 1252 can be used to form the groove, and the higher the reliability of the second sub-part 1252 itself; if the thickness of the portion of the second sub-part 1252 adjacent to the capacitor structure 106 is too thick, the height of the semiconductor structure used to form the capacitor structure 106 will be reduced, affecting the performance of the capacitor structure 106.

[0077] refer to Figure 4 In some embodiments, the capacitive contact structure 105 further includes a transition portion 135, which is located between the first portion 115 and the second portion 125. The transition portion 135 can improve the interface state between the first portion 115 and the second portion 125, thereby improving the signal transmission performance of the capacitive contact structure 105.

[0078] In some embodiments, the material of the first part 115 can be a semiconductor material such as polycrystalline silicon. The material of the first part 115 being a semiconductor material can reduce the material difference between the first part 115 and the active layer 101. The material of the transition part 135 can be a metal silicide, such as titanium silicide, tantalum silicide, molybdenum silicide, chromium silicide, zirconium silicide, or hafnium silicide, etc. The material of the second part 125 can be a metal, such as tungsten, copper, or titanium, etc. The transition part 135 is used to improve the material difference between the first part 115 and the second part 125, thereby avoiding the abnormality caused by the direct change from semiconductor material to metal material. The second part 125 being a metal material can reduce the contact resistance between the capacitor contact structure 105 and the capacitor structure 106.

[0079] refer to Figure 2 In some embodiments, the semiconductor structure may further include an adhesion layer 107, which is located between the capacitor contact structure 105 and the capacitor structure 106. By providing the adhesion layer 107, the bonding force between the capacitor contact structure 105 and the capacitor structure 106 can be improved, the probability of interface detachment can be reduced, and thus the reliability of the semiconductor structure can be improved.

[0080] The adhesion layer 107 may surround the sidewall of the portion of the capacitor structure 106 located inside the capacitor contact structure 105, and also cover the bottom surface of the capacitor structure 106 facing the capacitor contact structure 105.

[0081] In some embodiments, the material of the adhesion layer 107 may include titanium or titanium nitride, etc.

[0082] refer to Figure 4 In some embodiments, the semiconductor structure may further include a second insulating layer 108, which covers the top surface of the capacitor contact structure 105 and the sidewalls of the capacitor structure 106. The second insulating layer 108 can be used to isolate adjacent capacitor structures 106. Simultaneously, the second insulating layer 108 also covers the top surface of the capacitor contact structure 105, so that the surfaces of the capacitor contact structure 105 that are not in contact with the capacitor structure 106 are surrounded by the insulating layer 104 and the second insulating layer 108, thereby further preventing short circuits between adjacent capacitor contact structures 105.

[0083] In some embodiments, the width of the second insulating layer 108 covering the surface of the capacitor contact structure 105 is 1nm to 6nm, for example, it can be 1nm to 3nm or 3nm to 6nm, or it can be 1nm, 2nm, 3nm, 4nm, 5nm or 6nm, etc. The wider the width of the second insulating layer 108 covering the surface of the capacitor contact structure 105, the better the effect of the second insulating layer 108 in isolating adjacent capacitor contact structures 105. At the same time, if the width of the second insulating layer 108 covering the surface of the capacitor contact structure 105 is too wide, it means that the contact area between the capacitor contact structure 105 and the capacitor structure 106 is reduced, which affects the contact resistance between the capacitor structure 106 and the capacitor contact structure 105.

[0084] In some embodiments, the material of the second insulating layer 108 may include any one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a low dielectric constant material (such as carbon-doped silicon oxide, porous silicon oxide, etc.). The second insulating layer 108 may be formed by atomic layer deposition or chemical vapor deposition. The second insulating layer 108 formed by atomic layer deposition has better step coverage and film density, and can form a uniform second insulating layer in structures with high aspect ratios.

[0085] The second insulating layer 108 can also expose the top surface of the capacitor contact structure 105, and the second insulating layer 108 can also cover the top surface of the capacitor contact structure 105 but expose the top surface of the capacitor structure 106.

[0086] The top surface of the second insulating layer 108 can also be lower than the top surface of the capacitor structure 106, thereby facilitating the connection between the subsequent conductive structure and the capacitor structure.

[0087] The capacitor structure 106 may include: a lower electrode plate (not shown) electrically connected to the source / drain doped region 121; a capacitor dielectric layer (not shown) covering the surface of the lower electrode plate; and an upper electrode plate (not shown) covering the surface of the capacitor dielectric layer.

[0088] The material of the lower electrode plate may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer may include any one or any combination of ZrO, AlO, ZrNbO, ZrHfO, ZrAlO; the material of the upper electrode plate may include compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride or other conductive materials, or the material of the upper electrode plate may also be a conductive semiconductor material, such as polycrystalline silicon, germanium silicon, etc.

[0089] It is understandable that the relative area between the lower electrode plate and the upper electrode plate of the capacitor structure 106, the distance between the lower electrode plate and the upper electrode plate, and the material of the capacitor dielectric layer may all affect the capacitance of the capacitor structure 106. Therefore, the relative area between the lower electrode plate and the upper electrode plate, the distance between the lower electrode plate and the upper electrode plate, and the material of the capacitor dielectric layer of the capacitor structure 106 can be set according to actual needs.

[0090] In this embodiment of the present disclosure, the capacitor contact structure 105 is disposed within the insulating layer 104 located between adjacent bit line structures 103. Thus, the insulating layer 104 separates the bit line structures 103 while simultaneously separating the capacitor contact structures 105, thereby reducing the risk of short circuit between adjacent capacitor contact structures 105 during the formation of the capacitor contact structure 105, thereby improving the reliability of the semiconductor structure.

[0091] Another embodiment of this disclosure also provides a method for fabricating a semiconductor structure. This method can be used to form the above-mentioned semiconductor structure. The method for fabricating a semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the above embodiments can be referred to the above embodiments, and will not be repeated below.

[0092] refer to Figure 6 , Figure 6This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0093] In some embodiments, the method of fabricating a semiconductor structure may include: S10. providing a substrate and an active layer located on the substrate, the active layer including a channel region and source / drain doped regions located on both sides of the channel region.

[0094] The method for fabricating a semiconductor structure may also include: S11. forming a word line structure, wherein the word line structure is electrically connected to the channel region.

[0095] The method for fabricating a semiconductor structure may also include: S12. forming a bit line structure, wherein the bit line structure is electrically connected to the source / drain doped regions on one side of the channel region.

[0096] The method for fabricating a semiconductor structure may also include: S13. forming an insulating layer, wherein the insulating layer is located between adjacent bit line structures.

[0097] The method for fabricating a semiconductor structure may further include: S14. forming a capacitor contact structure, wherein the capacitor contact structure is located within an insulating layer and is electrically connected to the source / drain doped regions on the other side of the channel region.

[0098] The method for fabricating a semiconductor structure may also include: S15. forming a capacitor structure, wherein the capacitor structure is electrically connected to a capacitor contact structure.

[0099] In some embodiments, the method of forming a capacitor contact structure includes: forming an initial capacitor contact structure flush with an insulating layer; etching the initial capacitor contact structure so that the top surface of the initial capacitor contact structure is lower than the top surface of the insulating layer; and using the remaining initial capacitor contact structure as a capacitor contact structure.

[0100] During the etching of the initial capacitor contact structure, a reagent with a relatively high selectivity between etching the initial capacitor contact structure and etching the insulating layer can be selected for etching, thereby avoiding affecting the insulating layer during the etching of the initial capacitor contact structure.

[0101] In some embodiments, after forming the capacitor contact structure, a portion of the capacitor contact structure is etched to form a groove within the capacitor contact structure, providing a technological basis for subsequently increasing the contact area between the capacitor structure and the capacitor contact structure.

[0102] After etching the capacitor contact structure, inert gas purging can be used to remove the byproducts generated during etching, thus preventing the byproducts from affecting the reliability of the semiconductor structure.

[0103] This disclosure also provides an electronic device, which may include a semiconductor structure formed by the above-described semiconductor structure fabrication method, or the above-described semiconductor structure. It should be noted that the same or corresponding parts as those in the above embodiments can be referred to the above embodiments, and will not be repeated hereafter.

[0104] refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present disclosure.

[0105] The electronic device includes a processor 500 and a semiconductor structure 501. The semiconductor structure 501 is coupled to the processor 500, and the semiconductor structure 501 includes the semiconductor structure provided in any of the foregoing embodiments, or the semiconductor structure 501 formed by the manufacturing method of the semiconductor structure provided in any of the foregoing embodiments.

[0106] The processor 500 described above can refer to one or more processors. For example, a processor may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or neural network processor). When a processor includes multiple processors, these multiple processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0107] As illustrated, the processor 500 can be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0108] The processor 500 can integrate one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Electronic devices can include one or more of the following: for example, smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), MPEG 1 audio layer 3 (Moving Picture Experts Group Audio Layer III) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices can be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs). This electronic device can also be used in large servers, such as data centers or AI computers.

[0109] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, and an active layer on the substrate, the active layer including a channel region and source / drain doped regions on both sides of the channel region; A character line structure, wherein the character line structure is located on the channel region; Bit line structure, wherein the bit line structure is electrically connected to the source / drain doped region on one side of the channel region; An insulating layer is located between adjacent bit line structures; A capacitor contact structure is located within the insulating layer and is electrically connected to the source / drain doped region on the other side of the channel region. A capacitor structure, wherein the capacitor structure is electrically connected to the capacitor contact structure.

2. The semiconductor structure according to claim 1, characterized in that, The capacitor contact structure includes a first part and a second part that are connected to each other. The first part is connected to the active layer, and the second part is located on the side of the first part away from the active layer. The spacing between the second part and the bit line structure is smaller than the spacing between the first part and the bit line structure.

3. The semiconductor structure according to claim 2, characterized in that, The second part includes: The first sub-part, one end of which is connected to the first part; The second sub-part is connected to the other end of the first sub-part, and the second sub-part extends above the bit line structure.

4. The semiconductor structure according to claim 3, characterized in that, The extension direction of the first sub-part forms an angle with the extension direction of the first part.

5. The semiconductor structure according to claim 3 or 4, characterized in that, The angle between the extension direction of the first sub-part and the extension direction of the first part is 5°~10°.

6. The semiconductor structure according to claim 3, characterized in that, The orthographic projection of the second sub-part onto the substrate is elliptical or circular.

7. The semiconductor structure according to claim 3, characterized in that, The capacitor structure is also located within the second sub-section.

8. The semiconductor structure according to claim 7, characterized in that, The capacitor structure located in the second sub-section is stepped, hemispherical, or cylindrical.

9. The semiconductor structure according to claim 7, characterized in that, The thickness of the capacitor structure located in the second sub-section is 4nm~6nm.

10. The semiconductor structure according to claim 2, characterized in that, The capacitive contact structure further includes a transition portion, which is located between the first portion and the second portion.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: An adhesive layer is located between the capacitor contact structure and the capacitor structure.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: Bit line protection layer, which covers the surface of the bit line structure, and the bit line protection layer and the insulating layer are an integral structure.

13. The semiconductor structure according to claim 1, characterized in that, Also includes: A second insulating layer covers the top surface of the capacitor contact structure and the sidewalls of the capacitor structure.

14. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and an active layer is located on the substrate, the active layer including a channel region and source / drain doped regions located on both sides of the channel region; A word line structure is formed, wherein the word line structure is electrically connected to the channel region; A bit line structure is formed, wherein the bit line structure is electrically connected to the source / drain doped region on one side of the channel region; An insulating layer is formed between adjacent bit line structures; A capacitor contact structure is formed, which is located within the insulating layer and electrically connected to the source / drain doped region on the other side of the channel region. A capacitor structure is formed, and the capacitor structure is electrically connected to the capacitor contact structure.

15. An electronic device, characterized in that, It includes the semiconductor structure as described in any one of claims 1 to 13, or the semiconductor structure formed by the method of fabricating the semiconductor structure as described in claim 14.

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