Wafer edge structure adjustment method, semiconductor structure, and electronic device

Abstract

Embodiments of the present application provide a wafer edge structure adjustment method, a semiconductor structure and an electronic device; the wafer edge structure adjustment method comprises: before forming an etching hole of a capacitor structure, removing a photoresist layer in a first size range of a wafer edge by using a photoresist layer edge removal process to expose a first to-be-processed area of the wafer edge; simultaneously forming the etching hole, using the remaining photoresist layer as a mask, and performing a planarization treatment on the first to-be-processed area by using a dry etching process; after forming a first electrode of the capacitor structure, performing a planarization treatment on a second to-be-processed area by using a wafer edge chemical cleaning process; the second to-be-processed area is an area in a second size range of the wafer edge; the first size is greater than or equal to the second size.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a method for adjusting the edge structure of a wafer, a semiconductor structure, and an electronic device. Background Technology

[0002] In the semiconductor manufacturing process, defective dies (DIEs) typically exist in the wafer edge region. Although these DIEs do not contribute to the functionality of the final product, they are extremely unstable under actual process conditions such as high temperature and stress. As the manufacturing process continues, these unstable structures continuously peel off and fall onto the surface of normal dies, causing the normal dies to fail due to introduced defects, severely restricting the overall yield of the semiconductor structure. Therefore, it is urgent to effectively suppress structural peeling in the wafer edge region to prevent the diffusion of contaminants to the effective dies. Summary of the Invention

[0003] This application provides a method for adjusting the edge structure of a wafer, a semiconductor structure, and an electronic device.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a method for adjusting the edge structure of a wafer, the method comprising: Before forming the etched holes for the capacitor structure, a photoresist layer removal process is used to remove the photoresist layer within a first dimension range at the edge of the wafer, exposing the first area to be processed at the edge of the wafer. While forming the etched holes, the remaining photoresist layer is used as a mask to planarize the first area to be processed by a dry etching process. After forming the first electrode of the capacitor structure, a crystal edge chemical cleaning process is used to planarize the second region to be processed; the second region to be processed is the region within the second size range of the wafer edge; the first size is greater than or equal to the second size.

[0005] In some embodiments, the wafer includes a substrate and a stacked structure located on the surface of the substrate; a first region to be processed, exposing the edge of the wafer, includes: An initial mask layer and a photoresist layer are sequentially formed on the surface of the stacked structure; The photoresist layer is removed from the first-size region at the edge of the initial mask layer using a photoresist layer removal process.

[0006] In some embodiments, the substrate is provided with a plurality of vertically arranged transistors; the first area to be processed is planarized by a dry etching process, including: The remaining photoresist layer is exposed and developed to form a photoresist pattern; the photoresist pattern is a capacitor pattern. The photoresist pattern is transferred to the initial mask layer using a dry etching process to form a patterned mask layer; The exposed stacked structure is removed using the patterned mask layer as a mask, and the etching holes corresponding to the sources of each vertical transistor are formed while the first area to be processed is planarized.

[0007] In some embodiments, the stacked structure includes alternately stacked support layers and sacrificial layers; the second region to be treated is planarized using a crystal edge chemical cleaning process, including: After the first electrode is formed on the surface exposed by the etched hole, the sacrificial layer is removed; A crystal edge chemical cleaning process is used to remove the first electrode and the support layer in the second area to be treated, so as to perform planarization treatment on the second area to be treated.

[0008] In some embodiments, the first dimension ranges from 0 mm to 3.4 mm, and the second dimension ranges from 0 mm to 3.2 mm.

[0009] In some embodiments, the first dimension is 1.5 mm and the second dimension is 1.5 mm; or, the first dimension is 3.4 mm and the second dimension is 3.2 mm.

[0010] In some embodiments, a third-size region from the wafer edge is an invalid chip region, the third size being smaller than the sum of the first size and the second size.

[0011] In some embodiments, the substrate is formed by the following steps: Provide substrate; On the surface of the substrate, a plurality of vertical transistors are formed in an array arranged along a first direction and a second direction and extending in a vertical direction; Wherein, the first direction and the second direction are two intersecting directions on the plane where the substrate is located, and the vertical direction is perpendicular to the plane where the substrate is located.

[0012] In some embodiments, the method further includes: On the remaining exposed surface of the first electrode, a dielectric layer and a second electrode are sequentially formed; the first electrode, the dielectric layer, and the second electrode constitute the capacitor structure; and, The substrate is etched from one side of the substrate until the drain of the vertical transistor is exposed; a plurality of bit line structures are formed that are spaced apart along the first direction and extend along the second direction; each bit line structure contacts the drain of the plurality of vertical transistors arranged along the second direction.

[0013] In a second aspect, embodiments of this application provide a semiconductor structure manufactured using the wafer edge structure adjustment method described in any of the above embodiments, the semiconductor structure comprising: The substrate includes a first region and a second region surrounding the periphery of the first region; the second region is a region within a second dimension from the edge of the substrate; the first region is provided with a plurality of vertically arranged transistors. A first electrode that corresponds to the source of each of the vertical transistors and extends in the vertical direction; Multiple support layers are disposed between adjacent first electrodes and spaced apart along the vertical direction; At least a dielectric layer and a second electrode are sequentially located on the surface of the first electrode; the first electrode, the dielectric layer, and the second electrode constitute a capacitor structure. The vertical direction is perpendicular to the plane in which the semiconductor structure is located.

[0014] In some embodiments, the semiconductor structure further includes: A plurality of bit line structures are spaced apart along a first direction and extend along a second direction; each of the bit line structures contacts the drain of a plurality of vertical transistors arranged along the second direction. The first direction and the second direction are two intersecting directions on the plane where the semiconductor structure is located.

[0015] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor structure made by the wafer edge structure adjustment method as described in the above embodiments, or a semiconductor structure as described in the above embodiments.

[0016] This application provides a method for adjusting the wafer edge structure, a semiconductor structure, and an electronic device. The method for adjusting the wafer edge structure includes: before forming the etching hole of the capacitor structure, removing the photoresist layer within a first dimension range of the wafer edge using a photoresist layer removal process to expose a first region to be processed at the wafer edge; simultaneously forming the etching hole, using the remaining photoresist layer as a mask, planarizing the first region to be processed using a dry etching process; after forming the first electrode of the capacitor structure, planarizing a second region to be processed using a wafer edge chemical cleaning process; the second region to be processed is a region within a second dimension range of the wafer edge; the first dimension is greater than or equal to the second dimension.

[0017] Here, before etching the holes in the capacitor structure, a photoresist edge removal process is used to simultaneously eliminate irregular patterns caused by light leakage in the previous layer (such as silicon nitride layer) during the formation of the etching holes. Furthermore, during the formation of the capacitor structure, a crystal edge chemical cleaning process is used to remove columnar unstable structures generated at the wafer edge, thereby significantly reducing the risk of film peeling. Compared to a single etching process, the combined process in this application can reduce the number of defects in the capacitor structure by at least 36%, thereby ensuring the manufacturing yield and long-term reliability of the semiconductor structure. Attached Figure Description

[0018] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0019] Figure 1 A schematic flowchart illustrating the wafer edge structure adjustment method provided in this application embodiment; Figure 2 A schematic diagram of an irregular structure of the wafer edge structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of another irregular structure of the wafer edge structure provided in the embodiments of this application; Figure 4 A schematic diagram of yet another irregular structure of the wafer edge structure provided in an embodiment of this application; Figure 5 A schematic diagram of the substrate provided in the embodiments of this application; Figure 6 This is a schematic diagram of the stacked structure provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the initial mask layer and photoresist layer provided in the embodiments of this application; Figure 8 This is a schematic diagram of the etched hole structure provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of the first electrode provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a wafer edge region provided in an embodiment of this application; Figure 11 This is a schematic diagram of another wafer edge region structure provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the wafer edge region after planarization treatment provided in an embodiment of this application; Figure 13 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application; Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0021] In the following description, numerous details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0023] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] Currently, in the fabrication of front-end structures such as silicon nitride layers in Dynamic Random Access Memory (DRAM), due to uncontrollable etching rates and light leakage effects in the exposed areas, irregular lotus leaf-shaped patterns easily form at approximately 0.5 mm to 1.1 mm from the wafer edge. These patterns cannot be completely removed during the subsequent formation of the corresponding etched holes for capacitor structures due to differences in etching rates, becoming a potential source of defects that persists into later processes, thus forming irregular capacitor structures at 1.1 mm. For example, when using SNT (Silicon Nitride / Titanium Nitride) wafer edge exposure (WEE) technology, the removal rate of front-end silicon nitride pattern residues is low, making complete removal impossible.

[0027] Furthermore, due to the light leakage effect in the exposed area at the wafer edge, uncontrollable irregular void structures can be generated at approximately 3.1 mm from the wafer edge during the formation of the capacitor structure. For example, a titanium nitride columnar structure may form at the wafer edge, resulting in poor wafer edge stability. If this irregular void structure is not effectively removed, it will continue to peel off into the normal grain area in subsequent processes due to temperature, stress, and other factors. This will cause the normal grains to fail due to the introduction of defects, severely restricting product yield and long-term reliability.

[0028] Furthermore, irregular lotus leaf-shaped patterns (such as silicon nitride and silicon oxide byproducts) and irregular hollow structures (such as titanium nitride) are difficult to completely remove simultaneously using a single dry process or a single wet etching process. Traditional removal methods require additional etching steps, making the process complex and costly, thus limiting their effectiveness in treating these defects. Therefore, there is an urgent need for a comprehensive process method that can address complex pattern residues caused by front-layer light leakage, etching rate differences, and unstable crystal edge structures, in order to completely eliminate the source of defects and improve the manufacturing yield and product reliability of back-end structures (such as capacitor structures).

[0029] Based on this, embodiments of this application provide a method for adjusting the wafer edge structure, a semiconductor structure, and an electronic device; below, the method for adjusting the wafer edge structure, the semiconductor structure, and the electronic device in the embodiments of this application will be described in detail with reference to the accompanying drawings.

[0030] Before introducing the embodiments of this application, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. The three directions may include the X-axis (first), Y-axis (second), and Z-axis (vertical) directions. The Z-axis direction can be a direction perpendicular to the plane where the substrate (or semiconductor structure) is located; the X-axis and Y-axis directions are two intersecting directions on the plane where the substrate (or semiconductor structure) is located, wherein the Y-axis direction can be the direction in which the bit line structure extends.

[0031] This application provides a method for adjusting the edge structure of a wafer. Figure 1 This is a flowchart illustrating the wafer edge structure adjustment method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method for adjusting the wafer edge structure includes the following steps: In step S110, before forming the etched hole of the capacitor structure, the photoresist layer within the first size range of the wafer edge is removed by a photoresist layer removal process to expose the first area to be processed at the wafer edge.

[0032] In this embodiment, the photoresist edge removal process is also called the photoresist edge removal (EBR) process, which is used to precisely remove excess photoresist from the wafer edge after photoresist spin coating and before formal exposure. The photoresist edge removal process can be performed using any suitable method, such as chemical methods (e.g., chemical solvent dissolution) or optical methods (e.g., edge exposure + development).

[0033] Here, a photoresist layer removal process is used to remove the photoresist layer within the first dimension range of the wafer edge. On the one hand, this removes the uneven, raised "edge beads" formed by the centrifugal force that are thrown towards the wafer edge during the photoresist spin coating process, preventing the photoresist edge from peeling off and causing contamination in subsequent processes, while also improving the alignment accuracy of subsequent photolithography. On the other hand, it exposes the first area to be processed below (i.e., the area where the lotus leaf-shaped residue is located), preparing for subsequent dry etching.

[0034] In this embodiment, the first region to be processed refers to the area extending inward from the outermost edge of the wafer, defined by a first dimension. During the previous layer process, a process is performed in the first region to be processed. Figure 2 The irregular lotus leaf-shaped pattern residues (such as silicon nitride and silicon oxide byproduct residues at 0.5 mm to 1.1 mm) expose the first area to be processed, which can be etched in a subsequent step (i.e., step S120) without damaging the area covered by photoresist.

[0035] In step S120, while forming the etched hole, the remaining photoresist layer is used as a mask to planarize the first area to be processed by a dry etching process.

[0036] In this embodiment, the dry etching process can be, for example, plasma etching, reactive ion etching, or ion milling. Here, by adjusting the gas composition during dry etching (e.g., CHF3+Ar, Cl2 / HBr / O2), extremely high etching selectivity can be achieved for different materials, enabling precise removal of the target material. Simultaneously, utilizing the anisotropic nature of dry etching, the perpendicularity of the sidewalls after etching can be guaranteed. Based on these advantages, this process is particularly suitable for the selective removal of silicon nitride and silicon oxide in the front-layer structure, with minimal damage to the underlying silicon layer.

[0037] Step S130: After forming the first electrode of the capacitor structure, the second area to be processed is planarized using a crystal edge chemical cleaning process; the second area to be processed is the area within the second size range of the wafer edge; the first size is greater than or equal to the second size.

[0038] In this embodiment, the chemical cleaning process for the crystal edge adopts a wet cleaning process. The solution for the wet cleaning process can be selected according to the material properties of the residue on the surface of the second area to be treated. For example, for metal / metal nitrides (such as titanium nitride for the first electrode), SPM (a mixture of sulfuric acid and hydrogen peroxide) or SC-1 (a mixture of ammonia and hydrogen peroxide) is preferred. Its strong oxidizing properties are used to dissolve and remove the metallic residue. This chemical reaction process is not only highly selective and causes little damage, but also has low equipment cost and process complexity, making it suitable as the final step in crystal edge cleaning.

[0039] Here, after the first electrode of the capacitor structure is formed, the second region to be processed will form as shown in the figure. Figure 3 As shown and Figure 4 The irregular hollowed-out structure shown (such as needle-shaped titanium nitride at 1.1 mm) allows the second area to be treated to be processed through a crystal edge chemical cleaning process, ensuring a smooth wafer edge profile and thus significantly reducing the risk of defects caused by edge residue peeling off in subsequent processes.

[0040] It should be noted that the first and second processing areas are set based on the actual location of the defect, and this application does not limit this. For example, if the irregular hollow structure is mainly located at 1.1 mm from the wafer edge, then the second processing area can be an area that starts from the outermost edge of the wafer and extends inward at least to a width defined by 1.1 mm (i.e., the second dimension).

[0041] Furthermore, the first dimension is greater than or equal to the second dimension, so that the area covered by the edge chemical cleaning process is smaller than the area processed by the dry etching process; thus, the wet cleaning coverage is smaller, which can reduce the damage to the effective device area during wet cleaning.

[0042] This application fully considers the removal characteristics of different material systems in its process selection to adjust the wafer edge structure. Specifically, dry etching (especially plasma etching) processes have high anisotropy and excellent pattern fidelity, making them suitable for precise morphology shaping of dielectric materials (such as silicon nitride). Wet cleaning processes are essentially chemical reactions, exhibiting high selectivity for metals / metal compounds. Furthermore, their isotropic action allows for gentle leveling and cleaning of edge micro-protrusions and chemically damaged layers, with extremely low risk of physical damage. Compared to using a single dry process or a single wet cleaning process, this application is advantageous in improving the cleaning effect at wafer edges.

[0043] In summary, by employing a photoresist edge removal process before etching the holes in the capacitor structure, irregular patterns caused by light leakage in the previous layer (such as the silicon nitride layer) can be eliminated simultaneously during the formation of the etching holes. Furthermore, during the formation of the capacitor structure, the use of a wafer edge chemical cleaning process can remove the columnar unstable structures generated at the wafer edge, thereby significantly reducing the risk of film peeling. Compared to a single etching process, the combined process in this application can reduce the number of defects in the capacitor structure by at least 36%, thereby ensuring the manufacturing yield and long-term reliability of the semiconductor structure.

[0044] Next, we will explain in detail the method for adjusting the wafer edge structure. Figures 5 to 13 This is a schematic diagram of the structure in the wafer edge structure adjustment method provided in the embodiments of this application.

[0045] In some embodiments, step S110 is performed, whereby, before forming the etched hole 120a of the capacitor structure, a photoresist layer 132 edge removal process is used to remove the photoresist layer 132 within a first dimension range at the edge of the wafer 100, exposing the first unprocessed area A at the edge of the wafer 100 (the location can be referenced). Figure 10 ).

[0046] In some embodiments, prior to performing step S110, the following is provided: Figure 6 The wafer 100 shown includes a substrate 110 and a stacked structure 120 located on the surface of the substrate 110.

[0047] It should be noted that, Figures 5 to 9 The first processing region A and the second processing region B at the edge of wafer 100 are not shown in the diagram. The locations of the first processing region A and the second processing region B can be found in [reference needed]. Figures 10 to 12 To understand.

[0048] First, a substrate 110 is provided. The substrate 110 is formed by the following steps: steps S11 and S12.

[0049] Step S11, provide as follows Figure 5 The substrate 111 shown.

[0050] Here, the substrate 111 can be a silicon substrate, or it can include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), etc.

[0051] Step S12, on the surface of substrate 111, form as shown in the figure. Figure 5 The diagram shows multiple vertical transistors 112 arranged in an array along the X-axis and Y-axis directions and extending along the Z-axis direction.

[0052] In this embodiment, the vertical transistor 112 includes an active pillar 112a and a gate structure 112b. The gate structure 112b can control the conductivity of the channel in the active pillar 112a, thereby allowing current to flow between the source, channel, and drain of the active pillar 112a based on the gate structure 112b. Further, the gate structure 112b includes a gate dielectric layer 1121b and a gate metal layer 1122b, with multiple gate metal layers 1122b arranged along the X-axis direction interconnected to form word lines.

[0053] In this embodiment, the material of the gate dielectric layer 1121b can be silicon oxide or other suitable materials; the material of the gate metal layer 1122b can be any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0054] The deposition processes involved in the embodiments of this application include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0055] Please refer to the embodiments in this application. Figure 5 Since multiple vertical transistors 112 are arrayed along the X-axis and Y-axis directions and extend along the Z-axis direction, on the one hand, the size of the memory cell can be reduced and the storage density of the memory cell can be increased; on the other hand, the height of the channel region in the vertical transistor 112 can be increased to maintain the effective length without increasing the semiconductor structure area, thereby avoiding the short-channel effect.

[0056] In this embodiment of the application, after step S12, providing the substrate 110 may further include: forming, on the top surface of each vertical transistor 112, a... Figure 5 The capacitor contact structure 113 shown; and, a structure such as is formed between the vertical transistor 112 and the capacitor contact structure 113. Figure 5 The isolation structure 114 is shown.

[0057] In this embodiment, the material of the capacitor contact structure 113 can be a metal silicide. Since metal silicides have low resistance, the contact resistance with the vertical transistor 112 can be reduced. The material of the isolation structure 114 can be any suitable material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] In the embodiments of this application, when forming such Figure 5 When using substrate 110 as shown, light intensity uniformity in the edge region (such as light leakage or inaccurate focusing) can easily cause issues on the surface of substrate 110, such as... Figure 2 Irregular pattern residues (such as residues from etching isolation structure 114) can easily become potential sources of defects that continue into subsequent processes.

[0059] Next, on the surface of the substrate 110, a structure is formed as shown below. Figure 6 The stacked structure 120 shown.

[0060] In this embodiment of the application, the stacked structure 120 includes, as follows: Figure 6 The support layer 121 and sacrificial layer 122 are stacked alternately from bottom to top. Here, the higher the stacking structure 120 is, the larger the storage capacity of the capacitor structure formed subsequently. The height (i.e., the dimension along the Z-axis) and number of layers of the support layer 121 and sacrificial layer 122 can be set according to actual needs, and this application does not limit them.

[0061] In this embodiment, the material of the support layer 121 can be silicon nitride or silicon carbide nitride; in addition, the materials of the support layer 121 and the isolation structure 114 are different. The material of the sacrificial layer 122 can be silicon oxide, phosphoro silicate glass (PSG), or borophospho silicate glass (BPSG).

[0062] In some embodiments, step S110 includes steps S111 and S112.

[0063] Step S111, sequentially forming the following on the surface of the stacked structure 120 Figure 7 The initial mask layer 131a and photoresist layer 132 are shown.

[0064] In this embodiment, the material of the initial mask layer 131a can be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0065] Step S112: The photoresist layer 132 is removed from the first size area at the edge of the initial mask layer 131a using the photoresist layer 132 edge removal process.

[0066] In this embodiment, the minimum value of the first size is determined based on the following two aspects: First, during the spin coating process of photoresist, an uneven, raised "edge bead" is formed by being thrown towards the edge of the wafer by centrifugal force. If the first size is too small, it cannot completely cover these areas, resulting in uneven edges of the photoresist layer or a risk of contamination. Second, irregular residual patterns at the edges of previous processes are usually caused by the uniformity of light intensity in the edge area (such as light leakage or inaccurate focusing). Therefore, if the first size is too small, it cannot completely remove the irregular residual patterns left by previous processes. In other words, the minimum value of the first size is sufficient to remove the above defects. Furthermore, the maximum value of the first size is determined based on the following two aspects: First, the portion removed from the wafer edge cannot be used to manufacture any devices. If the first size is too large (e.g., greater than 3.4 mm), the effective device area in the wafer will be lost, resulting in a loss of yield. Second, the maximum size of the photoresist layer edge removal process that the equipment can perform is determined.

[0067] Therefore, the first dimension ranges from 0 mm to 3.4 mm; the first dimension can be 0.5 mm, 1.0 mm, 1.5 mm, 2.0 mm, 3.0 mm, 3.4 mm, or any two of these values; it can be selected based on the location of the defect. This not only removes uneven areas at the edges of the photoresist layer, preventing the photoresist edges from peeling off and causing contamination in subsequent processes, thus improving the alignment accuracy of subsequent photolithography, but also exposes the areas containing irregular residual patterns left by the preceding processes, preparing for subsequent dry etching. Simultaneously, it preserves as much effective area as possible.

[0068] In this embodiment, the photoresist layer within the first size region is removed to expose the area above the first region to be processed, A (the location can be referenced). Figure 10 (To understand).

[0069] In some embodiments, step S120 is performed, in which, while forming the etched hole 120a, the remaining photoresist layer 132 is used as a mask to planarize the first area to be processed A by a dry etching process.

[0070] In some embodiments, step S120 includes steps S121 and S123.

[0071] Step S121: Expose and develop the remaining photoresist layer 132 to form a layer as shown in the figure. Figure 8 The photoresist pattern F shown is a capacitor pattern.

[0072] It should be noted that at this time, the photoresist layer 132 also exposes the area within the first dimension of the edge of the initial mask layer 131a, and the edge of the initial mask layer 131a can be etched simultaneously in the subsequent step S122.

[0073] Step S122: The photoresist pattern F is transferred to the initial mask layer 131a using a dry etching process to form a pattern as shown in Figure 122. Figure 8 The patterned mask layer 131 shown.

[0074] Step S123: Using a patterned mask layer as a mask, remove the exposed stacked structure 120 to form a structure as shown in the figure. Figure 8 While etching holes 120a corresponding to the source of each vertical transistor 112 (i.e., capacitor contact structure 113), the first region A to be processed is planarized.

[0075] In this embodiment, by adjusting the gas composition (such as CHF3+Ar, Cl2 / HBr / O2) during dry etching, an extremely high etching selectivity can be achieved for different materials, enabling precise removal of the target material. Simultaneously, utilizing the anisotropic nature of dry etching, the perpendicularity of the sidewalls after etching can be guaranteed. Based on these advantages, this process is particularly suitable for the selective removal of silicon nitride and silicon oxide in the front-layer structure, with minimal damage to the underlying silicon layer. Subsequently, the mask layer 131 and photoresist layer 132 can be removed.

[0076] In this embodiment of the application, after forming the etched hole 120a, a surface exposed by the etched hole 120a is formed as shown in the figure. Figure 9 The first electrode 141 is shown. The support layer 121 and the sacrificial layer 122 are used to support the first electrode 141 during its formation, prevent the first electrode 141 from collapsing, and improve the stability of the formed semiconductor structure.

[0077] In some embodiments, step S130 is performed after forming the first electrode 141 of the capacitor structure, using a crystal edge chemical cleaning process to clean the surface. Figure 10 or Figure 11 The second area B to be processed, as shown, is flattened to form a shape like... Figure 12 The structure shown; the second region to be processed, B, is the region within the second dimension range of the edge of wafer 100; the first dimension is greater than or equal to the second dimension.

[0078] It should be noted that, Figures 10 to 12 This is only used to describe the edge region of the wafer, therefore detailed diagrams of the various structures within the wafer are not shown.

[0079] In some embodiments, step S130 includes steps S131 and S123.

[0080] Step S131: After forming the first electrode 141 on the surface exposed by the etched hole 120a, remove as... Figure 8 The sacrificial layer 122 shown forms as follows Figure 9 The structure shown.

[0081] Step S132: Using a crystal edge chemical cleaning process, the first electrode 141 and the support layer 121 in the second region to be treated B are removed to perform planarization treatment on the second region to be treated B.

[0082] In this embodiment, due to the light leakage effect in the exposed area at the wafer edge, after the formation of the first electrode 141, an uncontrollable irregular columnar hollow structure is triggered in the second area to be processed, resulting in poor wafer edge stability. This columnar hollow structure appears at the edge of the wafer 100 (e.g., ...). Figure 11 As shown), it can also appear near the inner edge of wafer 100 (e.g. Figure 10 (As shown in the image). Here, to ensure complete coverage of byproducts remaining at the wafer edge after dry etching during the edge chemical cleaning process, and to completely cover the irregular columnar hollow structure, the value range of the second dimension should not be too small. Furthermore, the portion removed from the wafer edge cannot be used to manufacture any devices. If the second dimension is too large (e.g., greater than 3.4 mm), the effective device area in the wafer will be lost, leading to a loss of yield.

[0083] Therefore, the value range of the second dimension is (0 mm, 3.2 mm); the value of the second dimension can be 0.5 mm, 1.0 mm, 1.5 mm, 2.0 mm, 3.0 mm, 3.2 mm, or any two of these values ​​within a range; specifically, it can be selected according to the location of the defect. In this way, by treating the second area to be processed through the edge chemical cleaning process, the wafer edge contour is ensured to be smooth, thereby significantly reducing the risk of defects caused by the peeling off of edge residues in subsequent processes.

[0084] In some embodiments, the first dimension may be 1.5 mm and the second dimension may be 1.5 mm.

[0085] Specifically, due to light leakage at 1.1 mm in the wafer edge exposure step (step S120), irregular titanium nitride patterns (first electrode) remain at this location; at the same time, due to the slow etching process rate at the edge, the lotus leaf-shaped silicon nitride layer (isolation structure) at the edge of the substrate 110 cannot be completely removed, thus affecting the product yield.

[0086] To address the aforementioned issues, firstly, in step S110, a photoresist removal process is used to remove the photoresist within 0-1.5 mm (i.e., the first dimension is 1.5 mm) of the wafer edge. This allows step S120 to effectively target the exposed area and thoroughly remove any residual silicon nitride layer within 1.5 mm. Next, in step S130, an edge chemical cleaning process is used to remove irregular titanium nitride patterns within 0-1.5 mm (i.e., the second dimension is 1.5 mm) of the wafer edge. This significantly reduces the defect rate in the subsequent interconnect processes, with an overall defect reduction of up to 36%.

[0087] In some embodiments, the first dimension may be 3.4 mm and the second dimension may be 3.2 mm.

[0088] Specifically, due to light leakage at 3.1 mm in the wafer edge exposure step (step S120), irregular titanium nitride patterns (first electrode) remain at this location; at the same time, due to the slow etching process rate at the edge, the lotus leaf-shaped silicon nitride layer (isolation structure) at the edge of the substrate 110 cannot be completely removed, thus affecting the product yield.

[0089] To address the aforementioned issues, firstly, in step S110, a photoresist removal process is used to remove the photoresist within 0-3.4 mm (i.e., the first dimension is 3.4 mm) of the wafer edge. This allows step S120 to effectively target the exposed area and thoroughly remove any residual silicon nitride layer within the 3.4 mm region. Next, in step S130, an edge chemical cleaning process is used to remove irregular titanium nitride patterns within 0-3.2 mm (i.e., the second dimension is 3.2 mm) of the wafer edge. Thus, after this treatment, the defect rate in the subsequent interconnect process is significantly reduced, with an overall defect reduction of 43%.

[0090] In this embodiment, the first dimension is greater than or equal to the second dimension, so that the area covered by the edge chemical cleaning process is smaller than the area processed by the dry etching process; thus, the wet cleaning coverage is smaller, which can reduce the damage to the effective device area during wet cleaning.

[0091] In some other embodiments, the first dimension may also be smaller than the second dimension; for example, when the lotus leaf-shaped silicon nitride layer at the edge of the substrate 110 is located at 3.2 mm and the irregular titanium nitride pattern is located at 3.4 mm, the first dimension is 3.2 mm and the second dimension is 3.4 mm; that is, the area covered by the edge chemical cleaning process is not smaller than the area processed by the dry etching process; in this way, since the wet cleaning has a wider coverage, it can ensure that the interface transition zone that may exist after dry etching is completely removed, leaving no processing blind spots.

[0092] In some embodiments, a region of a third dimension from the edge of wafer 100 is an invalid chip region, and the third dimension is smaller than the sum of the first and second dimensions.

[0093] Specifically, the third dimension can be determined based on the width of the invalid chip region in the actual wafer 100 fabrication; for example, the width of the invalid chip region (i.e. the third dimension) in a 12-inch wafer is typically between 2 mm and 5 mm, and exemplarily, the third dimension can be 3 mm, 5 mm, etc.

[0094] Since the unstable edge structure mentioned above peels off into the effective chip area (i.e., normal die), it will significantly reduce the yield of the effective chip area; therefore, the unstable edge structure can be removed first based on the above method. This may result in the loss of the effective chip area at the edge, but it can increase the yield of the overall structure.

[0095] In some embodiments, after removing the sacrificial layer 122, as... Figure 9 The remaining exposed surface of the first electrode 141, as shown, is sequentially covered by a dielectric layer (not shown) and a second electrode (not shown); the first electrode 141, the dielectric layer, and the second electrode constitute as shown in the figure. Figure 13 The capacitor structure 140 shown; and the substrate 111 is etched from one side of the substrate 111 until the drain of the vertical transistor 112 is exposed (located in...). Figure 13 (shown as the lower end along the Z-axis); forming multiple bit line structures 150 spaced apart along the X-axis and extending along the Y-axis; each bit line structure contacts the drain of multiple vertical transistors 112 arranged along the Y-axis.

[0096] In this embodiment, the materials of the first and second electrodes may include metal nitrides or metal silicides, such as titanium nitride. The material of the dielectric layer may include a high-k dielectric material, such as one or any combination of lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (Hf silicon oxide), or zirconium oxide (ZrO2).

[0097] In the embodiments of this application, the materials of the bit line structure include: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, or any combination thereof.

[0098] It should be noted that the wafer needs to be cut to form a semiconductor structure 200; here, the semiconductor structure 200 can be a circuit structure such as a chip.

[0099] In addition, this application embodiment also provides a semiconductor structure formed based on the above-described wafer edge structure adjustment method. Please refer to [link / reference]. Figure 13The semiconductor structure 200 includes: a substrate 110, including a plurality of vertical transistors 112 arranged in an array; and a first electrode 141 corresponding to the source of each vertical transistor 112 and extending along the Z-axis direction (the specific location can be found in the reference). Figure 9 Multiple support layers 121 are disposed between adjacent first electrodes 141 and spaced apart along the Z-axis; a dielectric layer and a second electrode are sequentially located on the exposed surface of the first electrode 141; the first electrode 141, the dielectric layer and the second electrode constitute a capacitor structure 140.

[0100] In the embodiments of this application, please refer to Figure 13 Multiple vertical transistors 112 are arranged in an array along the X-axis and Y-axis directions and extend along the Z-axis direction; wherein, the vertical transistor 112 includes an active pillar 112a and a gate structure 112b; the gate structure 112b includes a gate dielectric layer 1121b and a gate metal layer 1122b, and the multiple gate metal layers 1122b arranged along the X-axis direction are interconnected to form word lines.

[0101] In the embodiments of this application, please refer to Figure 13 The semiconductor structure 200 also includes: a capacitive contact structure 113 located at the source of the corresponding vertical transistor 112; and an isolation structure 114 located between the vertical transistor 112 and the capacitive contact structure 113.

[0102] In some embodiments, please refer to Figure 13 The semiconductor structure 200 also includes a plurality of bit line structures 150 spaced apart along the X-axis and extending along the Y-axis; each bit line structure is in contact with the drain of a plurality of vertical transistors 112 arranged along the Y-axis.

[0103] The semiconductor structure 200 provided in this application embodiment is formed by the wafer edge structure adjustment method provided in the above embodiment. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiment for understanding. Here, they will not be repeated.

[0104] This application also provides an electronic device. Figure 14 This is a schematic diagram of the structure of an electronic device 300 provided in an embodiment of this application, as shown below. Figure 14 As shown, the electronic device 300 includes any of the semiconductor structures 200 in the above embodiments.

[0105] It should be noted that for electronic devices, this can be such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDRSDRAM), etc., and no specific limitation is made here.

[0106] Furthermore, in some embodiments, the electronic device may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6; no specific limitation is made here.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0108] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0109] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A method for adjusting the edge structure of a wafer, characterized in that, The method includes: Before forming the etched holes for the capacitor structure, a photoresist layer removal process is used to remove the photoresist layer within a first dimension range at the edge of the wafer, exposing the first area to be processed at the edge of the wafer. While forming the etched holes, the remaining photoresist layer is used as a mask to planarize the first area to be processed by a dry etching process. After forming the first electrode of the capacitor structure, a crystal edge chemical cleaning process is used to planarize the second region to be processed; the second region to be processed is the region within the second size range of the wafer edge; the first size is greater than or equal to the second size.

2. The method according to claim 1, characterized in that, The wafer includes a substrate and a stacked structure located on the surface of the substrate; The first region to be processed, exposing the edge of the wafer, includes: An initial mask layer and a photoresist layer are sequentially formed on the surface of the stacked structure; The photoresist layer is removed from the first-size region at the edge of the initial mask layer using a photoresist layer removal process.

3. The method according to claim 2, characterized in that, The substrate is provided with multiple vertically arranged transistors; The first area to be processed is planarized using a dry etching process, including: The remaining photoresist layer is exposed and developed to form a photoresist pattern; the photoresist pattern is a capacitor pattern. The photoresist pattern is transferred to the initial mask layer using a dry etching process to form a patterned mask layer; The exposed stacked structure is removed using the patterned mask layer as a mask, and the etching holes corresponding to the sources of each vertical transistor are formed while the first area to be processed is planarized.

4. The method according to claim 3, characterized in that, The stacked structure includes alternately stacked support layers and sacrificial layers; The second area to be treated is planarized using a crystal edge chemical cleaning process, including: After the first electrode is formed on the surface exposed by the etched hole, the sacrificial layer is removed; A crystal edge chemical cleaning process is used to remove the first electrode and the support layer in the second area to be treated, so as to perform planarization treatment on the second area to be treated.

5. The method according to claim 1, characterized in that, The first dimension has a range of (0 mm, 3.4 mm), and the second dimension has a range of (0 mm, 3.2 mm).

6. The method according to claim 5, characterized in that, The first dimension is 1.5 mm and the second dimension is 1.5 mm; or, the first dimension is 3.4 mm and the second dimension is 3.2 mm.

7. The method according to claim 1, characterized in that, The third dimension region at the edge of the wafer is an invalid chip region, where the third dimension is smaller than the sum of the first dimension and the second dimension.

8. The method according to claim 4, characterized in that, The substrate is formed by the following steps: Provide substrate; On the surface of the substrate, a plurality of vertical transistors are formed in an array arranged along a first direction and a second direction and extending in a vertical direction; Wherein, the first direction and the second direction are two intersecting directions on the plane where the substrate is located, and the vertical direction is perpendicular to the plane where the substrate is located.

9. The method according to claim 8, characterized in that, The method further includes: On the remaining exposed surface of the first electrode, a dielectric layer and a second electrode are sequentially formed; the first electrode, the dielectric layer, and the second electrode constitute the capacitor structure; and, The substrate is etched from one side of the substrate until the drain of the vertical transistor is exposed; a plurality of bit line structures are formed that are spaced apart along the first direction and extend along the second direction; each bit line structure contacts the drain of the plurality of vertical transistors arranged along the second direction.

10. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the wafer edge structure adjustment method according to any one of claims 1 to 9, comprising: The substrate includes multiple vertically arranged transistors; A first electrode that corresponds to the source of each of the vertical transistors and extends in the vertical direction; Multiple support layers are disposed between adjacent first electrodes and spaced apart along the vertical direction; At least a dielectric layer and a second electrode are sequentially located on the surface of the first electrode; the first electrode, the dielectric layer, and the second electrode constitute a capacitor structure. The vertical direction is perpendicular to the plane in which the semiconductor structure is located.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A plurality of bit line structures are spaced apart along a first direction and extend along a second direction; each of the bit line structures contacts the drain of a plurality of vertical transistors arranged along the second direction. The first direction and the second direction are two intersecting directions on the plane where the semiconductor structure is located.

12. An electronic device, characterized in that, include: The semiconductor structure made by the wafer edge structure adjustment method as described in any one of claims 1 to 9, or the semiconductor structure as described in claim 10 or 11.

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