Contact pads and methods of making the same

Abstract

The application provides a contact pad and a preparation method thereof, and belongs to the field of semiconductors. The preparation method of the contact pad comprises the following steps: performing back etching on a silicon column to form a groove; performing etching on a silicon oxide layer to expose the sidewall of a part of the height of a silicon liner layer, and form a sidewall groove; forming a metal silicide, which fills the sidewall groove and covers the surface of the silicon column and the silicon liner layer; forming a barrier layer in the groove and filling metal to form a contact pad. The application forms a 3D structure by forming a groove and a sidewall groove, and the metal silicide covers the 3D structure, so that the contact area of the contact pad and the drain can be increased, the resistance can be reduced, and the groove is self-aligned with the silicon column. After the contact pad is formed by filling metal, the contact pad can be prevented from being connected to the drain of an adjacent unit transistor, so that the leakage can be avoided, and the performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a contact pad and its preparation method. Background Technology

[0002] 4F2 DRAM is a high-density dynamic random access memory. During DRAM fabrication, the source, channel, and drain are formed vertically within silicon pillars, and a landing pad (LP) is placed above the drain to electrically connect the capacitor to the drain. A larger contact area of ​​the landing pad results in lower contact resistance. However, existing landing pads suffer from small size and high resistance, which degrades the sensing margin. Furthermore, during landing pad formation, misalignment during photolithography can cause leakage between vertical transistors in adjacent cells, leading to leakage problems between adjacent cells.

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a contact pad and its preparation method to solve the problems of high resistance in contact pads and potential leakage between adjacent vertical transistors.

[0005] To solve the above technical problems, the present invention provides a method for preparing contact pads, comprising:

[0006] A substrate is provided, wherein a plurality of silicon pillars are formed on the surface of the substrate, an isolation structure is provided between adjacent silicon pillars, the top of the silicon pillars is exposed and a drain region is provided, and a silicon pad layer and a silicon oxide layer are formed sequentially along the transverse direction on the sidewall of the top of the silicon pillars.

[0007] The silicon pillar is etched back along its height direction, simultaneously reducing the height of the silicon pad layer to form a trench;

[0008] The silicon oxide layer is etched along the height direction of the silicon pillar to expose the sidewalls of a portion of the silicon pad layer, forming sidewall trenches.

[0009] A metal silicide is formed, which fills the sidewall trench and covers the surface of the silicon pillar and silicon pad layer;

[0010] A barrier layer is formed in the trench and then filled with metal to form contact pads.

[0011] Preferably, the depth of etching the silicon oxide layer along the height direction of the silicon pillar is greater than the depth of the trench.

[0012] Preferably, before etching back the silicon pillar along its height direction to simultaneously reduce the height of the silicon pad layer and form the trench, the method further includes:

[0013] Form bit line trenches;

[0014] Forming grooves for the letter lines.

[0015] Preferably, a nitride layer is further formed on the sidewall of the silicon oxide layer, the nitride layer being used to form an active region mesh structure, the formation of the active region mesh structure including:

[0016] The isolation structure is etched back for the first time to expose the drain region of the silicon pillar;

[0017] The silicon pad layer and the silicon oxide layer are sequentially formed on the exposed sidewall of the silicon pillar;

[0018] A nitride layer is deposited on the sidewall of the silicon oxide layer;

[0019] The nitride layer is etched to form an active region mesh structure.

[0020] Preferably, the material of the nitride layer includes SiN. x SiC y N z At least one of the following, where y and z are both integers greater than 0.

[0021] Preferably, after forming the active region mesh structure, the method further includes:

[0022] A gate structure is formed.

[0023] Preferably, an isolation layer is formed between the nitride layers of adjacent drain regions, and the material of the isolation layer includes SiN. x SiB m N n At least one of the following, wherein the isolation layer is used to form isolation between adjacent drains, wherein m and n are both integers greater than 0.

[0024] Preferably, after forming a barrier layer and filling a metal layer in the trench to form a contact pad, the method further includes:

[0025] The isolation layer and nitride layer are etched to expose the sidewalls of the metal layer;

[0026] A dielectric layer is filled into the gaps between adjacent metal layers.

[0027] Preferably, the material of the dielectric layer includes SiN.x SiB m N n At least one of the following, where m and n are both integers greater than 0.

[0028] Based on the same inventive concept, the present invention also provides a contact pad, which is prepared using the preparation method described above.

[0029] Compared with the prior art, the method for preparing contact pads of the present invention has the following advantages:

[0030] This invention involves etching back a silicon pillar to form a trench; etching the silicon oxide layer to expose a portion of the sidewalls of the silicon pad layer, forming a sidewall trench; forming a metal silicide that fills the sidewall trenches and covers the surfaces of the silicon pillar and silicon pad layer; forming a barrier layer in the trench; and filling the trench with metal to form contact pads. Because the trench and sidewall trenches constitute a 3D structure, and the metal silicide covers this 3D structure, the contact area of ​​the metal silicide is increased, thereby reducing resistance. Furthermore, by depositing the barrier layer and metal layer in the trench, self-alignment of the silicon pillar can be achieved without a contact pad photomask. The resulting contact pads have a width equal to the trench width, which is larger than the critical dimension of the silicon pillar. Therefore, the critical dimension of the contact pads can be increased, further reducing contact resistance. Moreover, the trench and silicon pillar are perfectly aligned. After the metal layer forms the contact resistance, the contact pads are prevented from connecting to the drain of adjacent unit transistors, thus avoiding leakage and improving device performance.

[0031] The contact pads provided by this invention and the method for preparing the contact pads provided by this invention belong to the same inventive concept. Therefore, the contact pads provided by this invention have at least all the advantages of the method for preparing the contact pads provided by this invention. While reducing contact resistance, they can also avoid leakage and short circuits, resulting in high device performance. Attached Figure Description

[0032] Figure 1 This is a front sectional view of a pad structure.

[0033] Figure 2 This is a front sectional view of another pad structure.

[0034] Figure 3 This is a flowchart of a method for preparing contact pads in one embodiment of the present invention.

[0035] Figure 4 This is a top view of the mask layer in one embodiment of the present invention.

[0036] Figure 5 This is a front sectional view of the formation of a mask layer in one embodiment of the present invention.

[0037] Figure 6 This is a top view of a bit-line isolation structure formed in one embodiment of the present invention.

[0038] Figure 7 This is a front sectional view of a bit-line isolation structure formed in one embodiment of the present invention.

[0039] Figure 8 This is a top view of a silicon nitride isolation structure formed in one embodiment of the present invention.

[0040] Figure 9 This is a side cross-sectional view of a silicon nitride isolation structure formed in one embodiment of the present invention.

[0041] Figure 10 This is a top view of the formation of a nitride layer in one embodiment of the present invention.

[0042] Figure 11 This is a front cross-sectional view of the formation of a nitride layer in one embodiment of the present invention.

[0043] Figure 12 This is a top view of the exposed top of the silicon pillar in one embodiment of the present invention.

[0044] Figure 13 This is a front sectional view of the exposed top of the silicon pillar in one embodiment of the present invention.

[0045] Figure 14 This is a front sectional view of the silicon pillar after being etched back in one embodiment of the present invention.

[0046] Figure 15 This is a top view of a metal silicide formed in one embodiment of the present invention.

[0047] Figure 16 This is a front cross-sectional view of a metal silicide formed in one embodiment of the present invention.

[0048] Figure 17 This is a top view after the barrier layer and metal layer have been formed in one embodiment of the present invention.

[0049] Figure 18 This is a front sectional view after the barrier layer and metal layer are formed in one embodiment of the present invention.

[0050] Figure 19 This is a front sectional view after the filling of the dielectric layer in one embodiment of the present invention.

[0051] In the picture,

[0052] 10. Epitaxial silicon pillar; 11. Metal silicide film; 12. Titanium nitride layer; 13. Metal contact layer; 14. Dielectric material; 100. Substrate; 200. Silicon-germanium stop layer; 300. Silicon epitaxial layer; 400. Buffer layer; 500. Mask layer; 310. Silicon pillar; 510. Shallow trench isolation structure; 520. Silicon nitride isolation; 540. Silicon pad layer; 550. Silicon oxide layer; 560. Nitride layer; 570. Isolation layer; 580. Gate oxide layer; 590. Metal gate; 511. Trench; 512. Sidewall trench; 513. Metal silicide; 514. Barrier layer; 515. Metal layer; 516. Dielectric layer; 531. Oxide material layer. Detailed Implementation

[0053] To make the objectives, advantages, and features of the present invention clearer, the contact pads and their preparation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the invention to scale, and the illustrative features used to illustrate certain principles of the invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0056] refer to Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a solder pad structure. Figure 2 This is a schematic diagram of another pad structure. In DRAM fabrication, the process for forming contact pads is as follows: a titanium nitride layer 12 and a metal contact layer 13 are sequentially deposited on a flat surface including the top surface of the exposed epitaxial silicon pillar 10. A metal silicide film layer 11 is also formed on the top surface of the epitaxial silicon pillar 10. A pad structure aligned with the epitaxial silicon pillar 10 is formed by photolithography and etching of the metal contact layer 13 and the titanium nitride layer 12, connecting the metal contact layer 13 to the drain at the top of the epitaxial silicon pillar 10. Subsequently, a dielectric material 14 is used to fill the gaps between the pad structures.

[0057] like Figure 1 As shown, in order to ensure alignment between the pad structure and the epitaxial silicon pillar 10, the critical dimensions of the pad structure (i.e., Figure 1 The D1 in the image is typically small, resulting in a small contact area between the pad structure and the epitaxial silicon pillar 10. This leads to a significant increase in the contact resistance of the pad structure, which in turn reduces the sensing margin and makes the device prone to failure. Furthermore, over-etching during the etching steps of the metal contact layer 13 and the titanium nitride layer 12 can damage the drain electrode underneath.

[0058] To reduce the resistance of the pad structure, the contact area between the contact pad and the epitaxial silicon pillar 10 can be increased to form a structure like... Figure 2 The structure shown, however, for Figure 2 The pad structure shown is prone to undesirable connections with the adjacent epitaxial silicon pillar 10 (i.e., the drain of other unit transistors) due to overlay deviation. This can lead to leakage current a between adjacent transistor units, resulting in short-circuit failure of the device.

[0059] The core idea of ​​this invention is to provide a method for preparing contact pads, which can reduce the resistance of the contact pads while avoiding the contact pads from connecting to the drain of adjacent unit transistors, thus preventing leakage.

[0060] To achieve the above-mentioned goals, this invention provides a method for preparing contact pads, as described above. Figures 3 to 19 A specific embodiment of the disclosed method for preparing a contact pad is described. The method for preparing the contact pad includes the following steps S1 to S5.

[0061] Step S1: Provide a substrate, on the surface of which a plurality of silicon pillars are formed, with an isolation structure between adjacent silicon pillars, the top of the silicon pillars is exposed and a drain region is provided, and a silicon pad layer and a silicon oxide layer are formed sequentially along the transverse direction on the sidewall of the top of the silicon pillars.

[0062] refer to Figure 4 and Figure 5 As shown, the substrate can be a substrate 100, a silicon-germanium stop layer 200, or a silicon-germanium stop layer 200 formed on the substrate 100.

[0063] The specific process of forming silicon pillars 310 on substrate 100 is as follows:

[0064] like Figure 5 As shown, a substrate 100 is provided. A silicon-germanium stop layer 200 is disposed on the surface of the substrate 100. A silicon epitaxial layer 300 is disposed on the surface of the silicon-germanium stop layer 200. A mask layer 500 can be directly disposed on the surface of the silicon epitaxial layer 300. However, in order to protect the underlying silicon epitaxial layer 300 during subsequent etching, a buffer layer 400 can be disposed between the silicon epitaxial layer 300 and the mask layer 500. The substrate material can include silicon (Si), such as single-crystal Si, polycrystalline Si, or amorphous Si. The buffer layer 400 material can include silicon oxide, and the mask layer 500 material can include silicon nitride. Of course, in some embodiments, the material of the substrate 100 is not limited to Si.

[0065] Next, the method further includes sequentially forming an isolation structure, a bit line trench, a word line trench, an active region mesh structure, and a gate structure, wherein the isolation structure can be a shallow trench isolation structure (STI).

[0066] refer to Figure 6 and Figure 7 The formation process of the shallow trench isolation structure 510 is as follows:

[0067] A patterned mask layer 500 is used as a mask to etch a silicon epitaxial layer 300, forming grooves and silicon pillars 310. The grooves are located between two adjacent silicon pillars 310. Next, silicon dioxide material is filled into the grooves to form shallow trench isolation structures 510, used for... Figure 6 or Figure 7 The X direction in the transistor acts as an isolation line between different transistor units.

[0068] After forming the STI, the process also includes forming the bit line (BL) trench, as follows:

[0069] Through photolithography and etching, along the height direction of silicon pillar 310 (i.e., Figure 7 The STI layer is vertically etched downwards along the Z-direction and extends into the silicon pillar 310, forming a high aspect ratio vertical BL trench (not shown in the figure). Next, a SiN liner and an oxide layer are deposited sequentially on the inner wall and bottom of the BL trench. Then, spin-on dielectric (SOD) is filled into the BL trench as a sacrificial dielectric layer, and the SOD is planarized. By filling the BL trench with SOD to occupy the position of the bit line, after the contact pads are fabricated, the SOD is removed, and metal is filled into the BL trench to form the bit line.

[0070] The steps to form the character line grooves are as follows:

[0071] refer to Figure 8 and Figure 9 As shown, the mask layer 500 is further patterned to form word lines (WL) patterns. Word line trenches are formed through photolithography and etching. Then, an oxide material layer 531 is formed on the inner wall and bottom of the WL trenches by atomic layer deposition. In subsequent processes, the oxide material layer 531 is etched to form sidewalls that isolate the WL. Next, silicon nitride material is deposited by fence deposition to form silicon nitride isolation 520 to define the word line region.

[0072] The process of forming the active region mesh structure is as follows:

[0073] refer to Figure 10 and Figure 11 As shown, the shallow trench isolation structure 510 is etched back for the first time, exposing the drain region of the silicon pillar 310.

[0074] A silicon pad layer 540 and a silicon oxide layer 550 are sequentially formed on the exposed sidewall of the silicon pillar 310.

[0075] A nitride layer 560 is deposited on the sidewall of the silicon oxide layer 550. That is, a silicon pad layer 540, a silicon oxide layer 550 and a nitride layer 560 are sequentially formed on the sidewall of the silicon pillar 310 in the drain region from the silicon pillar 310 outward.

[0076] The nitride layer 560 is etched back to expose the shallow trench isolation structure 510. The etched nitride layer 560 serves as the mesh structure of the active region. The material of the nitride layer 560 includes SiN. x SiC y Nz At least one of the following, where y and z are both integers greater than 0.

[0077] The specific process for forming the gate structure is as follows:

[0078] refer to Figure 12 and Figure 13 As shown, the exposed shallow trench isolation structure 510 is etched a second time to expose the region where the gate structure is located in the silicon pillar 310. Then, a gate oxide layer 580 is formed, and gate metal is deposited. Next, the gate metal is etched to form a metal gate 590.

[0079] It should be noted that the shallow trench isolation structure 510, bit line trench, word line trench, active area mesh structure and gate structure formed in sequence are already familiar to those skilled in the art, and the specific details will not be elaborated here.

[0080] refer to Figure 13 As shown, an isolation layer 570 is formed between the nitride layers 560 adjacent drain regions. The material of the isolation layer 570 includes SiN. x SiB m N n At least one of the following, the isolation layer 570 is used to form isolation between adjacent drains, where m and n are both integers greater than 0. The isolation layer 570 is used for the isolation structure of drains in different unit transistors.

[0081] Since the top of the silicon pillar is covered by a buffer layer 400 and a mask layer 500, before performing step S2, the method further includes: removing the buffer layer 400 and the mask layer 500 by wet etching, so that the top of the silicon pillar 310 in the drain region is exposed, forming a shape as shown in the image. Figure 12 and Figure 13 The structure shown.

[0082] Step S2: Along the height direction of the silicon pillar, the silicon pillar is etched back to simultaneously reduce the height of the silicon pad layer, forming a trench.

[0083] refer to Figure 14 As shown, along the direction of the height of silicon pillar 310 (i.e., Figure 14 In the Z-direction, either dry or wet etching is used to etch back the exposed silicon pillar 310 from its top, forming trench 511. For dry etching, gases such as Cl2 or BCl3 can be used to etch back the silicon pillar 310. For wet etching, a DHF mixture of hydrogen fluoride, nitric acid, and deionized water can be used to etch the silicon pillar 310. The depth of the trench 511 in the silicon pillar 310 can be controlled by adjusting the etching time.

[0084] It should be noted that since the silicon pad layer 540 and the silicon pillar 310 are made of the same material, when the silicon pillar 310 is etched back, the silicon pad layer 540 is also etched at the same time, and the height of the silicon pad layer 540 is reduced synchronously. Therefore, the silicon pad layer 540 and the silicon pillar 310 are etched to the same height.

[0085] It should also be noted that, in this embodiment, by forming a silicon pad layer 540 on the sidewall of the silicon pillar 310, the silicon pillar 310 can be strengthened in the lateral direction (i.e., Figure 14 The width in the X direction can increase the critical dimensions of the subsequently formed contact pads, thereby further increasing the contact area between the contact pads and the drain, reducing contact resistance, and improving device performance.

[0086] Step S3: Etch the silicon oxide layer along the height direction of the silicon pillar to expose the sidewalls of a portion of the silicon pad layer, forming sidewall trenches.

[0087] Continue to refer to Figure 14 As shown, along the direction of the height of silicon pillar 310 (i.e., Figure 14 Along the Z-direction, the silicon oxide layer 550 is etched using dry or wet etching to form sidewall trenches 512. The sidewall trenches 512 are arranged around the circumferential direction of the silicon pillar 310 and expose a portion of the height of the silicon pad layer 540, meaning the exposed height of the silicon pad layer 540 is less than its original height. Along the height direction of the silicon pillar (i.e.,...) Figure 14 In the Z-direction, the etching depth of the silicon oxide layer 550 is greater than the depth of the trenches, meaning the depth of the removed silicon oxide layer 550 is greater than the depth of the removed silicon pillars 310. The trenches 511 and sidewall trenches 512 constitute a 3D structure. It should be noted that, regardless of whether dry or wet etching is used, only the silicon oxide layer 550 is etched, avoiding etching of the silicon pillars 310 and the nitride layer 560. For dry etching, gases with high selectivity, such as CF4 and Ar, or C4F8 and Ar, can be used. For wet etching, HF or NH4F buffer (BOE) can be used to etch the silicon oxide layer 550.

[0088] Step S4: Form a metal silicide that fills the sidewall trench and covers the surface of the silicon pillar and silicon pad layer.

[0089] refer to Figure 15 and Figure 16As shown, metal silicide 513 is formed in the sidewall trenches 512 and 511 using a silicide process. The metal silicide 513 fills the sidewall trenches 512 and forms a certain thickness of metal silicide 513 on the surfaces of the silicon pillars 310 and the silicon pad layer 540 to reduce contact resistance. The material of the metal silicide 513 may include TiSi. x CoSi x NiSi x The metal silicide 513 covers a 3D structure, thereby increasing the contact area between the contact pads and the drain, reducing resistance, and the trench 511 and silicon pillar 310 are completely self-aligned. After the contact resistance is formed by the filling metal layer, the contact pads can be prevented from connecting to the drain of the adjacent unit transistor, thereby avoiding leakage and improving device performance.

[0090] Step S5: A barrier layer is formed in the trench, and a metal layer is filled to form a contact pad.

[0091] refer to Figure 17 and Figure 18 As shown, a barrier layer 514 is formed on the inner wall of the trench 511 and on the surface of the metal silicide 513. The material of the barrier layer 514 may include silicon nitride (TiN). x Tantalum nitride (TaN), tantalum (Ta), etc. A metal layer 515 is filled into a trench 511 with a barrier layer 514. The height of the metal layer 515 is higher than the height of the trench 511. Subsequently, the metal layer 515 is planarized by chemical mechanical polishing to form a shape such as... Figure 18 The structure shown. The material of the metal layer 515 can be tungsten (W). The barrier layer 514 serves to prevent the diffusion of tungsten.

[0092] from Figure 18 As can be seen, by depositing the barrier layer 514 and the metal layer 515 in the trench 511, self-alignment of the silicon pillar 310 can be achieved without a contact pad photomask. The resulting contact pads have a width equal to that of the trench 511, which is larger than the critical dimension of the silicon pillar 310. Therefore, the critical dimension of the contact pads can be increased, further reducing contact resistance. Furthermore, the complete alignment of the trench 511 and the silicon pillar 310, after the metal layer 515 forms the contact resistance, can prevent similar issues. Figure 2 Contact pads caused by overlay errors are connected to the drain of adjacent unit transistors, thereby avoiding leakage and improving device performance.

[0093] After step S5, the method further includes:

[0094] refer to Figure 19As shown, the isolation layer 570 and the nitride layer 560 are etched to expose the sidewalls of the metal layer 515.

[0095] A dielectric layer 516 is filled into the gaps between adjacent metal layers 515. The material of the dielectric layer 516 includes SiN. x SiB m N n At least one of the following, where m and n are both integers greater than 0. The dielectric layer 516 is used to isolate the contact pads between different transistor units. This completes the fabrication of the contact pads. It should be noted that these contact pads are used for electrical connection between the drain and the capacitor, which is fabricated in subsequent processes and will not be described in detail here.

[0096] To achieve the above-mentioned idea, this embodiment also discloses a contact pad prepared using the preparation method described above.

[0097] The contact pad provided in this embodiment and the method for preparing the contact pad provided in this embodiment belong to the same inventive concept. Therefore, the contact pad provided in this embodiment has at least all the advantages of the method for preparing the contact pad provided in this embodiment. While reducing contact resistance, it can also avoid leakage and short circuit, resulting in high device performance.

[0098] In summary, the above embodiments have provided detailed descriptions of different configurations of the contact pad preparation method. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for preparing contact pads, characterized in that, include: A substrate is provided, wherein a plurality of silicon pillars are formed on the surface of the substrate, an isolation structure is provided between adjacent silicon pillars, the top of the silicon pillars is exposed and a drain region of a vertical transistor is provided thereon, and a silicon pad layer and a silicon oxide layer are formed sequentially along the transverse direction on the sidewall of the top of the silicon pillars. The silicon pillar is etched back along its height direction, simultaneously reducing the height of the silicon pad layer to form a trench; The silicon oxide layer is etched along the height direction of the silicon pillar to expose the sidewalls of a portion of the silicon pad layer, forming sidewall trenches. A metal silicide is formed, which fills the sidewall trench and covers the surface of the silicon pillar and silicon pad layer; A barrier layer is formed in the trench, and then filled with metal to form contact pads. The silicon pad layer is made of the same material as the silicon pillar; Along the height direction of the silicon pillar, the depth of etching the silicon oxide layer is greater than the depth of the trench.

2. The method for preparing contact pads according to claim 1, characterized in that, Before etching back the silicon pillar along its height direction to simultaneously reduce the height of the silicon pad layer and form the trench, the method further includes: Form bit line trenches; Forming grooves for the letter lines.

3. The method for preparing contact pads according to claim 2, characterized in that, A nitride layer is also formed on the sidewall of the silicon oxide layer. The nitride layer is used to form an active region mesh structure, which includes: The isolation structure is etched back for the first time to expose the drain region of the silicon pillar; The silicon pad layer and the silicon oxide layer are sequentially formed on the exposed sidewall of the silicon pillar; A nitride layer is deposited on the sidewall of the silicon oxide layer; The nitride layer is etched to form an active region mesh structure.

4. The method for preparing contact pads according to claim 3, characterized in that, The material of the nitride layer includes SiN. x SiC y N z At least one of the following, where y and z are both integers greater than 0.

5. The method for preparing contact pads according to claim 3, characterized in that, After forming the active region mesh structure, the method further includes: A gate structure is formed.

6. The method for preparing contact pads according to claim 3, characterized in that, An isolation layer is formed between the nitride layers of adjacent drain regions, and the material of the isolation layer includes SiN. x SiB m N n At least one of the following, wherein the isolation layer is used to form isolation between adjacent drains, wherein m and n are both integers greater than 0.

7. The method for preparing contact pads according to claim 6, characterized in that, After forming a barrier layer and filling it with a metal layer to form contact pads in the trench, the method further includes: The isolation layer and nitride layer are etched to expose the sidewalls of the metal layer; A dielectric layer is filled into the gaps between adjacent metal layers.

8. The method for preparing contact pads according to claim 7, characterized in that, The material of the dielectric layer includes SiN. x SiB m N n At least one of the following, where m and n are both integers greater than 0.

9. A contact pad, prepared by the preparation method according to any one of claims 1-8.

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