Method for manufacturing bit line shallow trench isolation structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU XINGYUANCHI SEMICON CO LTD
- Filing Date
- 2026-07-09
- Publication Date
- 2026-08-07
AI Technical Summary
[0004]本发明的目的在于提供一种位线浅沟槽隔离结构的制备方法，以解决图形化过程中的不同图形之间的间距差异，形成的浅沟槽隔离存在深度偏差，导致位线浅沟槽隔离的关键尺寸均匀性变差，不仅使位线电阻离散性增大，还造成晶体管源极和漏极不对称的问题
[0027]本发明通过以图形化的掩模层为掩膜对硅外延层进行刻蚀，形成沟槽，之后，再进一步对位于硅锗停止层中的沟槽底部进行横向刻蚀，在硅柱的底部产生底切，并暴露硅柱的底部，从而能够避免沟槽的深度不同，并且形成的沟槽关键尺寸均匀一致，不仅能够避免位线电阻离散性增大，同时也能够避免出现晶体管源极和漏极不对称的问题，提高器件性能。
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Figure CN122534865A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a shallow trench isolation structure. Background Technology
[0002] 4F2 DRAM is a high-density dynamic random access memory (DRAM). During the fabrication of the final bit line layer, DRAM utilizes pre-formed shallow trench isolation (STI) on the front side of the wafer for self-alignment, completing the shallow trench isolation of the bit lines from the back side of the wafer. During the back-side bit line fabrication process, the silicon substrate is first thinned through wafer grinding, followed by etching of the silicon using dry etching and chemical mechanical polishing. This process uses the oxide layer filling the front-side shallow trench isolation as an etch stop layer. However, due to the spacing differences between different patterns during the patterning process, the shallow trench isolation formed in the array region exhibits depth deviations. These deviations cause sidewall tilting and dispersion in the shallow trench isolation, leading to problems such as bit line bridging (short circuits). It also results in poor uniformity of the critical dimensions of the self-aligned shallow trench isolation, increasing bit line resistance dispersion and causing uneven silicon pillar dimensions, leading to asymmetry between the transistor source and drain, and resulting in differences in device performance.
[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a shallow trench isolation structure for bit lines, in order to solve the problem of depth deviation in the shallow trench isolation caused by the spacing difference between different patterns during the patterning process. This leads to poor uniformity of the key dimensions of the shallow trench isolation, which not only increases the dispersion of bit line resistance, but also causes the problem of asymmetry between the source and drain of the transistor.
[0005] To solve the above technical problems, the present invention provides a method for fabricating a shallow trench isolation structure, comprising:
[0006] A substrate is provided, wherein a silicon-germanium stop layer is formed on the front side of the substrate, a silicon epitaxial layer is formed on the surface of the silicon-germanium stop layer, and a mask layer is formed on the surface of the silicon epitaxial layer;
[0007] The mask layer is patterned, and the silicon epitaxial layer is etched using the patterned mask layer as a mask to form trenches and silicon pillars located between adjacent trenches. The trenches extend from the surface of the silicon epitaxial layer to the silicon germanium stop layer.
[0008] Laterally etch the bottom of the trench located in the silicon-germanium stop layer to create an undercut at the bottom of the silicon pillar and expose the bottom of the silicon pillar;
[0009] Remove the mask layer;
[0010] The trench is filled with insulating material to form a bit line isolation structure.
[0011] Preferably, before removing the mask layer, the method further includes:
[0012] The silicon-germanium stop layer is isotropically etched using wet etching, wherein the wet etching reagent has an oxidizing effect on the exposed bottom of the silicon pillar to form an oxide product at the bottom of the exposed silicon pillar.
[0013] Preferably, the process of removing the mask layer also includes:
[0014] Remove the oxidation products.
[0015] Preferably, the wet etching reagent includes a mixture of ammonia, hydrogen peroxide, and deionized water.
[0016] Preferably, the mask layer and the oxidation products are removed simultaneously using a hydrogen fluoride solution.
[0017] Preferably, the silicon epitaxial layer is etched using dry etching to form trenches, and endpoint detection is performed simultaneously with the etching process.
[0018] Preferably, prior to lateral etching of the trench located in the silicon-germanium stop layer, the method further includes:
[0019] Based on the endpoint detection, the dry etching is controlled to be over-etching.
[0020] Preferably, atomic layer etching is used to etch the bottom of the trench in the silicon-germanium stop layer laterally.
[0021] Preferably, after forming the bit line isolation structure, the method further includes:
[0022] Using the silicon-germanium stop layer as an etching stop layer, the substrate is removed from the back side of the substrate;
[0023] Remove the silicon-germanium stop layer.
[0024] Preferably, after removing the silicon-germanium stop layer, the method further includes:
[0025] Create bit lines, wherein the bit line isolation structure is located between two adjacent bit lines.
[0026] Compared with the prior art, the method for preparing the shallow trench isolation structure of the bit line of the present invention has the following advantages:
[0027] This invention uses a patterned mask layer as a mask to etch a silicon epitaxial layer to form trenches. Then, it further etches the bottom of the trench in the silicon-germanium stop layer laterally, creating an undercut at the bottom of the silicon pillar and exposing the bottom of the silicon pillar. This avoids inconsistencies in trench depth and ensures that the key dimensions of the formed trenches are uniform. This not only avoids increased bit line resistance dispersion but also prevents transistor source-drain asymmetry, thus improving device performance. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the structure after the epitaxial layer has been etched.
[0029] Figure 2 It is a kind of Figure 1 A schematic diagram of the structure after further etching of the epitaxial layer.
[0030] Figure 3 This is a schematic diagram of a structure that forms shallow trench isolation for bit lines.
[0031] Figure 4 This is a flowchart of a method for preparing a shallow trench isolation structure for midline in one embodiment of the present invention.
[0032] Figure 5 This is a schematic diagram of a silicon epitaxial layer in one embodiment of the present invention.
[0033] Figure 6 This is a schematic diagram of the structure after etching the silicon epitaxial layer in one embodiment of the present invention.
[0034] Figure 7 yes Figure 6 A magnified structural diagram of point A in the middle.
[0035] Figure 8 This is a schematic diagram of the structure after removing the mask layer in one embodiment of the present invention.
[0036] Figure 9 yes Figure 8 A magnified structural diagram at point B in the middle.
[0037] Figure 10 This is a schematic diagram of a structure forming shallow trench isolation for bit lines in one embodiment of the present invention.
[0038] In the picture,
[0039] 10. Pillar; 11. First groove; 12. Second groove; 13. Isolation structure; 14. Unit bit line; 100. Substrate; 200. Silicon-germanium stop layer; 300. Silicon epitaxial layer; 310. Silicon pillar; 400. Mask layer; 500. Trench; 510. First trench; 520. Second trench; 600. Bit line isolation structure; 610. Bit line; 620. Silice layer; 630. Word line; 640. Pad; 650. Nitride layer; 660. Capacitor. Detailed Implementation
[0040] To make the objectives, advantages, and features of the present invention clearer, the shallow trench isolation structure and its preparation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that the drawings do not necessarily show the specific structure of the invention to scale, and the illustrative features used to illustrate certain principles of the invention in the drawings are also drawn in a slightly simplified manner. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0043] refer to Figures 1 to 3 As shown, Figure 1 This is a schematic diagram of the structure after the epitaxial layer has been etched. Figure 2 It is a kind of Figure 1 A schematic diagram of the structure after further etching of the epitaxial layer. Figure 3 This is a schematic diagram of a structure that forms shallow trench isolation along the bit line. (Reference) Figure 1 As shown, after etching the epitaxial layer, multiple first grooves 11 and multiple pillars 10 are formed. Figure 1 It can be seen that the depths of the multiple first grooves 11 are different, resulting in depth deviation, and the sidewalls at the bottom of the first grooves 11 show an inward inclination (e.g. Figure 2 As shown at point a in the diagram), depth deviations can cause the sidewalls of shallow trench isolation to tilt and become discrete. Subsequent bitline fabrication based on such shallow trench isolation can easily lead to problems such as bitline bridging (short circuits), and also result in poor uniformity of critical dimensions in self-aligned shallow trench isolation. To address this... Figure 1 The problem is that after forming the first groove 11, the bottom of the first groove 11 is further etched, forming something like... Figure 2 The second groove 12 is shown. However, since both etching processes involve etching the same material, the second groove 12 only increases the depth of the groove compared to the first groove 11. The groove depth still varies, and this discrepancy worsens during subsequent wafer backside processing (e.g., grinding). Regardless of whether the first groove 11 or the second groove 12 is used, the resulting groove will appear as shown... Figure 3 The isolation structure 13 shown, from Figure 3 It can be seen that the isolation structure 13 at point b has a break between adjacent cell bit lines 14. The isolation structure 13 cannot effectively isolate the cell bit lines 14 between different cell devices, thus causing a bit line short circuit problem. Furthermore, from... Figure 2 As can be seen at point a, both the first groove 11 and the second groove 12 have sharp defects at the bottom of the etched grooves, which makes the size of the pillars formed after etching uneven. Consequently, due to the asymmetry of the source and drain of the transistor, device performance differences occur.
[0044] The core idea of this invention is to provide a shallow trench isolation structure for bit lines and its fabrication method, which can eliminate the problem of inter-line bridging failure caused by inconsistent etching depth in shallow trench isolation, as well as the problem of uneven pillar size causing asymmetry between the source and drain of transistors and resulting in differences in device performance.
[0045] To achieve the above-mentioned goals, this invention provides a method for fabricating a shallow trench isolation structure for bit lines. Figures 4 to 10A specific embodiment of the method for fabricating a shallow trench isolation structure for bit lines is disclosed. The method for fabricating the shallow trench isolation structure for bit lines includes the following steps S1 to S5.
[0046] Step S1: Provide a substrate, wherein a silicon-germanium stop layer is formed on the front side of the substrate, a silicon epitaxial layer is formed on the surface of the silicon-germanium stop layer, and a mask layer is formed on the surface of the silicon epitaxial layer.
[0047] refer to Figure 5 As shown, a silicon-germanium stop layer 200 is formed on the front side of the substrate 100. A silicon epitaxial layer 300 is formed on the surface of the silicon-germanium stop layer 200. A mask layer 400 is formed on the surface of the silicon epitaxial layer 300. The material of the substrate 100 may include silicon (Si), such as single-crystal Si, polycrystalline silicon Si, or amorphous Si. Of course, in some embodiments, the material of the substrate 100 is not limited to Si. The material of the mask layer 400 includes silicon oxide, such as silicon dioxide (SiO2).
[0048] Step S2: Pattern the mask layer, and use the patterned mask layer as a mask to etch the silicon epitaxial layer to form trenches and silicon pillars. The trenches extend from the surface of the silicon epitaxial layer to the silicon germanium stop layer.
[0049] refer to Figure 6 and Figure 7 As shown, a patterned mask layer 400 is used to etch the silicon epitaxial layer 300 to form trenches 500, and also to form multiple spaced silicon pillars 310. The silicon pillars 310 are used for subsequent formation of the channel layer. The trenches 500 extend from the surface of the silicon epitaxial layer 300 into the silicon-germanium stop layer 200. Due to the difference in spacing between the etched patterns, from... Figure 6 and Figure 7 It can be seen that the depth of trench 500 varies, and at the bottom of silicon pillar 310 (i.e., Figure 7 At point c in the diagram, there is an inward tilt. Therefore, the critical dimension at the bottom of the trench 500 in the region where the silicon pillar 310 is located is different from the critical dimension at the top, and the critical dimension of the trench 500 also differs between different silicon pillars 310.
[0050] In this embodiment, dry etching is used to etch the silicon epitaxial layer 300 to form trenches 500, and endpoint detection is performed simultaneously with the etching. Dry etching is used, and an End Point Detection (EPD) machine is employed to detect and accurately identify when the etching reaches the silicon-germanium stop layer 200, thereby locking the etching endpoint and stopping the etching process.
[0051] In some embodiments, the dry etching is controlled to be over-etched based on the endpoint detection. In order to remove etching residues and make the morphology of the trench 500 more stable, the etching method further includes over-etching the trench 500, that is, stopping the etching after a delay of T seconds during dry etching, where T can be 10S-60S.
[0052] Step S3: Laterally etch the bottom of the trench located in the silicon-germanium stop layer to create an undercut at the bottom of the silicon pillar and expose the bottom of the silicon pillar.
[0053] refer to Figure 7 As shown, the trench located in the region where the silicon pillar 310 is located is defined as the first trench 510, and the trench located in the silicon-germanium stop layer 200 is defined as the second trench 520. The second trench 520 will be removed in subsequent processes. Therefore, it is sufficient to ensure that the depth of the first trench 510 is the same and that the critical dimensions are the same.
[0054] refer to Figure 8 and Figure 9 As shown, atomic layer etching (ALE) is used to laterally etch the bottom of the trench 500 located in the silicon-germanium stop layer 200 (i.e., the top of the second trench 520) to create an undercut and expose the bottom of the silicon pillar 310. Because ALE etching has a high selectivity, it only etches the silicon-germanium stop layer 200, leaving the silicon pillar 310 almost unetched. Furthermore, ALE etching rarely etches downwards; instead, it precisely, slowly, and controllably hollows out the silicon-germanium stop layer 200 at the bottom of the silicon pillar 310 towards both sides of the trench 500, ultimately increasing the lateral dimension of the top of the second trench 520 (i.e., ...). Figure 9 d2) is greater than the critical dimension of the first trench 510 (i.e., Figure 9 The key dimensions of the first trench 510 are kept consistent with those of the top and bottom, and the key dimensions of the first trench 510 between different silicon pillars 310 are kept consistent, thus avoiding depth deviations in the shallow trench isolation formed later, and also avoiding differences in the key dimensions of the first trench 510.
[0055] After performing step S3, the method further includes:
[0056] The silicon-germanium stop layer is isotropically etched using wet etching, wherein the wet etching reagent has an oxidizing effect on the exposed bottom of the silicon pillar to form an oxide product at the bottom of the exposed silicon pillar.
[0057] The reagents for wet etching include SC1 solution, which includes ammonia (NH4OH), hydrogen peroxide (H2O2), and deionized water (DIW). The concentration of ammonia can be a commonly used concentration, such as 29%, and the concentration of hydrogen peroxide can also be a commonly used concentration, such as 30%.
[0058] Isotropic etching of the silicon-germanium stop layer 200 is performed using an SC1 solution. The SC1 solution etches only the silicon-germanium stop layer 200, while only lightly etching the silicon material. This further refines the morphology of the trench 500, maintaining its symmetry, and further exposes the bottom of the silicon pillar 310, deepening the undercut. Furthermore, during the further etching of the silicon-germanium stop layer 200 with the SC1 solution, the hydrogen peroxide in the SC1 solution oxidizes the surface of the bottom of the silicon pillar 310 into a silicon dioxide (SiO2) film with a thickness ranging from 1 nm to 2 nm. Forming a silicon dioxide film on the bottom surface of the silicon pillar 310 prevents damage to the silicon substrate from the etching reagents used to remove the mask layer during subsequent removal, resulting in smoother sidewalls and more dimensionally stable silicon substrates, providing a uniform interface for subsequent trench 500 filling.
[0059] Step S5: Remove the mask layer.
[0060] Removing the mask layer also includes:
[0061] Remove the oxidation products.
[0062] The mask layer 400 is removed using wet etching. The wet etching reagent may include a hydrogen fluoride (HF) solution, and a commonly used concentration, such as 1%-2%, can be selected. While removing the mask layer 400 using the hydrogen fluoride solution, the silicon dioxide film on the bottom of the silicon pillar 310 is also removed.
[0063] Step S6: Fill the trench with insulating material to form a bit line isolation structure.
[0064] Please refer to the reference. Figure 6 , Figure 9 and Figure 10 Insulating material is filled into trench 500, with the height of the insulating material exceeding the height of the silicon pillars 310. Then, CMP (Chemical Mechanical Polishing) is used to planarize the insulating material above the silicon pillars 310, forming a uniform bit-line isolation structure 600 between the silicon pillars 310. This achieves bit-line self-alignment without additional photolithography or line cutting processes. The insulating material may include silicon dioxide.
[0065] After forming the bit-line isolation structure, the method further includes:
[0066] Using the silicon-germanium stop layer 200 as an etching stop layer, the substrate 100 is removed from the back side of the substrate 100. For example, after flipping the wafer, the substrate 100 is removed from the back side of the substrate 100 by CMP.
[0067] The silicon-germanium stop layer 200 is removed. After the substrate 100 is removed, the silicon-germanium stop layer 200 is removed by wet etching.
[0068] refer to Figure 10 As shown, after removing the silicon-germanium stop layer 200, the method further includes:
[0069] Bit lines 610 are fabricated, with the bit line isolation structure 600 located between two adjacent bit lines 610. Prior to fabricating the bit lines 610, a silicide layer 620 may be deposited. (Comparison...) Figure 3 and Figure 10 As can be seen, the bit line isolation structure 600 formed using the method of this invention has no bridging problem at all. The bit line 610 formed in this step serves as the bit line for the back-side device portion, and the front-side device portion will be fabricated subsequently.
[0070] Continue to refer to Figure 10 As shown, subsequent processes also include fabricating letter lines 630, solder pads 640, and capacitors 660, etc. It should also be noted that... Figure 10 The silicide layer 620 is used for subsequent fabrication of ohmic electrodes, the nitride layer 650 serves as an etch stop layer for subsequent processes, and the word line 630 is shared by the bit line 610 of the back-side device portion and the bit line of the front-side device portion. Subsequent front-side processes are consistent with conventional vertical channel transistor fabrication processes, which are already familiar to those skilled in the art and will not be described in detail here.
[0071] In this embodiment, the silicon epitaxial layer 300 is etched using a patterned mask layer 400 as a mask to form a trench 500. Then, the top of the second trench 520 is further etched laterally to create an undercut at the bottom of the silicon pillar 310 and expose the bottom of the silicon pillar 310. This avoids the inconsistency in the depth of the first trench 510 and ensures that the key dimensions of the formed first trench 510 are uniform. This not only avoids the increase in bit line resistance dispersion but also avoids the problem of transistor source and drain asymmetry, thereby improving device performance.
[0072] Furthermore, performing isotropic etching on the silicon-germanium stop layer 200 using wet etching can further modify the morphology of the trench 500, maintain the symmetry of the first trench 510 morphology, and further expose the bottom of the silicon pillar 310, deepening the undercut. This allows the critical dimensions of the first trench 510 to remain consistent, making the transistor source and drain symmetrical, and further improving the device performance.
[0073] In summary, the above embodiments have provided detailed descriptions of different configurations of the fabrication method of the shallow trench isolation structure. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for fabricating a shallow trench isolation structure, characterized in that, include: A substrate is provided, wherein a silicon-germanium stop layer is formed on the front side of the substrate, a silicon epitaxial layer is formed on the surface of the silicon-germanium stop layer, and a mask layer is formed on the surface of the silicon epitaxial layer; The mask layer is patterned, and the silicon epitaxial layer is etched using the patterned mask layer as a mask to form trenches and silicon pillars located between adjacent trenches. The trenches extend from the surface of the silicon epitaxial layer to the silicon germanium stop layer. Laterally etch the bottom of the trench located in the silicon-germanium stop layer to create an undercut at the bottom of the silicon pillar and expose the bottom of the silicon pillar; Remove the mask layer; The trench is filled with insulating material to form a bit line isolation structure.
2. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, Before removing the mask layer, the method also includes: The silicon-germanium stop layer is isotropically etched using wet etching, wherein the wet etching reagent has an oxidizing effect on the exposed bottom of the silicon pillar to form an oxide product at the bottom of the exposed silicon pillar.
3. The method for preparing the shallow trench isolation structure according to claim 2, characterized in that, Removing the mask layer also includes: Remove the oxidation products.
4. The method for preparing the shallow trench isolation structure according to claim 2, characterized in that, The reagents used in the wet etching process include a mixture of ammonia, hydrogen peroxide, and deionized water.
5. The method for preparing the shallow trench isolation structure according to claim 3, characterized in that, The mask layer and the oxidation products are removed simultaneously using a hydrogen fluoride solution.
6. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, The silicon epitaxial layer is etched using dry etching to form trenches, and endpoint detection is performed simultaneously with the etching process.
7. The method for preparing the shallow trench isolation structure according to claim 6, characterized in that, Prior to lateral etching of the trench located in the silicon-germanium stop layer, the method further includes: Based on the endpoint detection, the dry etching is controlled to be over-etching.
8. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, The bottom of the trench in the silicon-germanium stop layer is etched laterally using an atomic layer etching process.
9. The method for preparing the shallow trench isolation structure according to claim 1, characterized in that, After forming the bit-line isolation structure, the method further includes: Using the silicon-germanium stop layer as an etching stop layer, the substrate is removed from the back side of the substrate; Remove the silicon-germanium stop layer.
10. The method for preparing the shallow trench isolation structure according to claim 9, characterized in that, After removing the silicon-germanium stop layer, the method further includes: Create bit lines, wherein the bit line isolation structure is located between two adjacent bit lines.