Semiconductor structure and method of manufacturing the same, electronic device

Abstract

This disclosure provides a semiconductor structure and its manufacturing method, as well as an electronic device. The semiconductor structure includes: a substrate and a first dielectric layer on the substrate; a plurality of word line layers located within the first dielectric layer and extending along a first direction, each word line layer including a plurality of gate electrode portions spaced apart along the first direction and a connection portion for connecting two adjacent gate electrode portions; the first direction being parallel to the surface of the substrate; a plurality of semiconductor layers, each semiconductor layer including at least a first sublayer, the first sublayer at least covering the top surface of the gate electrode portion; wherein the material of the semiconductor layers includes an oxide semiconductor material; and a gate dielectric layer, at least a portion of which is located between the semiconductor layers and the word line layers.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] Semiconductor structures, such as dynamic random access memory (DRAM), typically include a substrate, transistors located on the substrate, word lines for controlling the switching of the transistors, and capacitor structures for storing data. The substrate material typically includes semiconductor materials such as silicon, and the source, drain, and channel regions of the transistors are formed by performing a doping process on the substrate.

[0003] As semiconductor structures continue to evolve towards miniaturization and high integration, the size of word lines is further reduced, which leads to increased leakage current, degrades the current driveability of transistors, and thus reduces the performance of semiconductor structures. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including: Substrate and a first dielectric layer located on the substrate; Multiple word line layers are located within a first dielectric layer and extend along a first direction. Each word line layer includes multiple gate electrode portions spaced apart along the first direction and a connection portion for connecting two adjacent gate electrode portions. The first direction is parallel to the surface of the substrate. Multiple semiconductor layers, each semiconductor layer including at least a first sublayer, the first sublayer at least covering the top surface of the gate electrode portion; wherein, the material of the semiconductor layer includes an oxide semiconductor material; A gate dielectric layer, at least a portion of which is located between the semiconductor layer and the word line layer.

[0005] In some embodiments, the oxide semiconductor material includes at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, zinc oxide, tin oxide, indium oxide, and indium tin zinc oxide.

[0006] In some embodiments, the semiconductor structure further includes: The second dielectric layer is located on the substrate, and the first dielectric layer covers the second dielectric layer; Multiple bit line layers are located below multiple word line layers; the bit line layers extend within a second dielectric layer along a second direction and are electrically connected to the semiconductor layer; the second direction intersects with the first direction and is parallel to the surface of the substrate.

[0007] In some embodiments, The semiconductor layer also includes a second sub-layer that covers the sidewalls and bottom surface of the gate electrode portion. The second sub-layer is connected to the first sub-layer to circumferentially surround the gate electrode portion. The bit line layer is in contact with a portion of the second sub-layer located on the bottom surface of the word line layer.

[0008] In some embodiments, the semiconductor structure further includes: A conductive layer covers the bottom surface and sidewalls of the gate electrode portion. A first sub-layer is connected to the conductive layer to circumferentially surround the gate electrode portion. A portion of the gate dielectric layer is located between the word line layer and the conductive layer. The bit line layer is in contact with at least a portion of the conductive layer located on the bottom surface of the word line layer.

[0009] In some embodiments, the semiconductor structure further includes: A conductive layer, which covers at least a portion of the bottom surface of the gate electrode portion or covers the bottom surface and a portion of the sidewalls of the gate electrode portion; The semiconductor layer also includes a second sub-layer, which covers the portion of the sidewall and bottom surface of the gate electrode portion that is not covered by the conductive layer. The second sub-layer, the first sub-layer, and the conductive layer are connected to surround the gate electrode portion circumferentially. A portion of the gate dielectric layer is located between the word line layer and the conductive layer. The bit line layer is in contact with at least a portion of the conductive layer located on the bottom surface of the word line layer.

[0010] In some embodiments, the semiconductor structure further includes: The third dielectric layer is located on the first dielectric layer and covers the first sublayer; Multiple contact plugs are located above the gate electrode portion and penetrate the third dielectric layer. The contact plugs are in contact with a portion of the first sublayer covering the top surface of the gate electrode portion. The fourth dielectric layer is located on top of the third dielectric layer; Multiple capacitor structures are located within the fourth dielectric layer and are electrically connected to multiple contact plugs one by one.

[0011] This disclosure also provides a method for manufacturing a semiconductor structure, including: A substrate is provided, and a first dielectric layer is formed on the substrate; The first dielectric layer is etched to form a plurality of grooves extending along a first direction within the first dielectric layer. The grooves include a plurality of first sub-segments and a plurality of second sub-segments that are alternately distributed along the first direction. The second sub-segments connect two adjacent first sub-segments. The first direction is parallel to the surface of the substrate. A word line layer, a gate dielectric layer, and a semiconductor layer are formed. The word line layer includes a gate electrode portion located in a first sub-segment and a connection portion located in a second sub-segment. The semiconductor layer includes at least a first sub-layer, which at least covers the top surface of the gate electrode portion. At least a portion of the gate dielectric layer is located between the semiconductor layer and the word line layer. The material of the semiconductor layer includes an oxide semiconductor material.

[0012] In some embodiments, before forming the first dielectric layer on the substrate, the method further includes: A second dielectric layer is formed on a substrate, and a first dielectric layer covers the second dielectric layer; Multiple bit line layers are formed within the second dielectric layer, the bit line layers extend along the second direction, the bottom of the first sub-segment exposes a portion of the bit line layer, and the semiconductor layer is electrically connected to the bit line layer; the second direction intersects the first direction and is parallel to the surface of the substrate.

[0013] In some embodiments, a word line layer, a gate dielectric layer, and a semiconductor layer are formed, including: A second sub-layer is formed within the groove, which covers the sidewalls and bottom surface of the first sub-segment and the portion of the bitline layer exposed at the bottom of the first sub-segment. A first gate dielectric layer and a word line layer are formed in the groove. The first gate dielectric layer at least covers the second sub-layer, and the word line layer covers the first gate dielectric layer and fills the groove. A second gate dielectric layer is formed, which at least covers the top surface of the gate electrode portion and is connected to the first gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer constitute a gate dielectric layer. A first sublayer is formed, at least a portion of which covers the second gate dielectric layer and is connected to the second sublayer to circumferentially surround the gate electrode portion. The first sublayer and the second sublayer constitute a semiconductor layer.

[0014] In some embodiments, before forming the word line layer, the gate dielectric layer, and the semiconductor layer, the method further includes: A conductive layer is formed in the groove, which covers the sidewalls and bottom surface of the first sub-segment and the portion of the bit line layer exposed at the bottom of the first sub-segment. Forming a word line layer, a gate dielectric layer, and a semiconductor layer, including: A first gate dielectric layer and a word line layer are formed in the groove. The first gate dielectric layer at least covers the conductive layer, and the word line layer covers the first gate dielectric layer and fills the groove. A second gate dielectric layer is formed, which at least covers the top surface of the gate electrode portion and is connected to the first gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer constitute a gate dielectric layer. A first sublayer is formed, at least a portion of which covers the second gate dielectric layer and is connected to the conductive layer to circumferentially surround the gate electrode portion.

[0015] In some embodiments, before forming the word line layer, the gate dielectric layer, and the semiconductor layer, the method further includes: A conductive layer is formed in the groove, the conductive layer covering at least a portion of the bottom surface of the first sub-segment or the bottom surface and a portion of the sidewalls of the first sub-segment, and covering a portion of the bit line layer exposed at the bottom of the first sub-segment; Forming a word line layer, a gate dielectric layer, and a semiconductor layer, including: A second sub-layer is formed within the groove, covering the portion of the sidewalls and bottom surface of the first sub-segment that is not covered by the conductive layer; A first gate dielectric layer and a word line layer are formed in the groove. The first gate dielectric layer at least covers the conductive layer and the second sub-layer. The word line layer covers the first gate dielectric layer and fills the groove. A second gate dielectric layer is formed, which at least covers the top surface of the gate electrode portion and is connected to the first gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer constitute a gate dielectric layer. A first sublayer is formed, at least a portion of which covers the second gate dielectric layer. The first sublayer, the second sublayer, and the conductive layer are connected to circumferentially surround the gate electrode portion. The first sublayer and the second sublayer constitute a semiconductor layer.

[0016] In some embodiments, after forming the word line layer, the gate dielectric layer, and the semiconductor layer, the method further includes: A third dielectric layer is formed, which covers the first dielectric layer and the first sublayer; Multiple contact plugs are formed, the contact plugs are located above the gate electrode portion and penetrate the third dielectric layer, and the contact plugs are in contact with a portion of the first sublayer covering the top surface of the gate electrode portion; A fourth dielectric layer is formed on the third dielectric layer, and multiple capacitor structures are formed within the fourth dielectric layer. The multiple capacitor structures are electrically connected to multiple contact plugs in a one-to-one correspondence.

[0017] This disclosure also provides an electronic device, including: A processing device, and a storage device electrically connected to the processing device, wherein at least one of the processing device and the storage device includes a semiconductor structure according to any of the above embodiments.

[0018] In the semiconductor structure provided in this embodiment, the word line layer includes a gate electrode portion, and the semiconductor layer includes a first sub-layer covering at least the top surface of the gate electrode portion. The gate electrode portion, the semiconductor layer covering the gate electrode portion, and the gate dielectric layer located between the gate electrode portion and the semiconductor layer can constitute a transistor. The semiconductor layer is made of an oxide semiconductor material, which can serve as a channel for charge transport. Oxide semiconductor materials have higher carrier mobility and lower leakage current, thus effectively mitigating or eliminating GIDL leakage, improving the transistor's on / off current ratio and current driveability, thereby enhancing the word line layer's driving capability for the transistor, reducing power consumption, and improving the performance of the semiconductor structure. Simultaneously, the semiconductor layer is formed through a deposition process, resulting in less etching damage, which can improve the performance stability of the semiconductor structure.

[0019] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 Some embodiments of this disclosure follow Figure 1 A schematic diagram of the cross-sectional structure taken by line A1A2 in the diagram; Figure 3 Some embodiments of this disclosure follow Figure 1 A schematic diagram of the cross-sectional structure taken by line B1B2 in the diagram; Figure 4 For other embodiments of this disclosure along Figure 1 A schematic diagram of the cross-sectional structure taken by line A1A2 in the diagram; Figure 5 For other embodiments of this disclosure along Figure 1 A schematic diagram of the cross-sectional structure taken by line B1B2 in the diagram; Figure 6 Further embodiments of this disclosure follow Figure 1 A schematic diagram of the cross-sectional structure taken by line A1A2 in the diagram; Figure 7 Further embodiments of this disclosure follow Figure 1 A schematic diagram of the cross-sectional structure taken by line B1B2 in the diagram; Figure 8 A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of this disclosure; Figure 9 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 1 ; Figure 10 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 ; Figure 11 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 3 ; Figure 12 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 4 ; Figure 13 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 5 ; Figure 14 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 6 ; Figure 15 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 7 ; Figure 16 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 8 ; Figure 17 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 9 ; Figure 18 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 ; Figure 19 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 10 one; Figure 20 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 two; Figure 21 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 10 three; Figure 22 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 Four; Figure 23 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 10 five; Figure 24 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 six; Figure 25 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 seven; Figure 26 Top view of the semiconductor structure during manufacturing process provided for other embodiments of this disclosure. Figure 10 eight; Figure 27 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 Nine; Figure 28 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 ten; Figure 29 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 eleven; Figure 30 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure Figure 2 twelve; Figure 31 The semiconductor structure provided in some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 Thirteen; Figure 32 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 2 fourteen; Figure 33 The semiconductor structure provided in some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 fifteen; Figure 34 The semiconductor structure provided in some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 sixteen; Figure 35 This is a structural block diagram of an electronic device provided in some embodiments of the present disclosure. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0024] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0026] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] In the semiconductor structure provided in this embodiment, the word line layer includes a gate electrode portion, and the semiconductor layer includes a first sub-layer covering at least the top surface of the gate electrode portion. The gate electrode portion, the semiconductor layer covering the gate electrode portion, and the gate dielectric layer located between the gate electrode portion and the semiconductor layer can constitute a transistor. The semiconductor layer is made of an oxide semiconductor material, which can serve as a channel for charge transport. Oxide semiconductor materials have higher carrier mobility and lower leakage current, thus effectively mitigating or eliminating GIDL leakage, improving the transistor's on / off current ratio and current driveability, thereby enhancing the word line layer's driving capability for the transistor, reducing power consumption, and improving the performance of the semiconductor structure. Simultaneously, the semiconductor layer is formed through a deposition process, resulting in less etching damage, which can improve the performance stability of the semiconductor structure.

[0029] Based on this, the following technical solutions of the embodiments of this disclosure are proposed. The specific implementation methods of this disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this disclosure, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0030] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0031] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] like Figures 1 to 7 As shown, the semiconductor structure includes: a substrate 10 and a first dielectric layer 13 located on the substrate 10; a plurality of word line layers 16 located within the first dielectric layer 13 and extending along a first direction, the word line layers 16 including a plurality of gate electrode portions 161 spaced apart along the first direction and a connection portion 162 for connecting two adjacent gate electrode portions 161; the first direction is parallel to the surface of the substrate 10; a plurality of semiconductor layers 14, each semiconductor layer 14 including at least a first sublayer 141, the first sublayer 141 at least covering the top surface of the gate electrode portions 161; wherein the material of the semiconductor layers 14 includes an oxide semiconductor material; and a gate dielectric layer 15, at least a portion of the gate dielectric layer 15 being located between the semiconductor layers 14 and the word line layers 16.

[0033] In some embodiments, the material of the substrate 10 may include a semiconductor material, which may include a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art, such as silicon.

[0034] In some embodiments, the semiconductor structure may further include: a second dielectric layer 11 located on the substrate 10, with a first dielectric layer 13 covering the second dielectric layer 11; a plurality of bit line layers 12 located below a plurality of word line layers 16; the bit line layers 12 extending within the second dielectric layer 11 along a second direction and electrically connected to the semiconductor layer 14, the first dielectric layer 13 further covering the plurality of bit line layers 12; wherein the second direction intersects (including perpendicular or oblique) the first direction and is parallel to the surface of the substrate 10.

[0035] In some embodiments, a plurality of bit line layers 12 are arranged at intervals along a first direction within a second dielectric layer 11, and the bit line layers 12 do not completely penetrate the second dielectric layer 11 in the vertical direction, and are separated from the substrate 10 by a portion of the second dielectric layer 11.

[0036] In some embodiments, a plurality of word line layers 16 are arranged at intervals along a second direction within a first dielectric layer 13, and the plurality of word line layers 16 intersect with the plurality of bit line layers 12. A plurality of gate electrode portions 161 may be located at the intersections of the plurality of word line layers 16 and the plurality of bit line layers 12, and are arranged in an array along a first direction and a second direction. A plurality of first sub-layers 141 may also be arranged in an array along the first direction and a second direction, and each sub-layer covers the plurality of gate electrode portions 161.

[0037] like Figure 1 As shown, in some embodiments, multiple first sub-layers 141 may be spaced apart from each other in the first and second directions. However, this is not a limitation; the multiple first sub-layers 141 arranged along the second direction may also be connected sequentially to increase scenario applicability.

[0038] In some embodiments, the materials of bit line layer 12 and word line layer 16 may each independently include tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), metal alloys, or any combination thereof.

[0039] In some embodiments, the materials of the first dielectric layer 13 and the second dielectric layer 11 may each independently include at least one of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), and carbides (e.g., silicon carbide).

[0040] In some embodiments, the material of the semiconductor layer 14 includes an oxide semiconductor material, which may include at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, zinc oxide, tin oxide, indium oxide, and indium tin zinc oxide.

[0041] However, this is not the only category; oxide semiconductor materials can also include Al-Zn oxides, In-Ga oxides, In-Ga-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, and In-Gd-Zn oxides. The oxides include, but are not limited to, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, and In-Lu-Zn ​​oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides.

[0042] In this embodiment, the word line layer 16 includes a gate electrode portion 161, and the semiconductor layer 14 includes a first sub-layer 141 covering at least the top surface of the gate electrode portion 161. The gate electrode portion 161, the semiconductor layer 14 covering the gate electrode portion 161, and the gate dielectric layer 15 located between the gate electrode portion 161 and the semiconductor layer 14 can constitute a transistor. The material of the semiconductor layer 14 includes an oxide semiconductor material, which can serve as a channel for transmitting charge. The oxide semiconductor material has higher carrier mobility and lower leakage current, thus effectively mitigating or eliminating GIDL leakage, improving the transistor's on / off current ratio and current driveability, thereby improving the driving capability of the word line layer 16 for the transistor, reducing power consumption, and improving the performance of the semiconductor structure. At the same time, the semiconductor layer is formed by a deposition process, with less etching damage, which can improve the performance stability of the semiconductor structure.

[0043] like Figures 2 to 3 As shown, in some embodiments, the semiconductor layer 14 may further include a second sub-layer 142, which covers the sidewall and bottom surface of the gate electrode portion 161. The second sub-layer 142 is connected to the first sub-layer 141 to circumferentially surround the gate electrode portion 161, and the bit line layer 12 is in contact with a portion of the second sub-layer 142 located on the bottom surface of the word line layer 16.

[0044] Here and in the following text, "around the circumferential direction of the gate electrode portion 161" means "around the gate electrode portion 161 along the outline of its cross-section in the vertical direction". The outline of the cross-section of the gate electrode portion 161 in the vertical direction can be a regular shape such as a rectangle or other irregular shapes.

[0045] Here and in the following text, the sidewall of the gate electrode portion 161 may refer to the sidewall of the gate electrode portion 161 in the second direction.

[0046] In some embodiments, there are multiple second sub-layers 142, and the multiple second sub-layers 142 cover the bottom surface and sidewalls of multiple gate electrode portions 161 in a one-to-one correspondence; in a first direction, the multiple second sub-layers 142 corresponding to the multiple gate electrode portions 161 of a word line layer 16 are distributed at intervals.

[0047] In some embodiments, the width of the gate electrode portion 161 in the first direction may be greater than or equal to the width of the bit line layer 12 in the first direction. Either side boundary of the gate electrode portion 161 in the first direction may be flush with the sidewall of the bit line layer 12 in the first direction, or protrude outward relative to the sidewall of the bit line layer 12 in the first direction. This allows for the addition of a second sub-layer 142 and / or a conductive layer (such as...). Figures 4 to 7 The portion located on the bottom surface of the gate electrode portion 161 has a contact area with the bit line layer 12, thereby reducing the contact resistance.

[0048] However, it is not limited to this. The width of the gate electrode portion 161 in the first direction can also be smaller than the width of the bit line layer 12 in the first direction to increase the applicability of different scenarios.

[0049] like Figures 2 to 3 As shown, in some embodiments, the gate dielectric layer 15 may include a first gate dielectric layer 151 and a second gate dielectric layer 152. The first gate dielectric layer 151 at least covers the bottom surface and sidewalls of the gate electrode portion 161 and may be sandwiched between the second sublayer 142 and the gate electrode portion 161. The second gate dielectric layer 152 at least covers the top surface of the gate electrode portion 161 and the top surface of the portion of the first gate dielectric layer 151 located on the sidewalls of the gate electrode portion 161, and may be sandwiched between the first sublayer 141 and the gate electrode portion 161. The first gate dielectric layer 151 and the second gate dielectric layer 152 are connected and surround the gate electrode portion 161 circumferentially.

[0050] In some embodiments, the first gate dielectric layer 151 may also cover the bottom surface and sidewalls of the word line layer 16 that are not covered by the second sub-layer 142, i.e. the bottom surface and sidewalls of the connection portion 162, thereby increasing the isolation performance between the connection portion 162 and the bit line layer 12 and avoiding short circuits.

[0051] In some embodiments, the second gate dielectric layer 152 may also cover at least a portion of the top surface of the connection portion 162, and the second gate dielectric layer 152 covering the top surface of the plurality of gate electrode portions 161 may also be connected sequentially along the first direction. In this way, it can provide better isolation between the first sub-layer 141 and the word line layer 16 and expand the process window.

[0052] In some embodiments, the gate dielectric layer 15 is made of a high dielectric constant material, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. Using a high dielectric constant material as the gate dielectric layer 15 in this embodiment can further improve the current-driven capability of the transistor.

[0053] like Figure 2 and Figure 3 As shown, in some embodiments, the first sublayer 141 at least covers the top surface of the gate electrode portion 161 and the top surface of the portion of the second sublayer 142 located on the sidewall of the gate electrode portion 161, so as to connect the second sublayer 142.

[0054] In some embodiments, the sidewall of the first sublayer 141 in the second direction may protrude outward relative to the edge of the second sublayer 142 in the second direction, and the first sublayer 141 may also cover part of the first dielectric layer 13. This can help to electrically connect the first sublayer 141 and the second sublayer 142 and expand the process window.

[0055] However, this is not the only one. In some other embodiments of this disclosure, the sidewall of the first sublayer 141 in the second direction may also be flush with the edge of the second sublayer 142 in the second direction to increase the applicability of different scenarios.

[0056] In some embodiments, the first sublayer 141 may also cover a portion of the connection portion 162, and the first sublayer 141 and the connection portion 162 are also separated by a portion of the second gate dielectric layer 152.

[0057] In this embodiment of the disclosure, the semiconductor layer 14 includes a first sub-layer 141 and a second sub-layer 142 that are connected to each other and surround the gate electrode portion 161 in the circumferential direction. By providing the semiconductor layer 14 to surround the gate electrode portion 161 in the circumferential direction, the channel length of the transistor can be increased, thereby further enhancing the gate control capability of the word line layer 16 and further reducing the leakage current.

[0058] like Figures 2 to 3As shown, in some embodiments, the semiconductor structure may further include: a third dielectric layer 17 located on the first dielectric layer 13 and covering the first sublayer 141; a plurality of contact plugs 18 located above the gate electrode portion 161 and penetrating the third dielectric layer 17, the contact plugs 18 being in contact with a portion of the first sublayer 141 covering the top surface of the gate electrode portion 161; a fourth dielectric layer 19 located on the third dielectric layer 17; and a plurality of capacitor structures 21 located within the fourth dielectric layer 19 and electrically connected to the plurality of contact plugs 18 one-to-one.

[0059] In some embodiments, the materials of the third dielectric layer 17 and the fourth dielectric layer 19 may each independently include at least one of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), and carbides (e.g., silicon carbide).

[0060] In some embodiments, the capacitor structure 21 is used to store data. The capacitor structure 21 can be a single-sided capacitor or a double-sided capacitor, and this disclosure does not make any special limitation in this regard.

[0061] In this embodiment, the gate electrode portion 161, the semiconductor layer 14 covering the gate electrode portion 161, and the gate dielectric layer 15 located between the gate electrode portion 161 and the semiconductor layer 14 can constitute a transistor. This transistor and the capacitor structure 21 electrically connected to it together form a memory cell. Multiple bit line layers 12 and multiple word line layers 16 intersect each other perpendicularly in space, and the memory cells are disposed at each intersection node, thus forming a square array arrangement. Simultaneously, the bit line layers 12, transistors, and capacitor structures 21 are stacked sequentially along a direction perpendicular to the substrate 10. Through this three-dimensional integrated architecture, the density of memory cells can be effectively increased, thereby improving the overall integration of the semiconductor structure.

[0062] Figure 2 and Figure 3 The bit line layer 12 shown is in contact with the second sub-layer 142, and the semiconductor layer 14 surrounds the gate electrode portion 161 in the circumferential direction.

[0063] However, this is not the only one. In other embodiments of this disclosure, the semiconductor structure may also include a conductive layer 22, and the bit line layer 12 may be in contact with at least a portion of the semiconductor layer 14. The semiconductor layer 14 and the conductive layer 22 may be connected to surround the gate electrode portion 161 in the circumferential direction.

[0064] Specifically, such as Figures 4 to 5As shown, the conductive layer 22 can cover at least a portion of the bottom surface of the gate electrode portion 161 or cover the bottom surface and a portion of the sidewalls of the gate electrode portion 161; the second sub-layer 142 of the semiconductor layer 14 covers the portion of the sidewalls and bottom surface of the gate electrode portion 161 that is not covered by the conductive layer 22; the second sub-layer 142, the first sub-layer 141, and the conductive layer 22 are connected to surround the gate electrode portion 161 circumferentially; a portion of the gate dielectric layer 15 is located between the word line layer 16 and the conductive layer 22; and the bit line layer 12 is in contact with at least a portion of the conductive layer 22 located on the bottom surface of the word line layer 16.

[0065] In some embodiments, the material of the conductive layer 22 may include tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicides (WSix, CoSix, NiSix, AlSix, etc.), metal alloys, or any combination thereof, such as titanium nitride.

[0066] In some embodiments, the conductive layer 22 may cover a portion of the bottom surface of the gate electrode portion 161, and the second sub-layer 142 may cover the sidewalls and a portion of the bottom surface of the gate electrode portion 161; or, the conductive layer 22 may completely cover the bottom surface of the gate electrode portion 161 without covering the sidewalls of the gate electrode portion 161, and the second sub-layer 142 may cover the sidewalls of the gate electrode portion 161; or, the conductive layer 22 may cover the bottom surface and a portion of the sidewalls of the gate electrode portion 161, and the second sub-layer 142 may cover a portion of the sidewalls of the gate electrode portion 161.

[0067] In some embodiments, the bit line layer 12 may only be in contact with the conductive layer 22, or the bit line layer 12 may be in contact with both the conductive layer 22 and a portion of the second sub-layer 142.

[0068] In some embodiments, the first gate dielectric layer 151 may also cover the portion of the bottom surface and sidewalls of the word line layer 16 that is not covered by the conductive layer 22 and the second sub-layer 142.

[0069] In this embodiment, the first sub-layer 141 and the second sub-layer 142 are connected and partially surround the gate electrode portion 161 in the circumferential direction, thereby shortening the channel length of the transistor, increasing the on-state drive current of the transistor, meeting the requirements of high-frequency applications, and by adjusting the area of ​​the conductive layer 22, the length of the semiconductor layer 14 covering the gate electrode portion 161 in the circumferential direction can be flexibly adjusted, thereby achieving the purpose of flexibly adjusting the channel length of the transistor, thus increasing the applicability of scenarios.

[0070] Figures 4 to 5 The conductive layer 22 shown does not completely cover the sidewalls and bottom surface of the gate electrode portion 161. However, it is not limited to this, as shown in... Figures 6 to 7As shown, in some embodiments of this disclosure, the conductive layer 22 may cover the bottom surface and sidewalls of the gate electrode portion 161, the first sub-layer 141 and the conductive layer 22 are connected to surround the gate electrode portion 161 circumferentially, a portion of the gate dielectric layer 15 is located between the word line layer 16 and the conductive layer 22, and the bit line layer 12 is in contact with at least a portion of the conductive layer 22 located on the bottom surface of the word line layer 16. Thus, the bit line layer 12 can be electrically connected to the first sub-layer 141 through the conductive layer 22.

[0071] In some embodiments, the first gate dielectric layer 151 may also cover the portion of the sidewall and bottom surface of the word line layer 16 that is not covered by the conductive layer 22, and the first sub-layer 141 may also cover the top surface of the portion of the conductive layer 22 located on the sidewall of the gate electrode portion 161.

[0072] In some embodiments, the sidewall of the first sublayer 141 in the second direction may protrude outward relative to the edge of the conductive layer 22 in the second direction, which can help to electrically connect the first sublayer 141 and the conductive layer 22 and expand the process window.

[0073] However, this is not the only one. In other embodiments of this disclosure, the sidewall of the first sublayer 141 in the second direction may also be flush with the edge of the conductive layer 22 in the second direction to increase the applicability of different scenarios.

[0074] In this embodiment, the semiconductor layer 14 is located above the plane containing the top surfaces of the first dielectric layer 13 and the word line layer 16. There is no need to form a second sub-layer 142 within the first dielectric layer 13. The formation process of the semiconductor layer 14 is simple, and it has better uniformity and performance consistency, thereby increasing the reliability of the semiconductor device.

[0075] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 8 As shown, the manufacturing method includes the following steps: Step S101: Provide a substrate and form a first dielectric layer on the substrate; Step S102: Etch the first dielectric layer to form a plurality of grooves extending along a first direction within the first dielectric layer. The grooves include a plurality of first sub-segments and a plurality of second sub-segments that are alternately distributed along the first direction. The second sub-segments connect two adjacent first sub-segments. The first direction is parallel to the surface of the substrate. Step S103: Forming a word line layer, a gate dielectric layer, and a semiconductor layer. The word line layer includes a gate electrode portion located in a first sub-segment and a connection portion located in a second sub-segment. The semiconductor layer includes at least a first sub-layer, which at least covers the top surface of the gate electrode portion. At least a portion of the gate dielectric layer is located between the semiconductor layer and the word line layer. The material of the semiconductor layer includes an oxide semiconductor material.

[0076] The manufacturing method provided by the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings. Figure 15 The second dielectric layer is omitted. Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 26 , Figure 30 as well as Figure 32 The first and second dielectric layers are omitted.

[0077] First, execute step S101, as follows: Figures 13 to 14 As shown, a substrate 10 is provided, and a first dielectric layer 13 is formed on the substrate 10.

[0078] like Figures 9 to 12 As shown, in some embodiments, before forming the first dielectric layer 13 on the substrate 10, the method may further include: A second dielectric layer 11 is formed on the substrate 10 (e.g., Figures 9 to 10 ); Multiple bit line layers 12 are formed within the second dielectric layer 11, and the bit line layers 12 extend along the second direction (e.g. Figures 11 to 12 ).

[0079] See you again Figures 11 to 12 In some embodiments, the bit line layer 12 can be formed by the following method: First, the second dielectric layer 11 can be etched to form a plurality of trenches T in the second dielectric layer 11, the trenches T not completely penetrating the second dielectric layer 11, and being separated from the substrate 10 by a portion of the second dielectric layer 11; then, a plurality of bit line layers 12 are formed in the plurality of trenches T, the plurality of bit line layers 12 being spaced apart along a first direction; wherein, the second direction intersects the first direction (including perpendicular or oblique) and is parallel to the surface of the substrate 10.

[0080] like Figures 13 to 14 As shown, in some embodiments, the first dielectric layer 13 covers the second dielectric layer 11 and a plurality of bit line layers 12.

[0081] The materials of the substrate 10, the first dielectric layer 13, the second dielectric layer 11, and the bit line layer 12 are as described above and will not be repeated here.

[0082] Next, proceed to step S102, as follows: Figures 15 to 16 As shown, the first dielectric layer 13 is etched to form a plurality of grooves S extending along a first direction within the first dielectric layer 13. The grooves S include a plurality of first sub-segments S1 and a plurality of second sub-segments S2 that are alternately distributed along the first direction. The second sub-segments S2 connect two adjacent first sub-segments S1. The first direction is parallel to the surface of the substrate 10.

[0083] like Figures 15 to 16As shown, in some embodiments, a plurality of grooves S can be arranged at intervals along the second direction, the plurality of grooves S intersect with a plurality of bit line layers 12, a first sub-segment S1 can be located at the intersection of the grooves S and the bit line layers 12, the plurality of first sub-segments S1 can be arranged in an array along the first direction and the second direction, and the bottom of the first sub-segment S1 exposes part of the bit line layer 12.

[0084] In some embodiments, the width of the first segment S1 in the first direction may be greater than or equal to the width of the bit line layer 12 in the first direction. Any edge of the first segment S1 in the first direction may be flush with the sidewall of the bit line layer 12 in the first direction, or protrude outward relative to the sidewall of the bit line layer 12 in the first direction. Thus, the bottom of the first segment S1 can fully expose the bit line layer 12, allowing for the subsequent addition of a second sublayer 142 formed within the first segment S1 (see...). Figure 18 ) or conductive layer 22 (see Figure 27 This reduces the contact area between the layer 12 and the bit line layer, thereby reducing the contact resistance.

[0085] However, it is not limited to this. The width of the first sub-segment S1 in the first direction can also be smaller than the width of the bit line layer 12 in the first direction to increase the applicability of different scenarios.

[0086] Next, proceed to step S103, as follows: Figures 17 to 24 as well as Figure 1 and Figure 25 As shown, a word line layer 16, a gate dielectric layer 15, and a semiconductor layer 14 are formed. The word line layer 16 includes a gate electrode portion 161 located in a first sub-segment S1 and a connection portion 162 located in a second sub-segment S2. The semiconductor layer 14 includes at least a first sub-layer 141, which at least covers the top surface of the gate electrode portion 161. At least a portion of the gate dielectric layer 15 is located between the semiconductor layer 14 and the word line layer 16. The material of the semiconductor layer 14 includes an oxide semiconductor material.

[0087] In practical applications, the material of the semiconductor layer 14 may include one or more oxide semiconductor materials as described above, and the semiconductor layer 14 may be formed by one or more thin film deposition processes. The thin film deposition processes may include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0088] In this embodiment, the word line layer 16 includes a gate electrode portion 161, and the semiconductor layer 14 includes a first sub-layer 141 covering at least the top surface of the gate electrode portion 161. The gate electrode portion 161, the semiconductor layer 14 covering the gate electrode portion 161, and the gate dielectric layer 15 located between the gate electrode portion 161 and the semiconductor layer 14 can constitute a transistor. The material of the semiconductor layer 14 includes an oxide semiconductor material, which can serve as a channel for transmitting charge. The oxide semiconductor material has higher carrier mobility and lower leakage current, thus effectively mitigating or eliminating GIDL leakage, improving the transistor's on / off current ratio and current driveability, thereby improving the driving capability of the word line layer 16 for the transistor, reducing power consumption, and improving the performance of the semiconductor structure. At the same time, the semiconductor layer is formed by a deposition process, with less etching damage, which can improve the performance stability of the semiconductor structure.

[0089] See you again Figures 17 to 24 as well as Figure 1 and Figure 25 In some embodiments, forming the word line layer 16, the gate dielectric layer 15, and the semiconductor layer 14 may include: A second sub-layer 142 is formed within the groove S, covering the sidewalls and bottom surface of the first sub-segment S1, and also covering the portion of the bitline layer 12 exposed at the bottom of the first sub-segment S1 (e.g., ...). Figures 17 to 18 ); A first gate dielectric layer 151 and a word line layer 16 are formed within the groove S. The first gate dielectric layer 151 at least covers the second sublayer 142, and the word line layer 16 covers the first gate dielectric layer 151 and fills the groove S (e.g., ...). Figures 19 to 22 ); A second gate dielectric layer 152 is formed, which at least covers the top surface of the gate electrode portion 161 and is connected to the first gate dielectric layer 151. The first gate dielectric layer 151 and the second gate dielectric layer 152 constitute the gate dielectric layer 15 (e.g., Figures 23 to 24 ); A first sublayer 141 is formed, at least a portion of which covers the second gate dielectric layer 152 and is connected to the second sublayer 142 to circumferentially surround the gate electrode portion 161. The first sublayer 141 and the second sublayer 142 constitute a semiconductor layer 14 (e.g., Figure 1 and Figure 25 ).

[0090] Here and in the following text, the sidewall of the first sub-segment S1 may refer to the sidewall of the first sub-segment S1 in the second direction.

[0091] like Figures 17 to 18As shown, there are multiple second sub-layers 142, which are arranged in an array along the first and second directions to cover the bottom and sidewalls of multiple first segments S1 respectively. The second sub-layers 142 are electrically connected to the bit line layer 12, thereby realizing the electrical connection between the semiconductor layer 14 and the bit line layer 12.

[0092] like Figures 19 to 20 As shown, in some embodiments, the first gate dielectric layer 151 may also cover the inner surface of the groove S not covered by the second sub-layer 142, i.e. the inner surface of the second sub-segment S2, thereby increasing the isolation performance between the connection portion 162 formed in the second sub-segment S2 and the bit line layer 12 and avoiding short circuits.

[0093] like Figures 21 to 22 As shown, in some embodiments, the word line layer 16 fills the space of the groove S that is not filled by the second sub-layer 142 and the first gate dielectric layer 151, and a plurality of gate electrode portions 161 are located at the intersection of a plurality of word line layers 16 and a plurality of bit line layers 12, and are arranged in an array along a first direction and a second direction.

[0094] like Figure 23 and Figure 24 As shown, in some embodiments, the second gate dielectric layer 152 at least covers the top surface of the gate electrode portion 161 and the top surface of the portion of the first gate dielectric layer 151 located on the sidewall of the first sub-segment S1, so as to connect the first gate dielectric layer 151 and expose the top surface of the second sub-layer 142.

[0095] In some embodiments, the second gate dielectric layer 152 may also cover at least a portion of the top surface of the connection portion 162, and the second gate dielectric layer 152 covering the top surface of the plurality of gate electrode portions 161 may also be connected sequentially along the first direction. In this way, it can provide better isolation between the first sub-layer 141 and the word line layer 16 and expand the process window.

[0096] like Figure 1 and Figure 25 As shown, in some embodiments, the first sublayer 141 at least covers the top surface of the gate electrode portion 161 and the top surface of the portion of the second sublayer 142 located on the sidewall of the first sub-segment S1, so as to connect the second sublayer 142.

[0097] In some embodiments, the sidewall of the first sublayer 141 in the second direction may protrude outward relative to the edge of the second sublayer 142 in the second direction, and the first sublayer 141 may also cover part of the first dielectric layer 13. This can help to electrically connect the first sublayer 141 and the second sublayer 142 and expand the process window.

[0098] However, this is not the only one. In some other embodiments of this disclosure, the sidewall of the first sublayer 141 in the second direction may also be flush with the edge of the second sublayer 142 in the second direction to increase the applicability of different scenarios.

[0099] In some embodiments, the first sublayer 141 may also cover a portion of the connection portion 162, and the first sublayer 141 and the connection portion 162 are also separated by a portion of the second gate dielectric layer 152.

[0100] like Figure 1 and Figure 25 As shown, in some embodiments, multiple first sub-layers 141 can be arranged in an array along a first direction and a second direction, with each of the multiple first sub-layers 141 corresponding to a multiple gate electrode portions 161 and spaced apart from each other. However, this is not a limitation; the multiple first sub-layers 141 arranged along the second direction can also be connected sequentially to increase the applicability of different scenarios.

[0101] In this embodiment of the disclosure, the semiconductor layer 14 includes a first sub-layer 141 and a second sub-layer 142 that are connected to each other and surround the gate electrode portion 161 in the circumferential direction. By providing the semiconductor layer 14 to surround the gate electrode portion 161 in the circumferential direction, the channel length of the transistor can be increased, thereby further enhancing the gate control capability of the word line layer 16 and further reducing the leakage current.

[0102] Next, as Figure 2 As shown, after forming the word line layer 16, the gate dielectric layer 15, and the semiconductor layer 14, the method may further include: A third dielectric layer 17 is formed, which covers the first dielectric layer 13 and the first sublayer 141. Multiple contact plugs 18 are formed, the contact plugs 18 are located above the gate electrode portion 161 and penetrate the third dielectric layer 17, and the contact plugs 18 are in contact with the portion of the first sublayer 141 covering the top surface of the gate electrode portion 161. A fourth dielectric layer 19 is formed on the third dielectric layer 17, and a plurality of capacitor structures 21 are formed within the fourth dielectric layer 19. The plurality of capacitor structures 21 are electrically connected to a plurality of contact plugs 18 in a one-to-one correspondence.

[0103] The materials of the third dielectric layer 17 and the fourth dielectric layer 19 have been described previously and will not be repeated here.

[0104] In some embodiments, the capacitor structure 21 is used to store data. The capacitor structure 21 can be a single-sided capacitor or a double-sided capacitor, and this disclosure does not make any special limitation in this regard.

[0105] In this embodiment, the gate electrode portion 161, the semiconductor layer 14 covering the gate electrode portion 161, and the gate dielectric layer 15 located between the gate electrode portion 161 and the semiconductor layer 14 can constitute a transistor. This transistor and the capacitor structure 21 electrically connected to it together form a memory cell. Multiple bit line layers 12 and multiple word line layers 16 intersect each other perpendicularly in space, and the memory cells are disposed at each intersection node, thus forming a square array arrangement. Simultaneously, the bit line layers 12, transistors, and capacitor structures 21 are stacked sequentially along a direction perpendicular to the substrate 10. Through this three-dimensional integrated architecture, the density of memory cells can be effectively increased, thereby improving the overall integration of the semiconductor structure.

[0106] Figures 17 to 25 as well as Figures 2 to 3 The second sublayer 142 shown covers the portion of the bit line layer 12 exposed by the first segment S1 of the recess S, and the bit line layer 12 is electrically connected to the second sublayer 142. However, this is not the only possibility. Figures 26 to 29 ,as well as Figures 4 to 5 As shown, in some other embodiments of this disclosure, a conductive layer 22 may also be formed, which may be connected to the semiconductor layer 14 to circumferentially surround the gate electrode portion 161, and the bit line layer 12 may also be electrically connected to the semiconductor layer 14 through the conductive layer 22.

[0107] Specifically, such as Figures 26 to 27 As shown, in some embodiments, before forming the word line layer 16, the gate dielectric layer 15, and the semiconductor layer 14, the method may further include: forming a conductive layer 22 in the groove S, the conductive layer 22 covering at least a portion of the bottom surface of the first sub-segment S1 or the bottom surface and a portion of the sidewalls of the first sub-segment S1, and covering a portion of the bit line layer 12 exposed at the bottom of the first sub-segment S1, such that the bit line layer 12 is electrically connected to the conductive layer 22.

[0108] See you again Figures 26 to 27 In some embodiments, forming the word line layer 16, the gate dielectric layer 15, and the semiconductor layer 14 may include: after forming the conductive layer 22, forming a second sub-layer 142 in the recess S, the second sub-layer 142 covering the portion of the sidewalls and bottom surface of the first sub-segment S1 not covered by the conductive layer 22 (e.g., Figures 26 to 27 ).

[0109] In some embodiments, the conductive layer 22 may cover a portion of the bottom surface of the first sub-segment S1, and the second sub-layer 142 may cover the sidewalls and a portion of the bottom surface of the first sub-segment S1; or, the conductive layer 22 may completely cover the bottom surface of the first sub-segment S1 without covering the sidewalls of the first sub-segment S1, and the second sub-layer 142 may cover the sidewalls of the first sub-segment S1; or, the conductive layer 22 may cover the bottom surface and a portion of the sidewalls of the first sub-segment S1, and the second sub-layer 142 may cover a portion of the sidewalls of the first sub-segment S1.

[0110] In some embodiments, the conductive layer 22 may cover the portion of the bit line layer 12 exposed by the first sub-segment S1, and the bit line layer 12 may be electrically connected to the second sub-layer 142 through the conductive layer 22; or, the conductive layer 22 and the second sub-layer 142 may simultaneously cover the portion of the bit line layer 12 exposed by the first sub-segment S1, and the bit line layer 12 may simultaneously be in contact with the conductive layer 22 and a portion of the second sub-layer 142.

[0111] Next, see Figures 28 to 29 As shown, the formation of word line layer 16, gate dielectric layer 15, and semiconductor layer 14 may further include: After the second sublayer 142 is formed, a first gate dielectric layer 151 and a word line layer 16 are formed in the groove S. The first gate dielectric layer 151 at least covers the conductive layer 22 and the second sublayer 142, and the word line layer 16 covers the first gate dielectric layer 151 and fills the groove S. A second gate dielectric layer 152 is then formed, which at least covers the top surface of the gate electrode portion 161 and is connected to the first gate dielectric layer 151. The first gate dielectric layer 151 and the second gate dielectric layer 152 constitute the gate dielectric layer 15 (e.g., ...). Figure 28 ); A first sublayer 141 is formed, at least partially covering the second gate dielectric layer 152. The first sublayer 141, the second sublayer 142, and the conductive layer 22 are connected to circumferentially surround the gate electrode portion 161. The first sublayer 141 and the second sublayer 142 constitute a semiconductor layer 14 (e.g., ...). Figure 29 ).

[0112] In some embodiments, the first gate dielectric layer 151 may also cover the portion of the inner wall of the groove S that is not covered by the conductive layer 22 and the second sub-layer 142.

[0113] In this embodiment, the first sub-layer 141 and the second sub-layer 142 are connected and partially surround the gate electrode portion 161 in the circumferential direction, thereby shortening the channel length of the transistor, increasing the on-state drive current of the transistor, meeting the requirements of high-frequency applications, and by adjusting the area of ​​the conductive layer 22, the length of the semiconductor layer 14 covering the gate electrode portion 161 in the circumferential direction can be flexibly adjusted, thereby achieving the purpose of flexibly adjusting the channel length of the transistor, thus increasing the applicability of scenarios.

[0114] Next, as Figure 4 and Figure 5 As shown, a third dielectric layer 17, multiple contact plugs 18, a fourth dielectric layer 19, and multiple capacitor structures 21 are formed.

[0115] Figures 26 to 29 as well as Figures 4 to 5 The conductive layer 22 shown does not completely cover the inner wall of the first sub-segment S1. However, it is not limited to this, as shown in... Figures 30 to 34 as well as Figures 6 to 7As shown, in some other embodiments of this disclosure, the conductive layer 22 may also completely cover the inner wall of the first segment S1.

[0116] Specifically, such as Figures 30 to 31 As shown, before forming the word line layer 16, the gate dielectric layer 15, and the semiconductor layer 14, the method may further include: forming a conductive layer 22 in the groove S, the conductive layer 22 covering the sidewalls and bottom surface of the first sub-segment S1, and covering the portion of the bit line layer 12 exposed at the bottom of the first sub-segment S1.

[0117] In some embodiments, there may be multiple conductive layers 22, which are arranged in an array along a first direction and a second direction and correspond one-to-one with multiple first segments S1.

[0118] Next, as Figures 32 to 34 As shown, the formation of word line layer 16, gate dielectric layer 15, and semiconductor layer 14 may include: After forming the conductive layer 22, a first gate dielectric layer 151 and a word line layer 16 are formed in the groove S. The first gate dielectric layer 151 at least covers the conductive layer 22, and the word line layer 16 covers the first gate dielectric layer 151 and fills the groove S. A second gate dielectric layer 152 is formed, which at least covers the top surface of the gate electrode portion 161 and is connected to the first gate dielectric layer 151. The first gate dielectric layer 151 and the second gate dielectric layer 152 constitute the gate dielectric layer 15 (e.g., ...). Figures 32 to 33 ); A first sublayer 141 is formed, at least partially covering the second gate dielectric layer 152 and connected to the conductive layer 22 to circumferentially surround the gate electrode portion 161 (e.g. Figure 34 ).

[0119] In some embodiments, the first gate dielectric layer 151 may also cover the portion of the inner surface of the groove S that is not covered by the conductive layer 22, and the second gate dielectric layer 152 exposes the top surface of the portion of the conductive layer 22 located on the sidewall of the first sub-segment S1.

[0120] In some embodiments, bit line layer 12 is electrically connected to first sub-layer 141 through conductive layer 22. The sidewall of first sub-layer 141 in the second direction can protrude outward relative to the edge of conductive layer 22 in the second direction. This can help to electrically connect first sub-layer 141 and conductive layer 22 and expand the process window.

[0121] However, this is not the only one. In some other embodiments of this disclosure, the sidewall of the first sublayer 141 in the second direction may also be flush with the edge of the conductive layer 22 in the second direction to increase the applicability of different scenarios.

[0122] In this embodiment, the semiconductor layer 14 is located above the plane containing the top surfaces of the first dielectric layer 13 and the word line layer 16. There is no need to form a second sub-layer 142 in the groove S. The formation process of the semiconductor layer 14 is simple, and it has better uniformity and performance consistency, thereby increasing the reliability of the semiconductor device.

[0123] Next, as Figure 6 and Figure 7 As shown, a third dielectric layer 17, multiple contact plugs 18, a fourth dielectric layer 19, and multiple capacitor structures 21 are formed.

[0124] like Figure 35 As shown, this disclosure also provides an electronic device 30 with a storage function. The electronic device 30 includes a processing device 31 and a storage device 32 electrically connected to the processing device 31. At least one of the processing device 31 and the storage device 32 includes a semiconductor structure as provided in any of the above embodiments.

[0125] In some embodiments, the processing device 31 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc.; the storage device 32 may be configured to store data to be processed by the processing device 31 and / or data processed by the processing device 31.

[0126] In some embodiments, the processing device 31 and the memory device 32 can be two separate chips forming an independent memory. In other embodiments, the processing device 31 and the memory device 32 can also be integrated into the same chip to form an embedded memory.

[0127] In some embodiments, the electronic device 30 can be a terminal device, such as a personal computer, mobile phone, tablet computer, consumer electronics such as smart home appliances, autonomous vehicles, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or a server, data center, etc. This electronic device 30 can solve the same technical problems and achieve the same expected results as the semiconductor structure provided in any of the above embodiments.

[0128] The technical features described in the above embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0129] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate and a first dielectric layer located on the substrate; Multiple word line layers are located within the first dielectric layer and extend along a first direction. Each word line layer includes multiple gate electrode portions spaced apart along the first direction and a connection portion for connecting two adjacent gate electrode portions. The first direction is parallel to the surface of the substrate. Multiple semiconductor layers, each semiconductor layer including at least a first sublayer, the first sublayer at least covering the top surface of the gate electrode portion; The semiconductor layer is made of an oxide semiconductor material; A gate dielectric layer, at least a portion of which is located between the semiconductor layer and the word line layer; wherein... The semiconductor structure further includes a conductive layer connected to the semiconductor layer to circumferentially surround the gate electrode portion, and a portion of the gate dielectric layer is also located between the conductive layer and the word line layer.

2. The semiconductor structure according to claim 1, characterized in that, The oxide semiconductor material includes at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, zinc oxide, tin oxide, indium oxide, and indium tin zinc oxide.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A second dielectric layer is located on the substrate, and the first dielectric layer covers the second dielectric layer; Multiple bit line layers are located below the multiple word line layers; the bit line layers extend within the second dielectric layer along a second direction and are electrically connected to the semiconductor layer; the second direction intersects the first direction and is parallel to the surface of the substrate.

4. The semiconductor structure according to claim 3, characterized in that, The conductive layer covers the bottom surface and sidewalls of the gate electrode portion, the first sub-layer is connected to the conductive layer to circumferentially surround the gate electrode portion, and the bit line layer is in contact with at least a portion of the conductive layer located on the bottom surface of the word line layer.

5. The semiconductor structure according to claim 3, characterized in that, The conductive layer covers at least a portion of the bottom surface of the gate electrode portion or covers the bottom surface and a portion of the sidewalls of the gate electrode portion; The semiconductor layer further includes a second sub-layer that covers the portion of the sidewall and bottom surface of the gate electrode portion that is not covered by the conductive layer. The second sub-layer, the first sub-layer, and the conductive layer are connected to circumferentially surround the gate electrode portion. The bit line layer is in contact with at least a portion of the conductive layer located on the bottom surface of the word line layer.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure also includes: A third dielectric layer is located on the first dielectric layer and covers the first sublayer; Multiple contact plugs are located above the gate electrode portion and penetrate the third dielectric layer. The contact plugs are in contact with a portion of the first sublayer covering the top surface of the gate electrode portion. The fourth dielectric layer is located on the third dielectric layer; Multiple capacitor structures are located within the fourth dielectric layer and are electrically connected to each of the multiple contact plugs.

7. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, and a first dielectric layer is formed on the substrate; The first dielectric layer is etched to form a plurality of grooves extending along a first direction within the first dielectric layer. The grooves include a plurality of first sub-segments and a plurality of second sub-segments that are alternately distributed along the first direction, and the second sub-segments connect two adjacent first sub-segments. The first direction is parallel to the surface of the substrate. A word line layer, a gate dielectric layer, and a semiconductor layer are formed. The word line layer includes a gate electrode portion located in a first sub-segment and a connection portion located in a second sub-segment. The semiconductor layer includes at least a first sub-layer, which at least covers the top surface of the gate electrode portion. At least a portion of the gate dielectric layer is located between the semiconductor layer and the word line layer. The semiconductor layer is made of an oxide semiconductor material; wherein... The method further includes: forming a conductive layer connected to the semiconductor layer to circumferentially surround the gate electrode portion, wherein a portion of the gate dielectric layer is also located between the conductive layer and the word line layer.

8. The manufacturing method according to claim 7, characterized in that, Before forming the first dielectric layer on the substrate, the method further includes: A second dielectric layer is formed on the substrate, wherein the first dielectric layer covers the second dielectric layer; A plurality of bit line layers are formed within the second dielectric layer, the bit line layers extending along a second direction, the bottom of the first sub-segment exposing a portion of the bit line layers, and the semiconductor layer being electrically connected to the bit line layers; the second direction intersects the first direction and is parallel to the surface of the substrate.

9. The manufacturing method according to claim 8, characterized in that, The formation of the conductive layer includes: Before forming the word line layer, gate dielectric layer, and semiconductor layer, a conductive layer is formed in the groove, the conductive layer covering the sidewalls and bottom surface of the first sub-segment, and covering the portion of the bit line layer exposed at the bottom of the first sub-segment; The formation of the word line layer, gate dielectric layer, and semiconductor layer includes: A first gate dielectric layer and a word line layer are formed in the groove, wherein the first gate dielectric layer at least covers the conductive layer, and the word line layer covers the first gate dielectric layer and fills the groove. A second gate dielectric layer is formed, which at least covers the top surface of the gate electrode portion and is connected to the first gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer constitute the gate dielectric layer. The first sublayer is formed, and at least a portion of the first sublayer covers the second gate dielectric layer and is connected to the conductive layer to circumferentially surround the gate electrode portion.

10. The manufacturing method according to claim 8, characterized in that, The formation of the conductive layer includes: Before forming the word line layer, gate dielectric layer, and semiconductor layer, a conductive layer is formed in the groove, the conductive layer covering at least a portion of the bottom surface of the first sub-segment or the bottom surface and a portion of the sidewalls of the first sub-segment, and covering the portion of the bit line layer exposed at the bottom of the first sub-segment; The formation of the word line layer, gate dielectric layer, and semiconductor layer includes: A second sub-layer is formed within the groove, the second sub-layer covering the portion of the sidewalls and bottom surface of the first sub-segment that is not covered by the conductive layer; A first gate dielectric layer and a word line layer are formed in the groove, wherein the first gate dielectric layer at least covers the conductive layer and the second sub-layer, and the word line layer covers the first gate dielectric layer and fills the groove. A second gate dielectric layer is formed, which at least covers the top surface of the gate electrode portion and is connected to the first gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer constitute the gate dielectric layer. A first sublayer is formed, at least a portion of which covers the second gate dielectric layer. The first sublayer, the second sublayer, and the conductive layer are connected to circumferentially surround the gate electrode portion. The first sublayer and the second sublayer constitute the semiconductor layer.

11. The manufacturing method according to any one of claims 7-10, characterized in that, After forming the word line layer, gate dielectric layer, and semiconductor layer, the method further includes: A third dielectric layer is formed, which covers the first dielectric layer and the first sublayer; Multiple contact plugs are formed, the contact plugs are located above the gate electrode portion and penetrate the third dielectric layer, and the contact plugs are in contact with the portion of the first sublayer covering the top surface of the gate electrode portion; A fourth dielectric layer is formed on the third dielectric layer, and a plurality of capacitor structures are formed within the fourth dielectric layer, wherein the plurality of capacitor structures are electrically connected to the plurality of contact plugs in a one-to-one correspondence.

12. An electronic device, characterized in that, include: A processing device, and a memory device electrically connected to the processing device, wherein at least one of the processing device and the memory device comprises the semiconductor structure described in any one of claims 1-6.

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