Method for manufacturing a memory device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-08-07
AI Technical Summary
[0003]在相关技术提供的存储器件的制造工艺中，以ETOX NOR闪存为例，在制备浮栅、控制栅堆叠结构前，通常要先进行阈值电压调节（CVT）离子注入来调整存储单元的阈值电压，由于CVT工序包括光刻及离子注入步骤且需要单独的光罩，这会导致工艺成本增加、生产周期拉长，还可能会引入缺陷，影响良率
[0024]本申请方法通过两次自对准掺杂，在衬底中形成第一掺杂源区和第二掺杂源区的垂直叠置结构，第一掺杂源区位于第二掺杂源区下方，这使得第一掺杂源区的杂质离子可以通过扩散效应进入沟道区域，形成阈值电压调节掺杂层，无需额外的CVT工序，通过调整形成第一掺杂源区的离子注入参数可调节阈值电压调节掺杂层中的杂质浓度分布，实现对阈值电压的调节，从而可以实现相关技术中CVT工序的阈值电压调节掺杂与自对准源极离子注入步骤的合并，也即可以在不影响器件阈值电压和其他性能的同时省略CVT光罩及CVT工序，有利于减少工艺步骤并降低工艺制造成本，缩短NOR闪存的生产周期，减少存储单元缺陷的来源，有助于提升产品良率。
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Figure CN122534868A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for manufacturing a memory device. Background Technology
[0002] Non-volatile memory (NVM) is a widely used type of information storage. Its core characteristic is the storage of charge in a floating gate (FG) through electron tunneling or hot electron injection to represent binary data (0 / 1). In NVM memory, NOR flash memory is developed based on the programmable read-only memory tunnel oxide (ETOX) structure proposed by Intel. The structure of ETOX NOR flash memory is similar to that of a metal-oxide-semiconductor field-effect transistor (MOSFET), achieving non-volatile data storage through a floating gate and corresponding dielectric layers, capturing the charge state via the floating gate.
[0003] In the manufacturing process of memory devices provided by related technologies, taking ETOX NOR flash memory as an example, before fabricating the floating gate and control gate stack structure, threshold voltage regulation (CVT) ion implantation is usually performed to adjust the threshold voltage of the memory cell. Since the CVT process includes photolithography and ion implantation steps and requires a separate photomask, this will lead to increased process costs, longer production cycles, and may also introduce defects, affecting yield. Summary of the Invention
[0004] This application provides a method for manufacturing a memory device that can omit the CVT mask and process without affecting the device's threshold voltage and other performance characteristics.
[0005] In view of this, this application provides a method for manufacturing a storage device, comprising:
[0006] S1, a substrate having a shallow trench isolation structure is provided, the shallow trench isolation structure being formed in the storage region and the peripheral region of the substrate, the top surface of the shallow trench isolation structure being higher than the substrate surface, and a double-layer well structure being formed in the substrate;
[0007] S2, a stacked structure is formed on the substrate, the stacked structure including, from bottom to top, a tunneling oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer;
[0008] S3, etching the stacked structure of the memory region to form a memory cell on the substrate, the memory cell including a memory cell gate structure, a first trench located between adjacent memory cell gate structures, and a second trench located on the periphery of the memory cell gate structure;
[0009] S4, perform the first self-aligned doping on the substrate region corresponding to the first trench to form the first doped source region in the substrate;
[0010] S5, perform a second self-aligned doping on the substrate region corresponding to the first trench to form a second doped source region superimposed on the first doped source region in the substrate. The second doped source region is located above the first doped source region and the type of impurity ions therein is opposite to the type of impurity ions in the first doped source region.
[0011] S6, doping is performed on the substrate region corresponding to the second trench to form a drain region in the substrate;
[0012] S7, forming the gate structure of a logic device on the substrate of the peripheral region;
[0013] S8 forms a source / drain region within the substrate surrounding the gate structure of the logic device.
[0014] Optionally, the cross-section of the first doped source region is comb-shaped, and the groove width between adjacent teeth of the comb gradually increases along the direction close to the substrate surface.
[0015] Optionally, the peripheral region includes a first device region and a second device region, wherein the first device region is the formation region of the first MOS device on the substrate, and the second device region is the formation region of the second MOS device on the substrate.
[0016] Optionally, the shallow trench isolation structure includes a first shallow trench isolation structure and a second shallow trench isolation structure. The first shallow trench isolation structure is located in the storage area and is used to isolate adjacent storage cells. The second shallow trench isolation structure is located in the peripheral area. The depth of the second shallow trench isolation structure is greater than that of the first shallow trench isolation structure. The second shallow trench isolation structure isolates the active area of the peripheral area.
[0017] Optionally, the method of forming a double-layer well structure in a substrate includes: forming an N-type well in the substrate; forming a first conductivity type well in a storage region and a second device region; forming a second conductivity type well in the first device region; wherein the depths of the first conductivity type well and the second conductivity type well are less than those of the N-type well.
[0018] Optionally, the first conductivity type is P-type and the second conductivity type is N-type.
[0019] Optionally, before performing step S8, a step of forming a lightly doped drain region in the substrate on the periphery of the logic device gate structure is further included.
[0020] Optionally, the floating gate layer includes a floating gate polysilicon layer.
[0021] Optionally, the control gate layer includes a control gate polysilicon layer.
[0022] Optionally, the inter-gate dielectric layer includes, from bottom to top, an oxide layer, a nitrided layer, and an oxide layer.
[0023] The technical solution of this application has at least the following advantages:
[0024] This application method forms a vertically stacked structure of a first doped source region and a second doped source region in the substrate through two self-aligned doping processes. The first doped source region is located below the second doped source region. This allows impurity ions from the first doped source region to enter the channel region through diffusion, forming a threshold voltage regulation doped layer without the need for an additional CVT process. By adjusting the ion implantation parameters that form the first doped source region, the impurity concentration distribution in the threshold voltage regulation doped layer can be adjusted, thereby achieving threshold voltage regulation. This allows the merging of the threshold voltage regulation doping and self-aligned source ion implantation steps in related technologies. In other words, the CVT mask and CVT process can be omitted without affecting the device's threshold voltage and other performance characteristics. This helps reduce process steps and manufacturing costs, shorten the production cycle of NOR flash memory, reduce the sources of memory cell defects, and improve product yield. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0026] Figure 1 This is a process flow diagram of a method for manufacturing a storage device provided in an exemplary embodiment of this application;
[0027] Figure 2 This is a schematic cross-sectional view of a method for manufacturing a memory device according to an exemplary embodiment of this application, after a double-layer well structure has been formed in a substrate.
[0028] Figure 3 This is a schematic cross-sectional view of a method for manufacturing a memory device according to an exemplary embodiment of this application, after forming a memory cell on a substrate;
[0029] Figure 4 This is a schematic cross-sectional view of a method for manufacturing a memory device according to an exemplary embodiment of this application, after forming a second doped source region in a substrate;
[0030] Figure 5 This is a schematic cross-sectional view of a method for manufacturing a memory device according to an exemplary embodiment of this application, in which a lightly doped drain region is formed in the substrate surrounding the gate structure of a logic device.
[0031] Figure 6 This is a schematic cross-sectional view of a method for manufacturing a memory device according to an exemplary embodiment of this application, in which a source / drain region is formed in the substrate on the periphery of the gate structure of a logic device.
[0032] The numbers in the diagram represent:
[0033] 100. Substrate;
[0034] 110. Storage region; 111. First shallow trench isolation structure; 113. First doped source region; 114. Second doped source region; 115. Drain region; 116. Threshold voltage adjustable doped layer;
[0035] 120. Peripheral region; 121. Second shallow trench isolation structure; 122. First device region; 123. Second device region; 124. Logic device gate structure; 125. Lightly doped drain region; 126. Source / drain region;
[0036] 130. N-type trap;
[0037] 140. First type of conductivity trap;
[0038] 150. Second type of conductivity trap;
[0039] 210. Through-hole oxide layer; 220. Floating gate layer; 230. Inter-gate dielectric layer; 240. Control gate layer; 250. First trench; 260. Second trench; Detailed Implementation
[0040] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0041] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0042] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0043] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0044] The following is combined with Figures 1 to 6 This describes an embodiment of the present application.
[0045] refer to Figure 1 The illustration shows an embodiment of this application, providing a method for manufacturing a storage device, comprising:
[0046] S1, a substrate 100 with a shallow trench isolation structure is provided. The shallow trench isolation structure is formed in the storage region 110 and the peripheral region 120 of the substrate 100. The top surface of the shallow trench isolation structure is higher than the surface of the substrate 100, forming a double-layer well structure in the substrate 100.
[0047] For example, the substrate 100 may be a silicon substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, or other materials suitable for the manufacture of memory devices.
[0048] In some embodiments, the peripheral region 120 includes a first device region 122 and a second device region 123, where the first device region 122 is the formation region of the first MOS device on the substrate 100, and the second device region 123 is the formation region of the second MOS device on the substrate 100.
[0049] For example, the first MOS device can be a high voltage (HV) P (Positive) MOS device, and the second MOS device can be a high voltage N (Negative) MOS device.
[0050] In some embodiments, the shallow trench isolation structure includes a first shallow trench isolation structure 111 and a second shallow trench isolation structure 121. The first shallow trench isolation structure 111 is located in the storage area 110 and is used to isolate adjacent storage cells. The second shallow trench isolation structure 121 is located in the peripheral area 120. The depth of the second shallow trench isolation structure 121 is greater than that of the first shallow trench isolation structure 111. The second shallow trench isolation structure 121 isolates the active area of the peripheral area 120.
[0051] For example, a shallow trench isolation structure is typically formed in the substrate 100 using a shallow trench isolation (STI) process. The formation of a first shallow trench isolation structure 111 in the storage region 110 and a second shallow trench isolation structure 121 in the peripheral region 120 can be achieved using a selective STI process.
[0052] In some embodiments, the method of forming a double-layer well structure in a substrate 100 includes: forming an N-type well 130 in the substrate 100; forming a first conductivity type well 140 in a storage region 110 and a second device region 123; and forming a second conductivity type well 150 in a first device region 122, wherein the depths of the first conductivity type well 140 and the second conductivity type well 150 are less than those of the N-type well 130.
[0053] For example, forming an N-type well 130 within the substrate 100 can be achieved by subjecting the substrate 100 to N-type impurity ions (e.g., phosphorus ions P). + Arsenic ions (As) + Antimony ions Sb + P-type impurity ion implantation is used to form a first conductivity type well 140 in the N-type well 130 of the storage region 110 and the second device region 123, and a second conductivity type well 150 in the N-type well 130 of the first device region 122. This can be achieved using selective ion implantation. For example, firstly, the storage region 110 and the second device region 123 on the substrate 100 are exposed using photoresist as ion implantation windows, and P-type impurity ion implantation is performed on the substrate 100 to form a P-type well in the N-type well 130 of the storage region 110 and the second device region 123. Then, the first device region 122 on the substrate 100 is exposed using photoresist as an ion implantation window, and N-type impurity ion implantation is performed on the substrate 100 to form an N-type well 130 in the N-type well 130 of the first device region 122.
[0054] S2, a stacked structure is formed on the substrate 100, the stacked structure including, from bottom to top, a tunneling oxide layer 210, a floating gate layer 220, an inter-gate dielectric layer 230 and a control gate layer 240.
[0055] In some embodiments, the tunneling oxide layer 210 includes a silicon oxide layer.
[0056] For example, a tunnel oxide layer 210 is typically grown on substrate 100 using thermal oxidation (TO).
[0057] In some embodiments, the floating gate layer 220 includes a floating gate polysilicon layer.
[0058] For example, chemical vapor deposition (CVD) is typically used to deposit the floating gate layer 220 on the tunneling oxide layer 210.
[0059] In some embodiments, the inter-gate dielectric layer 230 includes, from bottom to top, an oxide layer, a nitride layer, and an oxide layer.
[0060] For example, the inter-gate dielectric layer 230 is an oxide-nitride-oxide (ONO) layer, which is typically formed on the floating gate layer 220 using a combination of thermal oxidation and chemical vapor deposition processes.
[0061] In some embodiments, the control gate layer 240 includes a control gate polysilicon layer.
[0062] For example, a control gate polysilicon layer is typically deposited on the inter-gate dielectric layer 230 using chemical vapor deposition (CVD).
[0063] S3, etch the stacked structure of the memory region 110 to form a memory cell on the substrate 100. The memory cell includes a memory cell gate structure, a first trench 250 located between adjacent memory cell gate structures, and a second trench 260 located on the periphery of the memory cell gate structure.
[0064] For example, the etching process of the stacked structure of storage area 110 is typically achieved by using a patterned hard mask layer as an etching mask and employing dry etching.
[0065] S4, perform the first self-aligned doping on the substrate 100 region corresponding to the first trench 250 to form the first doped source region 113 in the substrate 100.
[0066] For example, the first self-aligned doping can be achieved by implanting P-type impurity ions into the substrate 100 region corresponding to the first trench 250 through a self-aligned process, and the first doping source region 113 formed in the substrate 100 is a P-type doping source region.
[0067] S5, perform a second self-aligned doping on the substrate 100 region corresponding to the first trench 250, and form a second doped source region 114 in the substrate 100 that is superimposed on the first doped source region 113. The second doped source region 114 is located above the first doped source region 113 and the type of impurity ions therein is opposite to the type of impurity ions in the first doped source region 113.
[0068] For example, after the first self-aligned doping, the substrate 100 region corresponding to the first trench 250 can be heavily doped with N-type impurity ions by self-aligned process to achieve the second self-aligned doping, and the second doping source region 114 formed in the substrate 100 is an N-type heavily doped source region.
[0069] By forming a vertically stacked structure of P-type doped source regions and N-type doped source regions in the substrate 100, with the P-type doped source region located below the N-type doped source region and in direct contact with it, impurity ions from the P-type doped source region can diffuse into the channel region to form a threshold voltage regulation doped layer 116. This eliminates the need for an additional CVT process. By adjusting the ion implantation parameters for forming the P-type doped source region, the impurity concentration distribution in the threshold voltage regulation doped layer 116 can be adjusted, thereby regulating the threshold voltage. This allows the merging of the threshold voltage regulation doping and self-aligned source ion implantation steps in the CVT process of related technologies. In other words, the CVT mask and CVT process can be omitted without affecting the device's threshold voltage and other performance characteristics. This reduces process steps and manufacturing costs, shortens the production cycle of NOR flash memory, reduces the sources of defects in memory cells, and helps improve product yield.
[0070] In some embodiments, the cross-section of the first doped source region 113 is comb-shaped, and the groove width between adjacent teeth of the comb gradually increases in the direction close to the surface of the substrate 100.
[0071] For example, the groove between adjacent teeth of the comb can be an inverted trapezoid, a V-shape, or other shapes that conform to the characteristic of being wider at the top and narrower at the bottom.
[0072] This topography design increases the contact area between the first doped source region 113 and the channel region, which can improve the diffusion efficiency of impurity ions in the first doped source region 113 into the channel region. This is beneficial to enhancing the ability to regulate the channel threshold voltage. Furthermore, the gradient design of the groove width can optimize the electric field distribution, which is beneficial to reducing the electric field concentration effect and improving the reliability of the device.
[0073] In some embodiments, the cross-sectional profile of the second doped source region 114 is adapted to the cross-sectional profile of the first doped source region 113.
[0074] This topography design not only ensures good contact between the second doped source region 114 and the first doped region, which helps to reduce contact resistance, but also optimizes the current distribution in the source region, which helps to reduce current concentration effects and thus improves the reliability of the device.
[0075] S6, doping is performed on the substrate 100 region corresponding to the second trench 260 to form a drain region 115 in the substrate 100.
[0076] S7, a logic device gate structure 123 is formed on the substrate 100 of the peripheral region 120.
[0077] For example, a method for forming a logic device gate structure 123 on a substrate 100 of a peripheral region 120 includes: performing photolithography and etching to remove the stacked structure on the peripheral region 120; growing a gate oxide layer on the substrate 100 of the peripheral region 120; depositing polysilicon on the gate oxide layer; and performing photolithography and etching to form the logic device gate structure 123 on the substrate 100 of the peripheral region 120.
[0078] S8, a source / drain region 125 is formed in the substrate 100 on the periphery of the logic device gate structure 123.
[0079] For example, forming the source / drain region 125 within the substrate 100 surrounding the gate structure 123 of the logic device can be achieved using a combination of photolithography and self-aligned ion implantation. For instance, photoresist is formed in the memory region 110 using photolithography, and self-aligned ion implantation is performed on the peripheral region 120 substrate 100 not covered by the photoresist, using the logic gate as a mask, to form the source / drain region 125. After the source / drain region 125 is formed, the photoresist in the memory region 110 is removed.
[0080] In some embodiments, prior to performing step S8, a step of forming a lightly doped drain (LDD) region 124 within the substrate 100 on the periphery of the logic device gate structure 123 is further included.
[0081] In the manufacturing process of memory devices provided by related technologies, threshold voltage regulation (CVT) ion implantation is usually performed to adjust the threshold voltage of the memory cell before fabricating the floating gate control gate stack structure. Since the CVT process includes photolithography and ion implantation steps and requires a separate photomask, it will increase the process cost, lengthen the production cycle, and may also introduce defects, affecting the yield.
[0082] This application forms a vertically stacked structure of a first doped source region 113 and a second doped source region 114 in a substrate 100 through two self-aligned doping processes. The first doped source region 113 is located below the second doped source region 114. This allows impurity ions in the first doped source region 113 to enter the channel region through diffusion, forming a threshold voltage regulation doped layer 116 without the need for an additional CVT process. By adjusting the ion implantation parameters for forming the first doped source region 113, the impurity concentration distribution in the threshold voltage regulation doped layer 116 can be adjusted, thereby achieving threshold voltage regulation. This allows the merging of the threshold voltage regulation doping and self-aligned source ion implantation steps in the CVT process of related technologies. In other words, the CVT mask and CVT process can be omitted without affecting the device threshold voltage and other performance (such as isolation performance, erase state drain current, etc.). This helps to reduce process steps and manufacturing costs, shorten the production cycle of NOR flash memory, reduce the sources of memory cell defects, and improve product yield.
[0083] Example 1:
[0084] A method for manufacturing a storage device, comprising:
[0085] S1, a substrate 100 with a shallow trench isolation structure is provided. The shallow trench isolation structure is formed in the storage region 110 and the peripheral region 120 of the substrate 100. The top surface of the shallow trench isolation structure is higher than the surface of the substrate 100, forming a double-layer well structure in the substrate 100.
[0086] In this embodiment, the substrate 100 is a silicon substrate 100.
[0087] In this embodiment, the peripheral region 120 includes a first device region 122 and a second device region 123. The first device region 122 is the formation region of the first MOS device on the substrate 100, and the second device region 123 is the formation region of the second MOS device on the substrate 100. The first MOS device is a high-voltage PMOS device, and the second MOS device is a high-voltage NMOS device. The operating voltage of the first MOS device and the second MOS device can be 5V.
[0088] In this embodiment, the shallow trench isolation structure includes a first shallow trench isolation structure 111 and a second shallow trench isolation structure 121. The first shallow trench isolation structure 111 is located in the storage area 110 and is used to isolate adjacent storage cells. The second shallow trench isolation structure 121 is located in the peripheral area 120. The depth of the second shallow trench isolation structure 121 is greater than that of the first shallow trench isolation structure 111. The second shallow trench isolation structure 121 isolates the active area in the peripheral area 120.
[0089] In this embodiment, the method for forming a double-layer well structure in the substrate 100 includes: forming an N-type well 130 in the substrate 100; forming a high-voltage P-type well in the storage region 110 and the second device region 123; and forming a high-voltage N-type well 130 in the first device region 122, wherein the well depths of the high-voltage P-type well and the high-voltage N-type well 130 are less than that of the N-type well 130.
[0090] S2, a stacked structure is formed on the substrate 100, the stacked structure including, from bottom to top, a tunneling oxide layer 210, a floating gate layer 220, an inter-gate dielectric layer 230 and a control gate layer 240.
[0091] In this embodiment, the tunneling oxide layer 210 includes a silicon oxide layer, the floating gate layer 220 includes a floating gate polysilicon layer, the inter-gate dielectric layer 230 includes an ONO layer, and the control gate layer 240 includes a control gate polysilicon layer.
[0092] S3, etch the stacked structure of the memory region 110 to form a memory cell on the substrate 100. The memory cell includes a memory cell gate structure, a first trench 250 located between adjacent memory cell gate structures, and a second trench 260 located on the periphery of the memory cell gate structure.
[0093] S4, perform the first self-aligned doping on the substrate 100 region corresponding to the first trench 250 to form the first doped source region 113 in the substrate 100.
[0094] In this embodiment, the first doped source region 113 is a P-type doped source region.
[0095] S5, perform a second self-aligned doping on the substrate 100 region corresponding to the first trench 250, and form a second doped source region 114 in the substrate 100 that is superimposed on the first doped source region 113. The second doped source region 114 is located above the first doped source region 113 and the type of impurity ions therein is opposite to the type of impurity ions in the first doped source region 113.
[0096] In this embodiment, the second doped source region 114 is an N-type heavily doped source region.
[0097] S6, doping is performed on the substrate 100 region corresponding to the second trench 260 to form a drain region 115 in the substrate 100.
[0098] S7, a logic device gate structure 123 is formed on the substrate 100 of the peripheral region 120.
[0099] S8, a source / drain region 125 is formed in the substrate 100 on the periphery of the logic device gate structure 123.
[0100] In this embodiment, before performing step S8, a step of forming a lightly doped drain region 124 in the substrate 100 on the periphery of the logic device gate structure 123 is also included.
[0101] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing a storage device, characterized in that, include: S1, a substrate having a shallow trench isolation structure is provided, the shallow trench isolation structure being formed in the storage region and the peripheral region of the substrate, the top surface of the shallow trench isolation structure being higher than the substrate surface, and a double-layer well structure being formed in the substrate; S2, a stacked structure is formed on the substrate, the stacked structure including, from bottom to top, a tunneling oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer; S3, etching the stacked structure of the memory region to form a memory cell on the substrate, the memory cell including a memory cell gate structure, a first trench located between adjacent memory cell gate structures, and a second trench located on the periphery of the memory cell gate structure; S4, perform the first self-aligned doping on the substrate region corresponding to the first trench to form the first doped source region in the substrate; S5, perform a second self-aligned doping on the substrate region corresponding to the first trench to form a second doped source region superimposed on the first doped source region in the substrate. The second doped source region is located above the first doped source region and the type of impurity ions therein is opposite to the type of impurity ions in the first doped source region. S6, doping is performed on the substrate region corresponding to the second trench to form a drain region in the substrate; S7, forming the gate structure of a logic device on the substrate of the peripheral region; S8 forms a source / drain region within the substrate surrounding the gate structure of the logic device.
2. The method according to claim 1, characterized in that, The cross-section of the first doped source region is comb-shaped, and the groove width between adjacent teeth of the comb gradually increases in the direction close to the substrate surface.
3. The method according to claim 1, characterized in that, The peripheral area includes a first device area and a second device area. The first device area is the formation area of the first MOS device on the substrate, and the second device area is the formation area of the second MOS device on the substrate.
4. The method according to claim 1, characterized in that, The shallow trench isolation structure includes a first shallow trench isolation structure and a second shallow trench isolation structure. The first shallow trench isolation structure is located in the storage area and is used to isolate adjacent storage cells. The second shallow trench isolation structure is located in the peripheral area and has a greater depth than the first shallow trench isolation structure. The second shallow trench isolation structure isolates the active area of the peripheral area.
5. The method according to claim 3, characterized in that, A method for forming a double-layer well structure in a substrate includes: forming an N-type well in the substrate; forming a first conductivity type well in a storage region and a second device region; forming a second conductivity type well in the first device region; wherein the depths of the first conductivity type well and the second conductivity type well are smaller than those of the N-type well.
6. The method according to claim 5, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.
7. The method according to claim 1, characterized in that, Before performing step S8, a step of forming a lightly doped drain region in the substrate surrounding the gate structure of the logic device is also included.
8. The method according to claim 1, characterized in that, The floating gate layer includes a floating gate polysilicon layer.
9. The method according to claim 1, characterized in that, The control gate layer includes a control gate polysilicon layer.
10. The method according to claim 1, characterized in that, The inter-gate dielectric layer comprises, from bottom to top, an oxide layer, a nitrided layer, and an oxide layer.