Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device that can be manufactured well. The semiconductor memory device of the embodiments has a substrate that has a first region and a second region arranged in a first direction. In addition, the first region of the semiconductor memory device has a plurality of first conductive layers and a plurality of first insulating layers alternately laminated in a second direction, a first semiconductor layer extending in the second direction and facing the plurality of first conductive layers and the plurality of first insulating layers, and a second semiconductor layer connected to the first semiconductor layer and extending in the first direction. In addition, the same configuration is provided in the second region of the semiconductor memory device. In addition, the semiconductor memory device has a third conductive layer bonded to the second semiconductor layer provided in the first region and the second region. In addition, the second semiconductor layers provided in the first region and the second region are provided apart from each other in the first direction.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on February 3, 2021, with application number 202110148581.3 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2020-146517 (filed on September 1, 2020). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0005] This embodiment relates to a semiconductor memory device. Background Technology

[0006] A known semiconductor memory device includes: a substrate; a plurality of conductive layers deposited in a direction intersecting the surface of the substrate; a semiconductor layer facing the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer has a storage section capable of storing data, such as an insulating charge storage layer like silicon nitride (Si3N4) or a conductive charge storage layer like a floating gate. Summary of the Invention

[0007] The implementation provides a semiconductor memory device that can be manufactured well.

[0008] One embodiment of a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The semiconductor memory device further includes: a plurality of first conductive layers and a plurality of first insulating layers disposed in the first region and alternately deposited in a second direction intersecting the surface of the substrate; a first semiconductor layer disposed in the first region, extending in the second direction and facing the plurality of first conductive layers and the plurality of first insulating layers; and a second semiconductor layer disposed in the first region, farther from the substrate than the plurality of first conductive layers and the plurality of first insulating layers, and connected to the first semiconductor layer. Additionally, the semiconductor memory device includes: a plurality of second conductive layers and a plurality of second insulating layers disposed in the second region and alternately deposited in the second direction; a third semiconductor layer disposed in the second region, extending in the second direction and facing the plurality of second conductive layers and the plurality of second insulating layers; and a fourth semiconductor layer disposed in the second region, farther from the substrate than the plurality of second conductive layers and the plurality of second insulating layers, and connected to the third semiconductor layer. Furthermore, the semiconductor memory device includes a third conductive layer, which is bonded to the surfaces of the second and fourth semiconductor layers furthest from the substrate in a second direction. Additionally, the second and fourth semiconductor layers are spaced apart from each other in a first direction.

[0009] One embodiment of a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The semiconductor memory device further includes: a plurality of first conductive layers and a plurality of first insulating layers disposed in the first region and alternately deposited in a second direction intersecting the surface of the substrate; and a first semiconductor layer disposed in the first region, extending in the second direction, and facing the plurality of first conductive layers and the plurality of first insulating layers. Additionally, the semiconductor memory device includes: a plurality of second conductive layers and a plurality of second insulating layers disposed in the second region and alternately deposited in the second direction; and a second semiconductor layer disposed in the second region, extending in the second direction, and facing the plurality of second conductive layers and the plurality of second insulating layers. Furthermore, the semiconductor memory device includes: a first structure disposed between a plurality of first conductive layers and a plurality of first insulating layers and a plurality of second conductive layers and a plurality of second insulating layers, and extending in a second direction; a third semiconductor layer, which is farther from the substrate than the plurality of first conductive layers and a plurality of first insulating layers, and a plurality of second conductive layers and a plurality of second insulating layers, and is connected to the first semiconductor layer and the second semiconductor layer; and a third conductive layer bonded to the surface of the third semiconductor layer that is farther from the substrate in the second direction. Additionally, in a first cross-section extending in the first direction and including the first structure, the third semiconductor layer, and the third conductive layer, at least a portion of the first structure faces the third conductive layer without being separated by the third semiconductor layer. Attached Figure Description

[0010] Figure 1This is a schematic perspective view showing the configuration of the memory die MD according to the first embodiment.

[0011] Figure 2 This indicates that chip C M A schematic bottom view of the structure.

[0012] Figure 3 This indicates that chip C M A schematic bottom view consisting of a portion of it.

[0013] Figure 4 This indicates that chip C M A schematic top view consisting of a portion of it.

[0014] Figure 5 This indicates that chip C M A schematic cross-sectional view consisting of a portion of it.

[0015] Figure 6 It is Figure 5 A portion of it constitutes an enlarged schematic cross-sectional view.

[0016] Figure 7 It is Figure 5 A portion of it constitutes an enlarged schematic cross-sectional view.

[0017] Figures 8 to 22 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0018] Figures 23-25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0019] Figure 26 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the third embodiment.

[0020] Figure 27 This is a schematic cross-sectional view showing a portion of another configuration example of the semiconductor memory device according to the third embodiment.

[0021] Figure 28 This is a schematic cross-sectional view showing a portion of the semiconductor memory device according to the fourth embodiment.

[0022] Figures 29-34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0023] Figure 35 This is a schematic top view showing a portion of the semiconductor memory device according to the fifth embodiment.

[0024] Figure 36This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0025] Figure 37 It is Figure 36 A portion of it constitutes an enlarged schematic cross-sectional view.

[0026] Figure 38 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0027] Figure 39 This is a schematic cross-sectional view showing a portion of another configuration example of the semiconductor memory device according to the first embodiment. Detailed Implementation

[0028] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments may be labeled with the same symbols, and descriptions may be omitted.

[0029] Furthermore, in this specification, when "semiconductor memory device" is mentioned, it sometimes refers to a memory die, and sometimes to a storage system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes refers to a device that includes a host, such as a smartphone, tablet, or personal computer.

[0030] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0031] In addition, in this specification, the specific direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0032] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to any of them.

[0033] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a component as a lower surface or lower end, it means the surface or end of that component on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that component on the side opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0034] In addition, when referring to "width", "length" or "thickness" in a specific direction in this specification, it sometimes refers to the width, length or thickness in a cross-section or the like observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0035] [First Implementation]

[0036] [Construction of Memory Die (MD)]

[0037] Figure 1 This is a schematic exploded perspective view showing an example of the configuration of a semiconductor memory device according to this embodiment. The semiconductor memory device of this embodiment includes a memory die MD. The memory die MD includes a chip C containing an array of memory cells. M and chip C containing peripheral circuits P .

[0038] In chip C M Multiple solder pad electrodes P are set on the upper surface. X Additionally, in chip C... M Multiple first bonding electrodes P are disposed on the lower surface. I1 Additionally, in chip C... P Multiple second bonding electrodes P are disposed on the upper surface. I2 The following section concerns chip C. M Multiple first bonding electrodes P will be set. I1 The side referred to as the front side will be where multiple solder pad electrodes P will be installed. X The side facing out is called the back side. Additionally, regarding chip C... P Multiple second bonding electrodes P will be set. I2 The side facing out is called the front side, and the side opposite the front side is called the back side. In the example shown, chip C P The front is set up to be better than chip C P On the back, near the top, chip C M The back is set up to be more than chip C M The front, near the top.

[0039] Chip C M and chip C P With chip C M The front of the chip C P The electrodes are arranged in a face-to-face configuration. Multiple first bonding electrodes P I1 Each of the multiple second bonding electrodes P I2 Correspondingly, it is set and configured to be attached to multiple second attachment electrodes P I2 Position of the first bonding electrode P. I1 With the second electrode P I2 As used to connect chip C M With chip C P The bonding electrodes, which adhere to each other and enable electrical conductivity between them, play a crucial role. (Pad electrode P) X It functions as an electrode for electrically connecting the memory die (MD) to a controller die (not shown) or the like.

[0040] in addition, Figure 1 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0041] Figure 2 This indicates that chip C M A schematic bottom view of the composition example. Figure 3 It is chip C M The diagram shows an enlarged view of the portion represented by A, in a schematic bottom view. Figure 4 This indicates that chip C M A portion of it constitutes an enlarged schematic top view. Figure 5 This indicates that chip C M A schematic cross-sectional view comprising a portion of it. Additionally, Figure 3 Corresponding to along line E-E' Figure 5 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 4 Corresponding to along line D-D' Figure 5 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 5 Corresponding to along line B-B' Figure 3 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 5 Corresponding to along line C-C' Figure 4 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, corresponding to the section along line C-C'... Figure 4 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Figure 6 and Figure 7 They are respectively to Figure 5 A portion of it constitutes an enlarged schematic cross-sectional view.

[0042] [Chip C] M [Construction]

[0043] For example, such as Figure 2 As shown, chip C M It has four memory cell array regions R arranged in the X and Y directions. MCA Storage cell array region R MCA Features: Multiple storage blocks (BLKs) arranged in the Y direction; 150 (units) of inter-block construction. Figure 3 ), respectively disposed between these multiple storage blocks BLK; and conductive layer 170 ( Figure 5 ), which is set on the upper surface of multiple storage blocks BLK and multiple inter-block structures 150.

[0044] For example, such as Figure 5 As shown, the memory block BLK includes: a plurality of conductive layers 110 arranged in the Z direction; a plurality of semiconductor layers 120 extending in the Z direction; a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120; and a semiconductor layer 140 connected to the upper end of the plurality of semiconductor layers 120.

[0045] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a laminated film containing barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). Alternatively, the conductive layer 110 may comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0046] The conductive layer 110 functions, for example, as a word line and the gate electrode of a plurality of memory cells connected to the word line. For example, as... Figure 3 As shown, one end of the conductive layer 110 in the X direction is connected to the contact 102. The conductive layer 110 connects to the first bonding electrode P via the contact 102. I1 Connected to chip C P The internal structure.

[0047] For example, such as Figure 3 As shown, the semiconductor layer 120 is arranged in a specific pattern in the X and Y directions. The semiconductor layer 120 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a polycrystalline silicon (Si) semiconductor layer. For example, as... Figure 5 As shown, the semiconductor layer 120 has a generally cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is disposed in the central portion. Figure 6In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by the conductive layer 110 and face each other.

[0048] An impurity region containing N-type impurities such as phosphorus (P) is formed at the lower end of the semiconductor layer 120. This impurity region is electrically connected to the bit line BL. The bit line BL is connected via the first bonding electrode P. I1 Electrically connected to chip C P The internal structure.

[0049] An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is formed at the upper end of semiconductor layer 120. This impurity region is electrically connected to semiconductor layer 140. Semiconductor layer 140 is connected via conductive layer 170, conductive layer 151, and the first bonding electrode P. I1 Electrically connected to chip C P The internal structure.

[0050] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 6 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction.

[0051] in addition, Figure 6 The diagram shows an example where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0052] For example, such as Figure 4 As shown, semiconductor layer 140 is a generally plate-shaped semiconductor layer extending in the X direction. Semiconductor layer 140 is connected to the upper ends of all semiconductor layers 120 contained in memory block BLK. Semiconductor layer 140 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B).

[0053] Additionally, for example, such as Figure 7As shown, the two sides of the semiconductor layer 140 in the Y direction are inclined at the following angles: the lower part is further away from the semiconductor layer 140 corresponding to the adjacent memory block BLK, and the upper part is closer to the semiconductor layer 140 corresponding to the adjacent memory block BLK. Therefore, the shortest distance between the lower surfaces of two adjacent semiconductor layers 140 in the Y direction is greater than the shortest distance between the upper surfaces of two adjacent semiconductor layers 140 in the Y direction.

[0054] The inter-block structure 150 includes a conductive layer 151 extending in the Z and X directions, and an insulating layer 152, such as silicon oxide (SiO2), disposed on the side of the conductive layer 151 in the Y direction. The conductive layer 151 may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 151 functions, for example, as part of a source line.

[0055] The conductive layer 170 may be, for example, a laminated film comprising a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu) or aluminum (Al). The conductive layer 170 may function as part of a source line, for example.

[0056] For example, such as Figure 7 As shown, the conductive layer 170 includes multiple portions 171 corresponding to multiple memory blocks BLK, and multiple portions 172 corresponding to multiple inter-block structures 150. Portions 171 are generally plate-shaped portions bonded to the upper surface of the semiconductor layer 140 and extending in the X direction corresponding to the semiconductor layer 140. Portions 172 are connected to the upper end of the conductive layer 151. Furthermore, portions 172 are bonded to the side surface of the semiconductor layer 140 in the Y direction.

[0057] Furthermore, the lower surface of portion 172 of conductive layer 170 (the contact surface with insulating layer 101) is located below the lower surface of portion 171 of conductive layer 170 (the bonding surface with semiconductor layer 140). Additionally, the upper surface of portion 172 of conductive layer 170 is located below the upper surface of portion 171 of conductive layer 170.

[0058] [Chip C] P [Construction]

[0059] For example, such as Figure 5 As shown, chip C P The device includes a semiconductor substrate 200 and a plurality of transistors Tr disposed on the surface of the semiconductor substrate 200. These plurality of transistors Tr are connected via the second bonding electrode P. I2 Connected to chip C MIt is internally configured and functions as peripheral circuitry for controlling the memory cell array. For example, during a read operation, this peripheral circuitry supplies voltage to the current path including bit line BL, semiconductor layer 120, semiconductor layer 140, conductive layer 170, and conductive layer 151, and determines the data recorded in the memory cell based on whether current flows.

[0060] [Manufacturing Method]

[0061] Next, refer to Figures 8 to 22 The manufacturing method of memory die MD is explained. Figures 8 to 22 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 5 The corresponding composition.

[0062] When manufacturing the memory die MD of this embodiment, for example, as Figure 8 As shown, on wafer W M Multiple sacrificial layers 110A and insulating layers 101 are formed on a semiconductor substrate 100. The sacrificial layers 110A may contain, for example, silicon nitride (Si3N4). This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0063] Next, for example, such as Figure 9 As shown, a plurality of through-holes 120A are formed at positions corresponding to the semiconductor layer 120. The through-holes 120A are through-holes extending in the Z direction, penetrating the insulating layer 101 and the sacrificial layer 110A, and exposing the upper surface of the semiconductor substrate 100. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0064] Next, for example, such as Figure 10 As shown, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed on the inner peripheral surface of the through-hole 120A. This step is performed, for example, by a method such as CVD.

[0065] Next, for example, such as Figure 11 As shown, a trench 150A is formed. The trench 150A is a trench that extends in the Z and X directions and cuts off the insulating layer 101 and the sacrificial layer 110A in the Y direction, exposing the upper surface of the semiconductor substrate 100. This step is performed, for example, by a method such as RIE.

[0066] Next, for example, such as Figure 12 As shown, a conductive layer 110 is formed. In this step, the sacrificial layer 110A is removed via the trench 150A, for example, by a method such as wet etching. Alternatively, the conductive layer 110 is formed by a method such as CVD.

[0067] Next, for example, such as Figure 13 As shown, an inter-block structure 150 is formed within the groove 150A. This step is performed, for example, by methods such as CVD and RIE.

[0068] Next, for example, such as Figure 14 As shown, bit line BL and the first bonding electrode P are formed. I1 This step can be performed, for example, by methods such as CVD, photolithography, and etching.

[0069] Next, for example, such as Figure 15 As shown, chip C M The corresponding wafer W M With chip C P The corresponding wafer W P Bonding. In this bonding step, for example by bonding the wafer W... M Towards the wafer W P Pressing down causes the wafer to W M Closely attached to wafer W P And undergo heat treatment, etc. Thus, via the first bonding electrode P I1 and the second bonding electrode P I2 wafer W M bonded to wafer W P .

[0070] Next, for example, such as Figure 16 As shown, remove wafer W M The semiconductor substrate 100 is included. Additionally, a portion of the gate insulating film 130 and the insulating layer 152 is removed, exposing the upper ends of the semiconductor layer 120 and the conductive layer 151. This step is performed, for example, by selectively removing the semiconductor substrate 100, and a portion of the gate insulating film 130 and the insulating layer 152 using methods such as wet etching or RIE.

[0071] Next, for example, such as Figure 17 As shown, a covering reference is formed. Figure 16 The insulating layer 160A on the upper surface of the described structure. The insulating layer 160A may contain, for example, silicon oxide (SiO2). This step is performed, for example, by a method such as CVD.

[0072] Next, for example, such as Figure 18 As shown, the portion of insulating layer 160A corresponding to the memory block BLK is removed, exposing the upper ends of the plurality of semiconductor layers 120. This forms a plurality of insulating layers 160 covering the upper ends of the conductive layer 151. This step is performed, for example, by a method such as RIE (Residual Insulation Layer).

[0073] Furthermore, the two sides of the insulating layer 160 in the Y direction are inclined at the following angles: the lower portion is closer to the semiconductor layer 120, and the upper portion is further away from the semiconductor layer 120. Therefore, the width of the lower surface of the insulating layer 160 in the Y direction is greater than the width of the upper surface of the insulating layer 160 in the Y direction.

[0074] Next, for example, such as Figure 19 As shown, a covering reference is formed. Figure 18 The amorphous silicon layer 140A on the upper surface of the illustrated structure is performed, for example, by a method such as CVD.

[0075] Next, for example, such as Figure 20 As shown, the crystal structure of the amorphous silicon layer 140A is modified to form a polycrystalline silicon layer 140B. This step is performed, for example, by methods such as laser annealing.

[0076] Next, for example, such as Figure 21 As shown, for reference Figure 20 The described structure undergoes planarization, removing a portion of the polysilicon layer 140B to form a semiconductor layer 140. This step is performed, for example, by methods such as CMP (Chemical Mechanical Polishing) with the insulating layer 160 as a terminating layer.

[0077] Next, for example, such as Figure 22 As shown, the insulating layer 160 is removed, exposing the upper end of the conductive layer 151. This step is performed, for example, by wet etching.

[0078] Next, for example, such as Figure 5 As shown, in Figure 22 A conductive layer 170 is formed on the upper surface of the structure shown. This step is performed, for example, by a method such as CVD.

[0079] Subsequently, a solder pad electrode P is formed on top of this structure. X etc., for the wafer W M W P The structure is cut to form the memory die (MD).

[0080] [Effect]

[0081] In read operations of semiconductor memory devices, current must flow from the bit line BL connected to the lower end of the semiconductor layer 120 to the source line connected to the upper end of the semiconductor layer 120. Therefore, the upper end of the semiconductor layer 120 must be electrically connected to the source line or the like provided above the memory cell.

[0082] In order to connect the upper end of the semiconductor layer 120 to the source line, for example, in the reference... Figure 10At the point in time after the formation of the gate insulating film 130 and before the formation of the semiconductor layer 120, the gate insulating film 130 can remain on the inner peripheral surface of the via 120A, and the gate insulating film 130 can be removed on the bottom surface of the via 120A, thereby exposing the surface of the semiconductor substrate 100, etc. This method can be performed, for example, by a method such as RIE. Furthermore, the semiconductor layer 120, which is connected to the semiconductor substrate 100, can then be formed inside the via 120A.

[0083] However, with the increasing integration of semiconductor memory devices, the number of conductive layers 110 arranged in the Z direction is constantly increasing. Consequently, as shown in the reference... Figure 9 The aspect ratio of the through-hole 120A continuously increases. In this case, the difficulty of removing the gate insulating film 130 on the bottom surface of the through-hole 120A gradually increases.

[0084] Therefore, in this embodiment, in order to connect the upper end of the semiconductor layer 120 to the source line, etc., while referring to Figure 16 In the described steps, the semiconductor substrate 100 is removed, exposing the upper end of the semiconductor layer 120. Furthermore, in a subsequent step, a semiconductor layer 140 or the like is formed connected to the upper end of the semiconductor layer 120. According to this method, it is unnecessary to remove the gate insulating film 130 from the bottom surface of the large aspect ratio through-hole 120A as described above. Therefore, it is relatively easy to manufacture a configuration that connects the upper end of the semiconductor layer 120 to the source line.

[0085] Here, in order to electrically connect the semiconductor layer 120 to the source line of a metal or the like, a semiconductor layer with a high impurity concentration must be formed at the upper end of the semiconductor layer 120. When forming such a semiconductor layer by methods such as CVD, heat treatment or similar processes must be performed to modify the crystal structure of the semiconductor layer. However, if the wafer W... M With wafer W P After bonding, heat treatment is performed, etc., then there is a first bonding electrode P I1 and the second bonding electrode P I2 There is a risk of metal atom diffusion in the bit line BL or the wiring layer near it, or the wiring layer near the transistor Tr. As a result, there is a risk that the memory die MD will no longer function properly.

[0086] Therefore, in this embodiment, when referring to Figure 19 After the amorphous silicon layer 140A is formed in the described steps, then, referring to... Figure 20 In the described steps, the crystal structure of the amorphous silicon layer 140A is modified by methods such as laser annealing. According to this method, the wafer W can be... MThe temperature on the upper surface rises locally. Therefore, it is believed that the diffusion of metal atoms as described above can be suppressed, and the crystal structure of the amorphous silicon layer 140A can be modified.

[0087] However, after intensive research, the inventors discovered that by modifying the crystal structure of the amorphous silicon layer 140A through methods such as laser annealing, for example, ... Figure 20 As shown, the roughness of the upper surface of the polysilicon layer 140B will increase relatively. In this case, it may affect subsequent steps.

[0088] Furthermore, when the crystal structure of the amorphous silicon layer 140A is modified by methods such as laser annealing, the laser may sometimes reach the conductive layer 151. In this case, heat may be transferred to the first bonding electrode P via the conductive layer 151. I1 , second bonding electrode P I2 The wiring layer, etc., leads to the diffusion of metal atoms as described above.

[0089] Therefore, in this embodiment, when referring to Figure 17 and Figure 18 In the steps described, on wafer W M An insulating layer 160 is formed on the upper surface of the conductive layer 151, covering the upper end of the conductive layer 151. Additionally, in reference... Figure 21 In the described steps, CMP and other processes are performed, using the insulating layer 160 as a termination layer, to planarize the upper surface of the polysilicon layer 140B.

[0090] According to this method, the upper surface of the polycrystalline silicon layer 140B can be effectively planarized. Furthermore, the insulating layer 160 can prevent laser light from reaching the conductive layer 151, thereby better suppressing the diffusion of metal atoms as described above. Therefore, the semiconductor memory device of this embodiment can be manufactured relatively easily.

[0091] [Second Implementation]

[0092] Next, refer to Figures 23-25 The semiconductor memory device of the second embodiment will be described. Figures 23-25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment, showing the... Figure 5 The corresponding composition.

[0093] The semiconductor memory device of the second embodiment is constructed in the same manner as the semiconductor memory device of the first embodiment. However, some of the manufacturing steps of the semiconductor memory device of the second embodiment differ from those of the semiconductor memory device of the first embodiment.

[0094] For example, as referenced Figure 17 and Figure 18As explained, in the manufacturing steps of the semiconductor memory device of the first embodiment, such as Figure 16 An insulating layer 160A is formed on the upper surface of the structure shown. A portion of the insulating layer 160A is selectively removed by methods such as RIE to form an insulating layer 160 covering the upper end of the conductive layer 151.

[0095] On the other hand, for example, such as Figure 23 As shown, in the manufacturing steps of the semiconductor memory device in the second embodiment, in such a way... Figure 16 An insulating layer 161A is formed on the upper surface of the structure shown, and an insulating layer 160A is formed on its upper surface. The insulating layer 161A contains, for example, silicon nitride (Si3N4). This step is performed, for example, by a method such as CVD.

[0096] Next, for example, such as Figure 24 As shown, the portion of insulating layer 160A corresponding to the memory block BLK is removed, exposing the upper surface of insulating layer 161A. This forms a plurality of insulating layers 160 covering the upper end of conductive layer 151. This step is performed, for example, by a method such as RIE (Reinforcing Interruption).

[0097] Next, for example, such as Figure 25 As shown, the portion of insulating layer 161A corresponding to the memory block BLK is removed, exposing the upper ends of the plurality of semiconductor layers 120. This forms a plurality of insulating layers 161 covering the upper ends of the conductive layer 151. This step can be performed, for example, by selectively removing a portion of the insulating layer 161A using a method such as wet etching.

[0098] [Third Implementation]

[0099] Next, refer to Figure 26 The semiconductor memory device of the third embodiment will be described. Figure 26 This is a schematic cross-sectional view used to illustrate the configuration of the semiconductor memory device according to the third embodiment.

[0100] The semiconductor memory device of the third embodiment is configured in a manner substantially the same as that of the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment replaces the inter-block structure 150 and the conductive layer 170 with an inter-block structure 350, an insulating layer 160, and a conductive layer 370.

[0101] The inter-block structure 350 is an insulating layer such as silicon oxide (SiO2) extending in the Z and X directions.

[0102] The conductive layer 370 may, for example, comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu) or aluminum (Al). The conductive layer 370 may, for example, function as part of a source line.

[0103] The conductive layer 370 covers the entire surface of the upper surfaces of the plurality of semiconductor layers 140 and the plurality of insulating layers 160 arranged in the Y direction. The conductive layer 370 is bonded to the upper surface of the semiconductor layers 140 and is in contact with the upper surface of the insulating layers 160.

[0104] In addition, the upper and lower surfaces of the conductive layer 370 are different from those of the conductive layer 170, and are formed in a generally flat manner.

[0105] The manufacturing method of the semiconductor memory device in the third embodiment is basically the same as that in the manufacturing method of the semiconductor memory device in the first embodiment. However, in the third embodiment, compared with the reference... Figure 13 In the steps described, an inter-block structure 350 is formed within the groove 150A. This step is performed, for example, by methods such as CVD and RIE. Additionally, the reference is not performed. Figure 22 The steps described.

[0106] Furthermore, in the manufacturing steps of the semiconductor memory device in the third embodiment, the reference can be performed in the same manner as in the second embodiment. Figures 23-25 The steps described herein are used instead of performing the same procedure as in the first embodiment. Figure 17 and Figure 18 The steps described. In this case, for example, as... Figure 27 As shown, an insulating layer 161 is provided between the inter-block structure 350 and the insulating layer 160 of the semiconductor memory device in the third embodiment.

[0107] [Fourth Implementation]

[0108] Next, refer to Figure 28 The semiconductor memory device of the fourth embodiment will be described. Figure 28 This is a schematic cross-sectional view used to illustrate the configuration of the semiconductor memory device according to the fourth embodiment.

[0109] The semiconductor memory device of the fourth embodiment is configured in a manner substantially the same as that of the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the fourth embodiment replaces the inter-block structure 150 and the conductive layer 170 with an inter-block structure 450 and a conductive layer 470.

[0110] The inter-bulk structure 450 is an insulating layer such as silicon oxide (SiO2) extending in the Z and X directions. The inter-bulk structure 450 includes: a first portion 451 disposed at a height position corresponding to the plurality of conductive layers 110 and insulating layers 101; and a second portion 452 disposed at a height position corresponding to the semiconductor layer 140.

[0111] The conductive layer 470 is constructed in essentially the same manner as the conductive layer 370 in the third embodiment. However, a portion of the lower surface of the conductive layer 470 is in contact with the upper surface of the inter-block structure 450, rather than with the upper surface of the insulating layer 160.

[0112] The manufacturing method of the semiconductor memory device in the fourth embodiment is basically the same as that in the manufacturing method of the semiconductor memory device in the first embodiment.

[0113] However, in the fourth embodiment, in relation to the reference Figure 11 The steps described correspond to steps such as, for example, Figure 29 As shown, groove 450A is formed. Groove 450A is formed in essentially the same manner as groove 150A. However, the height position of the bottom surface of groove 450A is adjusted to correspond to the height position of the upper end of the inter-block structure 450. The depth of groove 450A in the Z direction is at least greater than the depth of through hole 120A in the Z direction.

[0114] In addition, in comparison with the reference Figure 13 The steps described correspond to steps such as, for example, Figure 30 As shown, an inter-block structure 450 is formed within the groove 450A. This step is performed, for example, by methods such as CVD and RIE.

[0115] In addition, such as Figure 31 and Figure 32 As shown, the execution is as described in the reference. Figures 14-16 The steps described.

[0116] Additionally, the reference is not executed. Figure 17 and Figure 18 The steps described.

[0117] In addition, such as Figure 33 and Figure 34 As shown, the execution is as described in the reference. Figures 19-21 The steps described. However, as Figure 34 As shown, in relation to the reference Figure 21 In the steps described, the inter-block structure 450 is used as the termination layer for CMP, etc., instead of the insulating layer 160.

[0118] [Fifth Implementation]

[0119] Next, refer to Figures 35-38 The semiconductor memory device of the fifth embodiment will be described. Figure 35 This is a schematic top view used to illustrate the configuration of the semiconductor memory device according to the fifth embodiment. Figure 36 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 37 It is Figure 36A schematic cross-sectional view showing an enlarged portion of the structure. Figure 38 This is a schematic cross-sectional view showing an enlarged representation of a portion of the semiconductor memory device. Additionally, Figure 35 Corresponding to along line C-C' Figure 36 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 35 Corresponding to along line D-D' Figure 38 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 36 Corresponding to along line A-A' Figure 35 The structure shown is cut off, and the cross-section is observed along the direction of the arrow. Additionally, Figure 38 Corresponding to along line B-B' Figure 35 The structure shown is cut off, and the cross-section is observed along the direction of the arrow.

[0120] The semiconductor memory device of the fifth embodiment is configured in essentially the same manner as the semiconductor memory device of the third embodiment. However, the memory cell array region R of the semiconductor memory device of the third embodiment... MCA It comprises: a plurality of memory blocks BLK' arranged in the Y direction; a plurality of inter-block structures 350 disposed between the plurality of memory blocks BLK'; a semiconductor layer 540 disposed on the upper surface of the plurality of memory blocks BLK' and the plurality of inter-block structures 350; an insulating layer 560 disposed at the upper end of the inter-block structure 350; and a conductive layer 570 disposed on the upper surface of the semiconductor layer 540 and the insulating layer 560.

[0121] The memory block BLK' is constructed in essentially the same manner as the memory block BLK in the third embodiment. However, the memory block BLK' does not have a semiconductor layer 140.

[0122] Semiconductor layer 540 covers the entire surface of the upper surface of the plurality of memory blocks BLK' arranged in the Y direction, and is connected to the upper ends of all semiconductor layers 120 contained in the plurality of memory blocks BLK'. Additionally, as... Figure 35 As shown, a plurality of through holes 541 are provided at a specific interval in the X direction at a position on the semiconductor layer 540 corresponding to the inter-block structure 350.

[0123] In the illustrated example, in Figure 35 The cross section corresponding to line A-A' ( Figure 36 A through-hole 541 is provided. In this cross-section, the upper end of the inter-block structure 350 is not separated from the semiconductor layer 540, but faces the lower surface of the conductive layer 570 separated from the insulating layer 560. On the other hand, in Figure 35 The cross section corresponding to the B-B' line ( Figure 38No through-hole 541 is provided. In this cross-section, the upper end of the inter-block structure 350 faces the lower surface of the conductive layer 570 across the semiconductor layer 540.

[0124] In addition, such as Figure 37 As shown, the inner circumferential surface of the through hole 541 is inclined at the following angle: the lower part is further away from the central axis 542 of the through hole 541, and the upper part is closer to the central axis 542 of the through hole 541.

[0125] The insulating layer 560 may contain, for example, silicon oxide (SiO2). Figure 35 As shown, insulating layers 560 are arranged at specific intervals in the X direction along the upper end of the inter-block structure 350. Insulating layers 560 are respectively disposed inside the through-holes 541 provided in the semiconductor layer 540.

[0126] In addition, such as Figure 37 As shown, the outer peripheral surface of the insulating layer 560 is inclined at the following angle: the lower portion is further away from the central axis 542 of the through hole 541, and the upper portion is closer to the central axis 542 of the through hole 541. Therefore, the outer diameter of the lower surface of the insulating layer 560 is larger than the outer diameter of the upper surface of the insulating layer 560.

[0127] The conductive layer 570 is constructed in essentially the same manner as the conductive layer 370. The conductive layer 570 covers the upper surfaces of the semiconductor layer 540 and the insulating layer 560 across the entire surface. The conductive layer 570 is bonded to the upper surface of the semiconductor layer 540 and is in contact with the upper surface of the insulating layer 160.

[0128] The manufacturing method of the semiconductor memory device in the fifth embodiment is basically the same as that in the manufacturing method of the semiconductor memory device in the third embodiment.

[0129] However, in the fifth embodiment, in relation to the reference Figure 18 In the steps described, a portion of the insulating layer 160A corresponding to the memory block BLK and a portion of the insulating layer 160A corresponding to the inter-block structure 350 are removed, exposing the upper ends of the plurality of semiconductor layers 120 and a portion of the upper end of the inter-block structure 350. This forms a plurality of insulating layers 560 arranged in the X direction along the upper end of the inter-block structure 350. This step is performed, for example, by a method such as RIE.

[0130] Furthermore, the manufacturing steps of the semiconductor memory device in the fifth embodiment can be performed in the same manner as in the second embodiment. Figure 23 The steps described herein are used instead of performing the same procedures as in the first embodiment. Figure 17 The steps described herein. Alternatively, refer to... Figure 23 After the steps described, execute and refer to. Figure 18 The steps described correspond to the steps mentioned above. Alternatively, after this step, the steps described above can be performed and referenced. Figure 25 The steps described are the same as those steps.

[0131] In this case, an insulating layer 161 is provided between the inter-block structure 350 and the insulating layer 560 of the semiconductor memory device in the fifth embodiment.

[0132] [other]

[0133] In embodiments 1 to 4, referring to Figure 21 In the described steps, or the steps corresponding to those steps, methods such as CMP are performed, where the insulating layer 160 or the inter-block structure 450 is used as a terminating layer. Therefore, for example, as... Figure 39 As shown, the upper surface of the semiconductor layer 140 is sometimes formed as a concave surface, that is, the portion near the end in the Y direction is located on top, and the portion away from the end in the Y direction is located on the bottom. In addition, the upper and lower surfaces of the portion 171 of the conductive layer 170, the corresponding portion of the conductive layer 370, or the corresponding portion of the conductive layer 470 are sometimes also formed as planar surfaces corresponding to the upper surface of the semiconductor layer 140.

[0134] Similarly, in the fifth embodiment, in relation to the reference Figure 21 In the steps described, methods such as CMP are performed, where the insulating layer 560 is used as a termination layer. Therefore, the upper surface of the semiconductor layer 540 is sometimes formed as a concave surface, meaning the portion near the insulating layer 560 is on top, and the portion away from the insulating layer 560 is on the bottom. Additionally, the upper surface of the conductive layer 570 is sometimes formed as a corresponding planar surface.

[0135] Furthermore, several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0136] [Explanation of Symbols]

[0137] 110: Conductive layer

[0138] 120: Semiconductor layer

[0139] 130: Gate insulating film

[0140] 140: Semiconductor layer

[0141] 150: Interblock Structure

[0142] 160: Insulation layer

[0143] 170: Conductive layer.

Claims

1. A semiconductor memory device comprising: Substrate; Bit lines are disposed above the substrate and extend in a first direction parallel to the surface of the substrate; The first layer comprises a plurality of first conductive layers and a plurality of first insulating layers, wherein the plurality of first conductive layers and the plurality of first insulating layers are alternately deposited in a second direction intersecting the surface of the substrate; Multiple first semiconductor layers extend through the first stacked layer in the second direction, respectively; The second semiconductor layer extends in a third direction, parallel to the surface of the substrate, above the first semiconductor layer, and is electrically connected to each of the plurality of first semiconductor layers; The second stacked layer has a plurality of second conductive layers and a plurality of second insulating layers, the plurality of second conductive layers and the plurality of second insulating layers being stacked alternately in the second direction, and the first stacked layer and the second stacked layer being adjacent in the first direction; Multiple third semiconductor layers extend through the second stacked layer in the second direction; A fourth semiconductor layer extends over the second stacked layer in the third direction and is electrically connected to each of the plurality of third semiconductor layers; and The third conductive layer is in physical contact with the upper surface of the second semiconductor layer and the upper surface of the fourth semiconductor layer; wherein The second semiconductor layer and the fourth semiconductor layer extend parallel to each other in the third direction and are spaced apart from each other in the first direction.

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