A method for manufacturing a flash device

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides a FLASH device preparation method. The FLASH device preparation method can effectively eliminate the damage of the etching process to the select gate and the active region between the two adjacent select gates in the preparation process of the floating gate, the control gate and the erase layer. The improved process sequence can avoid damaging the top corner position of the select gate, avoid affecting the profile and the square resistance of the select gate, and thus ensure the electrical performance and reliability of the FLASH device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a FLASH device. Background Technology

[0002] As a core category of non-volatile memory, FLASH devices are widely used in smartphones, solid-state drives (SSDs), embedded systems, and other fields due to their advantages such as data retention after power failure, high read / write speeds, and long lifespan. With the evolution of semiconductor process nodes, the feature size of FLASH devices continues to shrink, and the three-dimensional integration of device structures continues to improve, placing stringent requirements on the fabrication accuracy and planarization quality of key layers.

[0003] The memory cell of a FLASH device typically includes key layers such as a semiconductor substrate, gate oxide (Gate OX), select gate (SG), control gate (CG), floating gate (FG), and erase polysilicon (EP). Among these, the select gate (SG) is the gate polysilicon responsible for the switching channel in the FLASH device's memory cell. In current FLASH device fabrication processes, the select gate (SG) is the first structure formed, and the gate oxide layer between the select gate (SG) and the semiconductor substrate is relatively thin (only 24 angstroms). Subsequent etching processes can damage the top corner of the select gate (SG), affecting its profile and sheet resistance (Rs), and may also damage the active region (AA) between adjacent select gates (SG).

[0004] Therefore, how to avoid damage to the select gate (SG) and the active region (AA) between two adjacent select gates (SG) during the etching process of FLASH devices, and ensure the electrical performance and reliability of FLASH devices, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a FLASH device. By postponing the etching process of the select gate, the problem of damage to the select gate and the active region between two adjacent select gates during the etching process of the FLASH device can be effectively eliminated, thereby ensuring the electrical performance and reliability of the FLASH device.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a FLASH device, the method comprising the following steps: forming an intermediate structure of the FLASH device, the intermediate structure comprising a semiconductor substrate having an active region, a gate oxide layer covering the surface of the active region, a select gate material layer located on the surface of the gate oxide layer, a select dielectric material layer covering the surface of the select gate material layer, a cell trench penetrating the select dielectric material layer and the select gate material layer, a sidewall located within the cell trench and covering the sidewall of the select gate material layer, two floating gates located within the cell trench and isolated by a control trench, and a sidewall covering the floating gate. A floating dielectric layer is formed on the electrode, and the control trench exposes the gate oxide layer; a control gate and a control dielectric layer are formed, the control gate filling the control trench and partially covering the floating dielectric layer, and the control dielectric layer covering the control gate; an erase layer is formed, the erase layer covering a portion of the select dielectric material layer, a portion of the floating dielectric layer, and a portion of the control dielectric layer; and the select dielectric material layer and the select gate material layer are etched to form a plurality of select gates, select dielectric layers, and connection trenches, the select gates being isolated from the floating gates by the sidewalls, and the connection trenches being located between two adjacent select gates and exposing the gate oxide layer.

[0007] The above technical solution, by improving the process sequence and placing the etching process of the select gate later, can effectively eliminate the problem of damage to the select gate and the active region between two adjacent select gates caused by the etching process involved in the preparation of the floating gate, control gate and erase layer. The improved process sequence can avoid damage to the top corner position of the select gate, avoid affecting the outline and sheet resistance of the select gate, thereby ensuring the electrical performance and reliability of the FLASH device. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic flowchart of a method for fabricating a FLASH device according to an embodiment of the present invention; Figures 2A-2E This is a schematic diagram of the structure after the intermediate structure of the FLASH device is formed, according to an embodiment of the present invention; Figures 3A-3D This is a schematic diagram of the structure after the formation of the control gate and the control dielectric layer according to an embodiment of the present invention; Figures 4A-4C This is a schematic diagram of the structure after the erasure layer is formed according to an embodiment of the present invention; Figures 5A-5B This is a schematic diagram of the structure after the formation of the select gate according to an embodiment of the present invention.

[0010] Explanation of reference numerals in the attached figures: 20. Semiconductor substrate; 201. Active region; 21. Gate oxide layer; 220. Select the gate material layer; 22. Select the gate; 230. Select the dielectric material layer; 23. Select the dielectric layer; 2301, First dielectric material layer; 231, First dielectric layer; 2302, Second dielectric material layer; 232, Second dielectric layer; 2303, Third dielectric material layer; 2303, Third dielectric layer; 209. Unit trench; 208. Control trench; 24. Side walls; 241. First sub-side wall; 242. Second sub-side wall; 243. Third sub-side wall; 25. Floating gate; 26. Floating dielectric layer; 270. Control gate material layer; 27. Control gate; 28. Control medium layer; 290. Erasure material layer; 29. ​​Erasure layer; 400. Patterned photoresist layer; 500. Connecting groove. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Please refer to the following: Figures 1-5B ,in, Figure 1 This is a schematic flowchart of a method for fabricating a FLASH device according to an embodiment of the present invention; Figures 2A-2E This is a schematic diagram of the structure after the intermediate structure of the FLASH device is formed, according to an embodiment of the present invention; Figures 3A-3D This is a schematic diagram of the structure after the formation of the control gate and the control dielectric layer according to an embodiment of the present invention; Figures 4A-4CThis is a schematic diagram of the structure after the erasure layer is formed according to an embodiment of the present invention; Figures 5A-5B This is a schematic diagram of the structure after the formation of the select gate according to an embodiment of the present invention.

[0013] like Figure 1 As shown, the fabrication method of the FLASH device includes the following steps: S1, forming an intermediate structure of the FLASH device, the intermediate structure including a semiconductor substrate having an active region, a gate oxide layer covering the surface of the active region, a select gate material layer located on the surface of the gate oxide layer, a select dielectric material layer covering the surface of the select gate material layer, a cell trench penetrating the select dielectric material layer and the select gate material layer, a sidewall located in the cell trench and covering the sidewall of the select gate material layer, two floating gates located in the cell trench and isolated by the control trench, and a floating dielectric layer covering the floating gates. S1. A control trench exposes the gate oxide layer; S2. A control gate and a control dielectric layer are formed, the control gate filling the control trench and partially covering the floating dielectric layer, the control dielectric layer covering the control gate; S3. An erase layer is formed, the erase layer covering a portion of the select dielectric material layer, a portion of the floating dielectric layer, and a portion of the control dielectric layer; and S4. The select dielectric material layer and the select gate material layer are etched to form a plurality of select gates, select dielectric layers, and connection trenches, the select gates being isolated from the floating gates by the sidewalls, and the connection trenches being located between two adjacent select gates and exposing the gate oxide layer.

[0014] Please refer to steps S1 and... Figure 2E This forms an intermediate structure for a FLASH device. The intermediate structure includes a semiconductor substrate 20 having an active region 201, a gate oxide layer 21 covering the surface of the active region 201, a select gate material layer 220 located on the surface of the gate oxide layer 21, a select dielectric material layer 230 covering the surface of the select gate material layer 220, a cell trench 209 penetrating the select dielectric material layer 230 and the select gate material layer 220, a sidewall 24 located in the cell trench 209 and covering the sidewall of the select gate material layer 220, two floating gates 25 located in the cell trench 209 and isolated by a control trench 208, and a floating dielectric layer 26 covering the floating gates 25. The control trench 208 exposes the gate oxide layer 21.

[0015] In some embodiments, the intermediate structure for forming a FLASH device described in step S1 can be implemented using the following steps: (11) providing a semiconductor substrate 20, wherein the active region 201 is formed within the semiconductor substrate 20, the surface of the active region 201 is covered by the gate oxide layer 21, the surface of the gate oxide layer 21 is covered by the selected gate material layer 220, and the surface of the selected gate material layer 220 is covered by the selected dielectric material layer 230, such as Figure 2A As shown; (12) forming a cell trench 209 penetrating the selected dielectric material layer 230 and the selected gate material layer 220, as shown. Figure 2B As shown; (13) A sidewall 24 is formed within the cell trench 209, covering the sidewall of the selected gate material layer 220, as shown. Figure 2C As shown; (14) Two floating gates 25 isolated by the control trench 208 are formed in the unit trench 209, the control trench 208 exposing the gate oxide layer 21 between the two floating gates 24, as shown. Figure 2D As shown; (15) forming the floating dielectric layer 26 covering the surface of the floating gate 25, as shown. Figure 2E As shown. That is, in this embodiment, the process sequence is to deposit the selected gate material layer 220 and the selected dielectric material layer 230, and then fabricate the floating gate 25. Since the area to be formed by the selected gate is protected by the thicker selected dielectric material layer, and the area to be formed by the connection trench is protected by both the selected dielectric material layer and the selected gate material layer, this protection mechanism can effectively eliminate the problem of damage to the selected gate and the active region between two adjacent selected gates caused by the etching process involved in the fabrication process of the floating gate and the subsequent control gate and erase layer, thereby ensuring the electrical performance and reliability of the FLASH device.

[0016] In some embodiments, the semiconductor substrate 20 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; it may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0017] In some embodiments, an active region 201 can be formed in the semiconductor substrate 20 by ion implantation; a gate oxide layer 21 is formed on the surface of the active region 201; a polysilicon material is deposited on the surface of the gate oxide layer 21 to form the selected gate material layer 220; a first dielectric material layer 2301 (e.g., silicon oxide layer), a second dielectric material layer 2302 (e.g., silicon nitride layer), and a third dielectric material layer 2303 (e.g., silicon oxide layer) are sequentially deposited; the three stacked dielectric material layers together serve as the selected dielectric material layer 230. The resulting structure is as follows: Figure 2A As shown, the three dielectric materials—silicon oxide, silicon nitride, and silicon oxide—are stacked together to form the selection dielectric material layer 230. This layer effectively protects the selection gate after the selection dielectric layer is formed, preventing charged particles in the selection gate from diffusing upwards. Furthermore, the thickness of the three stacked dielectric material layers increases sequentially, with the thickness of the bottom first dielectric material layer 2301 being greater than the thickness of the gate oxide layer 21; that is, the thickness of any stack of the selection dielectric material layers is greater than the thickness of the gate oxide layer. In other embodiments, the selection dielectric material layer 230 can also be a single-layer structure; wherein, the thickness of the selection dielectric material layer 230 is greater than the thickness of the gate oxide layer 21. Specifically, the thickness of the gate oxide layer 21 can be tens of angstroms, and the thickness of the selection dielectric material layer 230 can be hundreds of angstroms, with the specific thickness set according to the process and device performance requirements.

[0018] In some embodiments, a cell trench 209 can be formed through photolithography and etching processes, penetrating the selected dielectric material layer 230 and the selected gate material layer 220, exposing the underlying gate oxide layer 21. The resulting structure is as follows: Figure 2B As shown.

[0019] In some embodiments, sidewall material can be deposited and etched back within the cell trench 209 to form a sidewall 24 covering the sidewalls of the select gate material layer 220. The sidewall 24 electrically isolates the floating gate 25 from the subsequently formed select gate 22. The sidewall can be a single-layer structure or include a stacked multilayer structure. In this embodiment, the sidewall 24 includes a first sub-sidewall 241 (e.g., a silicon oxide layer), a second sub-sidewall 242 (e.g., a silicon nitride layer), and a third sub-sidewall 243 (e.g., a silicon oxide layer) sequentially stacked and covering the sidewalls of the select gate material layer 220; that is, the sidewall 24 has an ONO structure. The formed structure is as follows: Figure 2C As shown.

[0020] In some embodiments, polysilicon material is deposited and patterned within the unit trench 209 to form two floating gates 25 isolated from each other by an intermediate control trench 208, the control trench 208 exposing the gate oxide layer 21 in the region between the two floating gates 25. The resulting structure is as follows: Figure 2D As shown. The floating gate 25 and the selected gate material layer 220 can be made of the same material, for example, both comprising polysilicon.

[0021] In some embodiments, a dielectric material is deposited and patterned on the surface of the floating gate 25 to form the floating dielectric layer 26. The resulting structure is as follows: Figure 2E As shown. The floating dielectric layer 26 includes a silicon oxide layer covering the surface of the floating gate 25 opposite to the sidewall 24 and the gate oxide layer 21.

[0022] Please refer to step S2 and... Figure 3D A control gate 27 and a control dielectric layer 28 are formed, wherein the control gate 27 fills the control trench 208 and partially covers the floating dielectric layer 26, and the control dielectric layer 28 covers the control gate 27.

[0023] In some embodiments, the formation of the control gate 27 and the control dielectric layer 28 in step S2 can be implemented by the following steps: (21) forming a control gate material layer 270 that fills the control trench 208 and covers the selected dielectric material layer 230, such as Figure 3A As shown; (22) Etch back the control gate material layer 270, retaining the control gate material layer 270 within the control trench 208, as shown. Figure 3B As shown; (23) using the first mask (not shown) as a shield, etch the control gate material layer 270 within the control trench 208, and use the remaining control gate material layer 270 as the control gate 27, as shown. Figure 3C As shown; wherein, the first mask has an etching window exposing the control gate material layer within the control trench; (24) forming the control dielectric layer 28 covering the control gate 27, as shown Figure 3D As shown. The material of the control gate 27 can be the same as the material of the select gate material layer 220, for example, both comprising polysilicon. The control dielectric layer 28 includes a silicon oxide layer covering the surface of the control gate 27 opposite to the gate oxide layer 21.

[0024] The maximum thickness of the floating gate 25 is greater than the thickness of the control gate 27, thereby increasing the charge storage capacity of the floating gate, increasing the coupling capacitance and coupling coefficient between gates, and reducing crosstalk between devices.

[0025] Please refer to step S3 and... Figure 4C An erasure layer 29 is formed, which covers a portion of the selected medium material layer 230, a portion of the floating medium layer 26, and a portion of the control medium layer 28.

[0026] In some embodiments, the formation of the erase layer 29 in step S3 can be achieved by the following steps: (31) depositing polysilicon material to form an erase layer 290 covering the selected dielectric material layer 230, a portion of the floating dielectric layer 26 (specifically, the floating dielectric layer 26 exposed outside the control dielectric layer 28), and the control dielectric layer 28, such as Figure 4A As shown; (32) A patterned photoresist layer 400 is formed on the erasing material layer 290, the occlusion area of ​​the patterned photoresist layer 400 covering a portion of the selected medium material layer 230, a portion of the floating medium layer 26 (specifically, the floating medium layer 26 exposed outside the control medium layer 28), and a portion of the control medium layer 28, as shown. Figure 4B As shown; (33) The eraser layer 290 is etched using the patterned photoresist layer 400 as a mask, the remaining eraser layer is used as the eraser layer 29, and the patterned photoresist layer 400 is removed, resulting in the structure shown. Figure 4C As shown. The material of the erase layer 29 can be the same as the material of the selected gate material layer 220, for example, both include polysilicon.

[0027] Please refer to step S4 and... Figure 5B The selected dielectric material layer 230 and the selected gate material layer 220 are etched to form a plurality of selected gates 22, a selected dielectric layer 23 and a connection trench 500. The selected gates 22 are isolated from the floating gates 25 by the sidewalls 24. The connection trench 500 is located between two adjacent selected gates 22 and exposes the gate oxide layer 21.

[0028] In some embodiments, the etching of the selected dielectric material layer 230 and the selected gate material layer 220 in step S4 to form a plurality of selected gates 22, selected dielectric layers 23, and connection trenches 500 can be specifically implemented by the following steps: (41) Etching the selected dielectric material layer 230 with a second mask (not shown) as a shield, and using the remaining selected dielectric material layer as the selected dielectric layer 23, such as Figure 5AAs shown; wherein, the second mask has an etching window exposing the selected dielectric material layer to be formed in the region of the connection trench; (42) the selected gate material layer 220 is etched with the selected dielectric layer 23 as a mask and the gate oxide layer 21 as a stop layer to form the connection trench 500 penetrating the selected gate material layer 220, and the remaining selected gate material layer is used as the selected gate 22, as shown. Figure 5B As shown. That is, the connection trench 500 divides the select gate material layer 220 into a plurality of select gates 22 and the select dielectric material layer 230 into a plurality of select dielectric layers 23, thereby forming a plurality of independent unit structures. The connection trench 500 exposes the gate oxide layer 21 between two adjacent select gates 22, and the select dielectric layer 23 covers the surface of the select gate 22 that exposes the gate oxide layer 21 one-to-one.

[0029] In some embodiments, the connection trench 500 corresponds to the drain region of the active region 201. The connection trench 500 is used to subsequently form a connection structure to externally connect the drain region.

[0030] In this embodiment, the selection dielectric layer 23 includes a silicon oxide layer 231, a silicon nitride layer 232, and a silicon oxide layer 233 sequentially stacked and covering the surface of the selection gate 22. Furthermore, the thickness of any one of the stacked layers of the selection dielectric layer 23 (any one of the silicon oxide layer 231, silicon nitride layer 232, and silicon oxide layer 233) is greater than the thickness of the gate oxide layer. That is, even if the gate oxide layer between the selection gate and the semiconductor substrate is thin (e.g., only 24 angstroms), the improved process sequence in this embodiment can avoid damaging the active region (AA) between two adjacent selection gates.

[0031] In some embodiments, the maximum thickness of the floating gate 25 is greater than the thickness of the selected gate 22, thereby increasing the charge storage capacity of the floating gate, enhancing charge retention capability, and reducing crosstalk between devices.

[0032] The FLASH device fabrication method described in the above embodiments, by improving the process sequence and placing the etching process of the select gate later, can effectively eliminate the problem of damage to the select gate and the active region between two adjacent select gates caused by the etching process involved in the fabrication processes of the floating gate, control gate, and erase layer. The improved process sequence can avoid damage to the top corner of the select gate, avoid affecting the profile and sheet resistance (Rs) of the select gate, thereby ensuring the electrical performance and reliability of the FLASH device.

[0033] In the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessarily obscuring the concept of the present invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a…" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a FLASH device, characterized in that, The method includes the following steps: An intermediate structure for forming a FLASH device is provided, the intermediate structure including a semiconductor substrate having an active region, a gate oxide layer covering the surface of the active region, a select gate material layer located on the surface of the gate oxide layer, a select dielectric material layer covering the surface of the select gate material layer, a cell trench penetrating the select dielectric material layer and the select gate material layer, a sidewall located in the cell trench and covering the sidewall of the select gate material layer, two floating gates located in the cell trench and isolated by a control trench, and a floating dielectric layer covering the floating gates, wherein the control trench exposes the gate oxide layer; A control gate and a control dielectric layer are formed, wherein the control gate fills the control trench and partially covers the floating dielectric layer, and the control dielectric layer covers the control gate; An erasure layer is formed, which covers a portion of the selected medium material layer, a portion of the floating medium layer, and a portion of the control medium layer; as well as The selected dielectric material layer and the selected gate material layer are etched to form a plurality of selected gates, a selected dielectric layer and a connection trench. The selected gates are isolated from the floating gates through the sidewalls, and the connection trenches are located between two adjacent selected gates and expose the gate oxide layer.

2. The method according to claim 1, characterized in that, The specific steps involved in forming the intermediate structure of a FLASH device include: A semiconductor substrate is provided, wherein the active region is formed therein, the surface of the active region is covered by the gate oxide layer, the surface of the gate oxide layer is covered by the selected gate material layer, and the surface of the selected gate material layer is covered by the selected dielectric material layer; Forming a unit trench that penetrates the selected dielectric material layer and the selected gate material layer; A sidewall is formed within the cell trench, covering the sidewall of the selected gate material layer; Two floating gates are formed in the unit trench and isolated by the control trench, the control trench exposing the gate oxide layer between the two floating gates; The floating dielectric layer is formed to cover the surface of the floating gate.

3. The method according to claim 1, characterized in that, The steps for forming the control gate and the control dielectric layer specifically include: A control gate material layer is formed that fills the control trench and covers the selected dielectric material layer; The control gate material layer is etched back, while retaining the control gate material layer within the control trench; The control gate material layer within the control trench is etched using a first mask as a shield, and the remaining control gate material layer is used as the control gate, wherein the first mask has an etching window that exposes the control gate material layer within the control trench; The control dielectric layer is formed to cover the control gate.

4. The method according to claim 1, characterized in that, The steps for forming the eraser layer specifically include: Deposit polycrystalline silicon material to form an erasure material layer covering the selected dielectric material layer, a portion of the floating dielectric layer, and the control dielectric layer; A patterned photoresist layer is formed on the erasing material layer, and the occlusion area of ​​the patterned photoresist layer covers a portion of the selected medium material layer, a portion of the floating medium layer, and a portion of the control medium layer; The eraser layer is etched using the patterned photoresist layer as a mask, the remaining eraser layer is used as the eraser layer, and the patterned photoresist layer is removed.

5. The method according to claim 1, characterized in that, The step of etching the selected dielectric material layer and the selected gate material layer to form a plurality of selected gates, selected dielectric layers and interconnect trenches specifically includes: The selected dielectric material layer is etched using a second mask as a shield, and the remaining selected dielectric material layer is used as the selected dielectric layer. The second mask has an etching window that exposes the selected dielectric material layer to be formed in the connection trench region. The selected gate material layer is etched using the selected dielectric layer as a shield and the gate oxide layer as a stop layer to form the connection trench that penetrates the selected gate material layer, and the remaining selected gate material layer is used as the selected gate.

6. The method according to claim 1, characterized in that, The thickness of the selected dielectric layer is greater than the thickness of the gate oxide layer.

7. The method according to claim 1, characterized in that, The selected dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked and cover the surface of the selected gate. The sidewall includes a first sub-sidewall, a second sub-sidewall, and a third sub-sidewall that are sequentially stacked and cover the sidewall of the selection gate; The floating dielectric layer includes a silicon oxide layer covering the surface of the floating gate away from the sidewall and the gate oxide layer; The control dielectric layer includes a silicon oxide layer covering the surface of the control gate opposite to the gate oxide layer.

8. The method according to claim 7, characterized in that, The first dielectric layer and the third dielectric layer are made of silicon oxide, and the second dielectric layer is made of silicon nitride. The first sub-sidewall and the third sub-sidewall are made of silicon oxide, and the second sub-sidewall is made of silicon nitride.

9. The method according to claim 7, characterized in that, The thickness of any stack of the selected dielectric layer is greater than the thickness of the gate oxide layer.

10. The method according to claim 1, characterized in that, The maximum thickness of the floating gate is greater than the thickness of the selection gate, and the maximum thickness of the floating gate is greater than the thickness of the control gate.

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