Flash memory device and method of forming the same

Abstract

A flash memory device and a method of forming the same are provided. The flash memory device includes a substrate, a semiconductor stack structure, and a plurality of isolation parts. The semiconductor stack structure is disposed on the substrate. The semiconductor stack structure includes a first floating gate and a second floating gate. The isolation parts are disposed in the substrate such that the semiconductor stack structure is sandwiched between the isolation parts. The isolation parts include a first dielectric fill layer, a second dielectric liner layer, and a third dielectric fill layer. The first dielectric fill layer is located at a lower portion of the isolation part. The second dielectric liner layer conformally covers the first dielectric fill layer. The third dielectric fill layer is located at an upper portion of the isolation part. The first dielectric fill layer and the third dielectric fill layer are formed of a first material, and the second dielectric liner layer is formed of a second material different from the first material.

Description

Technical Field

[0001] This invention relates to flash memory devices and methods of forming them, and particularly to the isolation components of NAND type flash memory devices and methods of forming them. Background Technology

[0002] To increase component density and improve overall performance within flash memory devices, manufacturing technologies continue to strive for miniaturization of component size. However, flash memory manufacturing technology faces new challenges in the miniaturization process. Therefore, it is urgent to overcome the various problems that arise. Summary of the Invention

[0003] This invention provides a flash memory device, including a substrate, a semiconductor stack structure, and a plurality of isolation components. The semiconductor stack structure is disposed on the substrate. The semiconductor stack structure includes a first floating gate and a second floating gate. The second floating gate is disposed on the first floating gate. Isolation components are disposed in the substrate and extend beyond the substrate to sandwich the semiconductor stack structure between the isolation components. Each isolation component includes a first dielectric fill layer, a second dielectric liner, and a third dielectric fill layer. The first dielectric fill layer is located at the lower portion of the isolation component. The second dielectric liner conformably covers the first dielectric fill layer. The third dielectric fill layer is located at the upper portion of the isolation component, such that the second dielectric liner is sandwiched between the first and third dielectric fill layers. The first and third dielectric fill layers are formed of a first material, and the second dielectric liner is formed of a second material different from the first material.

[0004] This invention provides a method for forming a flash memory device, including providing a substrate; forming a semiconductor stack structure and a plurality of isolation components on the substrate. The isolation components protrude from the substrate such that the semiconductor stack structure is sandwiched between the isolation components. The semiconductor stack structure includes a first floating gate and a second floating gate. The second floating gate is disposed on the first floating gate. Forming each isolation component includes forming a first dielectric fill layer in the substrate adjacent to the semiconductor stack structure. A first top surface of the first dielectric fill layer is recessed into a second top surface of the semiconductor stack structure; a second dielectric pad material layer is compliantly formed on the semiconductor stack structure and the first top surface of the first dielectric fill layer; a third dielectric fill material layer is formed on the second dielectric pad material layer; and a portion of the second dielectric pad material layer and a portion of the third dielectric fill material layer are removed to expose a plurality of second side surfaces of the second floating gate. The first and third dielectric fill layers are formed of a first material, and the second dielectric pad material layer is formed of a second material, wherein the second material is different from the first material. Attached Figure Description

[0005] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings:

[0006] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A , Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B This is a partial cross-sectional schematic diagram of each manufacturing process stage of a method for forming a flash memory device according to some embodiments of the present invention.

[0007] Symbol explanation:

[0008] 10, 20: Position;

[0009] 100, 110, 120: Direction;

[0010] 200: Base;

[0011] 202: Tunneling dielectric layer;

[0012] 202S, 206US, 206LS: Side view;

[0013] 200T, 202T, 206LT, 210T, 220T, 226R1'T, 230T, 230R1T, 230R1'T, 230R2T, 216T, 236-1RT, 238-1T, 238-2T, 238-1RT, 240-2RT: Top surface;

[0014] 206L: First floating gate;

[0015] 206U: Second floating gate;

[0016] 210: Floating gate;

[0017] 212N: Nitride layer;

[0018] 212O: Oxide layer;

[0019] 216: Mask pattern;

[0020] 220, 250: Semiconductor stacking structure;

[0021] 224, 224R1, 224R1', 224R2, 236-1R, 236-2R: Dielectric sheath;

[0022] 226, 226R1, 226R1', 226R2, 238-1R: Dielectric filling layer;

[0023] 230, 230R1, 230R1', 230R2: Isolation structure;

[0024] 234: Dielectric spacer layer;

[0025] 236, 236-1, 236-2: Dielectric pad material layer;

[0026] 238-1, 238-2: Dielectric filling material layers;

[0027] 240-1, 240-2, 240-1R, 240-2R: Isolation components;

[0028] 240-1L: lower part;

[0029] 240-1U: Upper part;

[0030] 242: Gate dielectric layer;

[0031] 246: Control gate layer;

[0032] 500: Flash memory device;

[0033] O1, O2, O3, O4: Openings. Detailed Implementation

[0034] The invention is described more fully below with reference to the accompanying drawings of embodiments thereof. The invention may be implemented in various different ways, and is not limited to the embodiments described. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements.

[0035] In existing flash memory manufacturing processes, the isolation components in the source / drain regions of the flash memory device located in the array region exhibit recesses of varying depths in areas with different pattern densities, causing word line disturbance (WL disturb) and affecting the electrical performance and reliability of the final flash memory device. Therefore, a flash memory and its fabrication method are needed to solve the aforementioned problems.

[0036] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A , Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B These are cross-sectional schematic diagrams of positions 10 and 20 in the array region of the flash memory device 500 at various manufacturing process stages with different pattern densities. In some embodiments, position 10 is a position with a higher pattern density, and position 20 is a position with a lower pattern density. For example, position 10 may be a semiconductor stack structure 250 having a floating gate and a control gate. Figure 8A The position 20 can be located between adjacent semiconductor stack structures 250. Figure 1A , Figure 1B In the following diagrams, directions 100, 110, and 120 are shown as the x-direction, y-direction, and z-direction, respectively. Furthermore, directions 100 and 110 are substantially parallel to the top surface 200T of the substrate 200, and can also be referred to as the word line (width) direction and bit line (length) direction of the flash memory device 500, respectively. Direction 120 is substantially perpendicular to the top surface 200T of the substrate 200 (also referred to as the longitudinal direction 120).

[0037] like Figure 1A , Figure 1B As shown, a substrate 200 is provided. The substrate 200 may include an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate, gallium arsenide substrate, gallium phosphide substrate, indium phosphide substrate, indium arsenide substrate, and / or indium antimonide substrate; or an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or combinations thereof. In one embodiment, the substrate 200 may be an insulator-on-silicon substrate. In this embodiment, the substrate 200 is a silicon substrate.

[0038] Next, a plurality of tunneling dielectric layers 202, a plurality of semiconductor stacked structures 220, and a plurality of isolation structures 230R1 are formed on the substrate 200 at the location 10 where the floating gate is provided, and a plurality of mask patterns 216 and a plurality of isolation structures 230 are formed on the substrate 200 at the location 20 where the floating gate is not provided. The semiconductor stacked structure 220 may be formed by forming a tunneling dielectric material layer (not shown) and a semiconductor stacked layer (not shown) including a mask material layer on the substrate 200 at the location 10, and forming a mask material layer on the substrate 200 at the location 20. Next, a patterned mask is used to etch the tunneling dielectric material layer and semiconductor stack layer at location 10 and the mask material layer at location 20 using an etching process to form a plurality of trenches (not shown) in the substrate 200. The semiconductor stack layer at location 10 is divided into a plurality of tunneling dielectric layers 202 and a plurality of semiconductor stack structures 220 by the trenches, and the mask material layer at location 20 is divided into a plurality of mask patterns 216 by the trenches. In some embodiments, the etching process for forming the semiconductor stack structure 220 (or mask pattern 216) may include anisotropic etching processes, such as dry etching processes.

[0039] A tunneling dielectric layer 202 is disposed on a substrate 200 and sandwiched between the substrate 200 and the semiconductor stack structure 220. In some embodiments, the tunneling dielectric layer 202 may include an oxide, a nitride, an oxynitride, or a combination thereof. For example, the tunneling dielectric layer 202 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. In this embodiment, the tunneling dielectric layer 202 is, for example, silicon oxide. In some embodiments, the tunneling dielectric layer 202 may be formed using a deposition process or a thermal oxidation process.

[0040] In position 10, the semiconductor stacked structure 220 and the isolation structure 230R1 are staggered in direction 100, and in position 20, the mask pattern 216 and the isolation structure 230 are staggered in direction 100. Furthermore, the isolation structures 230 and 230R1 protrude from the substrate, such that the semiconductor stacked structure 220 in position 10 is sandwiched between the isolation structures 230R1 in direction 100, and the mask pattern 216 in position 200 is sandwiched between the isolation structures 230 in direction 100.

[0041] like Figure 1AAs shown, the semiconductor stack structure 220 sequentially includes a floating gate 210 and a mask pattern 216 from bottom to top. In some embodiments, the floating gate 210 includes a first floating gate 206L disposed on the tunneling dielectric layer and a second floating gate 206U disposed on the first floating gate 206L. The first floating gate 206L may not have dopants, and the second floating gate 206U may have dopants. In some embodiments, the floating gate 210 may include a conductive material. For example, the floating gate 210 may be doped or undoped polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, or a combination thereof. For example, the first floating gate 206L may be undoped polycrystalline silicon, and the second floating gate 206U may be doped polycrystalline silicon. In some embodiments, the dopant may include N-type or P-type dopants, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (BF). 3+ In this embodiment of the invention, the dopant is P-type to increase the number of electrons controlled by the subsequent control gate. In some embodiments, a deposition fabrication process can be used to form the floating gate 210.

[0042] In some embodiments, the mask pattern 216 includes an oxide layer 212O and a nitride layer 212N. The mask pattern 216 can be used as an etching mask for the etching process that forms the tunneling dielectric layer 202 and the floating gate 210, so as to protect the underlying film layers from the influence of the manufacturing process.

[0043] In some embodiments, the oxide layer 212O comprises an oxide, such as tetraethylorthosilicate (TEOS) oxide. In some embodiments, the nitride layer 212N comprises a nitride, such as silicon nitride (SiN) or silicon oxynitride (SiON). Figure 1A and Figure 1B As shown, the mask patterns 216 at positions 10 and 20 can have the same structure.

[0044] After forming the semiconductor stack structure 220 at position 10 and the mask pattern 216 at position 20, isolation structures 230R1 and 230 are formed at positions 10 and 20 of the substrate 200. The formation of the isolation structures 230R1 and 230 may include: performing a deposition process to deposit dielectric pad material layers (not shown) and dielectric fill material layers (not shown) in multiple trenches of adjacent semiconductor stack structures 220 at position 10 and adjacent mask patterns 216 at position 20. Next, a removal process is performed to remove excess dielectric pad material layers and dielectric fill material layers from the top surfaces of the semiconductor stack structures 220 at position 10 and the mask patterns 216 at position 20, thereby forming multiple isolation structures 230 at positions 10 and 20. Afterward, a patterning process may be performed to etch the isolation structures 230 at position 10 to form isolation structure 230R1 at position 10, and to form openings O1 between the semiconductor stack structures 220. In some embodiments, the patterning manufacturing process for forming the isolation structures 230R1, 230 may include anisotropic etching manufacturing processes, such as dry etching manufacturing processes. The removal manufacturing process may include planarization manufacturing processes or the aforementioned etching manufacturing processes. The aforementioned planarization manufacturing processes may include chemical mechanical polishing (CMP).

[0045] An isolation structure 230R1 is formed in a substrate 200 adjacent to the semiconductor stack structure 220, defining the active region at location 10 (located on both sides of the isolation structure 230R1). Similarly, an isolation structure 230 is formed in a substrate 200 adjacent to the mask pattern 216, defining the active region at location 20 (located on both sides of the isolation structure 230). In some embodiments, isolation structures 230 and 230R1 may be single-layer or multi-layer structures. In this embodiment, isolation structures 230 and 230R1 are multi-layer structures. For example, isolation structure 230R1 has a dielectric substrate 224R1 and a dielectric filling layer 226R1 disposed on the dielectric substrate 224R1, and isolation structure 230 has a dielectric substrate 224 and a dielectric filling layer 226 disposed on the dielectric substrate 224.

[0046] like Figure 1AAs shown, a dielectric liner 224R1 is formed in a substrate 200 adjacent to the semiconductor stack structure 220. The dielectric liner 224R1 surrounds the dielectric fill layer 226R1 and abuts the opposite sides of the tunneling dielectric layer 202 and the floating gate 210. The top surface 230R1T of the isolation structure 230R1 is recessed into the top surface 220T of the semiconductor stack structure 220. For example, the top surface 230R1T of the isolation structure 230R1 (including the top surface of the dielectric fill layer 226R1) is a concave arcuate surface. In some embodiments, the lowest point of the concave arcuate surface (top surface 230R1T) is located above the top surface 206LT of the first floating gate 206L and below the top surface 210T of the floating gate 210 (i.e., the top surface of the second floating gate 206U).

[0047] like Figure 1B As shown, a dielectric liner 224 is formed in a substrate 200 adjacent to the mask pattern 216. The dielectric liner 224 surrounds the dielectric fill layer 226 and is adjacent to the opposite side of the mask pattern 216. The top surface 230T of the isolation structure 230 is aligned with the top surface 216T of the mask pattern 216.

[0048] In some embodiments, the isolation structures 230, 230R1 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, fluorinated silicate glass, undoped silicon glass, organosilicon glass, or SiO2. x C y Spin-coated glass, tetraethoxysilane, low dielectric constant dielectric material, or a combination thereof. In some embodiments, the dielectric substrate 224 and dielectric filling layer 226 of the isolation structure 230 and the dielectric substrate 224R1 and dielectric filling layer 226R1 of the isolation structure 230R1 comprise the same material, such as silicon oxide.

[0049] It should be noted that the pattern density at position 10 is higher than that at position 20. The spacing P2 of the mask pattern 216 at position 20 is greater than the spacing P1 of the semiconductor stack structure 220 at position 10; therefore, the shapes exhibited by the isolation structures 230, 230R1 will also differ slightly. For example, as... Figure 1A As shown, the isolation structure 230R1 in position 10 has a large depth-to-width ratio, producing a teardrop-shaped profile. In contrast, as... Figure 1B As shown, the isolation structure 230 in position 20 has a small depth-to-width ratio, creating a trapezoidal profile (i.e., a wider bottom).

[0050] Next, a deposition process such as atomic layer deposition (ALD) can be performed to compliantly form a dielectric spacer layer 234 on the semiconductor stack structure 220, the mask pattern 216, and the isolation structures 230R1 and 230. The dielectric spacer layer 234 covers the top surface 220T and part of the side surface of the semiconductor stack structure 220, the top surface 216T of the mask pattern 216, the top surface 230R1T of the isolation structure 230R1, and the top surface 230T of the isolation structure 230.

[0051] In some embodiments, the dielectric spacer layer 234 and the dielectric liner 224 and dielectric fill layer 226 of the isolation structure 230, as well as the dielectric liner 224R1 and dielectric fill layer 226R1 of the isolation structure 230R1, comprise the same material, such as silicon oxide.

[0052] Next, as Figure 2A and Figure 2B As shown, an etching process, such as reactive ion etching (RIE), can be performed to etch the isolation structures 230R1 and 230 at locations 10 and 20, respectively, and to remove the dielectric spacer layer 234. The etching process etches the dielectric filling layer 226R1 and the dielectric liner layer 224R1 from the opening O1 at location 10, exposing the opposite side surface 206US of the second floating gate 206U (or completely exposing the opposite side surface 206US of the second floating gate 206U). At location 10, the etched isolation structure (including the dielectric filling layer and the dielectric liner layer) is designated as isolation structure 230R1' (including the dielectric filling layer 226R1' and the dielectric liner layer 224R1').

[0053] Furthermore, the dielectric filling layer 226 and dielectric liner 224 in the above-mentioned etching manufacturing process are etched in position 20, and an opening O2 is formed between the mask pattern 216. In position 20, the etched isolation structure (including the dielectric filling layer and the dielectric liner) is designated as isolation structure 230R2 (including dielectric filling layer 226R2 and dielectric liner 224R2).

[0054] In some embodiments, the top surface 230R1'T of the etched isolation structure 230R1' is a concave arcuate surface. This concave arcuate surface may intersect with the opposite side surface 206LS of the first floating gate 206L, and may partially expose the opposite side surface 206LS of the first floating gate 206L. Furthermore, the lowest point of the concave arcuate surface is located above the top surface 202T of the tunneling dielectric layer 202 and below the top surface of the first floating gate 206L. In some embodiments, the etched dielectric filling layer 226R1' (or isolation structure 230R1') may partially cover the opposite side surface 206LS of the first floating gate 206L.

[0055] Since the spacing P2 of the mask pattern 216 at position 20 is greater than that of the semiconductor stack structure 220 at position 10, the opening O2 formed in the isolation structure 230R2 is shallower.

[0056] Next, a cleaning manufacturing process is performed on the intermediate structure of the manufacturing process. In some embodiments, the isolation structures 230R1' and 230R2 may be further subjected to an annealing manufacturing process to further strengthen the isolation structures 230R1' and 230R2.

[0057] Next, as Figure 3A and Figure 3B As shown, a deposition manufacturing process such as atomic layer deposition (ALD) can be performed to compliantly form a dielectric pad material layer 236 on the top surface 220T of the semiconductor stacked structure 220, the top surface 216T of the mask pattern 216, the top surface 230R1'T of the isolation structure 230R1', and the top surface 230R2T of the isolation structure 230R2 in positions 10 and 20.

[0058] The dielectric pad material layer 236 covers the dielectric substrates 224R1' and 224R2 and the dielectric fill layers 226R1' and 226R2, and is adjacent to the opposite side 206US of the second floating gate 206U. Furthermore, in position 10, the dielectric substrate 224R1' and the dielectric pad material layer 236 are adjacent to different portions of the side 206LS of the first floating gate 206L. It should be noted that the dielectric pad material layer 236 does not completely fill the openings O1 and O2.

[0059] In some embodiments, the dielectric pad material layer 236 comprises a nitride, such as silicon nitride (SiN) or silicon oxynitride (SiON). In some embodiments, the material of the dielectric pad material layer 236 differs from the materials of the dielectric substrate 224R1' and dielectric fill layer 226R1' of the isolation structure 230R1' and the dielectric substrate 224R2 and dielectric fill layer 226R2 of the isolation structure 230R2. The material of the dielectric pad material layer 236 may be the same as the material of the nitride layer 212N. For example, the dielectric substrate 224R1' and dielectric fill layer 226R1' of the isolation structure 230R1' and the dielectric substrate 224R2 and dielectric fill layer 226R2 of the isolation structure 230R2 are formed of silicon oxide, while the dielectric pad material layer 236 and the nitride layer 212N are formed of silicon nitride. Furthermore, the interface between the dielectric pad material layer 236 and the nitride layer 212N, which are formed from the same material, is not obvious.

[0060] Next, as Figure 4A and Figure 4BAs shown, a deposition process such as spin-coated glass (SOG) can be performed to form a dielectric filler layer (not shown) over the dielectric pad material layer 236. The dielectric filler layer completely fills the openings O1 and O2 and covers the semiconductor stack structure 220, the mask pattern 216, the isolation structures 230R1' and 230R2, and the dielectric pad material layer 236.

[0061] Next, a planarization manufacturing process, such as chemical mechanical polishing (CMP), can be performed to remove a portion of the dielectric filling material layer and dielectric pad material layer 236 on the top surface 220T of the semiconductor stack structure 220 and the top surface 216T of the mask pattern 216 until the top surface 220T of the semiconductor stack structure 220 and the top surface 216T of the mask pattern 216 are exposed, so that a dielectric pad material layer 236-1 and a dielectric filling material layer 238-1 are formed in the opening O1 between the semiconductor stack structure 220, and a dielectric pad material layer 236-2 and a dielectric filling material layer 238-2 are formed in the opening O2 between the mask patterns 216. After the planarization manufacturing process described above, the top surface 220T of the semiconductor stacked structure 220 and the top surface 216T of the mask pattern 216 can be flush with the top surface 238-1T of the dielectric filling material layer 238-1 and the top surface 238-2T of the dielectric filling material layer 238-2.

[0062] After the above manufacturing process, multiple isolation components 240-1 can be formed in position 10, and multiple isolation components 240-2 can be formed in position 20. Isolation component 240-1, from bottom to top, includes an isolation structure 230R1', a dielectric pad material layer 236-1, and a dielectric fill material layer 238-1. Isolation component 240-2, from bottom to top, includes an isolation structure 230R2, a dielectric pad material layer 236-2, and a dielectric fill material layer 238-2.

[0063] Next, as Figure 5A and Figure 5BAs shown, an etching manufacturing process, such as dry etching, can be performed. At position 10, a portion of the dielectric pad material layer 236-1 and a portion of the dielectric fill material layer 238-1 of the isolation member 240-1 are removed, exposing the opposite side 206US of the second floating gate 206U, to form an isolation member 240-1R including an isolation structure 230R1', a dielectric pad layer 236-1R, and a dielectric fill layer 238-1R. Furthermore, at position 20, a portion of the dielectric pad material layer 236-2 and all of the dielectric fill material layer 238-2 of the isolation member 240-2 are removed, to form an isolation member 240-2R including an isolation structure 230R2 and a dielectric pad layer 236-2R. Because the etching selectivity ratios of dielectric pad material layers 236-1 and 236-2 and dielectric filling material layers 238-1 and 238-2 are different, after the above etching process, the top surface 238-1RT of the dielectric filling layer 238-1R can be lower than the top surface 236-1RT of the dielectric pad layer 236-1R. Furthermore, the above etching process can form openings O3 between the semiconductor stacked structures 220 at position 10 and openings O4 between the mask patterns 216 at position 20. The top surface 236-1RT of the dielectric liner 236-1R can be aligned with the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L), or the top surface 236-1RT of the dielectric liner 236-1R can be located below the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L).

[0064] In some embodiments, the dielectric filling layer 238-1R may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, fluorinated silicate glass, undoped silicon glass, organosilicon glass, or SiO2. x C y Spin-coated glass, tetraethoxysilane, low dielectric constant dielectric material, or a combination thereof. In some embodiments, the dielectric filling layer 238-1R, the dielectric substrate 224R1' of the isolation structure 230R1', the dielectric filling layer 226R1', and the dielectric substrate 224R2 and dielectric filling layer 226R2 of the isolation structure 230R2 comprise the same material, such as silicon oxide.

[0065] In some embodiments, the etching manufacturing process includes a selective etching manufacturing process, which can control the etching selectivity ratio of the etching manufacturing process, so that... Figure 4A and Figure 4B The etching rates of the dielectric filling material layers 238-1 and 238-2 (formed from silicon oxide) shown are greater than the etching rates of the dielectric pad material layers 236-1 and 236-2 (formed from silicon nitride).

[0066] It should be noted that the pattern density at position 10 is higher than that at position 20. Therefore, Figure 5A and Figure 5B The etching process shown will have different etching rates at positions 10 and 20. At this time, Figure 4A and Figure 4B The dielectric pad material layer 236-1 of the isolation component 240-1 and the dielectric pad material layer 236-2 of the isolation component 240-2 shown can serve as etching stop layers in the above-mentioned etching manufacturing process, so as to control the degree of recess of the isolation components 240-1R and 240-2R in positions 10 and 20 after the etching manufacturing process. For example, the lowest point of the top surface 240-2RT (concave arc surface) of the isolation component 240-2R in position 20 will not be lower than the lowest point of the dielectric pad layer 236-1R. By forming the isolation components 240-1 and 240-2 with a three-layer structure including silicon oxide / silicon nitride / silicon oxide (ONO), the above-mentioned patterning manufacturing process can avoid the excessive depth difference of the isolation components in the regions (positions 10 and 20) with different pattern densities in the array region, thereby improving the word line interference problem.

[0067] Next, as Figure 6A and Figure 6B As shown, a multi-pass etching process, including dry etching and wet etching, can be performed to remove the mask pattern 216 (including oxide layer 212O and nitride layer 212N) at positions 10 and 20, exposing the top surface 210T of the floating gate 210 at position 10 and the top surface 200T of the substrate 200 at position 20. This etching process may remove portions of the dielectric substrate 236-1R, 236-2R and dielectric fill layer 238-1R from openings O3 and O4.

[0068] Next, as Figure 7A and Figure 7B As shown, a deposition process can be performed to compliantly form a gate dielectric layer 242 on the isolation components 240-1R, 240-2R, and the floating gate 210. The gate dielectric layer 242 may cover the top surface of the isolation component 240-1R, but does not fill the opening O3 between the floating gates 210. The gate dielectric layer 242 may cover the dielectric substrate 236-2R of the isolation component 240-2R, but does not fill the opening O4 between the substrates 200. In one embodiment, the gate dielectric layer 242 comprises silicon oxide, silicon nitride, silicon oxynitride, or a three-layer structure comprising silicon oxide / silicon nitride / silicon oxide (ONO).

[0069] Next, as Figure 8A and Figure 8BAs shown, a deposition process can be performed to form a control gate layer 246 on the gate dielectric layer 242. The control gate layer 246 fills the opening O3 between the floating gates 210 at position 10 and the opening O4 between the substrate 200 at position 10. In some embodiments, the control gate layer 246 includes a polysilicon or other conductive material layer. After the above manufacturing process, a flash memory device 500 is formed.

[0070] like Figure 8A As shown, the flash memory device 500 includes a substrate 200, a semiconductor stack structure 250, and a plurality of isolation components 240-1R. The semiconductor stack structure 250 is disposed on the substrate 200. The semiconductor stack structure 250 includes a tunneling dielectric layer 202 and floating gates 210 (including a first floating gate 206L and a second floating gate 206U). The first floating gate 206L is disposed on the tunneling dielectric layer 202. The second floating gate 206U is disposed on the first floating gate 206L. Isolation components 240-1R are disposed in the substrate 200 adjacent to the semiconductor stack structure 250 and extend in direction 120 protruding from the substrate 200, such that the semiconductor stack structure 250 is sandwiched between the isolation components 240-1R. The isolation components 240-1R include a dielectric fill layer 226R1', a dielectric liner layer 236-1R, and a dielectric fill layer 238-1R. A dielectric filling layer 226R1' is located at the lower portion 240-1L of the isolation member 240-1R. A dielectric liner 236-1R conformably covers the dielectric filling layer 226R1'. A dielectric filling layer 238-1R is located at the upper portion 240-1U of the isolation member 240-1R, such that the dielectric liner 236-1R is sandwiched between the dielectric filling layer 226R1' and the dielectric filling layer 238-1R. In some embodiments, the dielectric filling layer 226R1' and the dielectric filling layer 238-1R are formed of a first material, and the dielectric liner 236-1R is formed of a second material, and the second material is different from the first material. In some embodiments, the first material includes an oxide, and the second material includes a nitride.

[0071] In some embodiments, the top surface 236-1RT of the dielectric liner 236-1R is aligned with the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L), or the top surface 236-1RT of the dielectric liner 236-1R is located below the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L). In other words, the top surface 236-1RT of the dielectric liner 236-1R is not higher than the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L). In some embodiments, the top surface of the insulating member 240-1R includes the top surface 236-1RT of the dielectric liner 236-1R and the top surface 238-1RT of the dielectric filler layer 238-1R.

[0072] In the isolation component 240-1R, the interface between the dielectric filling layer 226R1' and the dielectric liner 236-1R is a concave arc-shaped surface, and the lowest point of the concave arc-shaped surface is located above the top surface 202T of the tunneling dielectric layer 202.

[0073] In the isolation component 240-1R, the dielectric liner 236-1R covers the opposite side 206LS of the first floating gate 206L, and the opposite side 206US of the second floating gate 206U can be exposed from the dielectric liner 236-1R.

[0074] In some embodiments, the isolation member 240-1R may further include a dielectric liner 224R1'. The dielectric liner 224R1' surrounds the dielectric fill layer 226R1' and abuts the side 202S of the tunneling dielectric layer 202 and the side 206LS of the first floating gate 206L. In some embodiments, the tunneling dielectric layer 202 and the first floating gate 206L may be separated from the dielectric liner 236-1R by the dielectric liner 224R1', or the dielectric liner 224R1' and the dielectric liner 236-1R may abut different portions of the side 206LS of the first floating gate 206L. In some embodiments, the dielectric liner 224R1' is formed of a first material, such as an oxide.

[0075] The flash memory device 500 also includes a gate dielectric layer 242 and a control gate layer 246. The gate dielectric layer 242 is formed on the isolation member 240-1R and the floating gate 210. The control gate layer 246 is formed on the gate dielectric layer 242. In some embodiments, the gate dielectric layer 242 is adjacent to the dielectric fill layer 238-1R and the dielectric liner layer 236-1R.

[0076] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A flash memory device, characterized in that, include: One base; A semiconductor stack structure is disposed on the substrate, wherein the semiconductor stack structure includes: A first floating gate; and A second floating gate, disposed on the first floating gate; and A plurality of isolation components are disposed in the substrate and extend beyond the substrate such that the semiconductor stack structure is sandwiched between the isolation components, wherein each of the isolation components includes: A first dielectric filling layer is located below the isolation component; A second dielectric liner, conformably covering the first dielectric fill layer; and A third dielectric filling layer is located on an upper part of the isolation component, such that a second dielectric liner is sandwiched between the first dielectric filling layer and the third dielectric filling layer, wherein the first dielectric filling layer and the third dielectric filling layer are formed of a first material, and the second dielectric liner is formed of a second material, and the second material is different from the first material.

2. The flash memory device according to claim 1, characterized in that, Each of the isolation components has a first top surface including a third top surface of the third dielectric filling layer and a second top surface of the second dielectric liner.

3. The flash memory device according to claim 2, characterized in that, A second top surface of the second dielectric liner of each of the isolation components is aligned with or located below a first interface between the first floating gate and the second floating gate.

4. The flash memory device according to claim 1, characterized in that, The first material comprises an oxide, and the second material comprises a nitride.

5. The flash memory device according to claim 1, characterized in that, Also includes: A tunneling dielectric layer is sandwiched between the substrate and the semiconductor stack structure, wherein a second interface between the first dielectric filling layer and the second dielectric substrate is a concave arc-shaped surface, and the lowest point of the concave arc-shaped surface is located above the tunneling dielectric layer.

6. The flash memory device according to claim 1, characterized in that, The second dielectric liner covers multiple first sides of the first floating gate.

7. The flash memory device according to claim 1, characterized in that, A third top surface of the third dielectric filling layer of each of the isolation components is lower than a second top surface of the second dielectric liner.

8. The flash memory device according to claim 5, characterized in that, Each of the aforementioned isolation components further includes: A fourth dielectric liner surrounds the first dielectric fill layer and is adjacent to a plurality of third sides of the tunneling dielectric layer and a plurality of first sides of the first floating gate, wherein the fourth dielectric liner is formed of the first material.

9. The flash memory device according to claim 8, characterized in that, The second dielectric liner and the fourth dielectric liner are adjacent to different portions of the first side of the first floating gate.

10. The flash memory device according to claim 1, characterized in that, Also includes: A gate dielectric layer is formed on the isolation component and the floating gate; as well as A control gate layer is formed on the gate dielectric layer.

11. The flash memory device according to claim 10, characterized in that, The gate dielectric layer is adjacent to the third dielectric fill layer and the second dielectric liner.

12. A method for forming a flash memory device, characterized in that, include: Provide a base; as well as A semiconductor stack structure and a plurality of isolation components are formed on the substrate, wherein the isolation components protrude from the substrate such that the semiconductor stack structure is sandwiched between the isolation components, wherein the semiconductor stack structure includes: A first floating gate; and A second floating gate is disposed on the first floating gate; The isolation components formed therein include: A first dielectric filling layer is formed in the substrate adjacent to the semiconductor stack structure, wherein a first top surface of the first dielectric filling layer is recessed into a second top surface of the semiconductor stack structure; A second dielectric pad material layer is compliantly formed on the first top surface of the semiconductor stack structure and the first dielectric filling layer; A third dielectric filler layer is formed on the second dielectric pad material layer; and Remove a portion of the second dielectric pad material layer and a portion of the third dielectric fill material layer to expose a plurality of second sides of the second floating gate. The first dielectric filling layer and the third dielectric filling material layer are formed of a first material, and the second dielectric pad material layer is formed of a second material, wherein the second material is different from the first material.

13. The method for forming a flash memory device according to claim 12, characterized in that, Before the second dielectric pad material layer is formed, the first top surface of the first dielectric filler layer is a concave arc-shaped surface, and the lowest point of the concave arc-shaped surface is located below a third top surface of the first floating gate.

14. The method for forming a flash memory device according to claim 12, characterized in that, The second dielectric pad material layer is adjacent to a plurality of first sides of the first floating gate.

15. The method for forming a flash memory device according to claim 12, characterized in that, A fourth top surface of the second dielectric pad material layer is aligned with or located below a first interface between the first floating gate and the second floating gate.

16. The method for forming a flash memory device according to claim 12, characterized in that, Also includes: Before forming the semiconductor stack structure, a tunneling dielectric layer is formed on the substrate; as well as A fourth dielectric liner is formed in the substrate adjacent to the semiconductor stack structure, wherein the fourth dielectric liner surrounds the first dielectric fill layer and is adjacent to a plurality of third sides of the tunneling dielectric layer and a plurality of first sides of the first floating gate, wherein the fourth dielectric liner is formed of the first material.

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