Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of achieving improvement in strength and characteristics related to data readout and a manufacturing method thereof. The semiconductor storage device of the embodiments has a laminate and first to fifth insulators. The laminate has a plurality of first conductive layers laminated along a first direction, a second conductive layer below the first conductive layers, and a third conductive layer above the first conductive layers. The first and second insulators penetrate the laminate and extend along a second direction intersecting the first direction. The first insulator divides the plurality of first conductive layers, the second conductive layer, and the third conductive layer in a third direction intersecting the first and second directions. The third insulator is located between the first and second insulators, extends along the second direction, and divides the plurality of first conductive layers, the second conductive layer, and the third conductive layer in the third direction. The fourth and fifth insulators are provided between adjacent third insulators and extend along the first and second directions. The fourth and fifth insulators divide each of the second and third conductive layers in the third direction, respectively.

Description

[0001] Information related to divisional application This case is a divisional application. The parent application of this divisional application is the invention patent application filed on February 24, 2022, with application number 202210172593.4 and title "Semiconductor memory device and method for manufacturing semiconductor memory device".

[0002] [Related Applications] This application claims priority to Japanese Patent Application No. 2021-151000 (filed on September 16, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] NAND (Not AND) type flash memory is known to be obtained by stacking storage cells in three dimensions. Summary of the Invention

[0005] [The problem the invention aims to solve]

[0006] The present invention provides a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve strength and data readout characteristics.

[0007] The semiconductor memory device of the embodiment includes a stacked body, a first columnar body, a first insulator, a second insulator, a third insulator, a fourth insulator, and a fifth insulator. The stacked body includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layers are stacked along a first direction. The second conductive layer is disposed below the plurality of first conductive layers. The third conductive layer is disposed above the plurality of first conductive layers. The first columnar body penetrates the stacked body along the first direction and includes a semiconductor layer. The first insulator penetrates the stacked body along the first direction and extends along a second direction intersecting the first direction. The first insulator divides the plurality of first conductive layers, second conductive layers, and third conductive layers in a third direction intersecting the first and second directions. The second insulator is disposed at a position spaced apart from the first insulator in the third direction, penetrates the stacked body along the first direction, and extends along the second direction. The second insulator divides the plurality of first conductive layers, second conductive layers, and third conductive layers in the third direction. The third insulator has a first portion and a second portion disposed separately from the first portion in a second direction. The first portion and the second portion are located between the first insulator and the second insulator in a third direction, penetrate the laminate in the first direction, and extend in the second direction. The first portion and the second portion divide a plurality of first conductive layers, second conductive layers, and third conductive layers in the third direction. A fourth insulator is disposed between the first portion and the second portion and extends in both the first and second directions. The fourth insulator divides the second conductive layer in the third direction. A fifth insulator is disposed between the first portion and the second portion and extends in both the first and second directions. The fifth insulator divides the third conductive layer in the third direction. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the semiconductor memory device and memory controller according to the first embodiment.

[0009] Figure 2 This is a diagram showing a portion of the equivalent circuit of the memory cell array of the semiconductor memory device according to the first embodiment.

[0010] Figure 3A This is a top view showing a portion of the semiconductor memory device according to the first embodiment.

[0011] Figure 3B This is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0012] Figure 3C This is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0013] Figure 4A This is a cross-sectional view showing the columnar body of the semiconductor memory device according to the first embodiment.

[0014] Figure 4BThis is a cross-sectional view showing the columnar body of the semiconductor memory device according to the first embodiment.

[0015] Figure 4C This is a cross-sectional view obtained by magnifying the vicinity of the conductive layer of the semiconductor memory device of the first embodiment.

[0016] Figure 5A This is a top view showing a portion of a semiconductor memory device according to a first variation of the first embodiment.

[0017] Figure 5B This is a cross-sectional view showing a portion of a semiconductor memory device according to a first variation of the first embodiment.

[0018] Figure 5C This is a cross-sectional view showing a portion of a semiconductor memory device according to a first variation of the first embodiment.

[0019] Figures 6 to 13 This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0020] Figure 14A This is a top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0021] Figure 14B This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0022] Figure 14C This is a cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0023] Figures 15-19 This is a cross-sectional view used to illustrate a method for manufacturing a semiconductor memory device according to a first variation of the first embodiment.

[0024] Figure 20A This is a top view illustrating a method for manufacturing a semiconductor memory device according to a first variation of the first embodiment.

[0025] Figure 20B This is a cross-sectional view used to illustrate a method for manufacturing a semiconductor memory device according to a first variation of the first embodiment.

[0026] Figure 20C This is a cross-sectional view used to illustrate a method for manufacturing a semiconductor memory device according to a first variation of the first embodiment. Detailed Implementation

[0027] Hereinafter, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to embodiments will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions will be labeled with the same symbols. Furthermore, repeated descriptions of the components will sometimes be omitted. The accompanying drawings are schematic diagrams or conceptual diagrams, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in the actual object. In this application, "connection" is not limited to physical connection, but also includes electrical connection. In this application, "parallel," "orthogonal," or "same" also includes cases of "approximately parallel," "approximately orthogonal," or "approximately same," respectively. In this application, "extending along direction A" means, for example, that the dimension in direction A is larger than the smallest dimension among the dimensions in directions X, Y, and Z described below. The "direction A" referred to here is any direction.

[0028] First, the X, Y, and Z directions are defined. The X and Y directions are directions that are approximately parallel to the surface of the substrate 30 described below. The X and Y directions are orthogonal to each other. The Z direction is orthogonal to the X and Y directions and is away from the substrate 30. However, these expressions are used for convenience and do not specify the direction of gravity. In this embodiment, the Z direction is an example of the "first direction".

[0029] In the accompanying drawings, for example, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the substrate 30 used to form the semiconductor memory device 1. In the top view, some components are appropriately shaded for ease of reading. The shaded components in the top view are not necessarily related to the material or characteristics of the components to which the shaded components are attached. In the top and sectional views, some components such as wiring, contacts, and interlayer insulating films are appropriately omitted for ease of reading.

[0030] (First Embodiment)

[0031] Figure 1 This is a block diagram showing a semiconductor memory device 1 and a memory controller 2. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 includes, for example, a memory cell array 10, a row decoder 11, a sense amplifier 12, and a sequencer 13.

[0032] The memory cell array 10 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Each BLK block is a non-volatile memory cell transistor MT (refer to...). Figure 2 The memory cell array 10 is a collection of memory cells. Multiple bit lines and multiple word lines are provided in the array. Each memory cell transistor MT is connected to one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0033] The row decoder 11 selects one block BLK based on the address information ADD received from the external memory controller 2. The row decoder 11 controls the write and read operations of data for the memory cell array 10 by applying the required voltage to multiple word lines respectively.

[0034] The sensing amplifier 12 applies the required voltage to each bit line based on the write data DAT received from the memory controller 2. The sensing amplifier 12 determines the data stored in the memory cell transistor MT based on the voltage of the bit line and sends the determined read data DAT to the memory controller 2.

[0035] The sequencer 13 controls the operation of the entire semiconductor memory device 1 based on the instruction CMD received from the memory controller 2.

[0036] The semiconductor memory device 1 and memory controller 2 described above can also be combined to form a semiconductor device. Examples of semiconductor devices include memory cards such as SD (trademarked) cards or SSDs (Solid State Drives).

[0037] Next, the electrical configuration of the storage cell array 10 will be described.

[0038] Figure 2 This is a diagram showing a portion of the equivalent circuitry of the memory cell array 10. Figure 2 The storage cell array 10 extracts a block BLK and represents it. The block BLK contains multiple (e.g., 4) strings STR0 to STR3.

[0039] Each string STR0 to STR3 is a collection of multiple NAND strings NS. One end of each NAND string NS is connected to any one of the bit lines BL0 to BLm (where m is an integer greater than or equal to 1). The other end of the NAND string NS is connected to the source line SL. Each NAND string NS contains multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), a first selection transistor S1, and a second selection transistor S2.

[0040] Multiple memory cell transistors MT0 to MTn are electrically connected in series. Each memory cell transistor MT includes a control gate and a memory stack film (e.g., a charge storage film) to non-volatilely store data. The state of the memory stack film changes (e.g., storing charge in the charge storage film) according to the voltage applied to the control gate. The control gate of the memory cell transistor MT is connected to any one of the corresponding word lines WL0 to WLn. The memory cell transistor MT is electrically connected to the line decoder 11 via word line WL.

[0041] The first select transistor S1 in each NAND string NS is connected between multiple memory cell transistors MT0-MTn ​​and any bit line BL0-BLm. The drain of the first select transistor S1 is connected to any bit line BL0-BLm. The source of the first select transistor S1 is connected to the memory cell transistor MTn. The control gate of the first select transistor S1 in each NAND string NS is connected to any select gate line SGD0-SGD3. The first select transistor S1 is electrically connected to the row decoder 11 via the select gate line SGD. When a specified voltage is applied to any one of the select gate lines SGD0-SGD3, the first select transistor S1 connects the NAND string NS to the bit line BL.

[0042] The second select transistor S2 in each NAND string NS is connected between the multiple memory cell transistors MT0 to MTn and the source line SL. The drain of the second select transistor S2 is connected to the memory cell transistor MT0. The source of the second select transistor S2 is connected to the source line SL. The control gate of the second select transistor S2 is connected to the select gate line SGS. The second select transistor S2 is electrically connected to the row decoder 11 via the select gate line SGS. When a specified voltage is applied to the select gate line SGS, the second select transistor S2 connects the NAND string NS and the source line SL.

[0043] Furthermore, the memory cell array 10 can also be configured with other circuits besides those described above. For example, the number of each string STR contained in each BLK, the number of memory cell transistors MT contained in each NAND string NS, and the number of selection transistors STD and STS can also be changed. In addition, the NAND string NS can also contain more than one dummy transistor.

[0044] Figure 3A This is a top view showing a portion of the semiconductor memory device 1 according to the first embodiment. Figure 3B It is along Figure 3A A sectional view of plane A-A' in the diagram. Figure 3C It is along Figure 3A The cross-sectional view of plane B-B' in the diagram.

[0045] like Figure 3A As shown, the semiconductor memory device 1 of the first embodiment includes a memory cell array 10 and stepped portions S, for example, disposed at both ends of the stacked body 20 in the X-axis direction. A first slit ST1 and a second slit ST2 are disposed from one stepped portion S of the stacked body 20 through the memory cell array 10 to the other stepped portion S. Similarly, a third slit SST and a sixth slit SHE are disposed from one stepped portion S of the stacked body 20 through the memory cell array 10 to the other stepped portion S.

[0046] Next, an example of the structure of the memory cell array 10 of the semiconductor memory device 1 will be described. The memory cell array 10 has a cell array region and a peripheral region. A NAND string NS is integrated in the cell array region. Peripheral circuitry for the control unit array region is disposed in the peripheral region. The peripheral region may be adjacent to the cell array region in the X or Y direction, or it may be stacked relative to the cell array region in the Z direction. Hereinafter, an example of the peripheral region being stacked relative to the cell array region in the Z direction is shown.

[0047] like Figure 3A , Figure 3B As shown, the memory cell array 10 of the semiconductor memory device 1 has a substrate 30, a circuit layer PE, a stack 20, a plurality of pillars CL, a first insulator 41, a second insulator 42, a third insulator 43, a fourth insulator 44, and a fifth insulator 45. In this embodiment, the pillar CL is an example of a "first pillar".

[0048] The substrate 30 is, for example, a silicon substrate. Multiple component separation regions 30A are present on the surface region of the substrate 30. The component separation regions 30A contain, for example, silicon oxide. Between adjacent component separation regions 30A are the source and drain regions of a transistor Tr.

[0049] A circuit layer PE is located on substrate 30. Circuit layer PE includes a line decoder 11, a sense amplifier 12, and a sequencer 13 of the semiconductor memory device 1. Circuit layer PE includes, for example, multiple transistors Tr, multiple wiring layers D0, D1, and multiple vias C1, C2. The multiple transistors Tr, multiple wiring layers D0, D1, and multiple vias C1, C2 are located within an insulating layer E1. Insulating layer E1 is, for example, composed of silicon oxide. Via C1 connects the source or drain region of transistor Tr to wiring layer D0. Via C2 connects the gate region of transistor Tr to wiring layer D1. Wiring layers D0 and D1 extend in the X and Y directions. Wiring layer D1 is connected to contact plug CP1. Vias C1, C2, and wiring layers D0, D1 are, for example, composed of tungsten.

[0050] The laminate 20 has a conductive layer 21, multiple conductive layers 25, an insulating layer 22, and multiple insulating layers 24 in the Z direction. The conductive layers 21 and 25 are alternately laminated with the insulating layers 22 and 24. The multiple conductive layers 21 and 25 extend in both the X and Y directions, respectively. The multiple insulating layers 22 and 24 extend in both the X and Y directions, respectively. The multiple insulating layers 24 and multiple conductive layers 25 are alternately laminated in the Z direction.

[0051] Insulating layer 22 and multiple insulating layers 24 extend in the X and Y directions, respectively. Insulating layer 22 and multiple insulating layers 24 may comprise, for example, silicon oxide. Insulating layer 22 is located between conductive layer 21 and conductive layer 25. Insulating layer 24 is located between adjacent conductive layers 25 in the Z direction. Insulating layer 24 insulates between two adjacent conductive layers 25 in the Z direction. The number of insulating layers 24 is determined by the number of conductive layers 25.

[0052] Multiple conductive layers 25 extend in both the X and Y directions. That is, each conductive layer 25 is formed as a plate extending along both the X and Y directions. The conductive layers 25 are, for example, tungsten or polycrystalline silicon doped with impurities. The number of conductive layers 25 is arbitrary.

[0053] The plurality of conductive layers 25 includes: a plurality of first conductive layers 25A, deposited along the Z direction; a second conductive layer 25B, located in the Z direction between the substrate 30 and the plurality of first conductive layers 25A; and a third conductive layer 25C, located in the Z direction on the side opposite to the substrate 30 relative to the plurality of first conductive layers 25A. The plurality of conductive layers 25 may, for example, be functionally divided into three. The plurality of conductive layers 25 function as any one of the source-side select gate line SGS, word line WL, and drain-side select gate line SGD.

[0054] In the conductive layer 25, at least one second conductive layer 25B, starting from below the stacked body 20, functions as a source-side selected gate line (SGS). The conductive layer 25 functioning as the source-side selected gate line (SGS) can be a single layer or multiple layers. That is, the source-side selected gate line (SGS) can be composed of one conductive layer 25 or multiple conductive layers 25. Furthermore, when the source-side selected gate line (SGS) is composed of multiple layers, each conductive layer 25 can be composed of different conductors.

[0055] In the conductive layer 25, at least one third conductive layer 25C, starting from above the stacked body 20, functions as a drain-side selected gate line (SGD). The third conductive layer 25C functioning as the drain-side selected gate line (SGD) can be a single layer or multiple layers. That is, the drain-side selected gate line (SGD) can be composed of one third conductive layer 25C or multiple third conductive layers 25C. Furthermore, when the drain-side selected gate line (SGD) is composed of multiple layers, each third conductive layer 25C can be composed of different conductors.

[0056] In conductive layer 25, the conductive layer 25, except for the source-side select gate line SGS and the drain-side select gate line SGD, functions as a word line WL. The conductive layer 25 that functions as a word line WL, for example, surrounds the outer periphery of the columnar body CL.

[0057] The multiple conductive layers 25 may comprise, for example, a conductive metal. The conductive metal may be, for example, tungsten. The multiple conductive layers 25 may also be, for example, polycrystalline silicon doped with impurities.

[0058] A conductive layer 21 is disposed on top of the circuit layer PE. The conductive layer 21 includes semiconductor layers 21A, 21B, and 21C. Semiconductor layer 21A is located on the circuit layer PE. Semiconductor layer 21B is located on semiconductor layer 21A. Semiconductor layer 21C is located on semiconductor layer 21B. Details of semiconductor layers 21A, 21B, and 21C will be described below.

[0059] A cover insulating layer 50 is located on the uppermost insulating layer 24 of the stack 20. The cover insulating layer 50 insulates the stack 20 from the bit line BL. The cover insulating layer 50 may contain, for example, silicon oxide.

[0060] Bit lines BL are formed, for example, as lines extending along the Y direction on the covering insulating layer 50, and are electrically connected to any pillar CL and contact plug (not shown). Multiple bit lines BL are arranged along the X direction in an area not shown.

[0061] Multiple columnar structures CL are disposed within the laminate 20. Each columnar structure CL extends along the Z-direction. For example, each columnar structure CL penetrates the laminate 20 along the Z-direction. The lower portion of each columnar structure CL is in contact with the semiconductor layer 21A. The upper portion of each columnar structure CL is in contact with the covering insulating layer 50.

[0062] Figure 4A It is a cross-sectional view obtained by magnifying the vicinity of the columnar body CL of the semiconductor memory device 1. Figure 4B This is a cross-sectional view obtained by cutting along the conductive layer 25 near the columnar body CL of the semiconductor memory device 1. Figure 4A It is the cross-section obtained by cutting the columnar body CL along the YZ plane. Figure 4B It is the cross-section obtained by cutting the columnar body CL with the XY plane. Multiple columnar bodies CL are formed in the memory hole MH, and have an insulating core 60, a semiconductor layer 61 and a memory stack film 62 in sequence from the inside.

[0063] The insulating core 60 extends along the Z-direction and is columnar. The insulating core 60 comprises, for example, silicon oxide. When viewed from the Z-direction, the insulating core 60 is disposed at the central portion of the memory hole MH, including the central axis.

[0064] Semiconductor layer 61 extends along the Z direction. Semiconductor layer 61 is formed, for example, in a ring shape, covering the outer surface (outer peripheral surface) of insulating core 60. Semiconductor layer 61 contains, for example, silicon. The silicon is, for example, polycrystalline silicon obtained by crystallizing amorphous silicon. Semiconductor layer 61 functions as a channel for the first selection transistor S1, the plurality of memory cell transistors MT, and the second selection transistor S2. Here, a "channel" is a flow path for charge carriers between the source side and the drain side.

[0065] The memory stack film 62 extends along the Z-direction. The memory stack film 62 covers the outer surface (outer peripheral surface) of the semiconductor layer 61. The memory stack film 62 is located between the inner surface (inner peripheral surface) of the memory via MH and the outer surface (outer peripheral surface) of the semiconductor layer 61. The memory stack film 62 includes, for example, a tunnel insulating film 63, a charge storage film 64, and a cover insulating film 65. The plurality of films are arranged from the semiconductor layer 61 side in the order of tunnel insulating film 63, charge storage film 64, and cover insulating film 65.

[0066] The tunnel insulating film 63 covers the outer surface of the semiconductor layer 61. That is, the tunnel insulating film 63 is located between the charge storage film 64 and the semiconductor layer 61. The tunnel insulating film 63 may contain, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 63 is a potential barrier between the semiconductor layer 61 and the charge storage film 64.

[0067] The charge storage film 64 covers the outer surface of the tunnel insulating film 63. That is, the charge storage film 64 is located between each conductive layer 25 and the tunnel insulating film 63. The charge storage film 64 may contain, for example, silicon nitride. Each intersection of the charge storage film 64 and the plurality of conductive layers 25 functions as a transistor. The memory cell transistor MT stores data based on the presence or absence of charge, or the amount of charge stored, in each intersection of the charge storage film 64 and the plurality of conductive layers 25 (charge storage section). The charge storage section is located between each conductive layer 25 and the semiconductor layer 61 and is surrounded by an insulating material. The charge storage section has a so-called floating gate structure.

[0068] like Figure 4A As shown, a cover insulating film 65 is located, for example, between each insulating layer 24 and the charge storage film 64. The cover insulating film 65 comprises, for example, silicon oxide. The cover insulating film 65 protects the charge storage film 64 from etching during processing. The cover insulating film 65 may be absent or may be partially retained between the conductive layer 25 and the charge storage film 64 as a barrier insulating film.

[0069] Alternatively, barrier insulating films 25a and barrier films 25b may be provided between each conductive layer 25 and the insulating layer 24, and between each conductive layer 25 and the memory stacked film 62. The barrier insulating film 25a suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the conductive layer 25 towards the memory stacked film 62. The barrier film 25b improves the adhesion between the conductive layer 25 and the barrier insulating film 25a. The barrier insulating film 25a may be, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. For example, when the conductive layer 25 is tungsten, the barrier film 25b may be a stacked structure film of titanium nitride and titanium.

[0070] Figure 4CIt is a magnified cross-sectional view of the vicinity of the conductive layer 21 of the semiconductor memory device 1. Figure 4C This is the cross-section obtained by cutting the conductive layer 21 and the columnar bodies CL along the YZ plane. As described above, the conductive layer 21 includes, for example, semiconductor layers 21A, 21B, and 21C. The conductive layer 21 is connected to each of the plurality of columnar bodies CL. The conductive layer 21 is formed, for example, as a plate extending along the X and Y directions, and functions as a source line SL.

[0071] Semiconductor layer 21A is located on circuit layer PE. Semiconductor layer 21A is, for example, an n-type semiconductor. Semiconductor layer 21A is, for example, polycrystalline silicon doped with impurities. Semiconductor layer 21B is located on semiconductor layer 21A. Semiconductor layer 21B is connected to semiconductor layer 61 of pillar CL. Semiconductor layer 21B is, for example, an epitaxial film doped with impurities. Semiconductor layer 21B contains, for example, phosphorus. Semiconductor layer 21C is located on semiconductor layer 21B. Semiconductor layer 21C is, for example, an n-type or undoped semiconductor.

[0072] Here, as Figure 3A As shown, the semiconductor memory device 1 of this embodiment has a plurality of slits when viewed from the Z direction (refer to slits 1 to 5 below). The plurality of slits are grooves that divide the stacked body 20 in the Y direction. The plurality of slits all extend in the X direction.

[0073] The multiple slits are roughly divided into slit 1 (ST1), slit 2 (ST2), slit 3 (SST), slit 4 (ST4), slit 5 (ST5), and slit 6 (SHE).

[0074] Both the first slit ST1 and the second slit ST2 are deep slits that penetrate the laminate 20 and extend from the upper surface of the insulating layer 50 to the conductive layer 21. The second slit ST2 is located at a position spaced apart from the first slit ST1 in the Y direction.

[0075] The third slit SST is a deep slit that penetrates the laminate 20, extending from the upper surface of the covering insulating layer 50 to the conductive layer 21. When viewed from above in the Z direction, the third slit SST extends along the X direction and is arranged in a dashed line shape.

[0076] The fourth slit ST4 is located in the stacked body 20 at a position corresponding to the second conductive layer 25B (source-side selected gate line SGS) and between the adjacent third slits SST in the X direction, dividing the second conductive layer 25B in the Y direction.

[0077] The fifth slit ST5 is located in the stacked body 20 at a position corresponding to the third conductive layer 25C (drain-side selected gate line SGD), dividing the third conductive layer 25C in the Y direction. When viewed from the Z direction, the fifth slit ST5 extends along the X direction and is positioned to span between adjacent third slits SST in the X direction. The sixth slit SHE is a shallow slit, extending from the upper surface of the covering insulating layer 50 to the middle of the stacked body.

[0078] First insulator 41 and second insulator 42 are respectively disposed within first slit ST1 and second slit ST2. That is, first insulator 41 and second insulator 42 are disposed within the laminate 20 along the Z direction from the upper surface of the covering insulating layer 50 to the conductive layer 21. First insulator 41 extends along the X direction when viewed from the Z direction, and second insulator 42 extends along the X direction at a different position than first insulator 41 in the Y direction. First insulator 41 and second insulator 42 separate first conductive layer 25A, second conductive layer 25B, and third conductive layer 25C in the Y direction. First insulator 41 and second insulator 42, for example, each comprise silicon oxide. The laminate 20 between first insulator 41 and second insulator 42 is called a block, for example, constituting the smallest unit of data erasure.

[0079] The third insulator 43 is disposed within a deeper third slit SST, which is arranged in a dashed line shape when viewed from above. That is, the third insulator 43 has multiple insulators 43a and 43b separated from each other in the X direction between the first insulator 41 and the second insulator 42 in the Y direction. Insulator 43a is an example of the first part, and insulator 43b is an example of the second part. Furthermore, the third insulator 43 is disposed within the laminate 20 along the Z direction from the upper surface of the covering insulating layer 50 to the conductive layer 21, and is arranged in a dashed line shape in the X direction. The third insulator 43 may contain, for example, silicon oxide.

[0080] A fourth insulator 44 is disposed within a fourth slit ST4, which is located at a position corresponding to the second conductive layer 25B (source-side selected gate line SGS). Specifically, the fourth insulator 44 is disposed in the lower region of the substrate 30 side of the laminate 20, extending along both the Z and X directions, between adjacent third slits SST in the X direction (between insulators 43a and 43b). The second conductive layer 25B is divided in the Y direction by the fourth insulator 44. The fourth insulator 44 may also be disposed in contact with the ends of insulators 43a and 43b. Furthermore, the fourth insulator 44 is positioned to overlap with the fifth insulator 45 described below when viewed from the Z direction.

[0081] A fifth insulator 45 is disposed within a fifth slit ST5, which is located at a position corresponding to the third conductive layer 25C (drain-side selected gate line SGD). That is, the fifth insulator 45 is disposed in the upper region of the bit line BL side of the stacked body 20, spanning between adjacent third slits SST in the X direction (between insulators 43a and 43b). Furthermore, in Figure 3A In this configuration, the two ends of the fifth insulator 45 in the X direction are positioned to overlap with the third insulator 43 (insulators 43a and 43b) in the Z direction. However, the two ends of the fifth insulator 45 in the X direction may also be positioned to connect with the ends of insulators 43a and 43b. Furthermore, the fifth insulator 45 is positioned in the upper region on the bit line BL side of the laminate 20, extending along both the Z and X directions. The fifth insulator 45 divides the third conductive layer 25C in the Y direction. Additionally, the fifth insulator 45 is positioned to overlap with the fourth insulator 44 when viewed from above in the Z direction.

[0082] The widths of the fourth insulator 44 and the fifth insulator 45 in the Y direction should preferably be less than or equal to the width of the third insulator (i.e., the third slit SST) in the Y direction. The third slit SST is formed after the fourth insulator 44 and the fifth insulator 45 are formed, as will be described in detail later. Therefore, by setting the widths of the fourth insulator 44 and the fifth insulator 45 in the Y direction to less than or equal to the width of the third insulator (the third slit SST), the fourth insulator 44 and the fifth insulator 45 corresponding to the formation position of the third slit SST can be removed. As a result, the replacement process using the third slit SST can be reliably implemented.

[0083] Furthermore, a larger distance (interval) between adjacent third slits SST in the X direction (between insulators 43a and 43b) better prevents finger distortion. However, if this distance is too large, there is a concern that the laminate 20 may flex during replacement processing. Therefore, the distance (interval) between adjacent third slits SST in the X direction (between insulators 43a and 43b) should be set within a range that can prevent the laminate 20 from flexing during replacement processing.

[0084] Furthermore, a fourth insulator 44 and a fifth insulator 45 are respectively disposed at positions corresponding to the second conductive layer 25B (source-side select gate line SGS) and the third conductive layer 25C (drain-side select gate line SGD). On the other hand, a first conductive layer 25A (word line WL) between the fourth insulator 44 and the fifth insulator 45 in the Z direction extends from the first insulator 41 to the second insulator 42 in the Y direction. That is, although the second conductive layer 25B and the third conductive layer 25C between the third slits SST (between insulators 43a and 43b) are interrupted, the first conductive layer 25A (word line WL) is not interrupted, but is continuously connected between the first insulator 41 and the second insulator 42.

[0085] The sixth insulator 46 is disposed within the sixth slit SHE. The sixth insulator 46 is disposed along the Z direction from the upper end of the laminate 20 to the middle of the laminate 20.

[0086] As described above, the fifth insulator 45, which extends to the middle of the stacked body 20, forms the third conductive layer 25C of the drain-side selected gate line SGD through the upper region of the stacked body 20. The third conductive layer 25C forming the drain-side selected gate line SGD is spaced apart on both sides in the Y direction, separated by the third insulator 43 (the third slit SST), in the stacked body 20 between the first insulator 41 and the second insulator 42, which form a single block.

[0087] In this embodiment, when viewed from the Z direction, the area between the first insulator 41 and the second insulator 42 is called "block BLK", the area between the first insulator 41 and the third insulator 43 and the area between the second insulator 42 and the third insulator 43 are called "finger F", and the area separated by adjacent first insulator 41 and sixth insulator 46, adjacent third insulator 43 and sixth insulator 46 or two adjacent sixth insulators 46 is called "string STR".

[0088] In this embodiment, a drain-side select gate line (SGD) is formed by separating each of these fingers F by the third insulator 43. Therefore, during data writing and reading, one finger F in the block BLK can be selected through the drain-side select gate line (SGD). Furthermore, the number of strings (STRs) contained in one finger F is not limited, and the number of strings (STRs) is, for example, an odd number.

[0089] In addition, such as Figure 3A As shown, multiple columnar bodies CL are arranged in a staggered pattern in the Y direction when viewed from above in the Z direction. The number of columnar bodies CL arranged in a staggered pattern in the Y direction is, for example, the same in each string of STRs. Figure 3AWithin each of the STRs shown, four columnar bodies CL are arranged alternately in the Y direction. Furthermore, the sixth slit SHE is formed by etching away at least a portion of the columnar body CL at the corresponding position. Therefore, the columnar body CL formed at the position corresponding to the sixth slit SHE sometimes appears partially removed when viewed from above.

[0090] Furthermore, the planar layout of the memory cell array of the semiconductor memory device 1 is not limited to... Figure 3A The layout shown can also be other layouts. For example, the number and arrangement of columns (CL) within an adjacent string (STR) can be changed appropriately.

[0091] The semiconductor memory device 1 of the first embodiment improves the resistance to twisting of the finger F by using third insulators 43 (insulators 43a and 43b) arranged in a dashed line shape. Furthermore, a fourth insulator 44 and a fifth insulator 45 are provided between adjacent third insulators 43 (insulators 43a and 43b) in the X direction to separate the second conductive layer 25B (source-side select gate line SGS) and the third conductive layer 25C (drain-side select gate line SGD). With these features, during data writing and reading, one finger F within the block BLK can be set to a selected state, and the other finger F separated by the third insulators 43 can be set to a non-selected state. Furthermore, the string STR within the unselected finger F (i.e., the unread finger F) becomes floating. Therefore, when a voltage is applied to the first conductive layer 25A (WL), the string STR also rises, thus maintaining the potential difference between the string STR and the first conductive layer 25A (WL). As a result, the influence of the read voltage of the unselected string STR can be avoided, thereby improving read disturbance.

[0092] Furthermore, in the semiconductor memory device 1 of the first embodiment, instead of the dividing portion of the block BLK (i.e., the first insulator 41 and the second insulator 42), a fourth insulator 44 is provided in the inner region of the block BLK (the region surrounded by the first insulator 41 and the second insulator 42) to divide the second conductive layer 25B (source-side select gate line SGS). Furthermore, third insulators 43 penetrating the stacked layer 20 are respectively provided on both sides of the fourth insulator 44 in the X direction. This ensures the strength of the entire block BLK (especially its bending strength) and suppresses the read disturbance of the adjacent fingers F divided by the fourth insulator 44.

[0093] The "read interference" mentioned here refers to the generation of an electric field in a storage cell (hereinafter referred to as "non-read object storage cell") that is different from the storage cell of the data being read during the data read operation. This electric field causes a change in the amount of charge held by the non-read object storage cell (e.g., an increase in charge).

[0094] (Example of the first variation)

[0095] A first variation of the semiconductor memory device 1 according to the first embodiment will be described.

[0096] Figures 5A to 5C This is a cross-sectional view showing a portion of the semiconductor memory device 1A of the first variation. The configuration of the semiconductor memory device 1A of the first variation is the same as that of the semiconductor memory device 1 of the first embodiment, except for the configuration described below.

[0097] The semiconductor memory device 1A of the first variation may also have a plurality of second columnar bodies CLd that penetrate the laminate 20 in the first direction between adjacent third insulators 43 (between insulators 43a and 43b) in the X direction. That is, in the first variation, in addition to the fourth insulator 44 and the fifth insulator 45, a plurality of second columnar bodies CLd are provided in the laminate 20 between adjacent third insulators 43 (between insulators 43a and 43b) in the X direction.

[0098] As described above, the larger the distance (interval) between adjacent third insulators 43 in the X direction (between insulators 43a and 43b), the better the finger distortion can be prevented. However, if the distance is too large, there is a concern that the laminate 20 may flex during replacement processing. Therefore, in the first variation, by providing a plurality of second pillars CLd as reinforcements between adjacent third insulators 43 in the X direction, finger distortion and bending of the laminate 20 can be prevented. Furthermore, by strengthening the laminate 20 between adjacent third insulators 43 with the plurality of second pillars CLd, the distance (interval) between adjacent third insulators 43 can be made larger than in the first embodiment. As a result, compared with the first embodiment, the semiconductor device of the first variation can further prevent finger distortion.

[0099] Here, the second columnar body CLd functions as a reinforcing material. Therefore, the film composition of the second columnar body CLd is not particularly limited, and from the point of view of manufacturing efficiency, it can be the same as the film composition of the columnar body CL (see [reference]). Figure 4A and Figure 4B )same.

[0100] Furthermore, by constructing the first variation example, in addition to the aforementioned effects, the influence of the readout voltage of the string in the non-selected state can also be avoided, similar to the first embodiment.

[0101] (Manufacturing method)

[0102] Next, the manufacturing method of the semiconductor memory device 1 according to the first embodiment will be described. Figures 6 to 14C This is a cross-sectional view or top view used to illustrate the manufacturing method of the semiconductor memory device 1 according to the first embodiment. Furthermore, Figure 14A This is a top view showing the manufacturing process of semiconductor memory device 1. Figure 14B It is along Figure 14A A cross-sectional view of the X-X' plane. Figure 14C It is along Figure 14A A cross-sectional view of the Y-Y' plane.

[0103] First, such as Figure 6 As shown, a component separation region 30A is formed within the substrate 30, and a transistor Tr is formed within the circuit layer PE (see reference). Figure 1 The transistor Tr can be fabricated using well-known methods. Additionally, within the circuit layer PE and the insulating layer E1, multiple wiring layers D0, D1 and multiple vias C1, C2, electrically connected to the transistor Tr, are formed. The multiple wiring layers D0, D1 and the multiple vias C1, C2 can be fabricated using well-known methods.

[0104] Next, a semiconductor layer 21A, an intermediate film 21Ba, a first sacrificial film 21Bb, an intermediate film 21Bc, a semiconductor layer 21C, and an insulating layer 22 are sequentially deposited on the circuit layer PE. The intermediate films 21Ba and 21Bc, for example, comprise silicon oxide. The first sacrificial film 21Bb is, for example, silicon nitride. The semiconductor layers 21A and 21C, and the insulating layer 22 are the same as the insulating layer 22 described above.

[0105] Then, as Figure 7 As shown, an insulating layer 24 and a sacrificial film 85 are alternately deposited on the insulating layer 22 to form a first stacked body 20A. At this time, the insulating layer 24 and the sacrificial film 85 are deposited to the height corresponding to the second conductive layer 25B (source-side selected gate line SGS), that is, the height corresponding to the fourth insulator 44.

[0106] The insulating layer 24 is the insulating layer 24 described above, for example, comprising silicon oxide. The sacrificial film 85 comprises, for example, silicon nitride.

[0107] Next, a fourth slit ST4 extending in the X direction is formed in the insulating layer 24 and the sacrificial film 85 of the stacked layers, penetrating through the first stacked layer 20A. The fourth slit ST4 extends from the upper surface of the uppermost sacrificial film 85 to the middle of the insulating layer 22. The fourth slit ST4 is formed by etching. For example, anisotropic etching is performed from the upper surface of the uppermost sacrificial film 85 to the insulating layer 22. The anisotropic etching is, for example, reactive ion etching (RIE). Then, an insulator is filled into the fourth slit ST4 to form a fourth insulator 44. The fourth insulator 44 contains, for example, silicon oxide.

[0108] Next, as Figure 8 As shown, insulating layers 24 and sacrificial films 85 are alternately deposited on the first laminate 20A and the fourth insulator 44, and then an insulating layer 50 is formed on the uppermost sacrificial film 85 to form the second laminate 20B.

[0109] Next, as Figure 9 As shown, in Figure 8 A memory hole MH is formed in the second stacked layer 20B shown. The memory hole MH extends from the upper surface of the second stacked layer 20B to the middle of the semiconductor layer 41A. The memory hole MH is formed by etching. For example, anisotropic etching is performed from the upper surface of the second stacked layer 20B to the semiconductor layer 21A. Anisotropic etching is, for example, reactive ion etching (RIE).

[0110] Next, a memory stacked film 62, a semiconductor layer 61, and an insulating core 60 are sequentially formed within the memory hole MH. The memory hole MH is filled with the memory stacked film 62, the semiconductor layer 61, and the insulating core 60. Thus, a columnar body CL is formed within the memory hole MH.

[0111] Next, as Figure 10 As shown, an insulating layer 51 is formed on a laminate containing columnar bodies CL. Then, a first slit ST1 and a second slit ST2 are formed in the second laminate 20B, and an insulating layer 51 is formed as shown. Figure 3A and Figure 3B The third slit SST is shown. The third slit SST is not in Figure 10 As shown in the middle diagram, but as Figure 3A and Figure 3BAs shown, when viewed from the Z direction, it extends along the X direction and forms a dashed line. The first slit ST1 and the second slit ST2 are deep slits, both extending from the upper surface of the second laminate 20B to the middle of the sacrificial film 21Bb. The third slit SST is also a deep slit, extending from the upper surface of the second laminate 20B to the middle of the sacrificial film 21Bb. Therefore, a portion of the fourth insulator 44, formed in the lower part of the second laminate 20B in an X-direction manner, is removed through the third slit SST, leaving only the portion between adjacent third slits SST in the X direction (see reference). Figure 3A The first slit ST1, the second slit ST2, and the third slit SST are formed by anisotropic etching. A stop film 86 is formed on the inner wall of each of the first slit ST1, the second slit ST2, and the third slit SST. The stop film 86 is, for example, silicon oxide.

[0112] Next, as Figure 11 As shown, the sacrificial film 21Bb is isotropically etched via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 21Bb is removed by isotropic etching. The isotropic etching is performed using an etchant capable of etching silicon nitride earlier than silicon oxide. Furthermore, a portion of the memory stack film 62 is also removed by further etching. The portion of the memory stack film 62 exposed by the removal of the sacrificial film 21Bb is removed. By removing a portion of the memory stack film 62, a portion of the semiconductor layer 61 is exposed. The etching of the memory stack film 62 is performed using an etchant capable of etching silicon oxide earlier than silicon nitride. During the etching of the memory stack film 62, the intermediate films 21Ba, 21Bc, and the stop film 86 are also removed simultaneously with the memory stack film 62. A space Sp is formed between the semiconductor layer 41A and the semiconductor layer 41C.

[0113] Next, as Figure 12 As shown, a semiconductor layer 21B is formed by filling the space Sp with a semiconductor material through the first slit ST1, the second slit ST2, and the third slit SST. Thus, the exposed semiconductor layer 61 contacts the semiconductor layer 21B. The material of the semiconductor layer 21B is the material described above. For example, the semiconductor layer 21B contains phosphorus.

[0114] Next, as Figure 13As shown, the sacrificial film 85 is replaced with conductive layers 25 (25A, 25B, 25C). First, the sacrificial film 85 is removed via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 85 is removed by isotropic etching. The isotropic etching uses an etchant that can etch silicon nitrides earlier than silicon oxide and polysilicon. Then, the portion after the removal of the sacrificial film 85 is filled with a conductive material to form conductive layers 25 (25A, 25B, 25C). Thus, a laminate 20 is formed.

[0115] Next, the first slit ST1, the second slit ST2 and the third slit SST are filled with insulators, thereby forming the first insulator 41, the second insulator 42 and the third insulator 43 in the first slit ST1, the second slit ST2 and the third slit SST respectively.

[0116] Next, as Figures 14A to 14C As shown, the fifth slit ST5 and the sixth slit SHE are formed. Both the fifth slit ST5 and the sixth slit SHE extend from the upper surface of the stack 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). The fifth slit ST5 is formed across the space between adjacent third insulators 43 (insulators 43a and 43b) in the X direction. Alternatively, the end of the fifth slit ST5 may be formed to connect with the end of the third insulator 43. That is, both ends of the fifth slit ST5 in the X direction may also be formed to connect with the ends of insulators 43a and 43b. The fifth slit ST5 and the sixth slit SHE are fabricated by etching. For example, anisotropic etching is performed from the upper surface of the stack 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). Anisotropic etching is, for example, reactive ion etching (RIE).

[0117] Next, insulators are used to fill the fifth slit ST5 and the sixth slit SHE, thereby forming a fifth insulator 45 and a sixth insulator 46 within the fifth slit ST5 and the sixth slit SHE, respectively. At this time, both the fifth insulator 45 and the sixth insulator 46 are formed in a manner that extends along the X direction.

[0118] The semiconductor memory device 1 of the first embodiment is manufactured through the above steps. Furthermore, the manufacturing steps shown here are one example, and other steps may be inserted between them.

[0119] Next, the manufacturing method of the semiconductor memory device 1A of the first variation will be described. Figures 15-20C This is a cross-sectional view or top view used to illustrate the manufacturing method of the semiconductor memory device 1A in the first variation example. Furthermore, Figure 20A This is a top view showing the manufacturing process of semiconductor memory device 1A. Figure 20B It is along Figure 20A A cross-sectional view of the Z-Z' plane in the middle. Figure 20C It is along Figure 20A A cross-sectional view of the W-W' plane.

[0120] Furthermore, the manufacturing method of the semiconductor memory device 1A in the first variation example until Figure 8 Up to the step of alternately depositing the insulating layer 24 and the sacrificial film 85 shown, it is the same as in the first embodiment. Therefore, the following will describe the steps after the step of alternately depositing the insulating layer 24 and the sacrificial film 85, and the steps before this step will be omitted from the illustrations and descriptions.

[0121] After alternatingly stacking insulating layers 24 and sacrificial films 85 to form a second laminate 20B, as... Figure 15 As shown, a memory hole MH is formed. The memory hole MH is formed from... Figure 8 The upper surface of the second stack 20B shown extends to the middle of the semiconductor layer 41A. In the first embodiment, no memory hole MH is formed within the stack 20 located above the fourth insulator 44. However, in the first variation, to form a plurality of second pillars CLd, a memory hole MH is also formed at a location where it overlaps with the fourth insulator 44 in at least a portion of the Z-direction. The memory hole MH is formed by etching. For example, anisotropic etching is performed from the upper surface of the second stack 20B to the semiconductor layer 21A. Anisotropic etching is, for example, reactive ion etching (RIE).

[0122] Next, a memory stacked film 62, a semiconductor layer 61, and an insulating core 60 are sequentially formed within the memory hole MH. The memory hole MH is filled with the memory stacked film 62, the semiconductor layer 61, and the insulating core 60. At this time, the memory stacked film 62, the semiconductor layer 61, and the insulating core 60 are also sequentially formed within the memory hole MH corresponding to the second columnar body CLd. Thus, columnar body CL and the second columnar body CLd are formed within the memory hole MH.

[0123] Next, as Figure 16 As shown, an insulating layer 51 is formed on the second laminate 20B on which columnar bodies CL and CLd are formed. Then, similarly to the first embodiment, a first slit ST1 and a second slit ST2 are formed in the second laminate 20B, and an insulating layer 51 is formed as shown. Figure 5A The third slit SST is shown. Although the third slit SST is not in... Figure 16 As shown in the middle diagram, but as Figure 5AAs shown, when viewed from the Z direction, it extends along the X direction and forms a dashed line. The first slit ST1 and the second slit ST2 are deep slits, both extending from the upper surface of the laminate to the middle of the sacrificial film 21Bb. The third slit SST is also a deep slit, extending from the upper surface of the second laminate 20B to the middle of the sacrificial film 21Bb. Therefore, a portion of the fourth insulator 44, formed in the lower part of the second laminate 20B in an X-direction manner, is removed through the third slit SST, leaving only the portion between adjacent third slits SST in the X direction (see reference). Figure 5A The first slit ST1, the second slit ST2, and the third slit SST are formed by anisotropic etching. A stop film 86 is formed on the inner wall of each of the first slit ST1, the second slit ST2, and the third slit SST. The stop film 86 is, for example, silicon oxide.

[0124] Next, as Figure 17 As shown, the sacrificial film 21Bb is isotropically etched via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 21Bb is removed by isotropic etching. The isotropic etching is performed using an etchant capable of etching silicon nitride earlier than silicon oxide. Additionally, a portion of the memory stack film 62 is also removed by etching. The portion of the memory stack film 62 exposed by the removal of the sacrificial film 21Bb is removed. By removing a portion of the memory stack film 62, a portion of the semiconductor layer 61 is exposed. The etching of the memory stack film 62 is performed using an etchant capable of etching silicon oxide earlier than silicon nitride. During the etching of the memory stack film 62, the intermediate films 21Ba, 21Bc, and the stop film 86 are also removed simultaneously with the memory stack film 62. A space Sp is formed between the semiconductor layer 41A and the semiconductor layer 41C.

[0125] Next, as Figure 18 As shown, a semiconductor layer 21B is formed by filling the space Sp with a semiconductor material through the first slit ST1, the second slit ST2, and the third slit SST. Thus, the exposed semiconductor layer 61 contacts the semiconductor layer 21B. The material of the semiconductor layer 21B is the material described above. For example, the semiconductor layer 21B contains phosphorus.

[0126] Next, as Figure 19As shown, the sacrificial film 85 is replaced with conductive layers 25 (25A, 25B, 25C). Specifically, similar to the first embodiment, the sacrificial film 85 is first removed via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 85 is removed by isotropic etching. The isotropic etching uses an etchant capable of etching silicon nitrides earlier than silicon oxide and polysilicon. Then, the portion after the removal of the sacrificial film 85 is filled with a conductive material to form conductive layers 25 (25A, 25B, 25C). Thus, a laminate 20 is formed.

[0127] Next, the first slit ST1, the second slit ST2 and the third slit SST are filled with insulators, thereby forming the first insulator 41, the second insulator 42 and the third insulator 43 in the first slit ST1, the second slit ST2 and the third slit SST respectively.

[0128] Next, as Figures 20A to 20C As shown, the fifth slit ST5 and the sixth slit SHE are formed. Both the fifth slit ST5 and the sixth slit SHE are formed, similarly to the first embodiment, extending from the upper surface of the laminate 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). The fifth slit ST5 is formed across the space between adjacent third insulators 43 (insulators 43a and 43b) in the X direction. Alternatively, the end of the fifth slit ST5 may be formed to connect with the end of the third insulator 43. That is, both ends of the fifth slit ST5 in the X direction may also be formed to connect with the ends of insulators 43a and 43b. The fifth slit ST5 and the sixth slit SHE are fabricated by etching, in the same manner as in the first embodiment. By forming the fifth slit ST5, a portion of the second columnar body CLd is removed.

[0129] Next, insulators are used to fill the fifth slit ST5 and the sixth slit SHE, thereby forming a fifth insulator 45 and a sixth insulator 46 within the fifth slit ST5 and the sixth slit SHE, respectively. At this time, both the fifth insulator 45 and the sixth insulator 46 are formed in a manner that extends along the X direction.

[0130] By following the steps above, the semiconductor memory device 1A of the first variation is manufactured. Furthermore, the manufacturing steps shown here are one example, and other steps may be inserted between them.

[0131] Several embodiments have been described above, but the embodiments are not limited to the examples described. For example, the memory stack film may also be a ferroelectric film contained in a FeFET (Field Effect Transistor) memory that stores data according to the polarization direction. The ferroelectric film is formed, for example, from hafnium oxide.

[0132] According to at least one embodiment described above, by configuring the third insulator 43 (insulators 43a, 43b) in a dashed line shape, the strength against finger twisting can be improved. Furthermore, a fourth insulator 44 and a fifth insulator 45 are provided between adjacent third insulators 43 (insulators 43a, 43b) in the X direction to separate the second conductive layer 25B (source-side select gate line SGS) and the third conductive layer 25C (drain-side select gate line SGD). With these, during data writing and reading, one finger in the block can be set to a selected state, and another finger separated by the third insulator 43 can be set to a non-selected state. Moreover, the string in the non-selected finger (i.e., the unread finger) becomes a floating state, so when a voltage is applied to the first conductive layer 25A (WL), the string also rises, thereby maintaining the potential difference between the string and the first conductive layer 25A (WL). The result is that the influence of the read voltage of the string in the non-selected state can be avoided, thereby improving read disturbance.

[0133] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention as described in the claims and their equivalents.

[0134] [Explanation of Symbols]

[0135] 1.1A Semiconductor Memory Device

[0136] 2. Memory controller

[0137] 10-cell array

[0138] 11-line decoder

[0139] 12 Sensing Amplifier

[0140] 13 Sequencer

[0141] 20 laminated bodies

[0142] 21 Conductive layer

[0143] 21A, 21B, 21C Semiconductor Layers

[0144] 22 Insulation layer

[0145] 25A First conductive layer (WL)

[0146] 25B Second Conductive Layer (SGS)

[0147] 25C Third Conductive Layer (SGD)

[0148] 30 substrate

[0149] 41 First Insulator

[0150] 42 Second Insulator

[0151] 43 Third Insulator

[0152] 44. Fourth Insulator

[0153] 45. Fifth Insulator

[0154] 50, 51 Cover insulation layer

[0155] 60 Insulation Core

[0156] 61 Semiconductor layer

[0157] 62 Memory Stacked Film

[0158] 63 Tunnel insulation film

[0159] 64 Charge storage membrane

[0160] 65 Cover with insulating film

[0161] 85 Sacrificial membrane

[0162] 86. Barrier Film

[0163] BL bitline

[0164] BLK block

[0165] CL First column

[0166] CLd 2nd columnar body

[0167] MH memory hole

[0168] WL lettering

[0169] MT memory cell transistor

[0170] PE circuit layer

[0171] SGS Select Gate Line (Source Side)

[0172] SGD Select Gate Line (Drain Side)

[0173] SL source line

[0174] SLT slit

[0175] STR string

[0176] ST1 First Slit

[0177] ST2 Second Slit

[0178] SST Third Slit

[0179] ST4 Fourth Slit

[0180] ST5 Fifth Slit

[0181] SHE's 6th Narrow Slit

[0182] Tr (Transistor).

Claims

1. A semiconductor memory device comprising: A laminate includes a plurality of first metal layers laminated along a first direction, a second metal layer disposed below the plurality of first metal layers, and a third metal layer disposed above the plurality of first metal layers; A plurality of first columnar bodies penetrate the laminated body along the first direction, each of the first columnar bodies comprising a semiconductor layer; The first insulator penetrates the laminate along the first direction and extends along a second direction that intersects the first direction; A second insulator is located at a position spaced from the first insulator in a third direction intersecting the first and second directions. The second insulator penetrates the laminate along the first direction and extends along the second direction. The plurality of first columnar bodies comprises at least 10 first columnar bodies, arranged alternately between the first and second insulators along the third direction. A third insulator includes a first portion and a second portion, the first portion interrupting the second metal layer between the first insulator and the second insulator in the third direction, the second portion being above the first portion and interrupting the third metal layer between the first insulator and the second insulator in the third direction, the third insulator not interrupting the plurality of first metal layers between the first insulator and the second insulator.

2. The semiconductor memory device according to claim 1, wherein The first portion of the third insulator includes: a fourth insulator extending along the first direction and the second direction, and The second portion of the third insulator includes a fifth insulator extending above the fourth insulator along the first and second directions.

3. The semiconductor memory device according to claim 2, wherein the width of the fifth insulator in the third direction is smaller than the width of the fourth insulator in the third direction.

4. The semiconductor memory device of claim 2, wherein the plurality of first metal layers extend over the fourth insulator along the third direction.

5. The semiconductor memory device of claim 2, wherein the plurality of first metal layers extend along the third direction beneath the fifth insulator.

6. The semiconductor memory device according to claim 2, further comprising: A plurality of second columnar bodies extend through the laminated body along the first direction and are arranged along the fourth and fifth insulators in the second direction, each of the second columnar bodies comprising a semiconductor layer.

7. The semiconductor memory device of claim 6, wherein the plurality of second pillars comprises: a first column of second pillars arranged in the second direction, and a second column of second pillars arranged in the second direction.

8. The semiconductor memory device of claim 7, wherein the fifth insulator is located in the third direction between the first column second column and the second column second column.

9. The semiconductor memory device of claim 6, wherein the layer structure of at least one of the plurality of second pillars is substantially the same as the layer structure of one of the plurality of first pillars.

10. The semiconductor memory device of claim 1, wherein one of the segmented regions of the second metal layer is a first gate line, and the other of the segmented regions of the second metal layer is a second gate line.

11. The semiconductor memory device of claim 10, wherein one of the segmented regions of the third metal layer is a third gate line, and the other of the segmented regions of the third metal layer is a fourth gate line.

12. The semiconductor memory device according to claim 11, further comprising: The control circuit is configured as follows: During the first readout operation, a specified voltage is applied to the first gate line and the third gate line, but not to the second gate line and the fourth gate line; During the second readout operation, the specified voltage is applied to the second gate line and the fourth gate line, but not to the first gate line and the third gate line.

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