Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes: a gate structure including first to nth conductive layers which are sequentially stacked and extend in a first direction, n being an integer of 2 or more; first to m-1st slit structures which extend through the gate structure in the first direction and separate each of the first to nth conductive layers into first to mth gate lines, m being an integer of 2 or more; and first to mth contact plugs which are respectively connected to the first to mth gate lines, wherein at least one of the first to m-1st slit structures includes a bent portion which partially surrounds at least two of the first to mth contact plugs connected to gate lines of different conductive layers.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an electronic device, and more particularly to a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices used to form memory cells in a single layer on a substrate has approached its limit, three-dimensional (3D) semiconductor devices for stacking memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such 3D semiconductor devices. Summary of the Invention

[0003] In an embodiment, a semiconductor device may include: a gate structure comprising a first conductive layer to an nth conductive layer, which are stacked sequentially and extend in a first direction, where n is an integer of 2 or greater; a first slit structure to an (m-1)th slit structure, which extend through the gate structure in the first direction and separate each of the first conductive layer to the nth conductive layer into a first gate line to an mth gate line, where m is an integer of 2 or greater; and a first contact plug to an mth contact plug, which are respectively connected to the first gate line to the mth gate line, wherein at least one of the first slit structure to the (m-1)th slit structure may include a bent portion that partially surrounds at least two contact plugs of the first contact plug to the mth contact plug that are connected to gate lines of different conductive layers.

[0004] In one embodiment, a semiconductor device may include: a first gate structure comprising first gate lines stacked in a stepped shape, each of the first gate lines including a first line portion extending in a first direction and a first pad portion having a width greater than the first line portion, and the first line portion and the first pad portion being alternately arranged; and a second gate structure adjacent to the first gate structure in a second direction intersecting the first direction, the second gate structure comprising second gate lines stacked in a stepped shape, each of the second gate lines including a second line portion extending in the first direction and a second pad portion having a width greater than the second line portion, and the second line portion and the second pad portion being alternately arranged, wherein the first line portion and the second pad portion may face each other in the second direction, and the second line portion and the first pad portion may face each other in the second direction.

[0005] In an embodiment, a semiconductor device may include: a first gate structure, the first gate structure including first gate lines stacked in a stepped shape, each of the first gate lines including a first line portion extending in a first direction and a first pad portion wider than the first line portion, and the first line portion and the first pad portion being arranged alternately; a second gate structure adjacent to the first gate structure in a second direction intersecting the first direction, the second gate structure including second gate lines stacked in a stepped shape, each of the second gate lines including a second line portion extending in the first direction and a second pad portion surrounding the first pad portion, and the second line portion and the second pad portion being arranged alternately; a first contact plug, the first contact plug being respectively connected to the first pad portion located at an end of the first gate line; and a second contact plug, the second contact plug being respectively connected to the second pad portion located at an end of the second gate line. Attached Figure Description

[0006] Figures 1A to 1D This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0007] Figure 2A and Figure 2B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0008] Figures 3A to 3E This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0009] Figure 4A and Figure 4B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0010] Figure 5A and Figure 5B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0011] Figure 6A and Figure 6B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0012] Figure 7 This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0013] Figure 8 This is a schematic diagram showing the structure of a semiconductor device according to an embodiment.

[0014] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment.

[0015] Figure 10 This is a configuration diagram of a semiconductor device according to an embodiment. Detailed Implementation

[0016] Various embodiments of the present disclosure described herein can be described with reference to cross-sectional views, plan views, and block diagrams as ideal schematic diagrams of semiconductor devices. Note that variations in the structure of the figures can be made by manufacturing techniques and / or tolerances. Embodiments of the present disclosure are not limited to the described embodiments and the specific structures shown in the figures, but may include other embodiments or variations of the described embodiments (including any structural changes that may arise from the requirements of the manufacturing process). Therefore, the areas shown in the figures are schematic in nature, and the shapes of the areas shown in the figures are intended to illustrate the specific structure of the areas of the element, and are not intended to limit the scope of the present disclosure.

[0017] The following embodiments relate to semiconductor devices with stable structures and improved characteristics.

[0018] By stacking memory cells in three dimensions, the embodiments disclosed herein improve the integration density of semiconductor devices. The embodiments also provide a semiconductor device with a stable structure and improved reliability.

[0019] In the following description, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0020] Figures 1A to 1D This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 1A It is a floor plan, and Figure 1B It is along Figure 1A A cross-sectional view taken from line A-A'.

[0021] Reference Figure 1A and Figure 1B The semiconductor device may include a gate structure GST, slit structures SLS1 to SLSm-1, and contact plugs CT11 to CTmn (from right to left, from bottom to top). The gate structure GST may extend along a first direction I and may include a first conductive layer 11_1 to an nth conductive layer 11_n stacked in an n-layer stepped shape. Here, n may be an integer of 2 or greater. As an example, the gate structure GST may include alternating layers of conductive layers 11_1 to 11_n and an insulating layer 12.

[0022] The slit structures SLS1 to SLSm-1 can extend along the first direction I through the gate structure GST. The slit structures SLS1 to SLSm-1 can separate each of the first conductive layers 11_1 to the nth conductive layer 11_n into first gate lines GL11 to the mth gate line GLmn. Here, m can be an integer of 2 or greater, and can be an even number. In other words, the ending alphanumeric character in each element identifier can each correspond to a coordinate on a row, grid, layer, or element. For example, for GL11, the last two digits 1 and 1 can correspond to position 1 in the first direction and position 1 in the second direction. Therefore, GL11 should not be interpreted as GL eleven, but rather as GL1-1. The first gate line GL11 to the mth gate line GLmn can be a source select line or a drain select line. As an example, the first gate line GL11 to the mth gate line GLmn can be a drain select line, and the gate structure GST can be a DSL stack.

[0023] The gate structure GST may include first gate structures GST1 to m-th gate structures GSTm separated by first slit structures SLS1 to m-1 (i.e., m minus 1) slit structures SLSm-1. First gate structures GST1 to m-th gate structures GSTm may be adjacent to each other along a second direction II intersecting the first direction I. First gate structure GST1 may include first gate lines GL11 to GL1n, second gate structure GST2 may include second gate lines GL21 to GL2n, third gate structure GST3 may include third gate lines GL31 to GL3n, and m-th gate structure GSTm may include m-th gate lines GLm1 to GLmn.

[0024] Contact plugs CT11 to CTmn can be connected to gate lines GL11 to GLmn respectively. First contact plugs CT11 to m-th contact plugs CTm1 can be connected to first gate lines GL11 to m-th gate lines GLm1 respectively, first contact plugs CT12 to m-th contact plugs CTm2 can be connected to first gate lines GL12 to m-th gate lines GLm2 respectively, first contact plugs CT13 to m-th contact plugs CTm3 can be connected to first gate lines GL13 to m-th gate lines GLm3 respectively, and first contact plugs CT1n to m-th contact plugs CTmn can be connected to first gate lines GL1n to m-th gate lines GLmn respectively.

[0025] The first contact plugs CT11 to CTmn, connected to the same conductive layers 11_1 to 11_n, can be located at the vertices of a polygon with m sides (e.g., an m-sided polygon). As an example, the first conductive layer 11_1 may include first gate lines GL11 to GL41, and the first contact plugs CT11 to CT41, respectively connected to the first gate lines GL11 to GL41, can be located at the vertices of a quadrilateral. The first contact plugs CT11 and CT41 can be adjacent to each other along the second direction II, and the second contact plugs CT21 and CT31 can be adjacent to each other along the second direction II.

[0026] The first contact plugs CT11 to the m-th contact plugs CTmn can be arranged along a first direction I and a second direction II. As an example, the first contact plugs CT11 to CT1n and the second contact plugs CT21 to CT2n, respectively connected to the first gate structure GST1 and the second gate structure GST2, can be arranged in a row along the first direction I. The first contact plugs CT11 to CT1n and the second contact plugs CT21 to CT2n can be arranged alternately in units of two. The third contact plugs CT31 to CT3n and the fourth contact plugs CT41 to CT4n, respectively connected to the third gate structure GST3 and the fourth gate structure GST4, can be arranged in a row along the first direction I. The third contact plugs CT31 to CT3n and the fourth contact plugs CT41 to CT4n can be arranged alternately in units of two. The second contact plugs CT21 to CT2n connected to the second gate structure GST2 and the third contact plugs CT31 to CT3n connected to the third gate structure GST3 can be adjacent to each other along the second direction II.

[0027] The first slit structure SLS1 to the (m-1)th slit structure SLSm-1 can extend between the first contact plugs CT11 to the m-th contact plugs CTmn connected to the same conductive layers 11_1 to 11_n. As an example, the first slit structure SLS1 can extend between the first contact plugs CT11 and the second contact plugs CT21 that are adjacent to each other along the first direction I. The third slit structure SLS3 can extend between the third contact plugs CT31 and the fourth contact plug CT41 that are adjacent to each other along the first direction I. The first slit structure SLS1 to the third slit structure SLS3 (where, for example, m = 4 and m-1 = 3, and...) Figure 1A The SLSm-1 shown corresponds to SLS3) and can be adjacent to each other along the second direction II in the first contact plug CT11 and the fourth contact plug CT41 (in Figure 1AThe second slit structure SLS2 extends between the second contact plug CT21 and the third contact plug CT31, which are adjacent to each other along the second direction II.

[0028] At least one of the first slit structures SLS1 to the (m-1)th slit structure SLSm-1 may include bent portions B1 and B2 surrounding contact plugs CT11 to CTmn connected to gate lines GL11 to GLmn of different layers. The first bent portion B1 may extend along a second direction II, and the second bent portion B2 may extend in a direction opposite to the second direction II. In the plane defined by the first direction I and the second direction II, the first bent portion B1 may have a C-shape with one side open, and the second bent portion B2 may have a C-shape with the other side open. The two contact plugs CT12 and CT13 surrounded by the first bent portion B1 may be connected to different gate lines GL12 and GL13, respectively, and may be adjacent to each other along the first direction I.

[0029] The odd-numbered slit structures SLS1 and SLS3 in the first slit structure SLS1 to the (m-1)th slit structure SLSm-1 may each include bent portions B1 and B2. The even-numbered slit structures SLS2 and SLS4 in the first slit structure SLS1 to the (m-1)th slit structure SLSm-1 may not include bent portions and may each have a straight shape. As an example, the first slit structure SLS1 and the third slit structure SLS3 may each include bent portions B1 and B2, and may have symmetrical shapes based on the second slit structure SLS2.

[0030] Reference Figure 1C The first gate structure GST1 may include first gate lines GL11 to GL1n stacked in an n-layer stepped shape. The first gate lines GL11 to GL1n may be stacked along a third direction III. The third direction III may be perpendicular to the first direction I and the second direction II.

[0031] The first gate line GL11 of the first layer may include a first line portion L11 extending along a first direction I and a first pad portion P11 with a width greater than the first line portion L11. As an example, the first line portion L11 may have a first width W11, and the first pad portion P11 may have a second width W12 greater than the first width W11. The first line portion L11 and the first pad portion P11 may be arranged alternately. The first gate line GL12 of the second layer may include a first line portion L12 extending along a first direction I and a first pad portion P12 with a width greater than the first line portion L12, and the first line portion L12 and the first pad portion P12 may be arranged alternately. The first gate line GL13 of the third layer may include a first line portion L13 extending along a first direction I and a first pad portion P13 with a width greater than the first line portion L13, and the first line portion L13 and the first pad portion P13 may be arranged alternately. The first gate line GL1n of the nth layer may include a first line portion L1n extending along a first direction I and a first pad portion P1n with a width greater than that of the first line portion L1n. The first pad portions P11 to P1n may have substantially the same width along a second direction II.

[0032] Reference Figure 1D The first conductive layer 11_1 may include a first gate line GL11 to an m-th gate line GLm1. The first gate line GL11 to the m-th gate line GLm1 may be located in the same layer (e.g., the first layer) and may be arranged along the second direction II.

[0033] The first gate line GL11 may include a first line portion L11 extending along a first direction I and a first pad portion P11 with a width greater than the first line portion L11, and the first line portion L11 and the first pad portion P11 may be arranged alternately. The second gate line GL21 may include a second line portion L21 extending along the first direction I and a second pad portion P21 with a width greater than the second line portion L21, and the second line portion L21 and the second pad portion P21 may be arranged alternately. The third gate line GL31 may include a third line portion L31 extending along the first direction I and a third pad portion P31 with a width greater than the third line portion L31, and the third line portion L31 and the third pad portion P31 may be arranged alternately. The m-th gate line GLm1 may include an m-th line portion Lm1 extending along the first direction I and an m-th pad portion Pm1 with a width greater than the m-th line portion Lm1, and the m-th line portion Lm1 and the m-th pad portion Pm1 may be arranged alternately.

[0034] The first pad portion P11 and the second line portion L21 can face each other along the second direction II, the first line portion L11 and the second pad portion P21 can face each other along the second direction II, the third pad portion P31 and the fourth line portion L41 can face each other along the second direction II, and the third line portion L31 and the fourth pad portion P41 can face each other along the second direction II.

[0035] The first contact plug CT11 can be connected to the end portion of the first pad portion P11 included in the first gate line GL11. The end portion of the first pad portion P11 can be a real pad, and the remaining portion of the first pad portion P11 can be a dummy pad. The second contact plug CT21 can be connected to the end portion of the second pad portion P21 included in the second gate line GL21. The end portion of the second pad portion P21 can be a real pad, and the remaining portion of the second pad portion P21 can be a dummy pad. The third contact plug CT31 can be connected to the end portion of the third pad portion P31 included in the third gate line GL31. The end portion of the third pad portion P31 can be a real pad, and the remaining portion of the third pad portion P31 can be a dummy pad. The m-th contact plug CTm1 can be connected to the end portion of the m-th pad portion Pm1 included in the m-th gate line GLm1. The m-th pad portion Pm1 located at the end can be a real pad, and the remaining m-th pad portion Pm1 can be a dummy pad.

[0036] Based on the above structure, because the first slit structure SLS1 includes a bent portion, the first pad portion P11 can have sufficient area between the first slit structures SLS1. Therefore, the width of the pad portion along the second direction II can be increased without increasing the width of the gate structure GST along the second direction II.

[0037] Contact plugs CT11 to CTmn can be arranged along a first direction I, and gate lines GL11 to GLmn can have a symmetrical shape. Therefore, process margin can be ensured, and programming / reading speed can be improved while maintaining the conductivity of gate lines GL11 to GLmn.

[0038] Figure 2A and Figure 2B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 2A It is a floor plan, and Figure 2B It is along Figure 2A The cross-sectional view taken by line B-B'. In the following text, content repeated from the previous description may be omitted.

[0039] Reference Figure 2A and Figure 2B The semiconductor device may include a word line stack (WLST), a DSL stack (DSLST), a slit structure (SLS), a DSL contact plug (DSLCT), a channel structure (CH), a first support (SP1), a second support (SP2), a first isolation structure (IS1), a second isolation structure (IS2), a word line contact plug (WLCT), and a dummy stack (DST).

[0040] The word line stack (WLST) may include alternately stacked word lines (WL) and insulating layers (22). The WLST may include a cell region (CR), a buffer region (BR), and a word line pad region (WLPD). The cell region (CR) is the region where memory cells are stacked. The word line pad region (WLPD) is the region containing pad portions for applying drive bias to the stacked word lines (WL), and the WLST may have a stepped shape within the word line pad region (WLPD). The buffer region (BR) connects the cell region (CR) and the word line pad region (WLPD) to each other and may be located between the cell region (CR) and the word line pad region (WLPD).

[0041] The DSL stack-up DSLST can be located above the word line stack-up WLST and can include alternately stacked drain select lines DSL1 to DSL4 and an insulating layer 24. The DSL stack-up DSLST can include a cell region CR and a DSL pad region DSLPD. The cell region CR is the region where drain select transistors are stacked. The DSL pad region DSLPD is the region containing the pad portions for applying drive bias voltage to the stacked drain select lines DSL1 to DSL4, and the DSL stack-up DSLST can have a stepped shape within the DSL pad region DSLPD. A buffer region BR can be located below the DSL pad region DSLPD.

[0042] The channel structure CH can be located in the cell region CR and can extend through the word line stack WLST and the DSL stack DSLST. The channel structure CH may include a channel layer 25, a memory layer 26 surrounding the channel layer 25, and an insulating core 27 located in the channel layer 25. The drain select transistor can be located in the region where the channel structure CH intersects with the drain select lines DSL1 to DSL4, and the memory cell can be located in the region where the channel structure CH intersects with the word line WL.

[0043] The DSL stack-up DSLST can be separated into a first DSL stack-up DSLST1, a second DSL stack-up DSLST2, a third DSL stack-up DSLST3, and a fourth DSL stack-up DSLST4 using a slot structure (SLS). The first DSL stack-up DSLST1 may include a first drain select line DSL1 stacked in a stepped shape; the second DSL stack-up DSLST2 may include a second drain select line DSL2 stacked in a stepped shape; the third DSL stack-up DSLST3 may include a third drain select line DSL3 stacked in a stepped shape; and the fourth DSL stack-up DSLST may include a fourth drain select line DSL4 stacked in a stepped shape. DSL contact plugs DSLCT can be connected to the first drain select line DSL1 through the fourth drain select line DSL4 in the DSL pad area DSLPD.

[0044] Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a first width W1 in the cell region CR, a second width W2 in the pad portion, and a third width W3 in the line portion. The first width W1 may be greater than the third width W3, and the second width W2 may be greater than the first width W1.

[0045] Word line contact plugs (WLCTs) can be connected to word lines (WL) in the word line pad area (WLPD). The dummy stack (DST) can include alternating layers of a first insulating layer and a second insulating layer. A first isolation structure (IS1) can be located in the word line pad area (WLPD) and can surround the dummy stack (DST). A second isolation structure (IS2) can extend from the cell area (CR) to the word line pad area (WLPD) via the DSL pad area (DSLPD). A slot structure (SLS) can extend from the cell area (CR) to the DSL pad area (DSLPD) and may not be located in the word line pad area (WLPD).

[0046] The first support SP1 can be located in the word line pad area WLPD and between the word line contact plugs WLCT. The second support SP2 can be located in the DSL pad area DSLPD and between the DSL contact plugs DSLCT. The first support SP1 and the second support SP2 can have the same shape or different shapes.

[0047] According to the above structure, because the slit structure SLS includes a bent portion, the pad portion located between the slit structures SLS can have sufficient area, ensuring the distance between the drain select line contact plug DSLCT and the second support SP2. Because the slit structure SLS includes a bent portion, the drain select lines DSL1 to DSL4 can have different widths depending on the region. The drain select lines DSL1 to DSL4 can have a first width W1 in the cell region CR, and a second width W2 greater than the first width W1 in the pad portion. Therefore, the area where the DSL contact plug DSLCT is to be formed can be ensured (e.g., acquired, drawn, etc.). Because the width of the pad portion increases to the second width W2 but the width of the line portion decreases to the third width W3, the contact area can be ensured without increasing the spacing of the memory blocks MB.

[0048] Figures 3A to 3E This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 3A It is a floor plan, and Figure 3B It is along Figure 3A The cross-sectional view taken from line C-C'.

[0049] Reference Figure 3A and Figure 3B The semiconductor device may include a gate structure GST, slit structures SLS1 to SLSm-1 and contact plugs CT11 to CTmn.

[0050] The gate structure GST may extend along a first direction I and may include a first conductive layer 31_1 to an nth conductive layer 31_n stacked in a stepped shape of n layers. Here, n may be an integer of 2 or greater. As an example, the gate structure GST may include alternating layers of conductive layers 31_1 to 31_n and an insulating layer 32.

[0051] The slit structures SLS1 to SLSm-1 can extend along the first direction I through the gate structure GST. The slit structures SLS1 to SLSm-1 can separate each of the first conductive layers 31_1 to the nth conductive layer 31_n into a first gate line GL11 to the mth gate line GLmn. Here, m can be an integer of 2 or greater, and can be an even number. The first gate line GL11 to the mth gate line GLmn can be a source select line or a drain select line. As an example, the first gate line GL11 to the mth gate line GLmn can be a drain select line, and the gate structure GST can be a DSL stack.

[0052] The gate structure GST may include first gate structures GST1 to m-th gate structures GSTm separated by first slit structures SLS1 to (m-1)th slit structures SLSm-1. The first gate structures GST1 to m-th gate structures GSTm may be adjacent to each other along the second direction II. The first gate structure GST1 may include first gate lines GL11 to GL1n, the second gate structure GST2 may include second gate lines GL21 to GL2n, the third gate structure GST3 may include third gate lines GL31 to GL3n, and the m-th gate structure GSTm may include m-th gate lines GLm1 to GLmn.

[0053] Contact plugs CT11 to CTmn can be connected to gate lines GL11 to GLmn, respectively. In the first layer, first contact plugs CT11 to the m-th contact plug CTm1 can be connected to the first gate lines GL11 to the m-th gate lines GLm1, respectively. In the second layer, first contact plugs CT12 to the m-th contact plug CTm2 can be connected to the first gate lines GL12 to the m-th gate lines GLm2, respectively. In the third layer, first contact plugs CT13 to the m-th contact plug CTm3 can be connected to the first gate lines GL13 to the m-th gate lines GLm3, respectively. In the n-th layer, first contact plugs CT1n to the m-th contact plug CTmn can be connected to the first gate lines GL1n to the m-th gate lines GLmn, respectively.

[0054] The first contact plugs CT11 to CTmn connected to the same conductive layers 31_1 to 11_n can be arranged diagonally. As an example, the first contact plugs CT11 to CT41 connected to the first gate line GL11 to the fourth gate line GL41 of the first conductive layer 31_1 can be arranged along a first diagonal direction intersecting the first direction I and the second direction II. The first contact plugs CT12 to CT42 connected to the first gate line GL12 to the fourth gate line GL42 of the second conductive layer 31_2 can be arranged along a second diagonal direction intersecting the first diagonal direction. The first contact plugs CT11 to CTmn can be arranged in a wavy or sawtooth shape extending along the first direction I.

[0055] The first slit structure SLS1 to the (m-1)th slit structure SLSm-1 can extend between the first contact plugs CT11 to the m-th contact plug CTmn, which are connected to the same conductive layers 31_1 to 31_n. As an example, the first slit structure SLS1 can extend between the first contact plug CT11 and the second contact plug CT21, which are adjacent to each other along the first diagonal direction. The second slit structure SLS2 can extend between the second contact plug CT21 and the third contact plug CT31, which are adjacent to each other along the first diagonal direction. The third slit structure SLS3 can extend between the third contact plug CT31 and the fourth contact plug CT41, which are adjacent to each other along the first diagonal direction.

[0056] The first slit structure SLS1 to the (m-1)th slit structure SLSm-1 may include bent portions B1 and B2 surrounding contact plugs CT11 to CTmn connected to gate lines GL11 to GLmn of different layers. The first bent portion B1 may extend along a second direction II, and the second bent portion B2 may extend in a direction opposite to the second direction II. In the plane defined by the first direction I and the second direction II, the first bent portion B1 may have a C-shape with one side open, and the second bent portion B2 may have a C-shape with the other side open. Two contact plugs CT12 and CT13 surrounded by the first bent portion B1 may be connected to different gate lines GL12 and GL13, respectively, and may be adjacent to each other along the first direction I. Two contact plugs CT21 and CT22 surrounded by the second bent portion B2 may be connected to different gate lines GL21 and GL22, respectively, and may be adjacent to each other along the first direction I.

[0057] The first bent portion B1 and the second bent portion B2 can have different dimensions. The first bent portion B1 and the second bent portion B2 included in the first slit structure SLS1 can have different widths, and the second bent portion B2 can have a larger width than the first bent portion B1. The first bent portion B1 of the second slit structure SLS2 can have a larger width than the first bent portion B1 of the first slit structure SLS1, and can surround the first bent portion B1 of the first slit structure SLS1.

[0058] Reference Figure 3CThe first gate structure GST1 may include first gate lines GL11 to GL1n stacked in an n-layer stepped shape. The first gate line GL11 of the first layer may include a first line portion L11 extending along a first direction I and a first pad portion P11 with a width greater than the first line portion L11, and the first line portion L11 and the first pad portion P11 may be arranged alternately. The first gate line GL12 of the second layer may include a first line portion L12 extending along the first direction I and a first pad portion P12 with a width greater than the first line portion L12, and the first line portion L12 and the first pad portion P12 may be arranged alternately. The first gate line GL13 of the third layer may include a first line portion L13 extending along the first direction I and a first pad portion P13 with a width greater than the first line portion L13, and the first line portion L13 and the first pad portion P13 may be arranged alternately. The first gate line GL1n of the nth layer may include a first line portion L1n extending along the first direction I and a first pad portion P1n with a width greater than the first line portion L1n.

[0059] Reference Figure 3D The second gate structure GST2 may include second gate lines GL21 to GL2n stacked in an n-layer stepped shape. The second gate line GL21 of the first layer may include a second line portion L21 extending along a first direction I and a second pad portion P21 surrounding a first pad portion P11, and the second line portion L21 and the second pad portion P21 may be arranged alternately. The second gate line GL22 of the second layer may include a second line portion L22 extending along the first direction I and a second pad portion P22 surrounding a first pad portion P12, and the second line portion L22 and the second pad portion P22 may be arranged alternately. The second gate line GL23 of the third layer may include a second line portion L23 extending along the first direction I and a second pad portion P23 surrounding a first pad portion P13, and the second line portion L23 and the second pad portion P23 may be arranged alternately. The second gate line GL2n of the nth layer may include a second line portion L2n extending along the first direction I and a second pad portion P2n surrounding a first pad portion P1n.

[0060] The second contact plug CT21 can be connected to the end portion of the second pad portion P21 included in the second gate line GL21. The end portion of the second pad portion P21 can be a real pad, and the remaining portion of the second pad portion P21 can be a dummy pad. The second pad portion P21 can include a first portion P1 extending along a first direction I and a second portion P2 extending along a second direction II. The second contact plug CT21 can be connected to the second portion P2 of the second pad portion P21.

[0061] Reference Figure 3EThe first conductive layer 31_1 may include a first gate line GL11 to an m-th gate line GLm1. The first gate line GL11 to the m-th gate line GLm1 may be located in the same layer (e.g., the first layer) and may be arranged along the second direction II.

[0062] The first gate line GL11 may include a first line portion L11 extending along a first direction I and a first pad portion P11 with a width greater than the first line portion L11, and the first line portion L11 and the first pad portion P11 may be arranged alternately. The second gate line GL21 may include a second line portion L21 extending along the first direction I and a second pad portion P21 surrounding the first pad portion P11, and the second line portion L21 and the second pad portion P21 may be arranged alternately. The third gate line GL31 may include a third line portion L31 extending along the first direction I and a third pad portion P31 surrounding the second pad portion P21, and the third line portion L31 and the third pad portion P31 may be arranged alternately. The m-th gate line GLm1 may include an m-th line portion Lm1 extending along the first direction I and an m-th pad portion Pm1 with a width greater than the m-th line portion Lm1, and the m-th line portion Lm1 and the m-th pad portion Pm1 may be arranged alternately. The m-th pad portion Pm1 can be positioned to correspond to the (m-1)-th line portion Lm-1.

[0063] The second pad portion P21 may surround the first pad portion P11. The first pad portion P11 may have a first width WA, and the second pad portion P21 may have a second width WB greater than the first width WA. The third pad portion P31 may surround the second pad portion P21. The second pad portion P21 may have a second width WB, and the third pad portion P31 may have a third width WC greater than the second width WB.

[0064] According to the above structure, using slit structures SLS1 to SLSm-1 including bent portions, the width of the pad portion can be increased along the second direction II. Therefore, the width of the pad portion along the second direction II can be increased without increasing the width of the gate structure GST along the second direction II.

[0065] Figure 4A and Figure 4B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 4A It is a floor plan, and Figure 4B It is along Figure 4A A cross-sectional view taken by line D-D'. In the following text, content repeated from the previous description may be omitted.

[0066] Reference Figure 4A and Figure 4BThe semiconductor device may include a word line stack (WLST), a DSL stack (DSLST), a slit structure (SLS), a DSL contact plug (DSLCT), a channel structure (CH), a support (SP), a first isolation structure (IS1), a second isolation structure (IS2), a word line contact plug (WLCT), and a dummy stack (DST).

[0067] The word line stack-up (WLST) may include alternating word lines (WL) and an insulating layer 42. The WLST may include a cell region (CR), a buffer region (BR), and a word line pad region (WLPD). The DSL stack-up (DSLST) may be located above the WLST and may include alternating drain select lines (DSL1 to DSL4) and an insulating layer 44.

[0068] The channel structure CH can be located in the cell region CR and can extend through the word line stack WLST and the DSL stack DSLST. The channel structure CH may include a channel layer 45, a memory layer 46 surrounding the channel layer 45, and an insulating core 47 located in the channel layer 45.

[0069] The DSL stack-up DSLST can be separated into a first DSL stack-up DSLST1, a second DSL stack-up DSLST2, a third DSL stack-up DSLST3, and a fourth DSL stack-up DSLST4 using a slot structure (SLS). The first DSL stack-up DSLST1 may include a first drain select line DSL1 stacked in a stepped shape; the second DSL stack-up DSLST2 may include a second drain select line DSL2 stacked in a stepped shape; the third DSL stack-up DSLST3 may include a third drain select line DSL3 stacked in a stepped shape; and the fourth DSL stack-up DSLST may include a fourth drain select line DSL4 stacked in a stepped shape. DSL contact plugs DSLCT can be connected to the first drain select line DSL1 through the fourth drain select line DSL4 in the DSL pad area DSLPD.

[0070] Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a first width W1 in the cell region CR, a second width W2 in the pad portion, and a third width W3 in the line portion. The first width W1 may be greater than the third width W3, and the second width W2 may be greater than the first width W1.

[0071] Word line contact plugs (WLCTs) can be connected to word lines (WL) in the word line pad area (WLPD). The dummy stack (DST) can include alternating layers of a first insulating layer and a second insulating layer. A first isolation structure (IS1) can be located in the word line pad area (WLPD) and can surround the dummy stack (DST). A second isolation structure (IS2) can extend from the cell area (CR) to the word line pad area (WLPD) via the DSL pad area (DSLPD). A slot structure (SLS) can extend from the cell area (CR) to the DSL pad area (DSLPD), and in some cases, may not be located in the word line pad area (WLPD). A support member (SP) can be located in both the word line pad area (WLPD) and the DSL pad area (DSLPD).

[0072] According to the above structure, the slit structure SLS may include a bent portion, and the drain select lines DSL1 to DSL4 may have different widths depending on the region. The drain select lines DSL1 to DSL4 may have a first width W1 in the cell region CR, and a second width W2 greater than the first width W1 in the pad portion. Therefore, the area where the DSL contact plug DSLCT is to be formed can be ensured. Because the width of the pad portion increases to the second width W2 but the width of the line portion decreases to the third width W3, the contact area can be ensured without increasing the spacing of the memory blocks MB.

[0073] Figure 5A and Figure 5B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 5A It is a floor plan, and Figure 5B It is along Figure 5A The cross-sectional view taken by line E-E'. In the following text, content repeated from the previous description may be omitted.

[0074] Reference Figure 5A and Figure 5B The semiconductor device may include a word line stack (WLST), a DSL stack (DSLST), a slit structure (SLS), a DSL contact plug (DSLCT), a channel structure (CH), a first support (SP1), a second support (SP2), a first isolation structure (IS1), a second isolation structure (IS2), a word line contact plug (WLCT), and a dummy stack (DST).

[0075] The word line stack (WLST) may include alternating layers of word lines (WL) and insulating layer 52. The WLST may include cell regions (CR), buffer regions (BR), and word line pad regions (WLPD). The WLST may have a flat shape on its upper surface within the cell regions (CR), buffer regions (BR), and word line pad regions (WLPD).

[0076] The DSL stack-up DSLST may be located above the word line stack-up WLST and may include alternately stacked drain select lines DSL1 to DSL4 and an insulating layer 54. The DSL stack-up DSLST may include a cell region CR, a DSL pad region DSLPD, and a dummy region DR. The DSL stack-up DSLST may have a flat shape on its upper surface within the cell region CR, the DSL pad region DSLPD, and the dummy region DR. The DSL pad region DSLPD may be located above the buffer region BR, and the dummy region DR may be located above the word line pad region WLPD.

[0077] The channel structure CH can be located in the cell region CR and can extend through the word line stack WLST and the DSL stack DSLST. The channel structure CH may include a channel layer 55, a memory layer 56 surrounding the channel layer 55, and an insulating core 57 located in the channel layer 55.

[0078] The DSL stack DSLST can be separated into a first DSL stack DSLST1, a second DSL stack DSLST2, a third DSL stack DSLST3, a fourth DSL stack DSLST4, and a dummy DSL stack DDSLST through a slot structure SLS. The first DSL stack DSLST1 may include a stacked first drain select line DSL1, the second DSL stack DSLST2 may include a stacked second drain select line DSL2, the third DSL stack DSLST3 may include a stacked third drain select line DSL3, and the fourth DSL stack DSLST may include a stacked fourth drain select line DSL4. DSL contact plugs DSLCT can extend through the DSL stack DSLST at different depths in the DSL pad area DSLPD and can be connected to the first drain select line DSL1 through the fourth drain select line DSL4, respectively. The sidewalls of the DSL contact plugs DSLCT can be surrounded by insulating spacers 58.

[0079] Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a shape in which the pad portion and the line portion repeat in the DSL pad area DSLPD. Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a first width W1 in the cell area CR, a second width W2 in the pad portion, and a third width W3 in the line portion. The first width W1 may be greater than the third width W3, and the second width W2 may be greater than the first width W1.

[0080] The word line contact plug (WLCT) can penetrate the dummy area DR of the DSL stack-up DSLST and extend into the word line pad area WLPD of the word line stack-up WLST. The WLCT can extend to different depths and can be individually connected to word lines WL.

[0081] The first isolation structure IS1 can extend through the dummy region DR of the DSL stack-up DSLST and the word line pad region WLPD of the word line stack-up WLST, and can surround the dummy stack-up DST. The second isolation structure IS2 can extend from the cell region CR to the dummy region DR via the DSL pad region DSLPD.

[0082] The slot structure SLS can extend from the cell region CR to the DSL pad region DSLPD. The DSL pad region DSLPD and the dummy region DR can be separated from each other by the slot structure SLS, and in some cases, the slot structure SLS may not be located in the dummy region DR.

[0083] The first support SP1 can be located in the dummy area DR and the word line pad area WLPD, and can be located between the word line contact plugs WLCT. The second support SP2 can be located in the DSL pad area DSLPD and the buffer area BR, and can be located between the DSL contact plugs DSLCT. The first support SP1 and the second support SP2 can have the same shape or different shapes.

[0084] According to the above structure, the DSL stack-up DSLST and the word line stack-up WLST can include structures different from the stepped structure, and the DSL pad area DSLPD and the word line pad area WLPD can each have a flat upper surface. Because the slit structure SLS includes a bent portion, this structure provides the ability to ensure the distance between the drain select line contact plug DSLCT and the second support SP2, and to ensure the area where the DSL contact plug DSLCT is to be formed. Additionally, the contact area can be ensured without increasing the spacing of the memory blocks MB.

[0085] Figure 6A and Figure 6B This is a schematic diagram showing the structure of a semiconductor device according to an embodiment. Figure 6A It is a floor plan, and Figure 6B It is along Figure 6A The cross-sectional view taken by line F-F'. In the following text, content repeated from the previous description may be omitted.

[0086] Reference Figure 6A and Figure 6BThe semiconductor device may include a word line stack (WLST), a DSL stack (DSLST), a slit structure (SLS), a DSL contact plug (DSLCT), a channel structure (CH), a support (SP), a first isolation structure (IS1), a second isolation structure (IS2), a word line contact plug (WLCT), and a dummy stack (DST).

[0087] The word line stack (WLST) may include alternating word lines (WL) and an insulating layer 62. The WLST may include a cell region (CR), a buffer region (BR), and a word line pad region (WLPD). The DSL stack (DSLST) may be located above the WLST and may include alternating drain select lines (DSL1 to DSL4) and an insulating layer 64. The DSLST may include a cell region (CR), a DSL pad region (DSLPD), and a dummy region (DR).

[0088] The channel structure CH can be located in the cell region CR and can extend through the word line stack WLST and the DSL stack DSLST. The channel structure CH may include a channel layer 65, a memory layer 66 surrounding the channel layer 65, and an insulating core 67 located in the channel layer 65.

[0089] The DSL stack DSLST can be separated into a first DSL stack DSLST1, a second DSL stack DSLST2, a third DSL stack DSLST3, a fourth DSL stack DSLST4, and a dummy DSL stack DDSLST through a slit structure SLS. The DSL pad area DSLPD may include a flat upper surface. DSL contact plugs DSLCT can extend to different depths in the DSL pad area DSLPD and can be connected to the first drain select line DSL1 through the fourth drain select line DSL4, respectively. The sidewalls of the DSL contact plugs DSLCT may be surrounded by insulating spacers 68.

[0090] Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a shape in which the pad portion and the line portion repeat in the DSL pad area DSLPD. Each of the first drain select lines DSL1 to the fourth drain select lines DSL4 may have a first width W1 in the cell area CR, a second width W2 in the pad portion, and a third width W3 in the line portion. The first width W1 may be greater than the third width W3, and the second width W2 may be greater than the first width W1.

[0091] Word line contact plugs (WLCTs) can penetrate the DSL stack-up (DSLST) and extend to varying depths into the word line stack-up (WLST). WLCTs can be connected to word lines (WL) in the word line pad area (WLPD).

[0092] The first isolation structure IS1 can extend through the dummy region DR of the DSL stack-up DSLST and the word line pad region WLPD of the word line stack-up WLST, and can surround the dummy stack-up DST. The second isolation structure IS2 can extend from the cell region CR to the dummy region DR via the DSL pad region DSLPD.

[0093] The slot structure (SLS) can extend from the cell region (CR) to the DSL pad region (DSLPD). The DSL pad region (DSLPD) and the dummy region (DR) can be separated from each other by the slot structure (SLS), and in some cases, the slot structure (SLS) may not be located in the dummy region (DR). The support element (SP) can be located in the word line pad region (WLPD) and the DSL pad region (DSLPD).

[0094] In addition to the structure described above, the slit structure SLS can also include a bent portion, and the drain selection lines DSL1 to DSL4 can have different widths depending on the area. Therefore, the area where the DSL contact plug DSLCT is to be formed can be ensured, and the contact area can be guaranteed without increasing the spacing of the memory blocks MB.

[0095] Figure 7 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment. In the following text, content repeated from the previous description may be omitted.

[0096] Reference Figure 7 The semiconductor device may include a first semiconductor structure S1 and a second semiconductor structure S2. The second semiconductor structure S2 may be located above the first semiconductor structure S1, or the first semiconductor structure S1 may be located above the second semiconductor structure S2.

[0097] The first semiconductor structure S1 may include peripheral circuitry PC. The peripheral circuitry PC may include a line decoder, page buffer, input / output circuitry, logic circuitry, etc. As an example, the first semiconductor structure S1 may include a substrate 70, a transistor TR, a first interconnect structure IC1, and a first interlayer insulating layer IL1. The transistor TR may be part of the peripheral circuitry PC. The first interconnect structure IC1 may be formed in the first interlayer insulating layer IL1 and may be electrically connected to the peripheral circuitry PC. The first interconnect structure IC1 may include vias, wiring, etc.

[0098] The second semiconductor structure S2 may include a memory cell array comprising stacked memory cells. As an example, the second semiconductor structure S2 may include a source structure S, a stacked body ST, a channel structure CH, a slit structure SLS, a contact plug CT, a second interconnect structure IC2, and a second interlayer insulating layer IL2.

[0099] The stack ST can be located above the source structure S. The stack ST can include alternating layers of conductive layers 71 and insulating layers 72. The stack ST can include a word line stack, a DSL stack, and / or an SSL stack. The conductive layer 71 can be a gate line, and can be a word line, a drain select line, or a source select line. The contact plug CT can be a word line contact plug or a DSL contact plug. The channel structure CH can include a channel layer 75, a memory layer 76 surrounding the channel layer 75, and an insulating core 77 located in the channel layer 75.

[0100] The slit structure SLS can extend through the stack-up ST and can have sufficient depth to penetrate the drain select line. The second interconnect structure IC2 can be located in the second interlayer insulating layer IL2 and can be electrically connected to the memory cell array. The second interconnect structure IC2 may include vias, wiring, etc. Although the slit structure SLS and the second interlayer insulating layer IL2 are... Figure 7 The layers are shown as separate layers, but the interface between the slit structure SLS and the second interlayer insulation layer IL2 may be indistinguishable in the actual device.

[0101] According to the above structure, by stacking the first semiconductor structure S1 and the second semiconductor structure S2, the disclosed embodiment can increase the integration density of the semiconductor device. Furthermore, the disclosed embodiment can provide the ability to efficiently arrange or arrange the pad portions of the gate lines using a slit structure SLS including bent portions.

[0102] Figure 8 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment. In the following text, content repeated from the previous description may be omitted.

[0103] Reference Figure 8 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS. The first semiconductor structure S1 may include peripheral circuitry, and the second semiconductor structure S2 may include a memory cell array.

[0104] The first semiconductor structure S1 may include a substrate 80, a transistor TR, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The transistor TR may be part of the peripheral circuit. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1 and may include vias, wiring, etc. The first interconnect structure IC1 may be electrically connected to the peripheral circuit.

[0105] The second semiconductor structure S2 may include a source structure S, a stacked body ST, a channel structure CH, a slit structure SLS, a contact plug CT, a second interlayer insulating layer IL2, and a second interconnect structure IC2. The stacked body ST may include alternating layers of conductive layers 81 and insulating layers 82. The source structure S may be located above or below the stacked body ST. The channel structure CH may include a channel layer 85, a memory layer 86 surrounding the channel layer 85, and an insulating core 87 located in the channel layer 85.

[0106] The slit structure SLS can extend through the stack-up ST and can have a depth sufficient to penetrate the drain select line. The second interconnect structure IC2 can be located within the second interlayer insulating layer IL2 and can be electrically connected to the memory cell array. The second interconnect structure IC2 may include vias, wiring, etc. Although the slit structure SLS and the second interlayer insulating layer IL2 are... Figure 8 The layers are shown as separate layers, but the interface between the slit structure SLS and the second interlayer insulation layer IL2 may be indistinguishable in the actual device.

[0107] The bonding structure BS can be located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 can be manufactured separately and can be electrically connected to each other through the bonding structure BS. The memory cell array including the stacked body ST and the peripheral circuitry can be electrically connected to each other through the bonding structure BS.

[0108] The bonding structure BS may include a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding layer BL1 and the second bonding layer BL2 may be in contact with each other, and the first bonding pad BP1 and the second bonding pad BP2 may also be in contact with each other. The first bonding layer BL1 and the second bonding layer BL2 may each comprise silicon carbon nitride (SiCN), tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 may be electrically connected to the first interconnect structure IC1, and the second bonding pad BP2 may be electrically connected to the second interconnect structure IC2. The memory cell array and peripheral circuitry can be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0109] According to the above structure, the first semiconductor structure S1 and the second semiconductor structure S2 are joined to each other in a vertical direction, thus the implementation can increase the integration density of the semiconductor device. Furthermore, the disclosed implementation can provide the ability to efficiently arrange or arrange the pad portions of the gate lines using a slit structure SLS including bent portions.

[0110] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 9 and Figure 10A schematic configuration of a semiconductor device to which the above embodiments can be applied is shown.

[0111] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0112] Reference Figure 9 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and the memory cell array CA may be formed on the same substrate.

[0113] The substrate SUB can be made of or comprise a semiconductor material. In embodiments, the semiconductor material can include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors can include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors can include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors can include ZnS, ZnO, or CdS.

[0114] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0115] The substrate SUB can be a bulk wafer or epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0116] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In some embodiments, the peripheral circuitry PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, lines, etc.

[0117] A memory cell array (CA) may include memory cells. In one embodiment, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. In another embodiment, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0118] Figure 10 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0119] Reference Figure 10 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support base SP_B.

[0120] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. In an embodiment, after fabricating a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer can be electrically connected by a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer can be removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0121] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The support substrate SP_B can be monocrystalline, polycrystalline, or amorphous. The support substrate SP_B can include group II, III, IV, V, or VI impurities.

[0122] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded using wafer-on-wafer bonding, chip-on-wafer bonding, chip-on-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals and / or alloys such as copper and aluminum. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0123] In an alternative embodiment, the interconnect structures included in the memory cell array (CA) and / or the peripheral circuitry (PC) can be directly connected without pads. In this embodiment, the bonding layers included in the memory cell array (CA) and the bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and the interconnect structures included in the memory cell array (CA) and the interconnect structures included in the peripheral circuitry (PC) can be directly connected. Thus, contacts, plugs, lines, etc., formed on different wafers can be electrically connected without separate pads.

[0124] It can be compared with the above. Figure 9 Other configurations of a semiconductor device are implemented in a manner that is equivalent to or similar to the manner described.

[0125] At the same time, the semiconductor device can have the above reference Figure 9 and Figure 10 The described implementation scheme may have a structure that is partially modified. (Refer to...) Figure 9 and Figure 10 In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be additionally coupled to the reference. Figure 9 and Figure 10 The described implementation method. In this implementation method, a portion of the peripheral circuitry PC may be located in the memory cell array CA.

[0126] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely illustrative of embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Various substitutions, modifications, alterations, and combinations of the embodiments can be made by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the appended claims, and it should be understood that such substitutions, modifications, alterations, and combinations are within the scope of this disclosure.

[0127] Cross-references to related applications

[0128] This application claims priority to Korean Patent Application No. 10-2025-0014956, filed on February 6, 2025, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising a first conductive layer to an nth conductive layer that are sequentially stacked and extend in a first direction, where n is an integer of 2 or greater; The first slit structure to the (m-1)th slit structure extends through the gate structure in the first direction and separates each of the first conductive layer to the nth conductive layer into a first gate line to the mth gate line, where m is an integer of 2 or greater. as well as The first contact plug to the m-th contact plug are respectively connected to the first gate line to the m-th gate line. Wherein, at least one of the first slit structure to the (m-1)th slit structure includes a bent portion, the bent portion partially surrounding at least two contact plugs among the first contact plug to the mth contact plug that are connected to gate lines of different conductive layers.

2. The semiconductor device according to claim 1, wherein, At least one of the first slit structure to the (m-1)th slit structure includes: The first bend portion extends in a second direction intersecting the first direction; and The second bend extends in a direction opposite to the second direction.

3. The semiconductor device according to claim 1, wherein, The at least two contact plugs are partially surrounded by the bent portion and are adjacent to each other in the first direction.

4. The semiconductor device according to claim 1, wherein, The first gate line to the m-th gate line are drain selection lines.

5. The semiconductor device according to claim 1, wherein, The first conductive layer to the nth conductive layer are stacked in a stepped shape.

6. The semiconductor device according to claim 1, wherein, The first and second contact plugs from the first contact plug to the m-th contact plug are arranged in a row along the first direction; The first contact plug to the third and fourth contact plugs among the m-th contact plugs are arranged in a row along the first direction; The first contact plug and the fourth contact plug are adjacent to each other in a second direction intersecting the first direction; and The second contact plug and the third contact plug are adjacent to each other in the second direction.

7. The semiconductor device according to claim 1, wherein, The first contact plugs to the fourth contact plugs, which are respectively connected to the first gate line to the fourth gate line of the same conductive layer, are located at the corresponding vertices of the quadrilateral.

8. The semiconductor device according to claim 1, wherein, Each of the odd-numbered slit structures from the first slit structure to the (m-1)th slit structure includes a bent portion, and each of the even-numbered slit structures from the first slit structure to the (m-1)th slit structure does not include a bent portion.

9. The semiconductor device according to claim 1, wherein, The first slit structure and the third slit structure in the first slit structure to the (m-1)th slit structure have symmetrical shapes based on the second slit structure in the first slit structure to the (m-1)th slit structure.

10. The semiconductor device according to claim 1, wherein, The first gate line of the first conductive layer includes a first line portion extending in the first direction and a first pad portion with a width greater than the first line portion; The second gate line of the first conductive layer includes a second line portion extending in the first direction and a second pad portion with a width greater than the second line portion; The first line portion and the second pad portion face each other in a second direction intersecting the first direction; and The second line portion and the first pad portion face each other in the second direction.

11. The semiconductor device according to claim 1, wherein, The first contact plug connected to the first gate line of the first conductive layer and the fourth contact plug connected to the fourth gate line of the first conductive layer are adjacent to each other in a second direction intersecting the first direction, and The first slit structure to the third slit structure extends between the first contact plug and the fourth contact plug.

12. The semiconductor device according to claim 11, wherein, The second contact plug connected to the second gate line of the first conductive layer and the third contact plug connected to the third gate line of the first conductive layer are adjacent to each other in the second direction, and The second slit structure extends between the second contact plug and the third contact plug.

13. The semiconductor device according to claim 1, wherein, The bent portion of the second slit structure in the first slit structure to the (m-1)th slit structure has a wider width than the bent portion of the first slit structure and partially surrounds the bent portion of the first slit structure.

14. The semiconductor device according to claim 1, wherein, The first contact plugs to the m-th gate line, which are respectively connected to the first conductive layer, are arranged in a first diagonal direction intersecting the first direction.

15. The semiconductor device according to claim 14, wherein, The first gate line to the m gate line, which are respectively connected to the second conductive layer in the first conductive layer to the nth conductive layer, are arranged in a second diagonal direction intersecting the first diagonal direction.

16. The semiconductor device according to claim 1, wherein, The first gate line from the first gate line to the m-th gate line includes a first line portion extending in the first direction and a first pad portion with a width greater than the first line portion; and The second gate line from the first gate line to the m-th gate line includes a second line portion extending in the first direction and a second pad portion partially surrounding the first pad portion.

17. The semiconductor device according to claim 16, wherein, The second pad portion includes a first portion extending in the first direction and a second portion extending in a second direction intersecting the first direction, and The first contact plug to the second contact plug of the m-th contact plug are connected to the second part.

18. The semiconductor device according to claim 1, wherein, The first slit structure extends between the first contact plug and the second contact plug in the m-th contact plug; and The second slit structure extends between the second and third contact plugs from the first contact plug to the m-th contact plug.

19. A semiconductor device, the semiconductor device comprising: A first gate structure, the first gate structure including first gate lines stacked in a stepped shape, each of the first gate lines including a first line portion extending in a first direction and a first pad portion with a width greater than the first line portion, and the first line portion and the first pad portion are arranged alternately. as well as A second gate structure is adjacent to the first gate structure in a second direction intersecting the first direction. The second gate structure includes second gate lines stacked in a stepped shape. Each of the second gate lines includes a second line portion extending in the first direction and a second pad portion with a width greater than the second line portion. The second line portion and the second pad portion are arranged alternately. The first line portion and the second pad portion face each other in the second direction, and the second line portion and the first pad portion face each other in the second direction.

20. The semiconductor device of claim 19, further comprising: The first contact plug is connected to the first pad portion located at the end of the first gate line; as well as The second contact plug is connected to the second pad portion located at the end of the second gate line.

21. The semiconductor device according to claim 20, wherein, The first contact plug and the second contact plug are arranged in a row along the first direction.

22. The semiconductor device according to claim 21, wherein, The first contact plug and the second contact plug are arranged alternately in units of two.

23. The semiconductor device according to claim 19, wherein, The first gate line and the second gate line are drain select lines.

24. The semiconductor device of claim 19, further comprising: A third gate structure is adjacent to the second gate structure in the second direction. The third gate structure includes third gate lines stacked in a stepped shape. Each third gate line includes a third line portion extending in the first direction and a third pad portion with a width greater than the third line portion. The third line portion and the third pad portion are arranged alternately. as well as A fourth gate structure is adjacent to the third gate structure in the second direction. The fourth gate structure includes fourth gate lines stacked in a stepped shape. Each of the fourth gate lines includes a fourth line portion extending in the first direction and a fourth pad portion with a width greater than the fourth line portion. The fourth line portion and the fourth pad portion are arranged alternately.

25. The semiconductor device according to claim 24, wherein, The third line portion and the fourth pad portion face each other in the second direction, and the fourth line portion and the third pad portion face each other in the second direction.

26. The semiconductor device of claim 25, further comprising: The first contact plug is connected to the first pad portion located at the end of the first gate line; The second contact plug is connected to the second pad portion located at the end of the second gate line; The third contact plug is connected to the third pad portion located at the end of the third gate line; as well as The fourth contact plug is connected to the fourth pad portion located at the end of the fourth gate line.

27. The semiconductor device of claim 26, wherein, The first contact plug to the fourth contact plug connected to the first gate line to the fourth gate line on the same layer are arranged such that the first contact plug and the fourth contact plug are adjacent to each other in the second direction, and the second contact plug and the third contact plug are adjacent to each other in the second direction.

28. The semiconductor device according to claim 24, wherein, The first gate line, the second gate line, the third gate line, and the fourth gate line are drain select lines.

29. A semiconductor device, the semiconductor device comprising: A first gate structure, the first gate structure including first gate lines stacked in a stepped shape, each of the first gate lines including a first line portion extending in a first direction and a first pad portion with a width greater than the first line portion, and the first line portion and the first pad portion are arranged alternately. A second gate structure is adjacent to the first gate structure in a second direction intersecting the first direction. The second gate structure includes second gate lines stacked in a stepped shape. Each of the second gate lines includes a second line portion extending in the first direction and a second pad portion surrounding the first pad portion, and the second line portion and the second pad portion are arranged alternately. The first contact plug is connected to the first pad portion located at the end of the first gate line; as well as The second contact plug is connected to the second pad portion located at the end of the second gate line.

30. The semiconductor device according to claim 29, wherein, The second pad portion located at the end of the second gate line includes a first portion extending in the first direction and a second portion extending in the second direction; and The second contact plug is connected to the second portion of the second pad portion.

31. The semiconductor device according to claim 29, wherein, The first contact plug and the second contact plug, which are respectively connected to the first gate line and the second gate line on the same layer, are adjacent to each other in the diagonal direction intersecting the first direction and the second direction.

32. The semiconductor device according to claim 29, wherein, Each second pad portion has a width greater than that of each first pad portion.

33. The semiconductor device according to claim 29, wherein, The first gate line and the second gate line are drain select lines.

34. The semiconductor device of claim 29, further comprising: A third gate structure, which is adjacent to the second gate structure in the second direction, and includes third gate lines stacked in a stepped shape, each of the third gate lines including a third line portion extending in the first direction and a third pad portion partially surrounding the second pad portion, and the third line portion and the third pad portion are arranged alternately. as well as The third contact plug is connected to the third pad portion located at the end of the third gate line.

35. The semiconductor device according to claim 34, wherein, The third pad portion located at the end of the third gate line includes a first portion extending in the first direction and a second portion extending in the second direction; and The third contact plug is connected to the second portion of the third pad portion.

36. The semiconductor device according to claim 34, wherein, The first contact plugs to the third contact plugs, which are respectively connected to the first gate line to the third gate line on the same layer, are adjacent to each other in the diagonal direction intersecting the first direction and the second direction.

37. The semiconductor device of claim 34, wherein, Each third pad portion has a width greater than that of each second pad portion.

38. The semiconductor device according to claim 34, wherein, The first gate line, the second gate line, and the third gate line are drain select lines.

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