Semiconductor device

Abstract

A semiconductor device that improves uniformity of a write voltage is provided. A semiconductor device of an embodiment includes a first laminate in which a plurality of first wiring layers and a plurality of first insulator layers are alternately laminated along a first direction, and a first hole having a portion in which an inner diameter changes along the first direction extending in the first direction is formed; and a first columnar body extending in the first direction in the first hole, having a first semiconductor film from an inner side of the first hole in a second direction perpendicular to the first direction, a first tunnel insulating film provided outside the first semiconductor film, a first charge accumulation film provided outside the first tunnel insulating film, and a first barrier insulating film provided between the first charge accumulation film and the plurality of first wiring layers and the plurality of first insulator layers in the second direction; and in the second direction, at least one or more of the first barrier insulating film, the first charge accumulation film, and the first tunnel insulating film is set to a first film thickness when an inner diameter of the first hole is a first inner diameter, and is set to a second film thickness when the inner diameter of the first hole is a second inner diameter, and in the case where the first inner diameter is larger than the second inner diameter, the first film thickness is smaller than the second film thickness.

Description

Technical Field

[0001] The implementation relates to a semiconductor device. Background Technology

[0002] In recent years, semiconductor devices that integrate memory cells in three dimensions have been proposed. In such semiconductor devices, through-holes are formed by alternating layers of insulating and conductive layers. A memory layer and a silicon layer capable of storing charge are formed on the inner surface of the through-holes, and a memory cell is formed between the silicon layer and the conductive layer. Summary of the Invention

[0003] One embodiment provides a semiconductor device that improves the uniformity of write voltage.

[0004] One embodiment of a semiconductor device includes: a first stacked body in which a plurality of first wiring layers and a plurality of first insulating layers are alternately stacked along a first direction, and a first aperture is formed therein, the first aperture having a portion whose inner diameter varies along the first direction extending in the first direction; and a first columnar body extending in the first aperture along the first direction, having, in a second direction perpendicular to the first direction, a first semiconductor film, a first tunnel insulating film disposed on the outer side of the first semiconductor film, and a first tunnel insulating film disposed on the first tunnel insulating film, starting from the inner side of the first aperture. The first charge storage film on the outer side, and the first barrier insulating film disposed between the first charge storage film and the plurality of first wiring layers and the plurality of first insulating layers; and in the second direction, when at least one of the first barrier insulating film, the first charge storage film and the first tunnel insulating film has a thickness of 1 when the inner diameter of the first hole is the first inner diameter, and a thickness of 2 when the inner diameter of the first hole is the second inner diameter, the first film thickness is less than the second film thickness when the first inner diameter is greater than the second inner diameter. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of the memory system in the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment.

[0007] Figure 3 This is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment.

[0008] Figure 4 This is a perspective view showing the outline of the bonding structure of the semiconductor memory device according to the first embodiment.

[0009] Figure 5This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment.

[0010] Figure 6 This is a top view showing an example of the planar layout of the memory cell region of the memory cell array included in the semiconductor memory device of the first embodiment.

[0011] Figure 7 This is an example of a cross-sectional structure of the memory region of the memory cell array included in the semiconductor memory device of the first embodiment, and along... Figure 6 A sectional view along line VII-VII.

[0012] Figure 8 This is a diagram showing an example of the longitudinal cross-sectional structure of the columnar body disposed in the memory region.

[0013] Figure 9 This is a diagram showing an example of the cross-sectional structure of a columnar body disposed in the memory region.

[0014] Figure 10A This is a cross-sectional view showing an example of a memory hole formed in the memory cell region.

[0015] Figure 10B This is a cross-sectional view showing the state in which a blocking oxide film has formed in the memory hole.

[0016] Figure 10C This is a cross-sectional view showing the state after the thickness of the barrier oxide film has been adjusted by thinning.

[0017] Figure 11 This is a partially enlarged cross-sectional view showing an example of the cross-sectional structure of the memory hole and the blocking oxide film in the memory region of the memory system of the second embodiment.

[0018] Figure 12 This is a partially enlarged cross-sectional view showing an example of the cross-sectional structure of the memory hole and the blocking oxide film in the memory region of the memory system of the third embodiment. Detailed Implementation

[0019] Hereinafter, the semiconductor devices of various embodiments will be described in detail with reference to the accompanying drawings. The drawings are schematic and the dimensions and scales may not be identical to actual dimensions. Furthermore, the present invention is not limited to these embodiments.

[0020] In the following description, constituent elements having substantially the same function and structure are marked with the same symbols. In the following description, a first element being "connected" to another second element includes the first element being connected to the second element indirectly, or not directly, via an intermediate element that is always or selectively conductive.

[0021] "First Embodiment"

[0022] The semiconductor device of the first embodiment will be described. For example, a non-volatile semiconductor memory device (semiconductor memory) in which multiple memory cells are arranged in a three-dimensional direction.

[0023] 1.1 Composition

[0024] 1.1.1 Memory System

[0025] The semiconductor memory device of the first embodiment will be described. Figure 1 This is a block diagram illustrating an example of the configuration of the memory system according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host machine (not shown). The memory system 1 is, for example, an SD card. TM Memory cards such as Secure Digital Touch Memory Cards, UFS (Universal Flash Storage), or SSDs (Solid State Drives). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0026] The memory controller 2 is composed of an integrated circuit such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host machine. Specifically, the memory controller 2 writes data requested from the external host machine to the semiconductor memory device 3. Furthermore, the memory controller 2 reads data requested from the external host machine from the semiconductor memory device 3 and outputs it to the external host machine.

[0027] Semiconductor storage device 3 is, for example, a NAND (Not-AND) type flash memory that can store data non-volatilely.

[0028] Communication between the memory controller 2 and the semiconductor memory device 3 is based on, for example, an SDR (Single Data Rate) interface, a Toggle DDR (Double Data Rate) interface, or ONFI (Open NAND Flash Interface).

[0029] 1.1.2 Semiconductor memory devices

[0030] Next, refer to Figure 1The block diagram shown illustrates the internal configuration of the semiconductor memory device 3 according to the first embodiment. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequence generator 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.

[0031] The memory cell array 10 is a group of memory cell transistors and a collection of components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of non-volatile data storage. A block BLK is used, for example, as an erase unit when erasing data stored in the memory cell transistors. Furthermore, the memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0032] Input / output circuit 11 is an interface circuit responsible for sending and receiving input / output signals with memory controller 2. Input / output signals include, for example, data DAT, instruction CMD, address information ADD, and status information STA. Input / output circuit 11 inputs and outputs data DAT between sense amplifier module 17 and each of memory controller 2. Input / output circuit 11 outputs each of the instruction CMD and address information ADD transmitted from memory controller 2 to register 13. Input / output circuit 11 outputs the status information STA transmitted from register 13 to memory controller 2.

[0033] The logic control circuit 12 receives control signals from the memory controller 2. Based on these control signals, the logic control circuit 12 controls each of the input / output circuits 11 and the sequence generator 14. For example, the logic control circuit 12 notifies the input / output circuits 11 that the received input / output signal is an instruction (CMD) or address information (ADD), etc. The logic control circuit 12 commands the input / output circuits 11 to input or output the input / output signal. The logic control circuit 12 controls the sequence generator 14 to start the semiconductor memory device 3. Furthermore, the logic control circuit 12 outputs a signal indicating whether the semiconductor memory device 3 is in a ready or busy state to the memory controller 2.

[0034] Register 13 temporarily stores instruction CMD, address information ADD, and status information STA. Instruction CMD may contain commands that cause sequence generator 14 to perform read, write, or erase operations. Address information ADD may contain block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used to select block BLK, word line, and bit line, respectively. Status information STA is updated based on the control of sequence generator 14 and transmitted to input / output circuit 11.

[0035] The sequence generator 14 controls all operations of the semiconductor memory device 3. For example, based on the instruction CMD stored in the register 13, the sequence generator 14 controls the driver module 15, the line decoder module 16, and the sense amplifier module 17 to perform read operations, write operations, erase operations, etc.

[0036] Driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. Driver module 15 supplies the generated voltages to line decoder module 16 and sense amplifier module 17, etc. Furthermore, driver module 15 applies the generated voltages, for example, to signal lines corresponding to word lines selected based on page address PA stored in register 13.

[0037] The line decoder module 16 selects a corresponding block BLK within the memory cell array 10, for example, based on the block address BA stored in register 13. The line decoder module 16 transmits, for example, the voltage of the signal line applied by the driver module 15 to the selected word line within the selected block BLK.

[0038] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit lines, or a latch circuit for temporarily storing data. During a write operation, the sense amplifier module 17 applies a desired voltage to each bit line based on the write data DAT received from the input / output circuit 11. Furthermore, during a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Then, the sense amplifier module 17 transmits the determination result as read data DAT to the input / output circuit 11.

[0039] 1.1.3 Circuit configuration of memory cell array

[0040] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device 3 of the first embodiment. Figure 2 This represents a block (BLK). A block (BLK) may contain multiple string units (STRs) (e.g., four STR0 to STR3 units).

[0041] Each string cell STR contains multiple NAND strings NS associated with each bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains memory cell transistors MT0 to MTn and select transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section according to the voltage applied to the control gate via the word line WL, and non-volatilely stores the data.

[0042] The drain of the drain-side select transistor ST1 is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor ST1 is connected to any one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor ST1 is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor ST1 connects the NAND string NS to the bit line BL.

[0043] The drain of source-side selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of source-side selection transistor ST2 is connected to the source line SL. The control gate of source-side selection transistor ST2 is connected to any one of the source-side selection gate lines SGS0 to SGS3. When a specified voltage is applied to the source-side selection gate line SGS, source-side selection transistor ST2 connects the NAND string NS to the source line SL.

[0044] In addition, such as Figure 7 As shown, the source-side select gate line SGS0 can also be disconnected by the component SSE. In this case, it can be... Figure 7 The source-side select gate line SGS0 on the left and the source-side select gate line SGS0 on the right are connected to different power supplies and can be controlled independently.

[0045] Within the same block BLK, the control gates of memory cell transistors MT0 to MTn are commonly connected to their respective word lines WL0 to WLn. Within the same string cell STR, the control gate of drain-side select transistor ST1 is commonly connected to its corresponding drain-side select gate line SGD. The control gate of source-side select transistor ST2 is commonly connected to its corresponding source-side select gate line SGS. In the memory cell array 10, the bit line BL is shared by NAND strings NS in multiple string cells STR that are assigned the same column address.

[0046] Each word line WL0 to WLn is set per block BLK. The source line SL, for example, is shared among multiple block BLKs.

[0047] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string cell STR is called a cell group CU. For example, the storage capacity of a cell group CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, a cell group CU can have a storage capacity of 2 pages or more.

[0048] Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment is not limited to the description above. For example, the number of string cells STR included in each BLK can be designed to be arbitrary. However, the number of string cells STR included in each BLK is expected to be an even number. The number of memory cell transistors MT, and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to be arbitrary.

[0049] 1.1.4 Appearance of Semiconductor Memory Devices

[0050] The semiconductor memory device 3 of the first embodiment is formed by bonding two semiconductor circuit substrates, each on which a semiconductor circuit is formed, and then separating the bonded semiconductor circuit substrates according to each chip. That is, the semiconductor memory device 3 of the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is, for example, a silicon substrate.

[0051] The following description explains the removal of the semiconductor substrate W2 during the manufacturing process of the semiconductor memory device 3. Alternatively, depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may be retained after bonding.

[0052] Figure 3 This is a perspective view showing an example of the appearance of the semiconductor memory device according to the first embodiment. Figure 3 In the accompanying drawings, shading lines are added to improve visibility, but they are not necessarily related to the raw materials or characteristics of the constituent elements for which the shading lines are added. For example... Figure 3 As shown, the semiconductor memory device 3 has, for example, a structure in which a semiconductor substrate W1, a control circuit layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300 are sequentially stacked.

[0053] In the following description, the plane extending from the semiconductor substrate W1 is defined as the XY plane. The direction of the laminated structure from the semiconductor substrate W1 toward the wiring layer 300 is defined as the Z1 direction, and the direction from the wiring layer 300 toward the semiconductor substrate W1 is defined as the Z2 direction. Both the Z1 and Z2 directions are substantially perpendicular to the semiconductor substrate W1. Furthermore, without distinguishing between the Z1 and Z2 directions, each of the Z1 and Z2 directions is simply referred to as the Z direction. The Z direction is also called the first direction.

[0054] The control circuit layer 100 includes control circuitry formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., corresponding to the design of the control circuitry. The control circuit layer 100 includes, for example, an input / output circuitry 11, a logic control circuitry 12, a register 13, a sequence generator 14, a driver module 15, a line decoder module 16, and a sense amplifier module 17.

[0055] The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a control circuit disposed on the control circuit layer 100 to form part of a semiconductor circuit.

[0056] The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 disposed on the memory layer 200 to form part of a semiconductor circuit.

[0057] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2 (not shown).

[0058] Wiring layer 300 is formed after semiconductor substrates W1 and W2 are bonded together. Wiring layer 300 includes wiring or multiple solder pads PD for connection to semiconductor circuitry disposed on memory layer 200. Multiple solder pads PD are exposed on the surface of semiconductor memory device 3. Multiple solder pads PD are used for connection between semiconductor memory device 3 and memory controller 2, etc.

[0059] Figure 4 This is a perspective view showing the outline of the bonding structure of the semiconductor memory device according to the first embodiment. Figure 4 The bonding of semiconductor substrates W1 and W2 is explained.

[0060] like Figure 4As shown, the plurality of bonding pads BP1 in bonding layer B1 and the plurality of bonding pads BP2 in bonding layer B2 are interconnected. Thus, the control circuit disposed in the control circuit layer 100 and the memory cell array 10 disposed in the memory layer 200 are electrically connected to each other via bonding pads BP1 and BP2. The boundary portions between bonding layers B1 and B2 correspond to the boundary portions between the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2 (not shown).

[0061] 1.1.5 Construction of Storage Cell Array

[0062] Hereinafter, an example of the structure of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment will be described. In the following description, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction (first direction) is set as a direction orthogonal to the X direction and the Y direction. The Z direction is equivalent to the thickness direction of the semiconductor substrate W1. The planes extending along the X and Z directions are designated as the XZ plane. The planes extending along the Y and Z directions are designated as the YZ plane. In the top view, shaded lines are appropriately added to improve the visibility of the drawings. The shaded lines added in the top view are not necessarily related to the raw materials or characteristics of the constituent elements to which the shaded lines are added. In the cross-sectional view, the configuration is appropriately omitted to improve the visibility of the drawings.

[0063] 1.1.5.1 Summary

[0064] Figure 5 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment. Figure 5 In the diagram, the region corresponds to six blocks BLK0 to BLK5. The consecutive numbers used to distinguish the BLK blocks are numbered in ascending order from the top of the page. In the storage cell array 10, these are repeated, for example, in the Y direction. Figure 5 The layout shown. (As indicated) Figure 5 As shown, the memory cell array 10 includes multiple components SLT and multiple components SHE. The planar layout of the memory cell array 10 is, for example, divided into a memory region MA and a lead-out region HA in the X direction. The lead-out region HA is arranged adjacent to the memory region MA.

[0065] The lead-out area HA is the area used for the connection between the stacked wiring formed by stacking multiple wiring layers (such as word lines WL0 to WLn, and select gate lines SGS0, SGS1 and SGD) spaced apart from each other in the Z direction and the line decoder module 16.

[0066] Multiple component segments (SLTs) extend along the X direction and are arranged in the Y direction. Each component SLT traverses the memory region MA along the X direction at the boundary region between adjacent block BLKs. In other words, each region defined by the component SLT corresponds to one block BLK in the memory cell array 10. Each component SLT has, for example, a structure with embedded insulators and plate-like contacts. Each component SLT breaks the stacked wiring adjacent to it.

[0067] Multiple component SHEs are configured in memory region MA. Each component SHE corresponding to memory region MA is arranged traversing memory region MA in the X direction and aligned along the Y direction. The ends of each component SHE corresponding to memory region MA are contained in lead-out region HA. For example, in memory region MA, three component SHEs are respectively configured between adjacent components SLT in the Y direction. Each combination of regions separated by components SLT and SHE in memory region MA corresponds to one string cell STR in memory cell array 10. Each component SHE, for example, has a structure with an embedded insulator. Each component SHE breaks the select gate line SGD adjacent to the component SHE.

[0068] Furthermore, the planar layout of the memory cell array 10 included in the semiconductor memory device 3 of the first embodiment is not limited to the layout described above. For example, the number of components SHEs disposed between adjacent components SLTs can be designed to be any number. The number of string cells STRs formed between adjacent components SLTs can be varied based on the number of components SHEs disposed between adjacent components SLTs. In addition, the number of string cells STRs formed between adjacent components SLTs is expected to be an even number. That is, the number of components SHEs in one block BLK is expected to be an odd number.

[0069] The HA (Handout Area) contains multiple HP (Handout Sections). Each HP contains a connection point for the cabling layer in the stacked cabling process. The HPs are arranged along the Y-direction and configured per block BLK.

[0070] 1.1.5.2 Memory Region

[0071] (Floor plan layout)

[0072] Figure 6 This is a top view showing an example of the planar layout of the storage regions of the memory cell array included in the semiconductor memory device of the first embodiment. Additionally, in Figure 6 The image represents a typical construction within a block BLK in the memory region MA. For example... Figure 6As shown, in the memory region MA, the memory cell array 10 includes multiple pillars (memory pillars) MP, multiple contacts CV, and multiple bit lines BL. Furthermore, each component SLT includes contacts LI and spacers SP.

[0073] Each columnar MP functions as, for example, a NAND string NS. Multiple columnar MPs are arranged in a staggered pattern of 19 rows, for example, along the Y direction, in the region between two adjacent SLTs. Figure 6 In the example shown, each of the columnar columns MP in the 5th, 10th, and 15th rows from the top of the paper overlaps by one component SHE.

[0074] Multiple bit lines BL extend along the Y direction and are arranged along the X direction. Each bit line BL is configured to overlap with at least one columnar structure MP for each string unit STR. Figure 6 In the example shown, two bit lines BL are configured to overlap with one column MP. When multiple bit lines BL overlap with the column MP, one of the bit lines BL is electrically connected to the corresponding column MP via a contact CV. Alternatively, when only one bit line BL overlaps with the column MP, that bit line BL is electrically connected to the corresponding column MP via a contact CV.

[0075] For example, the contact CV between the pillar MP that contacts the component SHE and the corresponding bit line BL is omitted. In other words, the contact CV between the pillar MP that connects to the two different select gate lines SGD and the bit line BL is omitted. The number and arrangement of pillar MP or components SHE between adjacent components SLT are not limited. Figure 6 The configuration shown can be modified as appropriate. For example, the number of bit lines BL overlapping each column MP can be designed to be arbitrary.

[0076] The contact LI is a conductor extending in the XZ plane. The lower surface of the contact LI is connected to the source line SL (not shown). The spacer SP is an insulator disposed on the side of the contact LI. In other words, the spacer SP is disposed in connection with the contact LI in such a way that it clamps the contact LI in the Y direction.

[0077] (Cross-sectional structure)

[0078] Figure 7 This is an example of a cross-sectional structure of the memory region of the memory cell array included in the semiconductor memory device of the first embodiment, and along... Figure 6 A sectional view along line VII-VII. (See example...) Figure 7As shown, the memory cell array 10 also includes wiring layers 21-25, insulating layers 40-46, and components SSE. In the following description, the Z2 direction is sometimes described as upward and the Z1 direction as downward.

[0079] The stacked wiring included in the memory cell array 10 includes a wiring layer 22 corresponding to the select gate line SGS, a plurality of wiring layers 23 corresponding to word lines WL0 to WLn, and a wiring layer 24 corresponding to the select gate line SGD.

[0080] exist Figure 7 In the example shown, a 2-layer portion is provided corresponding to the wiring layer 22 of the selected gate line SGS.

[0081] In the following description, the select gate line SGS corresponding to the upper wiring layer 22 is referred to as the select gate line SGSa, and the select gate line SGS corresponding to the lower wiring layer 22 is referred to as the select gate line SGSb. Hereinafter, without distinguishing between select gate lines SGSa and SGSb, it will be simply referred to as the select gate line SGS. Each of the select gate lines SGSa and SGSb is connected to the gate of the select transistors ST2a and ST2b, respectively. The select transistors ST2a and ST2b function as a single select transistor ST2. Furthermore, the wiring layer 22 corresponding to the select gate line SGS can be one layer or three or more layers. Moreover, when the wiring layer 22 corresponding to the select gate line SGS is formed by multiple layers, each select transistor ST2a and ST2b can also be configured to function independently.

[0082] An insulating layer 41 is deposited above a semiconductor substrate (not shown), and a plurality of wiring layers 22 and a plurality of insulating layers 42 are alternately and sequentially deposited above it. Figure 7 In the example shown, two-layer wiring layers 22 and two-layer insulating layers 42 are alternately stacked. The wiring layers 22 are, for example, formed as plates extending along the X direction in the XY plane. Each wiring layer 22 serves as a select gate line SGSa and SGSb. Each wiring layer 22 contains, for example, tungsten (W) or molybdenum (Mo). Each of the insulating layers 41 and the plurality of insulating layers 42 contains, for example, silicon oxide (SiO).

[0083] Multiple wiring layers 23 and multiple insulating layers 43 are alternately deposited above the topmost insulating layer 42. Figure 7 In the example shown, n wiring layers 23 and (n-1) insulating layers 43 are alternately stacked. Each wiring layer 23 is, for example, formed as a plate extending along the X direction in the XY plane. Each wiring layer 23 is used sequentially as word lines WL0 to WLn, starting from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten. Each insulating layer 43 contains, for example, silicon oxide.

[0084] Above the topmost wiring layer 23, insulating layer 44, wiring layer 24, and insulating layer 45 are sequentially stacked. Wiring layer 24 is, for example, formed as a plate extending along the X direction in the XY plane. Wiring layer 24 is used as a select gate line (SGD). Wiring layer 24 contains, for example, tungsten. Insulator layers 44 and 45 contain, for example, silicon oxide.

[0085] A wiring layer 25 is deposited on top of an insulating layer 45. The wiring layer 25 is formed, for example, as a line extending along the Y direction. The wiring layer 25 is used as a bit line BL. In areas not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper.

[0086] Insulator layer 46 is deposited on top of wiring layer 25. Insulator layer 46 is a layer connected to bonding layer B2 and contains multiple wirings (not shown).

[0087] In the previous Figure 3 , Figure 4 Below the insulating layer 41 after the semiconductor substrate W2 has been removed (not shown in the diagram), a wiring layer 21 and an insulating layer 40 are sequentially disposed along the Z1 direction. The wiring layer 21 is, for example, formed as a plate extending along the X direction in the XY plane. The wiring layer 21 serves as a source line SL. The wiring layer 21, for example, contains phosphorus-doped silicon. Alternatively, it may be disposed below the insulating layer 40. Figure 3 The wiring layer 300 is shown. The wiring layer 300 includes a plurality of wirings not shown.

[0088] Each columnar element MP extends along the Z direction (first direction). The columnar elements MP penetrate the wiring layers 22-24 and the insulating layers 41-44.

[0089] exist Figure 7 In the example shown, the stacked structure of the wiring layer 23 and the insulating layer 43 near the insulating layer 40 side is referred to as the first stacked body 51. Moreover, it has a three-layer structure with the second stacked body 52 and the third stacked body 53 stacked on top of the first stacked body 51.

[0090] exist Figure 7 In the example shown, a three-layer structure with first to third stacked layers 51 to 53 is illustrated as an example of a stacked structure having multiple stacked layers. However, the number of stacked layers can also be any number of stacked layers, such as two or four or more.

[0091] The first stack 51 includes insulating layers 41 and 42 and wiring layers 22 stacked thereon, and also includes wiring layers 22 and insulating layers 43 stacked repeatedly above them.

[0092] The second stack 52 is stacked on top of the first stack 51 to form a structure of repeated stacked wiring layer 23 and insulating layer 43.

[0093] The third stack 53 is stacked on top of the second stack 52 and includes a structure of repeatedly stacked wiring layer 23 and insulating layer 43, and also includes insulating layer 44 and wiring layer 24.

[0094] exist Figure 7 In the example shown, the repeated laminated structure of wiring layer 23 and insulating layer 43 has a three-layer structure consisting of a first laminate 51, a second laminate 52, and a third laminate 53, each having a predetermined thickness from the insulating layer 42 side. Furthermore, the first laminate 51 has a first columnar member MP1 extending through it in the Z direction. The second laminate 52 has a second columnar member MP2 extending through it in the Z direction. The third laminate 53 has a third columnar member MP3 extending through it in the Z direction.

[0095] The first column MP1, the second column MP2, and the third column MP3 are connected in series along the Z direction to function as a single column (memory column) MP.

[0096] Each of the first to third columnar bodies MP1, MP2, and MP3, for example... Figure 9 As shown, the structure includes a core film 30, a semiconductor film 31, and a multilayer film 32. In each columnar structure MP, the core film 30 extends along the Z-direction. For example, the upper end of the core film 30 of the third columnar structure MP3 is located within the insulating layer 45, and the lower end of the core film 30 of the first columnar structure MP1 is located within the wiring layer 21. The core film 30 may contain an insulator such as silicon oxide. The semiconductor film 31 may cover the periphery of the core film 30. At the lower end of the first columnar structure MP1, a portion of the semiconductor film 31 contacts the wiring layer 21. The semiconductor film 31 may contain silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion of the semiconductor film 31 that contacts the wiring layer 21.

[0097] Figure 9 This shows an example of a cross-section of the columnar body MP included in the semiconductor memory device of the first embodiment. More specifically, Figure 9 This shows a cross-sectional structure of a columnar body MP in a layer containing wiring layer 23, parallel to the surface of a semiconductor substrate (not shown in the diagram). Figure 9 As shown, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a barrier insulating film 35.

[0098] In the cross-section including wiring layer 23, core film 30 is disposed, for example, at the center of columnar body MP. Semiconductor film 31 surrounds the sides of core film 30. Tunnel insulating film 33 surrounds the sides of semiconductor film 31. Charge storage film 34 surrounds the sides of tunnel insulating film 33. Barrier insulating film 35 surrounds the sides of charge storage film 34. Wiring layer 23 surrounds the sides of barrier insulating film 35.

[0099] In the columnar body MP, the core membrane 30, the semiconductor membrane 31, the tunnel insulating membrane 33, the charge storage membrane 34, and the barrier insulating membrane 35 are continuously connected from one end of the columnar body MP in the Z direction to the other end.

[0100] The semiconductor film 31, tunnel insulating film 33, charge storage film 34, and barrier insulating film 35 are formed to have a predetermined thickness in the XY direction (second direction), which intersects the Z direction (first direction). Therefore, in the second direction, the barrier insulating film 35 is disposed on multiple wiring layers 23 and multiple insulating layers 43. Similarly, in the second direction, the charge storage film 34 is disposed on the barrier insulating film 35. In the second direction, the tunnel insulating film 33 is disposed on the charge storage film 34. In the second direction, the semiconductor film 31 is disposed on the tunnel insulating film 33.

[0101] Semiconductor film 31 serves as a channel (current path) for memory cell transistors MT0 to MTn and selection transistors ST1 and ST2. Each of tunnel insulating film 33 and barrier insulating film 35 comprises, for example, silicon oxide. Charge storage film 34 has the function of storing charge and, for example, comprises silicon nitride (SiN). With this configuration, each pillar MP can function as a NAND string NS.

[0102] The first to third pillars MP1, MP2, and MP3 contain memory cells that are non-volatile semiconductor memory devices. The memory cells are, for example, charge-trap type memory cells.

[0103] The core membrane 30 functions as the region for forming channels.

[0104] Wiring layer 23 functions as the control gate of the memory cell.

[0105] The charge storage membrane 34 functions as a data storage layer for storing the charge injected from the core membrane 30.

[0106] In other words, a memory cell is formed at the intersection of the core film 30 and each wiring layer 23, in which the control gate surrounds the channel.

[0107] The barrier insulating film 35 is an insulating layer that prevents the charge accumulated in the charge storage film 34 from diffusing to the wiring layer 23. The barrier insulating film 35 is, for example, a silicon oxide layer.

[0108] The barrier insulating film 35 may be a multilayer structure with layers, and the layers contain a material having a dielectric constant higher than that of silicon oxide. Silicon nitride, for example, can be used as a high dielectric constant material.

[0109] In this embodiment, the cross-sectional areas (XY cross-sectional area, transverse cross-sectional area) along the XY plane of the first column MP1, the second column MP2, and the third column MP3 all gradually increase from their respective bottom to top. In other words, the cross-sectional area (XY cross-sectional area: transverse cross-sectional area) along the XY plane of the memory hole MH1 forming the first column MP1 gradually increases from bottom to top. That is, the memory hole MH1 has a portion where the inner diameter changes continuously from its bottom to top.

[0110] The first column MP1, the second column MP2, and the third column MP3, which are arranged to extend along the Z direction, are connected and function as a single column MP.

[0111] The first columnar body MP1 is formed in the first memory hole MH1 formed in the first stacked body 51. The second columnar body MP2 is formed in the second memory hole MH2 formed in the second stacked body 52. ​​The third columnar body MP3 is formed in the third memory hole MH3 formed in the third stacked body 53.

[0112] Therefore, the upper end of the first memory hole MH1 is connected to the lower end of the second memory hole MH2, making the two holes continuous. The upper end of the second memory hole MH2 is connected to the lower end of the third memory hole MH3, thus connecting the two holes.

[0113] The first stacked layer 51 has a first memory hole MH1 formed therein, and a first columnar body MP1 is housed within the first memory hole MH1. The second stacked layer 52 has a second memory hole MH2 formed therein, and a second columnar body MP2 is housed within the second memory hole MH2. The third stacked layer 53 has a third memory hole MH3 formed therein, and a third columnar body MP3 is housed within the third memory hole MH3.

[0114] exist Figure 8 The text is a brief record. Figure 7 The diagram shows the relative relationship between the stacked layers 51, 52, and 53 and the memory holes MH1, MH2, and MH3 that penetrate them along the Z direction. Furthermore, in... Figure 8 The diagram only shows the barrier insulating film 35 formed inside each memory hole MH1, MH2, and MH3. Figure 8 In the middle, the scale in the Z direction is set to the same as that in the middle. Figure 7 Different scales are used to depict the Z-axis lengths of memory holes MH1, MH2, and MH3 at reduced sizes. Therefore, in Figure 8 China and Israel can Figure 8 The degree indicated in the figure highlights the thickness variation of the barrier insulating film 35 in the Z direction.

[0115] like Figure 8 As shown, when the inner diameter of the hole at the upper end 35a of the first columnar body MP1 (the inner diameter at the Z2 direction end) is set to R1, and the thickness of the barrier insulating film 35 is set to d1, and the inner diameter of the portion of the first columnar body MP1 near the substrate is set to R2, and the thickness of the barrier insulating film 35 is set to d2, then d1 gradually increases relative to d2 from the Z2 direction along the Z1 direction. In other words, the thickness of the barrier insulating film 35 of the first columnar body MP1 is inversely related to the diameter of the first columnar body MP1. Or, conversely, the thickness of the barrier insulating film 35 of the first columnar body MP1 is inversely related to the inner diameter of the first memory hole MH1.

[0116] For example, in this embodiment, the thickness of the barrier insulating film 35 at the lower end of the first columnar body MP1 is more than 1 nm thicker than the thickness of the barrier insulating film 35 at the upper end of the first columnar body MP1. For example, in this embodiment, if the inner diameter of the lower end (minimum inner diameter position) of the first memory hole MH1 is compared with the inner diameter of the upper end (maximum inner diameter position), there is a difference of more than 10 nm. That is, the maximum inner diameter and the minimum inner diameter of the first memory hole MH1 have a difference of more than 10 nm.

[0117] Because the diameter of the upper end of the first memory hole MH1 is larger than that of the lower end of the second memory hole MH2, a peripheral step 54 is formed at the upper end of the first memory hole MH1 along the XY plane. The thickness of the protruding portion 35c of the barrier insulating film 35 formed along the inner surface of the peripheral step 54 is uniform. The protruding portion 35c connects the upper end of the barrier insulating film 35 of the first columnar body MP1 to the lower end of the barrier insulating film 35 of the second columnar body MP2. In the barrier insulating film 35, the thickness of the protruding portion 35c is smaller than the thickness of the upper end 35a of the barrier insulating film 35 on the first memory hole MH1 side.

[0118] For example, in this embodiment, the inner diameter of the upper end of the first memory hole MH1 is more than 10 nm larger than the inner diameter of the lower end of the second memory hole MH2. For example, the thickness of the barrier insulating film 35 located at the upper end of the first memory hole MH1 has a thickness difference of more than 1 nm from the thickness of the barrier insulating film 35 located at the lower end of the second memory hole MH2. For example, the thickness of the barrier insulating film 35 located at the lower end of the second memory hole MH2 is greater than the thickness of the barrier insulating film 35 located at the upper end of the first memory hole MH1.

[0119] In the blocking insulating film 35 of the second memory hole MH2, the upper end 35d located at the upper end (Z2 direction end) of the second column MP2 is the thinnest, gradually thickens from the Z2 direction along the Z1 direction, and the lower end 35e located at the lower end (Z1 direction end) of the second column MP2 is the thickest.

[0120] In other words, the thickness of the barrier insulating film 35 in the second column MP2 is inversely related to the diameter of the second column MP2. Or, conversely, the thickness of the barrier insulating film 35 in the second column MP2 is inversely related to the inner diameter of the second memory hole MH2.

[0121] For example, in this embodiment, the thickness of the barrier insulating film 35 at the lower end of the second columnar body MP2 is at least 1 nm thicker than the thickness of the barrier insulating film 35 at the upper end of the second columnar body MP2. For example, in this embodiment, if the inner diameter of the lower end of the second memory hole MH2 is compared with the inner diameter of the upper end, there is a difference of at least 10 nm. That is, the maximum inner diameter and the minimum inner diameter of the second memory hole MH2 differ by at least 10 nm.

[0122] Because the diameter of the upper end of the second memory hole MH2 is larger than that of the lower end of the third memory hole MH3, a peripheral step 54 is formed at the upper end of the second memory hole MH2 along the XY plane. The thickness of the protruding portion 35f of the barrier insulating film 35 formed along the inner surface of the peripheral step 54 is uniform. The protruding portion 35f connects the upper end of the barrier insulating film 35 of the second columnar body MP2 to the lower end of the barrier insulating film 35 of the third columnar body MP3. In the barrier insulating film 35, the thickness of the protruding portion 35f is smaller than the thickness of the upper end 35d of the barrier insulating film 35 on the second memory hole MH2 side.

[0123] In the blocking insulating film 35 of the third memory hole MH3, the upper end 35g located at the upper end (Z2 direction end) of the third column MP3 is the thinnest, gradually thickens from the Z2 direction along the Z1 direction, and is the thickest located at the lower end 35h located at the lower end (Z1 direction end) of the third column MP3.

[0124] In other words, the thickness of the barrier insulating film 35 in the third columnar body MP3 is inversely related to the diameter of the third columnar body MP3. Or, conversely, the thickness of the barrier insulating film 35 in the third columnar body MP3 is inversely related to the inner diameter of the third memory hole MH3.

[0125] For example, in this embodiment, the thickness of the barrier insulating film 35 at the lower end of the third columnar body MP3 is approximately 1 nm thicker than the thickness of the barrier insulating film 35 at the upper end of the second columnar body MP2. For example, in this embodiment, if the inner diameter of the lower end of the third memory hole MH3 is compared with the inner diameter of the upper end, there is a difference of 10 nm or more. That is, the maximum inner diameter and the minimum inner diameter of the third memory hole MH3 differ by 10 nm or more.

[0126] For example, in this embodiment, the inner diameter of the upper end of the second memory hole MH2 is more than 10 nm larger than the inner diameter of the lower end of the third memory hole MH3. For example, the thickness of the barrier insulating film 35 located at the upper end of the second memory hole MH2 has a thickness difference of more than 1 nm compared with the thickness of the barrier insulating film located at the lower end of the third memory hole MH3. For example, the thickness of the barrier insulating film 35 located at the lower end of the third memory hole MH3 is greater than the thickness of the barrier insulating film 35 located at the upper end of the second memory hole MH2.

[0127] The thickness of the barrier insulating film 35 formed in the first columnar body MP1, the second columnar body MP2, and the third columnar body MP3 has been explained above. In contrast, the tunnel insulating film 33 and the charge storage film 34 in each columnar body MP may also have the same film thickness relationship.

[0128] Alternatively, the total film thickness of the barrier insulating film 35 and the tunnel insulating film 33 may also be the same as the film thickness relationship explained in the comparison of the barrier insulating films 35. The total film thickness of the barrier insulating film 35 and the charge storage film 34 may also be the same as the film thickness relationship explained in the comparison of the barrier insulating films 35. The total film thickness of the tunnel insulating film 33 and the charge storage film 34 may also be the same as the film thickness relationship explained in the comparison of the barrier insulating films 35. The total film thickness of the barrier insulating film 35, the tunnel insulating film 33, and the charge storage film 34 may also be the same as the film thickness relationship explained in the comparison of the barrier insulating films 35.

[0129] For example, in the tunnel insulating film 33 of the first columnar body MP1, the upper end (Z2 direction end) of the first columnar body MP1 is the thinnest, gradually thickening from the Z2 direction along the Z1 direction, and the lower end (Z1 direction end) of the first columnar body MP1 is the thickest. The tunnel insulating films 33 formed in the second columnar body MP2 and the third columnar body MP3 also have the same film thickness relationship.

[0130] For example, in the charge accumulation film 34 of the first columnar body MP1, the upper end (Z2 direction end) of the first columnar body MP1 is the thinnest, gradually thickening from the Z2 direction along the Z1 direction, and the lower end (Z1 direction end) of the first columnar body MP1 is the thickest. The charge accumulation films 34 formed in the second columnar body MP2 and the third columnar body MP3 also have the same film thickness relationship.

[0131] and, Figure 7 , Figure 8 The relationship between the thickness of the first memory hole MH1, the second memory hole MH2, and the barrier insulating film 35 can be described as follows.

[0132] The first memory hole (one memory hole) MH1 and the second memory hole (another memory hole) MH2 are adjacent in the Z direction (first direction). The first memory hole MH1 is located close to the semiconductor substrate W1, and the second memory hole MH2 is located away from the semiconductor substrate W1. Furthermore, at the junction of the first memory hole MH1 and the second memory hole MH2, there is a portion where the inner diameter of the first memory hole MH1 and the second memory hole MH2 changes discontinuously.

[0133] A barrier insulating film 35 with the aforementioned film thickness relationship is formed in the first memory hole MH1 and the second memory hole MH2.

[0134] In a comparison of the positions where the inner diameters of memory holes MH1 and MH2 are smaller and larger, the insulating film 35 has a larger film thickness at the positions where the inner diameters of memory holes MH1 and MH2 are smaller.

[0135] For example, at the connection point between the first memory hole MH1 and the second memory hole MH2, the difference between the maximum inner diameter of the first memory hole MH1 and the minimum inner diameter of the second memory hole MH2 can be set to more than 10 nm.

[0136] For example, the difference between the thickness of the barrier insulating film 35 formed at the maximum inner diameter position of the first memory hole MH1 and the thickness of the barrier insulating film 35 formed at the minimum inner diameter position of the second memory hole MH2 can be set to 1 nm or more.

[0137] For example, the relationship can also be set in the same way in the relationship between the second memory hole MH2 and the third memory hole MH3 and the film thickness of the blocking insulating film 35.

[0138] For example, the relationship is not only applied to the barrier insulating film 35, but can also be applied to at least one or more of the barrier insulating film 35, charge storage film 34 and tunnel insulating film 33 as described above.

[0139] exist Figure 7 In the columnar structure MP shown, the portion of wiring layer 22 that intersects with columnar structure MP1 functions as selection transistor ST2. The portions of columnar structures MP1 to MP3 that intersect with each wiring layer 23 function as memory cell transistors MT0 to MTn, respectively. The portion of wiring layer 24 that intersects with columnar structure MP3 functions as selection transistor ST1.

[0140] A columnar contact CV is formed on the upper surface of the semiconductor film 31 within the columnar body MP. Figure 7 The area shown displays two contact points CV corresponding to two of the six columnar bodies MP. Within this area, columnar bodies MP that do not overlap with component SHE and are not connected to contact points CV are connected to other contact points CV in areas not shown.

[0141] One wiring layer 25, i.e., one bit line BL, contacts the upper surface of each contact CV. In one wiring layer 25, one contact CV is connected to each space defined by components SLT and SHE. That is, in each wiring layer 25, for example, one column MP in each region between adjacent components SLT and SHE, and one column MP in each region between two adjacent components SHE.

[0142] Component SLT is formed, for example, to extend along the XZ plane. Each component SLT has through wiring layers 22-24 and insulating layers 41-44. For example, the width of each component SLT in the Y direction increases from bottom to top.

[0143] Within component SLT, the contact LI is configured to extend along the XZ plane, and the spacer SP is disposed between the contact LI and wiring layers 22-24 and insulating layers 41-45. The upper end of the contact LI is located, for example, within insulating layer 45. The lower end of the contact LI is connected, for example, to wiring layer 21. Alternatively, the contact LI may be omitted depending on the configuration of the memory cell array 10.

[0144] Component SHE is formed, for example, as a plate extending along the XZ plane, dividing wiring layer 24. The upper end of component SHE is located within insulating layer 45. The lower end of component SHE is located, for example, within the uppermost insulating layer 43. Component SHE includes, for example, an insulator such as silicon oxide. Furthermore, the upper end of component SHE may or may not be aligned with the upper end of component SLT. Additionally, the upper end of component SHE may or may not be aligned with the upper end of columnar body MP.

[0145] Component SSE is formed, for example, in memory regions MA1 and MA2 as a plate extending along the XZ plane, dividing multiple wiring layers 22. For example, the upper end of component SSE may be located at the boundary between the uppermost insulating layer 42 and the lowermost wiring layer 23, or it may be located inside the uppermost insulating layer 42. For example, the lower end of component SSE may be located at the boundary between wiring layer 21 and insulating layer 41, or it may be located inside the insulating layer 41. Component SSE is preferably disposed in memory regions MA1 and MA2 at a position overlapping with one component SHE in the Z direction. Component SSE includes, for example, an insulator such as silicon oxide. Furthermore, the lower end of component SSE may or may not be aligned with the lower end of component SLT.

[0146] 1.2 Effects of the first embodiment

[0147] According to the first embodiment, the thickness of the barrier insulating film 35 in the first columnar body MP1 is inversely related to the diameter of the first columnar body MP1.

[0148] The concentration of the electric field acting on the barrier insulating film 35 differs between the larger and smaller diameter portions of the first column MP1. The electric field concentration is lower in the larger diameter portion of the first column MP1 and higher in the smaller diameter portion. Therefore, the concentration of the electric field acting on the barrier insulating film 35 differs between the larger and smaller diameter portions of the first column MP1. For example, writing is easier in the portion with higher electric field concentration and more difficult in the portion with lower electric field concentration.

[0149] In the construction of the first embodiment, as follows: Figure 8 As explained, the barrier insulating film 35 is thicker in the portion where the diameter of the first columnar body MP1 is smaller and the electric field concentration is higher, and thinner in the portion where the diameter of the first columnar body MP1 is larger and the electric field concentration is lower. When the barrier insulating film 35 is thicker, the electric field can be mitigated by the presence of a thicker barrier insulating film 35. Therefore, writing in the region where the diameter of the first columnar body MP1 is smaller and the electric field concentration is higher can be slowed down. As a result, the writing conditions can be consistent with those in the region where the diameter of the first columnar body MP1 is larger and the electric field concentration is lower. Therefore, the problem of inconsistent data writing to the memory based on the diameter of the first columnar body MP1 can be solved. In other words, the uniformity of the write voltage in the memory cell array 10 can be promoted.

[0150] The effect is not limited to the first column MP1, but can also be obtained in the second column MP2 and the third column MP3, which have the same structure as the first column MP1.

[0151] Therefore, the same effect can be obtained in the entire memory cell array 10, which is equipped with columnar MP.

[0152] Furthermore, in current semiconductor memory devices, when reading data from memory, a predetermined voltage lower than the write voltage is applied for data reading. In this case, even if the read voltage is lower than the write voltage, a small amount of writing may still occur. Depending on the diameter of the columnar mass MP, the likelihood of a small amount of writing increases when the electric field concentration is higher in the smaller diameter portion.

[0153] In this regard, the electric field strength can be adjusted according to the thickness of the insulating barrier 35 in the configuration of the first column MP1, the second column MP2, and the third column MP3. Therefore, the problem of minor invalid writes that may occur during reading can also be reduced.

[0154] Furthermore, in current semiconductor memory devices, a stack with 100 or more layers of wiring layer 23 and insulating layer 43 has been implemented.

[0155] When forming memory holes (MH) in such a stacked structure, the number of stacked layers that can be applied is limited. Therefore, currently, as... Figure 7 As shown, a multilayer structure is adopted, which consists of a first stacked layer 51, a second stacked layer 52, and a third stacked layer 53, or a structure with more stacked layers. Furthermore, a first memory hole MH1 is formed after the first stacked layer 51 is formed, a second memory hole MH2 is formed after the second stacked layer 52 is formed, and a third memory hole MH3 is formed after the third stacked layer 53 is formed, thereby achieving multilayering.

[0156] If this thicker multilayer structure is etched to form memory holes MH, then depending on the different processing times on the bottom and top sides of the multilayer or the characteristics of the etchant, holes with smaller inner diameters on the bottom side and larger inner diameters on the top side will inevitably be formed. Therefore, the first to third columnar bodies MP1, MP2, and MP3 formed in the first to third multilayers 51, 52, and 53 also become... Figure 8 The illustrated cross-sectional shape.

[0157] Therefore, if the structure of this embodiment is adopted, the uniformity of the write voltage can be promoted even in a multilayered stacked structure.

[0158] Furthermore, the effects of setting the thickness of the barrier insulating film 35 to the inverse correlation described above have been explained in the above description. However, this is not limited to the barrier insulating film 35; the thicknesses of the tunnel insulating film 33 and the charge storage film 34 can also be set to the inverse correlation as described. By setting the thicknesses of the tunnel insulating film 33 and the charge storage film 34 to the inverse correlation, the same effect can be obtained.

[0159] Furthermore, in the embodiments described above, an example of applying this embodiment to a stacked structure in which three stacked bodies are overlapped has been described, but the number of stacked bodies may also be two or four or more, and there is no limitation on the number of stacked bodies.

[0160] 1.3 Regarding barrier insulating film

[0161] Figure 10A This shows an example shape of a memory hole MH0 formed in part of a stacked body. Figure 10A The memory hole MH0 shown corresponds to Figure 9 The memory hole MH is shown, and is represented as a cross-section of a portion of the wiring layer 23.

[0162] The cross-sectional profile of the memory hole MH0 is not a circle, but rather a shape with a deviated radius of curvature. Such memory holes MH0 with deviated radii of curvature are sometimes found in memory cells with microstructures having an inner diameter of tens of nanometers.

[0163] When a barrier insulating film is formed on the inner surface of the memory hole MH0, such as Figure 10B As shown, a thick film 55 of material constituting a barrier insulating film is pre-formed. Then, the thick film 55 is thinned to form... Figure 10C The target film thickness of the barrier insulating film 56 is shown.

[0164] In this case, the barrier insulating film 56 is formed in such a way that the deviation of the radius of curvature on the inner peripheral side in the cross-sectional profile of the barrier insulating film 56 is smaller than the deviation of the radius of curvature shown in the cross-sectional profile of the memory hole MH0 formed in the wiring layer 23 of the laminate.

[0165] Thus, the preferred configuration is the barrier insulating film 56 where the deviation of the radius of curvature on the inner circumference side is small, as described below. For example, through thinning processing, the portion of the outer circumference contour of the barrier insulating film 56 with a smaller radius of curvature (in...) Figure 10C The film thickness is retained at the location indicated by the symbol 'a'. Furthermore, the portion with a larger radius of curvature of the outer periphery of the blocking insulating film 56 (in...) Figure 10C The film thickness (represented by the symbol b) is reduced (curvature deviation is decreased). This allows for a more uniform application of the electric field to the channel (in the XY direction and circumferential direction), making it a preferred configuration.

[0166] Furthermore, the thinning process after thick film formation is not limited to the barrier insulating film 56, but can also be applied to either the tunnel insulating film 33 or the charge storage film 34 used in the structure of the first embodiment.

[0167] Therefore, by applying thinning processing, either the tunnel insulating film 33 or the charge storage film 34 can reduce curvature deviation in the same way as described above. As a result, the manner in which an electric field is applied to the channel can be homogenized.

[0168] Therefore, by thinning the film after its formation, deviations in the radius of curvature of at least one of the inner circumferences of the tunnel insulating film 33, the charge storage film 34, and the barrier insulating film 56 can be suppressed. This allows for the homogenization of the manner in which an electric field is applied to the channel.

[0169] 2. Second Implementation Method

[0170] Next, refer to Figure 11 The semiconductor memory device of the second embodiment is described.

[0171] In the semiconductor memory device of the second embodiment, the shapes of the memory holes formed in the first stacked layer 51, the second stacked layer 52 and the third stacked layer 53 of the first embodiment are different, and the shapes of the columnar bodies formed in the memory holes are different.

[0172] Regarding other structures, since they are the same as those in the first embodiment, the structures of the memory hole and the column will be described below.

[0173] In the second embodiment, such as Figure 11 As shown, a first memory hole MH4 is formed in a first laminate 51 with the same structure as in the first embodiment, a second memory hole MH5 is formed in a second laminate 52, and a third memory hole MH6 is formed in a third laminate 53. The structure in which a first columnar body is formed inside the first memory hole MH4, a second columnar body is formed inside the second memory hole MH5, and a third columnar body is formed inside the third memory hole MH6 is also the same as in the first embodiment.

[0174] Figure 11 Corresponding to Figure 8 The scale of the barrier insulating film formed inside each memory hole is changed for emphasis. In the columnar body of the second embodiment, the structure of the columnar body formed by stacking the barrier insulating film, charge storage film, tunnel insulating film, semiconductor film and core film is also the same as that of the first embodiment.

[0175] In the second embodiment, the shape of the first memory hole MH4 formed on the first stacked body 51 is the same as the shape of the first memory hole MH1 formed on the first stacked body 51 in the first embodiment. Therefore, the shape of the barrier insulating film 35 formed along the inner surface of the first memory hole MH4 is the same as the barrier insulating film 35 in the first embodiment.

[0176] In the second embodiment, the cross-sectional area (XY cross-sectional area) of the second memory hole MH5 gradually increases from bottom to top along the XY plane from its upper side to its lower side. However, in the second memory hole MH5, a connecting portion 60 is formed at the bottom, and the connecting portion 60 gradually increases from its upper side to its lower side along the XY plane (XY cross-sectional area).

[0177] Due to the shape of the second memory hole MH5, when the inner diameter of the upper side of the second memory hole MH5 is set to R3 and the thickness of the second barrier insulating film 62A is set to d3, and the inner diameter of the lower side of the second memory hole MH5 is set to R4 and the thickness of the second barrier insulating film 62A is set to d4, d4 gradually increases relative to d3 as it moves from the upper side to the lower side. Furthermore, the thickness of the bottom barrier insulating film 62B formed on the connecting portion 60 gradually decreases as it approaches the first memory hole MH1. The thickness is thickest at the junction of the second barrier insulating film 62A and the bottom barrier insulating film 62B. The second barrier insulating film 62A is formed to gradually thin as it moves upward, and the bottom barrier insulating film 62B is formed to gradually thin as it moves downward.

[0178] In the second embodiment, the structure of the third memory hole MH6 is the same as that of the second memory hole MH5. That is, the thickness of the third barrier insulating film 63A, which is formed from the upper side to the lower side of the third memory hole MH6, gradually increases as it moves from the upper side to the lower side. Furthermore, the thickness of the bottom barrier insulating film 62B formed on the connecting portion 63 gradually decreases as it approaches the second memory hole MH5. The thickness is greatest at the junction of the third barrier insulating film 63A and the bottom barrier insulating film 63B, with the third barrier insulating film 63A gradually thinning as it moves upward and the bottom barrier insulating film 63B gradually thinning as it moves downward.

[0179] In the construction of the second embodiment, the thickness of the barrier insulating film 35 is also approximately inversely related to the diameter of the first columnar body MP1.

[0180] like Figure 11 As indicated, the barrier insulating film 35 of the portion of the first columnar body MP1 with a smaller diameter and a higher electric field concentration is made thicker, while the barrier insulating film 35 of the portion of the first columnar body MP1 with a larger diameter and a lower electric field concentration is made thinner.

[0181] Therefore, writing in regions where the diameter of the first column MP1 is small and the electric field concentration is high can be reduced. This allows for writing conditions to be consistent with those in regions where the diameter of the first column MP1 is large and the electric field concentration is low. Therefore, the problem of inconsistent data writing to the memory based on the diameter of the first column MP1 can be resolved.

[0182] The same effect can be obtained in the second column MP5, which has the same structure as the first column MP4, and in the third column MP6, which has the same structure as the first column MP4.

[0183] Therefore, in the second embodiment, the same effect as in the first embodiment can be obtained in the entire storage cell array 10 provided with columnar bodies MP.

[0184] 3. Third Implementation Method

[0185] Next, refer to Figure 12 The semiconductor memory device of the third embodiment is described.

[0186] In the semiconductor memory device of the third embodiment, the shapes of the memory holes formed in the first stacked layer 51, the second stacked layer 52 and the third stacked layer 53 of the first embodiment are different, and the shapes of the columnar bodies formed in the memory holes are different.

[0187] Regarding other structures, since they are the same as those in the first embodiment, the structures of the memory hole and the column will be described below.

[0188] In the third embodiment, such as Figure 12 As shown, a first memory hole MH7 is formed in a first laminate 51 with the same structure as in the first embodiment, a second memory hole MH8 is formed in a second laminate 52, and a third memory hole MH9 is formed in a third laminate 53. The structure in which a first columnar body is formed inside the first memory hole MH7, a second columnar body is formed inside the second memory hole MH8, and a third columnar body is formed inside the third memory hole MH9 is also the same as in the first embodiment.

[0189] Figure 12 In, corresponding to Figure 8 Only the barrier insulating film formed inside each memory hole is shown. In the columnar body of the third embodiment, the structure of the columnar body formed by stacking the barrier insulating film, charge storage film, tunnel insulating film, semiconductor film and core film is also the same as that of the first embodiment.

[0190] In the third embodiment, the shape of the first memory hole MH7 formed on the first stacked body 51 is the same as the shape of the first memory hole MH1 formed on the first stacked body 51 in the first embodiment. Therefore, the shape of the barrier insulating film 35 formed along the inner surface of the first memory hole MH7 is the same as the barrier insulating film 35 in the first embodiment.

[0191] In the third embodiment, the inner diameter of the upper end of the second memory hole MH8 is set to R5, the thickness of the barrier insulating film 64B is set to d5, the inner diameter of the lower end is set to R6, and the thickness of the barrier insulating film 64A is set to d6. In this case, as the diameter decreases from top to bottom, d5 is smaller than d6, and the cross-sectional area (XY cross-sectional area) along the XY plane gradually decreases from top to bottom. However, a connecting portion 67 is formed at the top of the second memory hole MH8. Furthermore, the connecting portion 67 has a shape where the cross-sectional area (XY cross-sectional area) gradually decreases from its bottom to top along the XY plane.

[0192] The second memory hole MH8 has the aforementioned shape. According to this relationship, the thickness of the second barrier insulating film 64A, formed from the bottom to near the top of the second memory hole MH8, gradually decreases as it moves upwards from the bottom of the second memory hole MH8. Furthermore, the thickness of the top barrier insulating film 64B formed on the connecting portion 67 gradually increases as it approaches the third memory hole MH9. The thickness is thinnest at the junction of the second barrier insulating film 64A and the top barrier insulating film 64B, which is formed to gradually thicken upwards.

[0193] In the third embodiment, the cross-sectional area (XY cross-sectional area) of the third memory hole MH9 gradually increases from bottom to top along the XY plane. However, in the third memory hole MH9, a connecting portion 67 is formed at the top, and the connecting portion 67 has a shape in which the cross-sectional area (XY cross-sectional area) gradually decreases from its lower side to its upper side.

[0194] The third memory hole MH9 has the aforementioned shape. According to this relationship, the thickness of the third barrier insulating film 65A, formed from the bottom of the third memory hole MH9 to near the top, gradually decreases as it moves upwards from the bottom of the third memory hole MH9. Furthermore, the thickness of the top barrier insulating film 65B formed on the connecting portion 67 gradually increases as it approaches the top. The thickness is thinnest at the junction of the third barrier insulating film 65A and the top barrier insulating film 65B, which is formed to gradually thicken upwards.

[0195] In the third embodiment, the thickness of the barrier insulating film 35 is also approximately the same as in the first and second embodiments, and is inversely related to the size of the inner diameter of the memory hole MH7.

[0196] As from Figure 12 As envisioned, the blocking insulating film 35 is thicker in the portion of the first column MP7 with a smaller diameter and higher electric field concentration, and thinner in the portion of the first column MP with a larger diameter and lower electric field concentration.

[0197] Therefore, writing in the region where the inner diameter of the first memory hole MH7 decreases and the electric field concentration increases can be reduced. This allows for writing conditions to be consistent with those in the region where the diameter of the first memory hole MH7 increases and the electric field concentration decreases. Therefore, the problem of inconsistent data writing to the memory based on the diameter of the first column can be resolved.

[0198] The same effect can be obtained in the second column MP8, which is inversely correlated with the size indication of the inner diameter of the second memory hole MH8. Furthermore, the same effect can be obtained in the third column MP9, which is inversely correlated with the size indication of the inner diameter of the third memory hole MH9.

[0199] Therefore, it is possible to use in the settings Figure 12 The entire columnar MP storage cell array 10 of the shown structure achieves the same effect as in the first embodiment.

[0200] While embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and similarly, are included within the scope of the invention as described in the claims and its equivalents.

[0201] [Explanation of Symbols]

[0202] 1. Memory System

[0203] 3 Semiconductor memory devices

[0204] 10-cell array

[0205] 23 Wiring Layer

[0206] 31 Semiconductor film

[0207] 33 Tunnel insulation film

[0208] 34 Charge storage membrane

[0209] 35 Barrier Insulating Film

[0210] 43, 44, 45, 46 Insulating layers

[0211] 51 First layered body

[0212] 52 Second layered body

[0213] 53 Third layered body

[0214] 62A Barrier Insulating Film

[0215] 62B Bottom Barrier Insulating Film

[0216] 63 Connecting part

[0217] 63A Barrier Insulating Film

[0218] 63B Bottom Barrier Insulating Film

[0219] 64A Second Barrier Insulating Film

[0220] 64B Top Barrier Insulating Film

[0221] 67 Connecting part

[0222] 65A Third Barrier Insulating Film

[0223] 65B Top Barrier Insulation Film

[0224] BL bitline

[0225] BLK block

[0226] MH memory hole

[0227] MH1, MH4, MH7 First memory hole

[0228] MH2, MH5, MH8 Second memory hole

[0229] MH3, MH6, MH9 3rd memory hole

[0230] MP columnar body

[0231] MP1 First column

[0232] MP2 Second column

[0233] MP3 Third column

[0234] MP4 First column

[0235] MP5 Second column

[0236] MP6 Third column

[0237] MP7 1st column

[0238] MP8 Second column

[0239] MP9 Third column

[0240] MT, MT0~MTn memory cell transistors

[0241] W1 semiconductor substrate

[0242] WL, WL0~WLn character lines.

Claims

1. A semiconductor device comprising: The first stacked body has a plurality of first wiring layers and a plurality of first insulating layers alternately stacked along a first direction, and forms a first aperture, the first aperture having a portion whose inner diameter varies along the first direction extending in the first direction; and The first column extends in the first hole along the first direction and has, in a second direction perpendicular to the first direction, a first semiconductor film, a first tunnel insulating film disposed on the outside of the first semiconductor film, a first charge storage film disposed on the outside of the first tunnel insulating film, and a first barrier insulating film disposed between the first charge storage film and the plurality of first wiring layers and the plurality of first insulating layers, starting from the inside of the first hole. and In the second direction, at least one of the following film thicknesses is... When the inner diameter of the first hole is the first inner diameter, the first film thickness is set. When the inner diameter of the first hole is the second inner diameter, the second film thickness is set. When the first inner diameter is greater than the second inner diameter, the first film thickness is less than the second film thickness.

2. The semiconductor device according to claim 1, wherein The difference between the first inner diameter and the second inner diameter of the first aperture is greater than 10 nm, and the difference between the first film thickness and the second film thickness of the first aperture is greater than 1 nm.

3. The semiconductor device according to claim 1, wherein The first film thickness and the second film thickness are the film thicknesses of the first barrier insulating film.

4. The semiconductor device according to claim 1, wherein The first film thickness and the second film thickness are the film thicknesses of the first tunnel insulating film.

5. The semiconductor device according to claim 1, wherein The first film thickness and the second film thickness are the film thicknesses of the first charge storage film.

6. The semiconductor device according to claim 1, wherein The first barrier insulating film, the first charge storage film, the first tunnel insulating film, and the first semiconductor film are continuously formed from one end of the first stack in the first direction to the other end in the first direction.

7. The semiconductor device according to claim 1, wherein The deviation of the radius of curvature relative to the cross-sectional profile of the first hole The deviation of the radius of curvature of the inner periphery of the cross-sectional profile of the first barrier insulating film, The deviation of the radius of curvature of the inner periphery of the cross-sectional profile of the first charge storage film, and At least one of the deviations in the radius of curvature of the inner circumference of the cross-sectional profile of the first tunnel insulating film is relatively small.

8. The semiconductor device according to claim 1, wherein In the first stacked body, As it moves from one end of the first direction toward the other end of the first direction, The inner diameter of the first hole gradually increases. The thickness of the first barrier insulating film gradually decreases.

9. The semiconductor device according to claim 1, comprising: The second laminate is disposed above the first laminate in the first direction, and A second via is formed by alternately stacking a plurality of second wiring layers and a plurality of second insulating layers along the first direction, the second via having a portion whose inner diameter varies along the first direction extending in the first direction; and A second columnar body extends in the second hole along the first direction, and in the second direction, starting from the inside of the second hole, has a second semiconductor film, a second tunnel insulating film disposed on the outside of the second semiconductor film, a second charge storage film disposed on the outside of the second tunnel insulating film, and a second barrier insulating film disposed between the second charge storage film and the plurality of second wiring layers and the plurality of second insulating layers; and The inner diameter of the upper end of the first hole is larger than the inner diameter of the lower end of the second hole.

10. The semiconductor device of claim 9, wherein In the second direction, at least one of the following film thicknesses is... When the inner diameter of the second hole is the third inner diameter, the third film thickness is set. When the inner diameter of the second hole is the fourth inner diameter, and the film thickness is set to the fourth thickness, When the third inner diameter is greater than the fourth inner diameter, the third film thickness is less than the fourth film thickness.

11. The semiconductor device of claim 10, wherein The third film thickness and the fourth film thickness are the film thicknesses of the second barrier insulating film.

12. The semiconductor device of claim 10, wherein The third film thickness and the fourth film thickness are the film thicknesses of the second tunnel insulating film.

13. The semiconductor device of claim 10, wherein The third film thickness and the fourth film thickness are the film thicknesses of the second charge storage film.

14. The semiconductor device of claim 9, wherein The second hole has a portion whose inner diameter increases and a portion whose inner diameter decreases as it moves from the lower end of the second hole toward the upper end.

15. The semiconductor device of claim 9, wherein the inner diameter of the upper end of the first hole is at least 10 nm larger than the inner diameter of the lower end of the second hole.

16. The semiconductor device of claim 9, wherein The thickness of the insulating film at the lower end of the second hole is more than 1 nm greater than the thickness of the film at the upper end of the first hole.

17. The semiconductor device of claim 9, wherein The first column has a protruding portion at its upper end.

18. The semiconductor device of claim 17, wherein The protruding portion connects the upper end of the first barrier insulating film of the first columnar body to the lower end of the second barrier insulating film of the second columnar body.

19. The semiconductor device of claim 9, wherein In the first direction, a source electrode line is formed below the first column and a placement line is formed above the second column.

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