Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device can sufficiently bury a via contact and suppress an increase in wiring resistance. The semiconductor device of the present embodiment includes a first wiring and a second wiring provided along a first direction of the first wiring. A first contact electrically connects between the first wiring and the second wiring. A third wiring is provided along a second direction of the second wiring, and has a width in the second direction that is narrower than the second wiring and the first contact. The first contact is composed of a first conductive material. The second and third wirings are composed of a second conductive material having a lower resistance than the first conductive material.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As via contacts in semiconductor devices become miniaturized, their aspect ratio increases. During the via contact formation process, the film deposition step continuously reduces temperature to ensure conductor coverage. In this case, narrower linewidth wiring may be embedded in the conductor formed by the low-temperature film deposition, similar to the via contact, resulting in high resistance in that wiring. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device can fully embed via contacts and suppress the rise of wiring resistance.

[0004] The semiconductor device of this embodiment includes a first wiring and a second wiring disposed along a first direction of the first wiring. A first contact electrically connects the first wiring and the second wiring. A third wiring is narrower than the second wiring and the first contact in a second direction intersecting the first direction, and is disposed along a second direction of the second wiring. The first contact is made of a first conductive material. The second and third wirings are made of a second conductive material with a lower resistance than the first conductive material. Attached Figure Description

[0005] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0006] Figure 2 This is a schematic top view representing a laminated volume.

[0007] Figure 3 This is a schematic cross-sectional view illustrating a three-dimensional storage unit.

[0008] Figure 4 This is a schematic cross-sectional view illustrating a three-dimensional storage unit.

[0009] Figure 5 This is a cross-sectional view showing an example of the configuration of the wiring portion of the array chip in the first embodiment.

[0010] Figure 6 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 7 It means succession Figure 6 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0012] Figure 8 It means succession Figure 7A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0013] Figure 9 It means succession Figure 8 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0014] Figure 10 It means succession Figure 9 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0015] Figure 11 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the second embodiment.

[0016] Figure 12 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0017] Figure 13 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the third embodiment.

[0018] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic diagrams or conceptual diagrams. In the specification and drawings, the same elements are labeled with the same symbols.

[0020] (First Embodiment)

[0021] Figure 1 This is a cross-sectional view showing an example configuration of the semiconductor device according to the first embodiment. In this embodiment, the semiconductor device 1 is, for example, a NAND flash memory. However, this embodiment is not limited to NAND flash memory and can also be applied to other memory or semiconductor devices.

[0022] Hereinafter, the lamination direction of the laminate 20 is defined as the Z direction. A direction intersecting the Z direction, for example, or orthogonal to it, is defined as the Y direction. A direction intersecting both the Z and Y directions, for example, or orthogonal to it, is defined as the X direction. Furthermore, in this specification, the Z direction is an example of the first direction. The X direction is an example of the third direction, and the Y direction is an example of the second direction. Figure 1 The instructions state that the +Z direction is set to upwards, but... Figure 2 The following instructions will set the -Z direction to upward.

[0023] Semiconductor device 1 includes an array chip 2 having an array of memory cells and a CMOS chip 3 having CMOS circuitry. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1 and are electrically connected to each other via wiring joined at the bonding surface. Figure 1 The image shows the state where an array chip 2 is provided on the CMOS chip 3.

[0024] The CMOS chip 3 includes a substrate 30, transistors 31, vias 32, wiring 33 and 34, and an interlayer insulating film 35. RCMOS is the area where the CMOS is located. PD is its peripheral area.

[0025] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS or PMOS transistor disposed on the substrate 30. The transistor 31, for example, constitutes a CMOS circuit for controlling the memory cell array of the array chip 2. Multiple transistors 31 constitute logic circuits such as sense amplifiers, row decoders, and column decoders. Other semiconductor elements such as resistive elements and capacitive elements besides transistors 31 may also be formed on the substrate 30.

[0026] Through-hole 32 electrically connects transistor 31 to wiring 33 or wiring 33 to wiring 34. Wiring 33 and 34 form a multilayer wiring structure within interlayer insulating film 35. Wiring 34 is embedded within interlayer insulating film 35 and exposed on the surface of interlayer insulating film 35, approximately at the same plane as it. Wiring 33 and 34 are electrically connected to transistor 31, etc. Through-hole 32, wiring 33 and 34 are made of metals such as copper or tungsten. Interlayer insulating film 35 covers and protects transistor 31, through-hole 32, wiring 33 and 34. Interlayer insulating film 35 is made of insulating film such as silicon oxide film.

[0027] The array chip 2 includes a stacked layer 20, a columnar layer CL, a slit ST (LI), a source layer BSL, a metal layer 40, contact plugs CCw, contacts 29, wiring 50, and an interlayer insulating film 25. R20 is the region where the stacked layer 20 is located. PD is its peripheral region.

[0028] The stack 20 is disposed above the transistor 31 and is located in the Z direction relative to the substrate 30. The stack 20 is constructed by alternately stacking multiple electrode films 21 and multiple insulating films 22 along the Z direction. The stack 20 constitutes a memory cell array. The electrode films 21 are, for example, conductive metals such as tungsten. The insulating films 22 are, for example, insulating films such as silicon oxide films. The insulating films 22 insulate the electrode films 21 from each other. That is, multiple electrode films 21 are stacked in a mutually insulating state. The number of electrode films 21 and insulating films 22 stacked is arbitrary. The insulating film 22 may also be, for example, a porous insulating film or an air gap.

[0029] One or more electrode films 21 at the upper and lower ends of the stacked layer 20 in the Z direction function as the source-side select gate (SGS) and drain-side select gate (SGD), respectively. The electrode film 21 between the source-side select gate (SGS) and the drain-side select gate (SGD) functions as the word line (WL). The word line (WL) is the gate electrode of the memory cell (MC). The source-side select gate (SGS) is the gate electrode of the source-side select transistor (SMT). The drain-side select gate (SGD) is the gate electrode of the drain-side select transistor (SMT). The source-side select gate (SGS) is located in the upper region of the stacked layer 20. The drain-side select gate (SGD) is located in the lower region of the stacked layer 20. The upper region refers to the region of the stacked layer 20 away from the CMOS chip 3 (near the metal layer 40), and the lower region refers to the region of the stacked layer 20 near the CMOS chip 3.

[0030] Semiconductor device 1 has multiple memory cells MC connected in series between a source-side select transistor and a drain-side select transistor. The configuration of the source-side select transistor, memory cells MC, and drain-side select transistor connected in series is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a via contact 28. The bit line BL is located below the stack 20 and along the X direction (…). Figure 1 The bit line BL extends in the direction of the paper (the direction of the paper). Therefore, the bit line BL will be referred to as bit line 23 below.

[0031] A plurality of columnar bodies CL are provided within the laminate 20. The columnar bodies CL extend through the laminate 20 in the lamination direction (Z direction) of the laminate 20, and are disposed from the via contact 28 connected to the bit line 23 to the source layer BSL. The internal structure of the columnar bodies CL will be described below. Furthermore, in this embodiment, the columnar bodies CL are formed in two segments in the Z direction. However, the columnar bodies CL may also be formed in one segment. Alternatively, the columnar bodies CL may be formed in three or more segments.

[0032] in addition, Figure 1 Although not illustrated, multiple slits ST are provided within the laminate 20 (see reference). Figure 2 The slit ST extends along the Y direction and penetrates the stacked body 20 in the stacking direction (Z direction). An insulating film, such as a silicon oxide film, is filled within the slit ST, and the insulating film is plate-shaped. The slit ST electrically separates the electrode film 21 of the stacked body 20. Alternatively, an insulating film, such as a silicon oxide film, can be coated on the inner wall of the slit ST, and a conductive material can be embedded inside the insulating film. In this case, the conductive material can also function as a source wiring reaching the source layer BSL.

[0033] A source layer BSL is provided on top of the stacked layer 20. The source layer BSL is an example of a first semiconductor layer. The source layer BSL is disposed corresponding to the stacked layer 20. The source layer BSL has a first surface F1 and a second surface F2 opposite to the first surface F1. The stacked layer 20 (memory cell array) is provided on the first surface F1 side of the source layer BSL, and a metal layer 40 is provided on the second surface F2 side. The metal layer 40 includes a source line 41 and a power line 42. The source layer BSL is commonly connected to one end of a plurality of pillars CL, imparting a common source potential to the plurality of pillars CL located in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode of the memory cell array 2m. The source layer BSL uses, for example, a conductive material such as doped polysilicon. The metal layer 40 uses, for example, a metal material with a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten. Furthermore, 2s is a stepped portion of the electrode film 21 provided for connecting the contact plug CCw to each electrode film 21. Regarding the stepped portion 2s, please refer to... Figure 2 This will be described below.

[0034] Contact plugs CCw are disposed at the ends of the stack 20 and extend in the Z direction within the interlayer insulating film 25. Contact plugs CCw electrically connect the electrode films 21 (word lines WL) to the wiring 24. Contact plugs CCw are also disposed in stepped portions 2s formed in a stepped shape at the ends of the stack 20 and electrically connected to each electrode film 21. Contact plugs CCw are provided for transmitting word line voltages from the CMOS chip 3 to each electrode film 21. Contact plugs CCw are made of metals such as tungsten.

[0035] A via contact 28, wiring 23, and wiring 24 are provided below the stacked layer 20 (in the -Z direction). Wiring 23 and 24 are embedded within the interlayer insulating film 25. Wiring 24 is exposed on the surface of the interlayer insulating film 25, approximately at the same plane as it. Wiring 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL, etc. The via contact 28, wiring 23, and wiring 24 are, for example, made of a metal such as tungsten. The interlayer insulating film 25 covers and protects the stacked layer 20, via contact 28, wiring 23, and wiring 24. The interlayer insulating film 25 is, for example, made of an insulating film such as a silicon oxide film.

[0036] On the other hand, wiring 50 is provided in the peripheral region PD of the multilayer 20. Wiring 50 can be connected, for example, to a bonding pad (not shown) that receives power or signals from the outside of the semiconductor device 1. Wiring 50 is provided at one end of the contact 29 in the Z direction. Wiring 50 is connected to the transistor 31 of the CMOS chip 3 via contact 29, wiring 24, and wiring 34. Therefore, for example, external power supplied from wiring 50 is supplied to transistor 31. Or, signals are supplied to transistor 31 or memory cell array 2m via wiring 50.

[0037] Contact 29 is disposed in the peripheral region PD of the laminate 20 and extends along the Z direction in the interlayer insulating film 25. Contact 29 is a contact disposed between wiring 24 and wiring 50. Contact 29 and the contact plug CCw connected to the word line WL are formed simultaneously in the same step.

[0038] Contact 29 connects to wiring 50 and wiring 23p. Contact 29 is in the XY plane and has a generally circular, generally quadrilateral, or generally elliptical shape, and does not extend in the X or Y direction. Contact 29 can be used, for example, to supply power supply voltage or signals from wiring 50 to array chip 2 or CMOS chip 3. Contact 29 is made of metals such as copper or tungsten. The power supply voltage is, for example, the power supply voltage VDD, or a reference voltage (e.g., ground voltage) VSS that is lower than the power supply voltage VDD. The signal can be an external control signal, or data being written or read.

[0039] Wiring 23p is located in the peripheral area PD. Wiring 23p connects to contact 29 and through-hole contact 28V. Wiring 23p extends within the insulating film 25 in the X or Y direction. Figure 1 In this configuration, wiring 23p extends along the X direction. Wiring 23p is on the same layer as bit line 23 and is formed simultaneously in the same step. However, wiring 23p differs from bit line 23, functioning as wiring in the peripheral region PD. Wiring 23p uses the same conductive material (e.g., tungsten) as bit line 23.

[0040] A via contact 28v is disposed in the peripheral area PD. The via contact 28v connects to wiring 23p and wiring 24. The via contact 28v is in the XY plane, and has a generally circular, generally quadrilateral, or generally elliptical shape, and does not extend in the X or Y direction. The via contact 28v is on the same layer as the via contact 28 and is formed simultaneously in the same step. The via contact 28v uses the same conductive material (e.g., tungsten) as the via contact 28.

[0041] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and bonded together on the bonding surface B1. Therefore, no transistor 31 is disposed within the array chip 2. Furthermore, no stacked layer 20 (memory cell array) is disposed within the CMOS chip 3. Both the transistor 31 and the stacked layer 20 are located on the first surface F1 side of the source layer BSL. The transistor 31 is located on the side opposite to the second surface F2 where the metal layer 40 is located.

[0042] Interlayer insulating film 25 and interlayer insulating film 35 are bonded together on bonding surface B1. Correspondingly, wiring 24 and wiring 34 are bonded together on bonding surface B1 in a substantially coplanar manner. Thus, array chip 2 and CMOS chip 3 are electrically connected via wiring 24 and wiring 34.

[0043] Figure 2This is a schematic top view of the stacked layer 20. The stacked layer 20 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is provided, for example, at one end of the stacked layer 20. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. A slit ST (LI) is provided from the stepped portion 2s at one end of the stacked layer 20, through the memory cell array 2m, to the stepped portion 2s at the other end of the stacked layer 20. A slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST (LI) in the Z direction and extends substantially parallel to the slit ST (LI). The slit SHE electrically separates the electrode film 21 for each drain side using a selected gate SGD. Alternatively, the slit ST may also be a source wiring LI that is electrically separated from the electrode film 21 of the stacked layer 20 and electrically connected to the source layer BSL. That is, the slit ST can also be a source wiring LI that is electrically separated from the electrode film 21 of the stacked body 20 constituting the memory cell array and electrically connected to the source layer BSL.

[0044] Figure 2 The portion of the stack 20 shown, sandwiched between two slits ST, is called a block. A block, for example, constitutes the smallest unit of data erasure. Slits SHE are disposed within the block. The stack 20 between the slits ST and SHE is called a finger structure. Drain-side select gates SGD are separated by each finger structure. Therefore, during data writing and reading, one finger structure within the block can be selected via the drain-side select gates SGD.

[0045] Figure 3 and Figure 4 These are schematic cross-sectional views illustrating a three-dimensional memory cell structure. Multiple columnar sections CL are respectively disposed within memory vias MH within the stacked matrix 20. Each columnar section CL is configured to extend from one end of the stacked matrix 20 along the Z-direction, reaching into the stacked matrix 20 and the source layer BSL. Each columnar section CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each columnar section CL includes a core layer 230 disposed at its center, a semiconductor body (semiconductor component) 210 disposed around the core layer 230, and a memory film 220 disposed around the semiconductor body 210. The semiconductor body 210 extends within the stacked matrix 20 along the stacking direction (Z-direction). The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is disposed between the semiconductor body 210 and the electrode film 21 and has a charge trapping portion. Multiple columnar sections CL, selected sequentially from each finger structure, are... Figure 1 The via contacts 28 are all connected to one bit line 23. Each column CL is, for example, located in a region of the memory cell array 2m.

[0046] like Figure 3As shown, the shape of the memory hole MH on the XY plane is, for example, a circle or an ellipse. A barrier insulating film 221a, forming part of the memory film 220, may be disposed between the electrode film 21 and the insulating film 22. The barrier insulating film 221a is, for example, silicon oxide or a metal oxide. An example of a metal oxide is aluminum oxide. Figure 4 As shown, a barrier film 21b may also be provided between the electrode film 21 and the insulating film 22, and between the electrode film 21 and the memory film 220. For example, when the electrode film 21 is tungsten, the barrier film 21b may be a multilayer film of titanium nitride and titanium. The barrier insulating film 221a suppresses reverse tunneling of charge from the electrode film 21 to the memory film 220. The barrier film 21b improves the adhesion between the electrode film 21 and the barrier insulating film 221a.

[0047] The semiconductor body 210 has a bottomed cylindrical shape, for example. The semiconductor body 210 is made of polycrystalline silicon, for example. The semiconductor body 210 is made of undoped silicon, for example. Alternatively, the semiconductor body 210 can also be p-type silicon. The semiconductor body 210 serves as the channel for each of the drain-side selection transistor, the memory cell MC, and the source-side selection transistor. That is, multiple memory cells MC have a storage region between the semiconductor body 210 and the electrode film 21, which serves as the word line WL, and are stacked along the Z-direction. One end of multiple semiconductor bodies 210 within the same memory cell array 2m is commonly electrically connected to the source layer BSL.

[0048] The memory film 220 includes, for example, a covering insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a barrier insulating film 221a. The portion of the memory film 220, except for the barrier insulating film 221a, is disposed between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical. The charge trapping film 222 and the tunnel insulating film 223 extend along the Z-direction.

[0049] An insulating cover 221 is disposed between the insulating film 22 and the charge trapping film 222, and between the blocking insulating film 221a and the charge trapping film 222. The insulating cover 221 comprises, for example, silicon oxide. The insulating cover 221 protects the charge trapping film 222 from etching when the sacrificial film (not shown) is replaced with the electrode film 21 (replacement step). Alternatively, if the replacement step is not used when forming the electrode film 21, the insulating cover 221 may not be necessary.

[0050] A charge trapping film 222 is disposed between the covering insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 may contain, for example, silicon nitride, and has trapping sites for capturing charges. The portion of the charge trapping film 222 sandwiched between the electrode film 21 (which serves as the word line WL) and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC varies depending on whether there is charge in the charge trapping section, or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC stores information.

[0051] A tunnel insulating film 223 is disposed between the semiconductor substrate 210 and the charge trapping film 222. The tunnel insulating film 223 may comprise, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 acts as a potential barrier between the semiconductor substrate 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor substrate 210 into the charge trapping film 222 (writing operation) and when holes are injected from the semiconductor substrate 210 into the charge trapping film 222 (erasing operation), the electrons and holes respectively tunnel through (tunnel) the potential barrier of the tunnel insulating film 223.

[0052] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and has insulating properties.

[0053] Figure 5 This is a cross-sectional view showing an example of the configuration of the wiring portion of the array chip in the first embodiment. Figure 5 This diagram shows an example of the configuration of a region R20 containing a laminate 20 and its surrounding region PD. Hereinafter, the -Z direction will be described with the direction above.

[0054] The semiconductor device 1 of this embodiment includes interlayer insulating films 25_1 and 25_2. A wiring 50, a contact 29, a wiring 23p, a barrier metal layer 61, a nucleation film 62, and a conductive film 63 are provided in the peripheral region PD of the semiconductor device 1. A bit line 23, a barrier metal layer 61, a nucleation film 62, and a conductive film 63 are provided in the region R20 where the laminate 20 of the semiconductor device 1 is located. Furthermore, there are cases where the boundaries or thicknesses of the barrier metal layer 61, the nucleation film 62, and the conductive film 63 are unclear. Therefore, the barrier metal layer 61, the nucleation film 62, and the conductive film 63 can be referred to as the barrier metal region 61, the nucleation region 62, and the conductive region 63, respectively. The thickness of the barrier metal layer 61, the nucleation film 62, and the conductive film 63 should preferably be within a specified range centered on the peak concentration of their respective components.

[0055] Interlayer insulating films 25_1 and 25_2 are Figure 1A portion of the interlayer insulating film 25 is disposed on the laminate 20. Interlayer insulating film 25_1 is an insulating film with wiring 50 and contacts 29 internally. Interlayer insulating film 25_2 is an insulating film with wiring 23p and bit line 23 internally.

[0056] Wiring 50, serving as the first wiring, is disposed within the interlayer insulating film 25_1. Wiring 50 may be made of conductive materials such as tungsten, copper, or doped silicon.

[0057] Wiring 23p, serving as the second wiring, is disposed within the interlayer insulating film 25_2. Wiring 23p is positioned above wiring 50 (in the -Z direction) and is electrically connected to wiring 50 via contact 29. Wiring 23p may be made of a second conductive material such as tungsten.

[0058] Contact 29, serving as the first contact point, is provided between wiring 50 and wiring 23p, electrically connecting wiring 50 and wiring 23p. Contact 29 is located within contact hole H29 provided within the interlayer insulating film 25_1. Although in Figure 5 The diagram is simplified, but contact 29 extends deeper downwards (in the +Z direction) within the interlayer insulating film 25_1. Contact 29 may use a first conductive material such as tungsten.

[0059] Bit line 23, serving as the third wiring, is disposed in region R20 where the laminate 20 is located. Bit line 23 is disposed in the same layer as wiring 23p and is positioned in the -Y direction of wiring 23p. Bit line 23 is configured to extend in the X direction within the interlayer insulating film 25_2. Bit line 23 uses the same material as wiring 23p, such as a second conductive material like tungsten.

[0060] A barrier metal layer 61 is disposed in the peripheral region PD between the contact 29 and the interlayer insulating film 25_1, and between the wiring 23p and the interlayer insulating films 25_1 and 25_2. In region R20, the barrier metal layer 61 is disposed between the bit line 23 and the interlayer insulating films 25_1 and 25_2. The barrier metal layer 61 is disposed in a manner that prevents the diffusion of the material (e.g., tungsten) or byproducts of the contact 29, wiring 23p, and bit line 23. The barrier metal layer 61 may be made of, for example, Ti or TiN, or a laminated film thereof.

[0061] The nucleation film 62, serving as the first conductive film, is disposed between the contact 29 and the wiring 50. Furthermore, the nucleation film 62 is disposed on the side of the contact 29. Moreover, the nucleation film 62 is disposed on the side of the wiring 23p and the side of the bit line 23, separated by the conductive film 63.

[0062] The nucleation film 62 has the function of promoting the formation of conductive materials (e.g., tungsten). The nucleation film 62 may be, for example, a tungsten film containing boron or a tungsten film containing silicon.

[0063] The conductive film 63, serving as the second conductive film, is disposed between the wiring 23p and the nucleation film 62, and between the bit line 23 and the nucleation film 62, but not between the contact 29 and the nucleation film 62. That is, the conductive film 63 is not disposed within the contact hole H29. The conductive film 63 may be made of a conductive material such as nitrogen-containing tungsten (WN). The nitrogen concentration in the conductive film 63 is higher than that in the nucleation film 62. Tungsten with a higher nitrogen concentration is difficult to deposit on it. Alternatively, the conductive film 63 may also be tungsten containing boron in addition to nitrogen.

[0064] The first conductive material constituting contact 29 is, for example, tungsten formed at a low temperature below 350°C. Tungsten formed at such a low temperature is unlikely to deposit on the conductive film 63 (e.g., nitrogen-containing tungsten (WN)), but can be deposited on the nucleation film 62 (e.g., tungsten with a low nitrogen concentration). On the other hand, tungsten formed at a high temperature above 350°C is easily reduced by the material gas (WF6), thus facilitating deposition. Therefore, tungsten formed at high temperatures can also be deposited on the conductive film 63. As described above, the conductive film 63 is a material from which tungsten is more difficult to deposit than the nucleation film 62. Therefore, depending on the formation temperature of the first conductive material (e.g., tungsten), it is possible to selectively deposit the first conductive material on the nucleation film 62 without depositing it on the conductive film 63.

[0065] The following explanation will be based on the example of tungsten formed at low temperature.

[0066] Within the contact hole H29, a conductive material (e.g., tungsten) is disposed on the nucleation film 62 of the contact point 29. No conductive film 63 is disposed within the contact hole H29. Furthermore, the first conductive material of the contact point 29 is, for example, tungsten formed at a low temperature below 350°C. If the tungsten is formed at such a low temperature, the reduction of the material gas (e.g., WF6) will take time. That is, the incubation time becomes longer. Therefore, the material gas (e.g., WF6) can reach the bottom of the contact hole H29 before reduction. Thus, the tungsten coverage of the contact point 29 is good, and the film can be formed to the bottom of the contact hole H29. Additionally, the absence of a conductive film 63 within the contact hole H29 promotes the exposure of the nucleation film 62 for tungsten formation. Therefore, tungsten can fill the contact hole H29 with a high aspect ratio.

[0067] On the other hand, as mentioned above, the tungsten formed at low temperatures requires a longer cultivation time and will not form on the conductive film 63. Therefore, it is impossible to use the same tungsten as contact 29 to form wiring 23p and bit line 23. In addition, the tungsten formed at low temperatures has a relatively high concentration of impurities (e.g., fluorine), resulting in higher resistance. Therefore, assuming that the same tungsten formed at low temperatures as contact 29 is used to form wiring 23p and bit line 23, the wiring resistance of wiring 23p and bit line 23 will be high.

[0068] In this embodiment, the wiring 23p and bit line 23 are filled, for example, with tungsten film formed at a high temperature of 350°C or above. If the tungsten is formed at a high temperature, it is easily reduced by the material gas (e.g., WF6), and the growth time is relatively short. Therefore, the coverage of this high-temperature formed tungsten is poor, and it is not easy to fill the contact 29, but it is easy to deposit on the conductive film 63, and it can fill the wiring 23p and bit line 23.

[0069] Furthermore, tungsten formed at high temperatures has a lower concentration of impurities (e.g., fluorine) and a larger particle size compared to tungsten formed at low temperatures, resulting in lower resistance. Therefore, wiring 23p and bit line 23 can achieve lower resistance by using tungsten formed at high temperatures as filler. That is, wiring 23p and bit line 23 can be filled with a second conductive material whose resistance is lower than that of the first conductive material of contact 29. The second conductive material of wiring 23p and bit line 23 is, for example, the same tungsten as the first conductive material of contact 29. However, the second conductive material is, for example, tungsten formed at a high temperature above 350°C, with a lower concentration of impurities (e.g., fluorine) than the tungsten of the first conductive material, resulting in lower resistance. Therefore, it can be said that a second conductive material suitable for wiring 23p and bit line 23 is appropriate.

[0070] The following explanation will be based on the example of assuming that the second conductive material of wiring 23p and bit line 23 is tungsten formed at high temperature.

[0071] For example, as the memory cell array 2m is miniaturized, the linewidth and line spacing (line-to-gap) of the bit line 23 also become narrower. Therefore, the width W23 of the bit line 23 in the Y direction is much smaller than the width W29 of the contact 29 and the width W23p of the wiring 23p in the Y direction (W23 < W29 < W23p). Furthermore, as the memory capacitance increases, the length of the bit line 23 becomes longer. Therefore, the wiring resistance of the bit line 23 tends to increase. In this situation, using high-resistance tungsten formed at low temperatures to form the bit line 23 is not preferred. However, using low-resistance tungsten formed at high temperatures to form the wiring 23p and the bit line 23 is preferable. In particular, using low-resistance tungsten to form the continuously miniaturized bit line 23 is advantageous.

[0072] As described above, in this embodiment, contact 29 is filled with tungsten with good coverage formed at low temperature, and wiring 23p and bit line 23 are filled with tungsten with low resistance formed at high temperature. Thus, contact 29 can be filled with tungsten with good coverage, and wiring 23p and bit line 23 can be filled with tungsten with low resistance.

[0073] The second conductive material disposed within wiring 23p and bit line 23 is the same tungsten as the first conductive material disposed within contact 29, but with a lower impurity concentration (e.g., fluorine concentration) and a larger particle size. Therefore, the second conductive material formed at high temperature has a lower resistance compared to the first conductive material formed at low temperature.

[0074] The first conductive material and the second conductive material are tungsten with different impurity concentrations and particle sizes. Therefore, there is an interface between the first conductive material at contact 29 and the second conductive material at wiring 23p.

[0075] A barrier metal layer 61 and a nucleation film 62 are provided between the wiring 50 and the contact 29. On the other hand, the barrier metal layer 61, the nucleation film 62, and the conductive film 63 are not disposed between the contact 29 and the wiring 23p. That is, the contact 29 and the wiring 23p are in direct contact. This is because the contact 29 is formed using the first conductive material, and then the wiring 23p is formed using the second conductive material. That is, it can be seen that this embodiment uses a double-layer metal inlay method for formation.

[0076] Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described.

[0077] Figures 6-10 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0078] First, a laminate 20 is formed in region R20 of the substrate (not shown), and an interlayer insulating film 25_1 is formed on the substrate.

[0079] Next, wiring 50 is formed within the interlayer insulating film 25_1 of the peripheral region PD. Wiring 50 may be made of a conductive material such as tungsten. Interlayer insulating film 25_1 may be made of an insulating material such as silicon oxide. Wiring 50 may be wiring formed on a substrate, but is not limited to this, and may also be an impurity diffusion layer formed on a substrate.

[0080] Next, material for interlayer insulating film 25_1 is deposited on wiring 50, and interlayer insulating film 25_2 is deposited on interlayer insulating film 25_1. Interlayer insulating film 25_2 is, for example, made of insulating material such as silicon oxide. In addition, although not shown, wiring and via contacts (not shown) connected to the laminate 20 are also formed in region R20.

[0081] Next, using photolithography and etching techniques, contact holes H29 and trenches TR23p and TR23 are formed within the interlayer insulating films 25_1 and 25_2. In the peripheral region PD, contact hole H29 extends along the -Z direction within the interlayer insulating film 25_1 and reaches wiring 50. Trench TR23p is disposed in the -Z direction of contact hole H29 and communicates with contact hole H29. Trench TR23p is disposed within the interlayer insulating film 25_2, for example, extending along the X direction. Trench TR23p is used to form wiring 23p. In region R20, trench TR23 is disposed within the interlayer insulating film 25_2, for example, extending along the X direction. Trench TR23 is used, for example, for bit line 23, thus reaching the via contact (not shown) within the stacked body 20 that connects to the semiconductor body 210 of the pillar CL.

[0082] Here, the width Wtr23p of the trench TR23p in the Y direction is greater than the width Wh29 of the contact hole H29 in the Y direction. The width Wtr23 of the trench TR23 in the Y direction is less than the width Wh29 of the contact hole H29 and the width Wtr23p of the trench TR23p.

[0083] Next, methods such as CVD (Chemical Vapor Deposition) and chemical mechanical polishing are used. Figure 6 As shown, a barrier metal layer 61 is formed on the inner walls of trenches TR23p and TR23 and contact hole H29. The barrier metal layer 61 may be made of, for example, Ti or TiN, or a laminated film thereof. The barrier metal layer 61 facilitates the deposition of metallic materials such as tungsten.

[0084] Next, methods such as CVD are used. Figure 7 As shown, a nucleation film 62 is formed within trenches TR23p, TR23, and contact hole H29. The nucleation film 62 is formed on the inner walls of trenches TR23p, TR23, and contact hole H29, separated by a barrier metal layer 61. The nucleation film 62 is tungsten formed, for example, by adding diborane (B2H6) or silane (SiH4) as a reducing gas to a material gas (tungsten fluoride: WF6). This tungsten becomes a relatively high-resistivity tungsten containing a large amount of boron or silicon. However, the nucleation film 62 can promote the deposition of the first conductive material (e.g., tungsten) of the subsequently formed contact 29, thereby improving the adhesion between the first conductive material and the wiring 50 or interlayer insulating film 25_1.

[0085] Next, methods such as CVD are used. Figure 8As shown, a conductive film 63 is selectively formed on the nucleation film 62 within trenches TR23p and TR23. The conductive film 63 is formed by reducing the coverage or limiting the supply rate of the material gas using methods such as plasma CVD. Therefore, the conductive film 63 is formed on the nucleation film 62 within trenches TR23p and TR23, but almost none is formed on the nucleation film 62 within the contact hole H29. The conductive film 63 is, for example, tungsten formed by adding ammonia (NH3) as a reducing gas to the material gas (tungsten fluoride: WF6). This tungsten contains a large amount of nitrogen, resulting in tungsten with a higher resistivity than the nucleation film 62 (e.g., tungsten nitride (WN)). Tungsten nitride is less conducive to tungsten growth compared to tungsten boride or tungsten silicide. Therefore, compared to the nucleation film 62, the conductive film 63 is less likely to deposit the material (e.g., tungsten) of the contact 29, wiring 23p, and bit line 23. That is, the conductive film 63 functions as a mask material to inhibit the formation of materials for the contact 29, wiring 23p, and bit line 23. Alternatively, the conductive film 63 can be formed by adding ammonia (NH3) and diborane (B2H6) as reducing gases to a material gas (WF6). In this case, the conductive film 63 becomes tungsten (WBN) containing a large amount of nitrogen and boron and having relatively high resistance. Although the conductive film 63 is tungsten (WBN), it can still maintain its function.

[0086] Next, for example, a conductive material (e.g., tungsten) is deposited at a low temperature below 350°C. At temperatures below 350°C, the reduction of the material gas (e.g., WF6) will take time, resulting in a longer incubation period. Therefore, the material gas (e.g., WF6) can reach the bottom of the contact hole H29 before reduction. Thus, as... Figure 9 As shown, the conductive material coverage of contact 29 is good, and it can fill the bottom of the high aspect ratio contact hole H29. Thus, contact 29 is formed using a first conductive material (e.g., tungsten with a relatively high impurity concentration).

[0087] On the other hand, the tungsten formed at low temperature promotes the deposition of the nucleation film 62, but not on the conductive film 63. Therefore, the tungsten formed at low temperature is selectively embedded within the contact hole H29, but hardly formed within the trenches TR23p and TR23. The tungsten formed at low temperature has good coverage, but the concentration of impurities (e.g., fluorine) is relatively high, resulting in high resistance. Therefore, this first conductive material is preferably used only to form the high aspect ratio contact 29, and not for forming the wiring 23p and bit line 23.

[0088] Next, for example, the conductive material (second conductive material) (e.g., tungsten) of wiring 23p and bit line 23 is film-formed at a high temperature above 350°C. A high temperature above 350°C promotes the reduction of the material gas (e.g., WF6), resulting in a shorter incubation time. Therefore, the material gas (e.g., WF6) is reduced quickly, and tungsten is easily deposited even on the conductive film 63. Thus, tungsten of the second conductive material is deposited within the trenches TR23p and TR23. Therefore, as... Figure 10 As shown, trenches TR23p and TR23 can be filled with tungsten formed at high temperatures. The impurity concentration of tungsten formed at high temperatures is lower than that of tungsten formed at low temperatures. Therefore, wiring 23p and bit line 23 are formed using a second conductive material (e.g., tungsten with a relatively low fluorine concentration) with a lower impurity concentration than the first conductive material. Wiring 23p is formed above (in the -Z direction) the contact 29 and is in direct contact with the contact 29. Bit line 23 is formed in the -Y direction of wiring 23p and is electrically insulated from the contact 29 and wiring 23p.

[0089] The tungsten formed at high temperature is also deposited on a conductive film 63 that has the function of inhibiting tungsten formation. Therefore, tungsten formed at a temperature higher than the formation temperature of the contact 29 can be formed in the trenches TR23p and TR23. Consequently, the concentration of tungsten impurities (e.g., fluorine) formed at a temperature higher than the formation temperature of the contact 29 is relatively low, resulting in lower resistance. Therefore, by using the tungsten formed at high temperature in wiring 23p and bit line 23, the wiring resistance of wiring 23p and bit line 23 can be reduced.

[0090] Next, CMP (Chemical Mechanical Polishing) is used to polish the wiring 23p, bit line 23, conductive film 63, nucleation film 62, and barrier metal layer 61 until the interlayer insulating film 25_2 is exposed. This allows for the production of... Figure 5 The structure shown.

[0091] Then, it is bonded to a separately formed CMOS wafer, and the substrate on the back side (+Z side) of the stack 20 is removed. A metal layer 40 is formed on the back side of the stack 20 as needed. Then, the bonded wafer is monolithically divided into individual chips using a dicing step. Thus, the semiconductor device 1 is completed.

[0092] As described above, in this embodiment, the contact 29 is formed, for example, of tungsten with good coverage formed at a low temperature, and the wiring 23p and bit line 23 are formed, for example, of tungsten with low resistance formed at a high temperature. Thus, the contact 29 can be formed of tungsten with good coverage, and the wiring 23p and bit line 23 can be formed of tungsten with low resistance.

[0093] In this embodiment, after the contact 29 is formed using tungsten formed at a low temperature, the wiring 23p is then formed using tungsten formed at a high temperature. Thus, this embodiment uses a double-track metal damascene method. Therefore, the wiring 50 is in direct contact with the contact 29, and no barrier metal layer 61, nucleation film 62, or conductive film 63 is placed between them.

[0094] Furthermore, conductive film 63 is disposed on a portion of the side and bottom surfaces of trenches TR23p and TR23, but not on the side and bottom surfaces of contact hole H29. Conductive film 63 functions as a mask material during the formation step of contact 29. Therefore, during the formation step of contact 29, nucleation film 62 is exposed on the side and bottom surfaces of contact hole H29. Consequently, low-temperature formed tungsten is selectively formed within contact hole H29, and almost none is formed in trenches TR23p and TR23. On the other hand, high-temperature formed tungsten is formed in trenches TR23p and TR23. Thus, contact hole H29 is filled with well-covered tungsten, and trenches TR23p and TR23 are filled with low-resistance tungsten. This reduces the wiring resistance of wiring 23p and bit line 23.

[0095] (Second Implementation)

[0096] Figure 11 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the second embodiment. In the second embodiment, no conductive film 63 remains. Wiring 23p is in direct contact with the nucleation film 62. Bit line BL is also in direct contact with the nucleation film 62.

[0097] In the first embodiment, the conductive film 63 is, for example, made of nitrogen-containing tungsten (WN), which has relatively high resistance. In the second embodiment, a second conductive material with lower resistance is used instead of the relatively high-resistance conductive film 63, which provides the wiring 23p and bit line 23. As a result, the resistance of the wiring 23p and bit line 23 is reduced.

[0098] The other configurations of the second embodiment should preferably be the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0099] Figure 12 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. The second embodiment is based on... Figures 6-9 Following the steps described, heat treatment is performed. Figure 9In the case where the conductive film 63 is, for example, tungsten (WN) containing nitrogen, nitrogen is removed from the conductive film 63 by heat treatment in a hydrogen environment, thereby reducing the nitrogen concentration. This transforms the conductive film 63 into tungsten (63') with a lower nitrogen concentration. Furthermore, the heat treatment enlarges the tungsten particle size in the conductive film 63. This tungsten (63') has a lower resistance than tungsten with a higher nitrogen concentration, is homogeneous with the tungsten formed at high temperatures, and becomes approximately the same type of tungsten as the tungsten constituting wiring 23p and bit line 23.

[0100] Then, after reference Figure 10 The steps described Figure 11 The semiconductor device 1 shown is now complete.

[0101] In this way, the second embodiment modifies the conductive film 63 used to selectively embed the contact 29 into the contact hole H29 by heat treatment, thereby transforming it into a low-resistance tungsten with a lower nitrogen concentration. As a result, the conductive film 63 becomes tungsten of substantially the same composition as the tungsten constituting the wiring 23p and the bit line 23. Consequently, the resistance of the wiring 23p and the bit line 23 can be further reduced.

[0102] (Third Implementation)

[0103] Figure 13 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the third embodiment. In the third embodiment, no conductive film 63 remains. Wiring 23p is in direct contact with the nucleation film 62. Bit line BL is also in direct contact with the nucleation film 62.

[0104] In the first embodiment, the conductive film 63 is, for example, tungsten (WN) containing nitrogen, which has relatively high resistance. In the third embodiment, instead of the conductive film 63 with relatively high resistance, a nucleation film 62 is provided. In the third embodiment, the nucleation film 62 is, for example, tungsten containing boron. Tungsten containing boron has lower resistance than tungsten containing nitrogen. Therefore, the resistance of the wiring 23p and bit line 23 in contact with the nucleation film 62 can be reduced.

[0105] The thickness of the nucleation film 62 disposed on the side of wiring 23p and bit line 23 is greater than the thickness of the nucleation film 62 disposed between contact 29 and wiring 50 and on the side of contact 29. This is because the conductive film 63 is modified into the nucleation film 62 (e.g., tungsten containing boron) during the manufacturing process.

[0106] The other configurations of the third embodiment should preferably be the same as those of the first embodiment. Therefore, the third embodiment can achieve the same effects as the first embodiment.

[0107] Figure 14 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment. The third embodiment will be described with reference to... Figures 6-9 The steps described. At this point, Figure 8The conductive film 63 is formed, for example, by adding ammonia (NH3) and diborane (B2H6) as reducing gases to a material gas (WF6). Therefore, the conductive film 63 is, for example, tungsten (WBN) containing nitrogen and boron. Then, after reference... Figure 9 The steps described form contact 29.

[0108] Next, heat treatment is performed. Figure 9 In the case where the conductive film 63 is, for example, tungsten (WBN) containing nitrogen and boron, nitrogen is removed from the conductive film 63 through heat treatment. As a result, the conductive film 63 is modified into tungsten containing boron with a lower nitrogen concentration. This tungsten has a lower electrical resistance compared to tungsten with a higher nitrogen concentration and is substantially homogeneous with the boron-containing tungsten of the nucleation film 62. Therefore, in Figure 14 In the diagram, conductive film 63 is shown as the same film as nucleation film 62. Conductive film 63 is not formed within contact hole H29, but is formed within trenches TR23p and TR23. Therefore, the thickness of nucleation film 62 is relatively thin within contact hole H29 and relatively thick within trenches TR23p and TR23.

[0109] Then, after reference Figure 10 The steps described Figure 13 The semiconductor device 1 shown is now complete.

[0110] In this way, the third embodiment modifies the conductive film 63 used to selectively embed the contact 29 into the contact hole H29 by heat treatment, transforming it into a low-resistance boron-containing tungsten with a low nitrogen concentration. Thus, the conductive film 63 becomes a material substantially homogeneous with the boron-containing tungsten constituting the nucleation film 62. As a result, the resistance of the wiring 23p and the bit line 23 can be further reduced.

[0111] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and their equivalents.

[0112] [Explanation of Symbols]

[0113] 1: Semiconductor devices

[0114] 25_1, 25_2: Interlayer insulating film

[0115] 50: Wiring

[0116] 29:Contact

[0117] 23p: Wiring

[0118] 23: Bit Line

[0119] 61: Barrier Metal Layer

[0120] 62: Nucleation membrane

[0121] 63: Conductive film.

Claims

1. A semiconductor device comprising: a first wiring; The second wiring is provided on the first direction side of the first wiring; The first contact electrically connects the first wiring to the second wiring; and The third wiring is narrower than the second wiring and the first connection in the second direction, which intersects the first direction, and is provided on the second direction side of the second wiring; and The first contact is made of a first conductive material. The second and third wirings are made of a second conductive material with a lower resistance than the first conductive material.

2. The semiconductor device of claim 1, wherein the impurity concentration contained in the second conductive material is lower than the impurity concentration contained in the first conductive material.

3. The semiconductor device according to claim 2, wherein the impurity concentration is a fluorine concentration.

4. The semiconductor device according to claim 1, wherein the particle size of the second conductive material is larger than the particle size of the first conductive material.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a first conductive region disposed between the first contact and the first wiring, on the side of the first contact, on the side of the second wiring, and on the side of the third wiring.

6. The semiconductor device according to claim 5, wherein the first conductive region is a tungsten film containing boron or a tungsten film containing silicon.

7. The semiconductor device of claim 5, further comprising a second conductive region disposed between the second wiring and the first conductive region, and between the third wiring and the first conductive region, but not disposed between the first contact and the first conductive region.

8. The semiconductor device of claim 7, wherein the second conductive region comprises nitrogen-containing tungsten.

9. The semiconductor device of claim 7, wherein the second conductive region comprises tungsten containing nitrogen and boron.

10. The semiconductor device of claim 5, wherein the first conductive region disposed on the sides of the second and third wirings is thicker than the first conductive region disposed between the first contact and the first wirings and on the sides of the first contact.

11. The semiconductor device of claim 1, wherein the second wiring is in direct contact with the first contact.

12. A method for manufacturing a semiconductor device, comprising: A contact hole, a first trench, and a second trench are formed on a first insulating film disposed along the first direction side of the first wiring. The contact hole reaches the first wiring. The first trench is disposed on the first direction side of the contact hole and communicates with the contact hole. Its width in a second direction intersecting the first direction is wider than that of the contact hole. The second trench is disposed on the second direction side of the first trench and its width in the second direction is narrower than that of the contact hole and the first trench. A first conductive region is formed in the first and second trenches and in the contact hole. A second conductive region is selectively formed on the first conductive region on the inner wall of the first and second trenches, and a first contact is formed by selectively embedding the first conductive material in the contact hole. By embedding a second conductive material in the second conductive region within the first and second trenches at a higher temperature than that used in the formation of the first conductive material, a second wiring is formed on the first direction side of the first contact, and a third wiring is formed on the second direction side of the second wiring.

13. The manufacturing method according to claim 12, wherein the first conductive region is formed by adding diborane (B2H6) or silane (SiH4) to tungsten fluoride (WF6).

14. The manufacturing method according to claim 12, wherein the second conductive region is formed by adding ammonia (NH3) to tungsten fluoride (WF6).

15. The manufacturing method according to claim 14, wherein the nitrogen concentration of the second conductive region is reduced by performing heat treatment after the formation of the second wiring.

16. The manufacturing method according to claim 12, wherein the second conductive region is formed by adding ammonia (NH3) and diborane (B2H6) to tungsten fluoride (WF6).

17. The manufacturing method according to claim 16, wherein the nitrogen concentration of the second conductive region is reduced by performing heat treatment after the formation of the second wiring.

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