Memory device and method of manufacturing the memory device

Abstract

The present application relates to a memory device and a manufacturing method of the memory device. A memory device includes a laminate including conductive layers and interlayer insulating layers alternately laminated with each other. The memory device further includes a cell plug penetrating the laminate. The memory device further includes a support pattern spaced apart from the laminate and the cell plug, wherein the support pattern includes a through region. The memory device additionally includes a contact penetrating the support pattern through the through region. The support pattern includes openings arranged in a first direction and a second direction in which the support pattern extends.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to memory devices and methods of manufacturing the same, and more specifically, to a memory device comprising a memory block having a three-dimensional structure and a method of manufacturing the same. Background Technology

[0002] Memory devices can be non-volatile memory devices that retain stored data even during power outages. Depending on the arrangement of their memory cells, non-volatile memory devices can have a two-dimensional or three-dimensional structure. Memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate. Memory cells of a three-dimensional non-volatile memory device can be vertically stacked on a substrate. Because the integration density of three-dimensional non-volatile memory devices is higher than that of two-dimensional non-volatile memory devices, the number of electronic devices using three-dimensional non-volatile memory devices has been increasing in recent years. Summary of the Invention

[0003] According to one embodiment, a memory device may include: a stack comprising conductive layers and interlayer insulating layers alternately stacked on top of each other; a cell plug penetrating the stack; a support pattern spaced apart from the stack and the cell plug, the support pattern including a through region; and a contact penetrating the support pattern through the through region. The support pattern includes openings arranged in a first direction and a second direction in which the support pattern extends.

[0004] According to an embodiment, a method of manufacturing a memory device may include the following steps: forming a support layer extending in a first direction and a second direction; forming a support pattern including openings arranged in the first direction and the second direction, and forming a through region with a width greater than the openings by removing a portion of the support layer; forming an insulating layer that fills the openings and the through region; and forming a contact that penetrates the insulating layer and extends through the through region. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0006] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figures 3A to 3D This is a diagram illustrating the support pattern included in a memory device according to an embodiment of the present disclosure;

[0008] Figures 4A to 4E This is a diagram illustrating a method for manufacturing a support pattern according to an embodiment of the present disclosure;

[0009] Figure 5A and Figure 5B These are diagrams illustrating various embodiments of the support pattern according to this disclosure;

[0010] Figure 6 This is a diagram illustrating a memory card system using the memory device of this disclosure; and

[0011] Figure 7 This is a diagram illustrating a solid-state drive (SSD) system using the memory device of this disclosure. Detailed Implementation

[0012] Specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are shown only to illustrate examples of embodiments of the concepts, which may be implemented in various forms, but these descriptions are not limited to the examples of embodiments described in this specification.

[0013] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0014] Some embodiments of this disclosure relate to a memory device and a method of manufacturing the memory device, such that warping of the memory device is reduced or prevented.

[0015] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0016] Reference Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0017] The memory cell array 110 may include first memory blocks BLK1 through i-th memory blocks BLKi. Each of the first memory blocks BLK1 through i-th memory blocks BLKi may include a memory cell capable of storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL may be connected to each of the first memory blocks BLK1 through i-th memory blocks BLKi. Bit line BL may be collectively connected to the first memory blocks BLK1 through i-th memory blocks BLKi.

[0018] The first memory block BLK1 to the i-th memory block BLKi may have a three-dimensional structure. A memory block with a three-dimensional structure may include memory cells vertically stacked on a substrate. The memory block may include a stack comprising conductive layers and interlayer insulating layers alternately stacked in a vertical direction. Because the stack extends in one direction, it may cause warping of the memory block. However, according to some embodiments of this disclosure, defects in the memory device 100 can be reduced or prevented by adding support patterns that can reduce or prevent warping of the memory block. Referring below... Figure 3A To describe the support pattern.

[0019] Depending on how the memory cells are programmed, a memory cell can store one, two, or more bits of data. For example, a single memory cell storing one bit of data is called a single-level cell, a single memory cell storing two bits of data is called a multi-level cell, a single memory cell storing three bits of data is called a three-level cell, and a single memory cell storing four bits of data is called a four-level cell. Additionally, five bits of data can be stored in a single memory cell.

[0020] The peripheral circuitry 170 can perform programming operations to store data in the memory cell array 110, reading operations to output data stored in the memory cell array 110, and erasing operations to erase data stored in the memory cell array 110. For example, the peripheral circuitry 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and input / output circuitry 160.

[0021] Voltage generator 120 can generate various operating voltages Vop for programming, reading, or erasing operations in response to opcode OPCD. For example, voltage generator 120 can generate programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, or erase voltage in response to opcode OPCD. The operating voltage Vop generated by voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the memory block selected by line decoder 130.

[0022] A programming voltage can be applied to a selected word line (WL) during programming operations and can be used to increase the threshold voltage of the memory cell connected to the selected word line. A turn-on voltage can be applied to the drain select line (DSL) or the source select line (SSL) and can be used to turn on the drain select transistor or the source select transistor. A turn-off voltage can be applied to the drain select line (DSL) or the source select line (SSL) and can be used to turn off the drain select transistor or the source select transistor. For example, the turn-off voltage can be set to 0V. A precharge voltage can be higher than 0V and can be applied to the bit line during read operations. A verification voltage can be used during verification operations to determine when the threshold voltage of the selected memory cell rises to a target level. The verification voltage can be set to various levels depending on the target level and can be applied to the selected word line.

[0023] A read voltage can be applied to a selected word line during a read operation on a selected memory cell. For example, the read voltage can be set to various levels depending on how the selected memory cell is programmed. A voltage can be applied to unselected word lines in the word line WL during a programming or read operation and can be used to turn on memory cells connected to unselected word lines. An erase voltage can be used to erase memory cells included in a selected memory block during an erase operation and can be applied to the source line SL.

[0024] The row decoder 130 can transmit the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL connected to the memory block selected according to the row address RADD. For example, the row decoder 130 can be connected to the voltage generator 120 via a global line and to the first memory block BLK1 through the i-th memory block BLKi via the drain select line DSL, word line WL, source select line SSL, and source line SL.

[0025] Page buffer group 140 may include page buffers (not shown) respectively connected to first memory blocks BLK1 through i-th memory blocks BLKi. Each page buffer is connected to the first memory blocks BLK1 through i-th memory blocks BLKi via bit lines BL. During a read operation, the page buffer can sense the current or voltage on the bit line that varies according to the threshold voltage of the selected memory cell in response to the page buffer control signal PBSIG, and can temporarily store the sensed data.

[0026] The column decoder 150 can transfer data between the page buffer group 140 and the input / output circuitry 160 in response to the column address CADD. For example, the column decoder 150 can be coupled to the page buffer group 140 via the column line CL and transmit an enable signal via the column line CL. The page buffers included in the page buffer group 140 can receive or output data via the data line DL in response to the enable signal.

[0027] Input / output circuitry 160 can receive or output commands (CMD), addresses (ADD), or data via input / output lines I / O. For example, input / output circuitry 160 can transmit commands (CMD) and addresses (ADD) received from an external controller to control circuitry 180 via input / output lines I / O, and can transmit data received from an external controller to page buffer group 140 via input / output lines I / O. Alternatively, input / output circuitry 160 can output data received from page buffer group 140 to an external controller via input / output lines I / O.

[0028] In response to the command CMD and address ADD, the control circuit 180 can output at least one of the following: opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD. For example, when the command CMD input to the control circuit 180 corresponds to a programming operation, the control circuit 180 can control the peripheral circuit 170 to perform a programming operation on the memory block selected by the address ADD. When the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 can control the peripheral circuit 170 to perform a read operation on the memory block selected by the address ADD and output the read data. When the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 can control the peripheral circuit 170 to perform an erase operation on the selected memory block.

[0029] Figure 2 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0030] Reference Figure 2 The memory device 100 may include a peripheral circuit structure PC disposed on a substrate SUB and first memory blocks BLK1 to BLKi. The first memory blocks BLK1 to BLKi may overlap with the peripheral circuit structure PC.

[0031] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by selective epitaxial growth.

[0032] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and control circuitry 180, which constitutes circuitry for controlling the operation of the first memory block BLK1 to the i-th memory block BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the first memory blocks BLK1 to the i-th memory block BLKi. The peripheral circuit structure PC may be arranged between the substrate SUB and the first memory blocks BLK1 to the i-th memory block BLKi.

[0033] Each of the first memory blocks BLK1 to the i-th memory block BLKi may include a source structure, bit lines, a string of cells electrically connected to the source structure and the bit lines, a word line electrically connected to the string of cells, and a select line electrically connected to the string of cells. Each string of cells may include memory cells and select transistors connected in series via cell plugs. Each select line may serve as the gate electrode of the corresponding select transistor, and each word line may serve as the gate electrode of the corresponding memory cell. The first memory blocks BLK1 to the i-th memory block BLKi may be separated from each other by slits.

[0034] Each of the first storage blocks BLK1 to the i-th storage block BLKi can extend in the X direction. Therefore, warping may occur in the first storage blocks BLK1 to the i-th storage block BLKi. However, according to some embodiments of this disclosure, defects included in the memory device 100 can be reduced or prevented by adding support patterns that can reduce or prevent warping of the first storage blocks BLK1 to the i-th storage block BLKi. Referring below... Figure 3A Describe the support pattern.

[0035] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the first memory blocks BLK1 to the i-th memory blocks BLKi can be configured according to... Figure 2 The stacking order is the reverse of the given order. For example, the peripheral circuit structure PC can be arranged on top of the first memory block BLK1 to the i-th memory block BLKi.

[0036] In another embodiment, with Figure 2 Unlike the peripheral circuit structure PC shown, the peripheral circuit structure PC can be arranged on some areas of the substrate SUB that do not overlap with the first memory blocks BLK1 to the i-th memory blocks BLKi. For example, the peripheral circuit structure PC and the first memory blocks BLK1 to the i-th memory blocks BLKi can be arranged on the non-overlapping areas of the substrate SUB.

[0037] Figures 3A to 3D This is a diagram illustrating a support pattern included in a memory device according to an embodiment of the present disclosure. Figure 3B Is with Figure 3A The plan view corresponding to the A-A' cross section. Figure 3C Is with Figure 3A The plan view corresponding to the B-B' cross section. Figure 3D Is with Figure 3A The plan view corresponding to the C-C' cross section.

[0038] Reference Figure 3A Memory devices (e.g., Figure 1 and Figure 2 Memory device 100 Figure 2The first storage block BLK1 to the i-th storage block BLKi (at least one of these storage blocks) may include a stack STK and a dummy stack DST. An isolation structure SR may be located between the stack STK and the dummy stack DST. The dummy stack DST may be spaced apart from the stack STK and the isolation structure SR may be inserted therebetween.

[0039] The stack STK may include a conductive layer CD and an interlayer insulating layer IL. The conductive layer CD and the interlayer insulating layer IL may be stacked alternately in the Z direction. The conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si). The interlayer insulating layer IL may include an oxide layer (e.g., silicon oxide). The conductive layer CD may correspond to a gate line (e.g., ...). Figure 1 The drain select line (DSL), word line (WL), and source select line (SSL) are used in this process.

[0040] The stacked structure STK may include a stepped structure. The stacked structure STK may include multiple steps. Each of the multiple steps may include a pair comprising a conductive layer CD and an interlayer insulating layer IL. For example, each of the multiple steps may include a single conductive layer CD and an interlayer insulating layer IL beneath the conductive layer CD. In another example, with... Figure 3A Conversely, each of the multiple steps may include a single conductive layer CD and an interlayer insulating layer IL above the conductive layer CD. Although Figure 3A The steps are shown arranged in the X direction, but the shape of the stepped structure is not affected. Figure 3A The example limitations are as follows. For instance, a stacked structure STK may include steps arranged in the Y direction. In another example, a stacked structure STK may include steps arranged in both the X and Y directions. Additionally, Figure 3A The steps shown are only a part of the stack STK, and the number of steps can correspond to the number of conductive layers CD.

[0041] A dummy stack (DST) may include a sacrificial layer (SF) and an interlayer insulating layer (IL). The sacrificial layer (SF) and the interlayer insulating layer (IL) may be stacked alternately in the Z-direction. The sacrificial layer (SF) may include an insulating material that has etch selectivity relative to the interlayer insulating layer (IL). For example, the interlayer insulating layer (IL) may include an oxide layer (e.g., a silicon oxide layer), and the sacrificial layer (SF) may include a nitride layer. The sacrificial layer (SF) of the dummy stack (DST) may be located at the same height as the conductive layer (CD) of the stack (STK). The sacrificial layer (SF) may be spaced apart from the conductive layer (CD), and an isolation structure (SR) may be interposed therebetween. The interlayer insulating layer (IL) of the dummy stack (DST) may be located at the same height as the interlayer insulating layer (IL) of the stack (STK), and may include the same material.

[0042] The first upper insulating layer UIL1 can be disposed on the laminate STK and the dummy laminate DST. The first upper insulating layer UIL1 can cover the laminate STK and the dummy laminate DST. The first upper insulating layer UIL1 can cover the stepped structure of the laminate STK.

[0043] An isolation structure SR may be disposed between the laminate STK and the dummy laminate DST. The isolation structure SR can separate the dummy laminate DST from the laminate STK. In one embodiment, a preliminary laminate comprising sacrificial layers SF and interlayer insulating layers IL stacked alternately may be formed, and some of the sacrificial layers SF may be replaced by conductive layers CD to form the laminate STK. The sacrificial layers SF that are not replaced by the conductive layers CD and are retained constitute the dummy laminate DST. For example, although some sacrificial layers are removed from the preliminary laminate, the sacrificial layers SF corresponding to the dummy laminate DST are not removed by the isolation structure SR. The isolation structure SR may include an insulating material such as an oxide layer.

[0044] The source structure SC can be disposed below the stack STK. The source structure SC can overlap with the stack STK. The source structure SC can extend from the bottom of the stack STK to the bottom of the dummy stack DST. The source structure SC may include an upper source structure USC, an interlayer source structure FSC, and a lower source structure LSC. The interlayer source structure FSC can be located between the upper source structure USC and the lower source structure LSC. The source structure SC can correspond to... Figure 1 The source line SL.

[0045] In one implementation, after the lower source structure LSC, the source sacrificial layer, and the upper source structure USC are sequentially stacked to form the cell plug CPL, the source sacrificial layer can be replaced by an interlayer source structure FSC to form the source structure SC. Through the space created by the removal of the source sacrificial layer, a portion of the memory layer ML can be etched away to expose the channel layer CH. Therefore, the interlayer source structure FSC can directly contact the channel layer CH.

[0046] Each of the upper source structure (USC), the interlayer source structure (FSC), and the lower source structure (LSC) may include a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof). Each of the upper source structure (USC), the interlayer source structure (FSC), and the lower source structure (LSC) may include at least one of n-type and p-type impurities. For example, at least one of the upper source structure (USC), the interlayer source structure (FSC), or the lower source structure (LSC) may include a polycrystalline silicon layer doped with n-type impurities.

[0047] An insulating pattern IP may be disposed below the dummy stack DST. The insulating pattern IP may overlap at least a portion of the dummy stack DST. The insulating pattern IP may penetrate the source structure SC. The insulating pattern IP may be located at the same height as the source structure SC. The upper surface of the insulating pattern IP may be at the same height as the upper surface of the upper source structure USC, and the lower surface of the insulating pattern IP may be at the same height as the lower surface of the lower source structure LSC. The insulating pattern IP may include an insulating material (e.g., an oxide or a nitride).

[0048] Cell plugs (CPLs) can penetrate the stack-up layer (STK). Cell plugs (CPLs) can abut against the source structure (SC). Cell plugs (CPLs) can extend through the stack-up layer (STK) into the source structure (SC). Cell plugs (CPLs) can penetrate the upper source structure (USC) and the interlayer source structure (FSC), and can extend into the lower source structure (LSC). Memory layers (ML) can be disposed between the channel layer (CH) and the upper source structure (USC), and between the channel layer (CH) and the lower source structure (LSC). Memory layers (ML) are not disposed between the channel layer (CH) and the interlayer source structure (FSC). Therefore, the channel layer (CH) can directly contact the interlayer source structure (FSC).

[0049] Memory cells and select transistors can be formed at the intersection between the cell plug CPL and the conductive layer CD, respectively. The cell plug CPL can be used as the channel region of the cell string. For example, drain select transistors, memory cells, and source select transistors can be formed at the intersection between the cell plug CPL and the conductive layer CD, respectively.

[0050] Each cell plug CPL may include a memory layer ML, a channel layer CH, a core post CO, and a capping layer CAP. The memory layer ML may have a cylindrical shape. The memory layer ML may contact the laminate STK. Although not shown, the memory layer ML may include a barrier layer, a charge trapping layer, and a tunnel isolation layer. The barrier layer, charge trapping layer, and tunnel isolation layer may be sequentially disposed from the side surface of the laminate STK. The channel layer CH may be formed along the inner wall of the memory layer. The core post CO may have a columnar shape surrounded by the channel layer CH. The capping layer CAP may be attached to the channel layer CH on the core post CO.

[0051] The barrier layer and tunnel isolation layer included in the memory layer ML may comprise an oxide layer (e.g., a silicon oxide layer) or an oxide-oxygen nitride layer (e.g., a silicon oxynitride layer), or a combination thereof. The charge trapping layer included in the memory layer ML may comprise a nitride layer or a variable resistance material. The channel layer CH and the capping layer CAP may comprise undoped or doped silicon layers. The capping layer CAP and the channel layer CH may comprise the same material or a homogeneous material. Therefore, the interface between the capping layer CAP and the channel layer CH may be absent or not clearly observable. The core CO may comprise an insulating layer or a conductive layer.

[0052] The second upper insulating layer UIL2 can be disposed above the stack STK and the dummy stack DST. The second upper insulating layer UIL2 can cover the stack STK and the dummy stack DST. The second upper insulating layer UIL2 can overlap with the cell plug CPL. The second upper insulating layer UIL2 can abut against the upper surface of the first upper insulating layer UIL1.

[0053] The unit contact CCT may be formed in the second upper insulating layer UIL2. The unit contact CCT may penetrate the second upper insulating layer UIL2. The unit contact CCT may be individually connected to the unit plug CPL. The unit contact CCT may directly contact the capping layer CAP of the unit plug CPL. The unit contact CCT may include a conductive material such as tungsten.

[0054] Gate line contacts GCT can be connected to the conductive layer CD of the stack STK. Gate line contacts GCT can be electrically connected to the conductive layer CD. Gate line contacts GCT can contact the conductive layer CD. Gate line contacts GCT can contact the steps included in the stack STK. Gate line contacts GCT can extend from the conductive layer CD in the Z direction. Gate line contacts GCT can penetrate the first upper insulating layer UIL1 and the second upper insulating layer UIL2. Figure 3A Only some gate line contacts (GCTs) are shown in the diagram. The memory block may include a number of gate line contacts (GCTs) corresponding to the number of conductive layers (CDs) formed.

[0055] The peripheral circuit structure PC and substrate SUB may be located below the source structure SC and insulating pattern IP. The peripheral circuit structure PC may be located above the substrate SUB. The peripheral circuit structure PC may include transistors TR, peripheral contact plugs PPL, and peripheral lines PLN. Depending on the configuration of the peripheral circuit structure PC, the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may have various patterns. For example, the number or arrangement of transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may vary. A lower insulating layer LIL may be located between the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN. For example, the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may be formed in the lower insulating layer LIL. The lower insulating layer LIL may include an insulating material such as an oxide layer.

[0056] The peripheral circuit contact PCT can penetrate the dummy laminate DST and the insulating pattern IP. The peripheral circuit contact PCT can penetrate the sacrificial layer SF and the interlayer insulation layer IL of the dummy laminate DST. The peripheral circuit contact PCT can penetrate the first upper insulation layer UIL1 and the second upper insulation layer UIL2. The peripheral circuit contact PCT can extend into the lower insulation layer LIL to connect to the peripheral circuit structure PC. For example, the peripheral circuit contact PCT can contact at least one peripheral line PLN included in the peripheral circuit structure PC.

[0057] The peripheral circuit contact PCT may include a first portion PCT1 and a second portion PCT2. The first portion PCT1 may penetrate the insulating pattern IP and extend into the lower insulating layer LIL. The first portion PCT1 may be in direct contact with the peripheral line PLN. The second portion PCT2 may be located on top of the first portion PCT1. The second portion PCT2 may be electrically connected to the first portion PCT1. The second portion PCT2 may penetrate the dummy stack DST, the first upper insulating layer UIL1, and the second upper insulating layer UIL2. The width of the first portion PCT1 may be greater than the width of the second portion PCT2. The first portion PCT1 and the second portion PCT2 may each include a conductive material.

[0058] The third upper insulating layer UIL3, the fourth upper insulating layer UIL4, the fifth upper insulating layer UIL5, the sixth upper insulating layer UIL6, and the seventh upper insulating layer UIL7 may be sequentially stacked on top of the second upper insulating layer UIL2. The third upper insulating layer UIL3, the fifth upper insulating layer UIL5, and the seventh upper insulating layer UIL7 may include insulating materials such as oxide layers. The fourth upper insulating layer UIL4 and the sixth upper insulating layer UIL6 may include insulating materials such as nitride layers.

[0059] The wiring structure can be formed in the third upper insulating layer UIL3, the fourth upper insulating layer UIL4, the fifth upper insulating layer UIL5, the sixth upper insulating layer UIL6, and the seventh upper insulating layer UIL7. For example... Figure 3A The wiring structure shown is just an example; various other arrangements are also possible.

[0060] The first contact CT1 may be disposed within the third upper insulating layer UIL3. The first contact CT1 may penetrate the third upper insulating layer UIL3. The first contact CT1 may make contact with the unit contact CCT, the gate line contact GCT, and the peripheral circuit contact PCT, respectively. The first contact CT1 may be electrically connected to the unit contact CCT, the gate line contact GCT, and the peripheral circuit contact PCT, respectively. The first contact CT1 may include a conductive material.

[0061] The second contact CT2 may be disposed within the fourth upper insulating layer UIL4. The second contact CT2 may penetrate the fourth upper insulating layer UIL4. The second contact CT2 may contact the first contact CT1 respectively. The second contact CT2 may be electrically connected to the first contact CT1 respectively. The second contact CT2 may include conductive material.

[0062] The first upper wiring UL1 may be disposed within the fifth upper insulating layer UIL5. The first upper wiring UL1 may penetrate the fifth upper insulating layer UIL5. The first upper wiring UL1 may be electrically connected to the second contact CT2. The first upper wiring UL1 may extend in the horizontal direction. For example, the first upper wiring UL1 electrically connected to the cell plug CPL may correspond to a bit line (e.g., Figure 1The bit line BL in the middle). The first upper wiring UL1 may include conductive material.

[0063] The third contact CT3 can penetrate the sixth upper insulating layer UIL6. The third contact CT3 can be electrically connected to the first upper wiring UL1. The third contact CT3 can extend into the seventh upper insulating layer UIL7. The second upper wiring UL2 can be electrically connected to the third contact CT3. Figure 3A In the diagram, the third contact CT3 is shown as penetrating the bottom of the seventh upper insulating layer UIL7, not its top. However, Figure 3A The seventh upper insulating layer UIL7 can refer to multiple layers formed in multiple stages. The third contact CT3 and the second upper wiring UL2 may include conductive material.

[0064] The memory device according to this disclosure may include a support pattern SP. The memory device may include at least one support pattern SP. For example... Figure 3A As shown, the memory device may include all three support patterns (SP1, SP2, and SP3), but this is for illustrative purposes only, and the number of support patterns SP does not limit the scope of this disclosure. For example, the memory device may include the first support pattern SP1 and may not include the second support pattern SP2 and the third support pattern SP3. In another example, the memory device may include the second support pattern SP2 and may not include the first support pattern SP1 and the third support pattern SP3. In yet another example, the memory device may include the second support pattern SP2 and the third support pattern SP3 and may not include the first support pattern SP1. Hereinafter, the first support pattern SP1 to the third support pattern SP3 will be described in the same figure for ease of description.

[0065] Support patterns SP can be spaced apart from the stack STK. Support patterns SP can be spaced apart from the stack STK, the dummy stack DST, and the unit plug CPL. Each support pattern SP can be spaced apart from the stack STK in the vertical direction. For example, the first support pattern SP1 and the second support pattern SP2 can be located in the Z direction of the stack STK. Additionally, the third support pattern SP3 can be located in the opposite direction to the Z direction of the stack STK. The second support pattern SP2 and the third support pattern SP3 can be located at the upper and lower parts of the stack STK, respectively. The first support patterns SP1 to the third support patterns SP3 can be spaced apart from each other in the vertical direction. For example, the second support pattern SP2 and the third support pattern SP3 can be spaced apart from each other, and the stack STK is inserted between them.

[0066] The support pattern SP can extend in the horizontal direction. The support pattern SP can extend in both the X and Y directions. The support pattern SP can have a plate shape that extends in the horizontal direction.

[0067] The support pattern SP may have a mesh structure. The support pattern SP may have a grid pattern. (See reference...) Figures 3B to 3D The support pattern SP may include openings OP arranged in the X and Y directions. The openings OP may be continuously arranged in the support pattern SP. For example, in the support pattern SP, the openings OP may be continuously arranged in all regions except for the through region PP. The spacing between the openings OP in the support pattern SP may be constant. The openings OP may be equally spaced in the X direction. Additionally, the openings OP may be positioned at equal intervals in the Y direction. The openings OP may be filled with an insulating layer, such as a lower insulating layer LIL, a second upper insulating layer UIL2, or a seventh upper insulating layer UIL7.

[0068] For example, refer to Figure 3D The supporting pattern SP may include a first sub-pattern SSP1 extending in the X direction and a second sub-pattern SSP2 extending in the Y direction. The first sub-pattern SSP1 may be arranged in the Y direction. The second sub-pattern SSP2 may be arranged in the X direction. The first sub-pattern SSP1 and the second sub-pattern SSP2 may intersect each other. An opening OP may be located at these intersections between the first sub-pattern SSP1 and the second sub-pattern SSP2. In other words, the opening OP may be arranged in the X direction between adjacent first sub-patterns SSP1. Additionally, the opening OP may be arranged in the Y direction between adjacent second sub-patterns SSP2. The opening OP may have a square plan view.

[0069] The support pattern SP may include a through region PP. Contacts included in the memory device (e.g., cell contacts CCT, gate line contacts GCT, and peripheral circuit contacts PCT) may penetrate the support pattern SP through the through region PP. For example, the contacts may pass through the through region PP. The through region PP may be filled with an insulating layer (e.g., a lower insulating layer LIL, a second upper insulating layer UIL2, and a seventh upper insulating layer UIL7). These contacts may be spaced apart from the support pattern SP by the insulating layer.

[0070] The first support pattern SP1 may be formed in the seventh upper insulating layer UIL7. The first support pattern SP1 may be located between portions of the wiring structure above the stack STK. The first support pattern SP1 may extend through the wiring structure. (See reference...) Figure 3A and Figure 3BThe first support pattern SP1 may include a through region PP corresponding to the position of the third contact CT3. For example, the first support pattern SP1 may include two through regions PP. The first support pattern SP1 may include a through region PP through which the third contact CT3, connected to the gate line contact GCT, penetrates. The first support pattern SP1 may also include a through region PP through which the third contact CT3, connected to the peripheral circuit contact PCT, penetrates. The through region PP may be filled with a seventh upper insulating layer UIL7. The third contact CT3 may be surrounded by the seventh upper insulating layer UIL7. The third contact CT3 may be spaced apart from the first support pattern SP1 through the seventh upper insulating layer UIL7. The third contact CT3 may penetrate the first support pattern SP1 through the through region PP.

[0071] The second support pattern SP2 may be formed in the second upper insulating layer UIL2. The second support pattern SP2 may be located above the laminate STK. The second support pattern SP2 may extend between portions of the wiring structure connected to the laminate STK. (Refer to...) Figure 3A and Figure 3C The second support pattern SP2 may include through regions PP corresponding to the positions of the cell contact CCT, the gate line contact GCT, and the peripheral circuit contact PCT. For example, the second support pattern SP2 may include three through regions PP. The second support pattern SP2 may include through regions PP through which the cell contact CCT penetrates, through regions PP through which the gate line contact GCT penetrates, and through regions PP through which the second portion PCT2 of the peripheral circuit contact PCT penetrates. The through regions PP may be filled with a second upper insulating layer UIL2. The cell contact CCT, the gate line contact GCT, and the second portion PCT2 of the peripheral circuit contact PCT may contact the second upper insulating layer UIL2. The cell contact CCT, the gate line contact GCT, and the second portion PCT2 of the peripheral circuit contact PCT may be spaced apart from the second support pattern SP2 by the second upper insulating layer UIL2. The cell contact CCT, the gate line contact GCT, and the second portion PCT2 of the peripheral circuit contact PCT may extend into the through regions PP. The second part PCT2 of the unit contact CCT, gate line contact GCT and peripheral circuit contact PCT can penetrate the second support pattern SP2 through the through area PP.

[0072] The third support pattern SP3 can be formed in the lower insulating layer LIL. The third support pattern SP3 can be located below the stack-up STK. The third support pattern SP3 can be located in the peripheral circuit structure PC. (See reference...) Figure 3A and Figure 3DThe third support pattern SP3 may include a through region PP corresponding to the location of the peripheral circuit contact PCT. For example, the third support pattern SP3 may include a through region PP through which a first portion PCT1 of the peripheral circuit contact PCT penetrates. The through region PP may be filled with a lower insulating layer LIL. The first portion PCT1 of the peripheral circuit contact PCT may contact the lower insulating layer LIL. The first portion PCT1 of the peripheral circuit contact PCT may be spaced apart from the third support pattern SP3 by the lower insulating layer LIL. The first portion PCT1 of the peripheral circuit contact PCT may extend into the through region PP. The first portion PCT1 of the peripheral circuit contact PCT may penetrate the third support pattern SP3 through the through region PP.

[0073] The support pattern SP may have a stiffness higher than that of the interlayer insulating layer IL. Additionally, the support pattern SP may have a stiffness higher than that of the first upper insulating layer UIL1 through the seventh upper insulating layer UIL7 or the isolation structure SR. For example, the support pattern SP may include one or more of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), and copper (Cu). As used herein, the term "stiffness" refers to the property of a layer to maintain its shape without deformation even when stress is applied to it. The greater the maximum stress at which a material can maintain its shape without deformation when subjected to stress, the harder the material is considered to be. For example, oxide layers (e.g., silicon oxide layers) included in the first upper insulating layer UIL1 through the seventh upper insulating layer UIL7 or the isolation structure SR may maintain their shape up to 70 to 75 gigapascals (GPa). The support pattern SP may include silicon carbide that can maintain its current shape up to 450 GPa, aluminum oxide that can maintain its current shape up to 370 GPa, boron nitride that can maintain its current shape up to 360 GPa, tungsten carbide that can maintain its current shape up to 500 to 700 GPa, tungsten that can maintain its current shape up to 400 GPa, iron that can maintain its current shape up to 211 GPa, and copper that can maintain its current shape up to 130 GPa. Therefore, the stiffness of the support pattern SP can be higher than that of the first upper insulating layer UIL1 to the seventh upper insulating layer UIL7 or the isolation structure SR.

[0074] According to some embodiments, warping of the memory device can be reduced or prevented by a support pattern SP having high stiffness. The stiffness of the memory device can be increased by a support pattern SP extending in both the X and Y directions. The support pattern SP can have a mesh shape in all regions except for some areas forming contacts, thereby improving the in-plane stiffness of the memory device. Therefore, a memory device according to this disclosure including at least one support pattern SP may include little or no defects (e.g., cracks) that occur when the memory device bends.

[0075] Figures 4A to 4EThis is a diagram illustrating a method for manufacturing a support pattern SP according to an embodiment of the present disclosure.

[0076] Figures 4A to 4E A method for manufacturing the support pattern SP is shown. The following description can be adapted and applied. Figure 3A The first support pattern SP1 to the third support pattern SP3 are shown. For ease of explanation, a support pattern SP with a shape similar to the first support pattern SP1 is mainly described.

[0077] Reference Figure 4A A support layer SPL may be formed on the first insulating layer IIL1 and the second insulating layer IIL2. The support layer SPL may cover the first insulating layer IIL1 and the second insulating layer IIL2. The support layer SPL may extend in a horizontal direction (e.g., the X and Y directions). The support layer SPL may have a stiffness higher than that of the first insulating layer IIL1 and the second insulating layer IIL2. For example, the first insulating layer IIL1 may include a nitride layer, and the second insulating layer IIL2 may include an oxide layer. The support layer SPL may include one or more of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), and copper (Cu).

[0078] Subsequently, a hard mask HM can be formed on the support layer SPL. The hard mask HM can cover the support layer SPL. The hard mask HM can contact the upper surface of the support layer SPL. The hard mask HM may include a nitride material.

[0079] Reference Figure 4B A photoresist layer can be formed on a hard mask (HM). The photoresist layer can cover the hard mask (HM). The photoresist layer can include materials whose chemical properties change due to light.

[0080] Subsequently, a portion of the photoresist layer can be removed to form the photoresist PR. For example, a mask comprising light-transmitting and light-blocking areas can be aligned on the photoresist layer. Light can be applied to the photoresist layer using the mask. Exposed and unexposed areas within the photoresist layer can have different characteristics. Depending on the type of photoresist layer, exposed areas can be removed and unexposed areas can be retained, or unexposed areas can be removed and exposed areas can be retained. The remaining portion of the photoresist layer can be referred to as the photoresist PR. The photoresist PR may include openings corresponding to the areas of the photoresist layer that have been removed.

[0081] Subsequently, the hard mask HM and the support layer SPL can be etched using photoresist PR. By using the opening regions included in the photoresist PR, a portion of the hard mask HM and a portion of the support layer SPL can be removed. A portion of the support layer SPL can be removed to form the support pattern SP.

[0082] The support pattern SP may include openings OP arranged in the X and Y directions. The openings OP may be arranged continuously in the support pattern SP. For example, in the support pattern SP, the openings OP may be arranged continuously in all regions except for the through region PP. The spacing between the openings OP in the support pattern SP may be constant. The openings OP may be equally spaced in the X direction. The openings OP may be equally spaced in the Y direction.

[0083] The support pattern SP can have a mesh structure. The support pattern SP can have a lattice shape. For example, as shown in the reference... Figure 3D As shown, the support pattern SP may include a first sub-pattern SSP1 extending in the X direction and a second sub-pattern SSP2 extending in the Y direction. The opening OP may be located between the first sub-pattern SSP1 and the second sub-pattern SSP2.

[0084] The support pattern SP may include through regions PP. Each through region PP may have an area larger than that of each opening OP. The through region PP may be surrounded by the opening OP. The position of the through region PP may be determined by the position where the contact is formed.

[0085] In one embodiment, the through region PP and the opening OP can be formed simultaneously. In another embodiment, the through region PP and the opening OP may not be formed simultaneously. For example, the opening OP can be formed first, and then the through region PP can be formed using a separate photoresist. In another example, the through region PP can be formed first, and then the opening OP can be formed using a separate photoresist.

[0086] Reference Figure 4C It can remove photoresist (PR) and hard mask (HM).

[0087] Reference Figure 4D A third insulating layer IIL3 can be formed to cover the support pattern SP. The third insulating layer IIL3 can fill the opening OP and the through area PP of the support pattern SP. The third insulating layer IIL3 may include a material equivalent to the second insulating layer IIL2. The interface between the second insulating layer IIL2 and the third insulating layer IIL3 may not exist or may not be clearly observed.

[0088] Reference Figure 4E A contact CTT can be formed extending into the through-area PP. The contact CTT can penetrate the first insulating layer IIL1 and the second insulating layer IIL2. The contact CTT can penetrate a portion of the third insulating layer IIL3 that fills the through-area PP. The contact CTT may include... Figure 3AThe third contact CT3, cell contact CCT, gate line contact GCT, or peripheral circuit contact PCT are used. Additionally, wiring LN can be formed above contact CTT. Wiring LN can contact the upper surface of contact CTT. Contact CTT and wiring LN can be formed simultaneously, or wiring LN can be formed after contact CTT. Wiring LN can be surrounded by a third insulating layer IIL3.

[0089] like Figures 3B to 3D and Figures 4A to 4E The mesh structure of the support pattern SP shown is illustrative and does not limit the scope of this disclosure. See below for reference. Figure 5A and Figure 5B Describe the various forms of mesh structures supporting the pattern SP.

[0090] Figure 5A and Figure 5B This is a diagram illustrating various embodiments of the support pattern SP according to the present disclosure.

[0091] Reference Figure 5A The opening OP can have different widths in the X and Y directions. The opening OP can have a rectangular planar shape. The spacing between the second sub-patterns SSP2 can be greater than the spacing between the first sub-patterns SSP1.

[0092] Reference Figure 5B The orientation of the opening OP may not be the X and Y directions. For example, the opening OP can be arranged in a first direction and a second direction, where the first direction may be between the X and Y directions, and the second direction may be opposite to the X direction and between the Y and X directions. The first sub-pattern SSP1 may extend in the first direction, and the second sub-pattern SSP2 may extend in the second direction.

[0093] Figure 5A and Figure 5B Here are some examples of structures corresponding to the support pattern SP. The support pattern SP can have various other shapes. For example, the opening OP can be rectangular and arranged in a first direction and a second direction. In another example, the opening OP can be rhomboid, circular, or elliptical in shape, rather than square or rectangular. In yet another example, the opening OP can have different areas, the spacing between the opening OPs may be uneven, or they may only be formed in a portion of the total area of ​​the support pattern SP.

[0094] Figure 6 This is a block diagram illustrating a memory card system 3000 according to an embodiment of the present disclosure.

[0095] Reference Figure 6 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0096] Controller 3100 may be coupled to memory device 3200. Controller 3100 may access memory device 3200. For example, controller 3100 may control programming operations, read operations, erase operations, or background operations of memory device 3200. Controller 3100 may be configured to provide an interface between memory device 3200 and a host. Controller 3100 may be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0097] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. For example, controller 3100 can communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 3300 may be defined by at least one of the aforementioned communication protocols.

[0098] Memory device 3200 may include a plurality of memory cells and in accordance with Figure 1 The memory device 100 shown is configured in the same manner.

[0099] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as PCMCIA cards, compact flash memory (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), universal flash memory (UFS), etc.

[0100] Figure 7 This is a block diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0101] Reference Figure 7The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 via a signal connector 4001 and may receive power via a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0102] The controller 4210 can control a plurality of memory devices 4221 to 422n in response to signals received from the host 4100. In an embodiment, the signals may be based on the interface between the host 4100 and the SSD 4200. For example, the signals may be defined by at least one of a variety of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0103] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured in accordance with... Figure 1 The memory device 100 shown is configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0104] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be supplied with power from host 4100 and used for charging. When there is no smooth power supply from host 4100, auxiliary power supply 4230 can supply power to SSD 4200. In implementations, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located in the motherboard and supply auxiliary power to SSD 4200.

[0105] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM and PRAM.

[0106] According to some embodiments of this disclosure, warping of the memory device can be reduced or prevented by adding structural configurations.

[0107] It will be apparent to those skilled in the art that various modifications can be made to the above-described embodiments of this disclosure without departing from the spirit or scope of the invention. Therefore, the invention is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0108] Cross-references to related applications

[0109] This application claims priority to Korean Patent Application No. 10-2025-0015736, filed on February 7, 2025, with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: A laminate comprising conductive layers and interlayer insulating layers stacked alternately on top of each other; A unit plug that penetrates the stack; A support pattern, which is spaced apart from the stack and the unit plug, includes a through area; as well as The contact point penetrates the support pattern through the through area. The support pattern includes openings arranged in a first direction and a second direction in which the support pattern extends.

2. The memory device according to claim 1, wherein, The stiffness of the support pattern is higher than that of the interlayer insulation layer.

3. The memory device according to claim 1, wherein, The support pattern includes at least one of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), and copper (Cu).

4. The memory device according to claim 1, wherein, The support pattern is spaced apart from the stack in the direction in which the conductive layer and the interlayer insulating layer are alternately stacked.

5. The memory device according to claim 1, wherein, The conductive layer and the interlayer insulating layer are alternately stacked in a direction perpendicular to the plane defined by the first direction and the second direction extending from the support pattern.

6. The memory device according to claim 1, wherein, The support pattern includes a mesh structure.

7. The memory device according to claim 1, wherein, The support pattern includes: A first sub-pattern, the first sub-pattern extending in the first direction; and The second sub-pattern extends in the second direction, and Each of the openings is located at the intersection between a first sub-pattern in the first sub-pattern and a second sub-pattern in the second sub-pattern.

8. The memory device according to claim 1, wherein, The openings are arranged continuously in the support pattern, except for the through area of ​​the support pattern.

9. The memory device according to claim 1, wherein, The openings are spaced at regular intervals in the support pattern.

10. The memory device of claim 1, further comprising: A first insulating layer fills the through region; as well as A second insulating layer fills the opening.

11. The memory device according to claim 10, wherein, The contact penetrates the first insulating layer and separates from the support pattern through the first insulating layer.

12. The memory device of claim 1, further comprising a peripheral circuit structure located beneath the stack, in, The support pattern is located in the peripheral circuit structure.

13. The memory device of claim 1, further comprising a dummy stack located in the first direction of the stack, in, The contacts include peripheral circuit contacts that penetrate the dummy stack, and The peripheral circuit contacts extend through the through area of ​​the support pattern.

14. The memory device of claim 1, further comprising a first upper insulating layer disposed above the laminate. in, The support pattern is located in the first upper insulating layer.

15. The memory device according to claim 14, wherein, The contacts include unit contacts that penetrate the first upper insulating layer and are connected to the unit plug, and The unit contact extends through the through area of ​​the support pattern.

16. The memory device according to claim 1, wherein, The contacts include gate line contacts respectively connected to the conductive layer, and The gate line contact extends through the through region of the support pattern.

17. The memory device of claim 1, further comprising a wiring structure disposed over the stack, in, The support pattern extends through the wiring structure.

18. A method of manufacturing a memory device, the method comprising the steps of: A support layer extending in the first and second directions is formed; A support pattern is formed including openings arranged in the first direction and the second direction, and a through area with a width greater than the width of the opening is formed by removing a portion of the support layer; An insulating layer is formed to fill the opening and the through area; as well as A contact is formed that penetrates the insulating layer and extends through the through area.

19. The method according to claim 18, wherein, The support layer is formed to include at least one of silicon carbide (SiC), aluminum oxide (Al2O3), boron nitride (BN), tungsten carbide (WC), tungsten (W), iron (Fe), and copper (Cu).

20. The method according to claim 18, wherein, The support layer is formed to extend in the first direction and the second direction.

21. The method according to claim 18, wherein, The support pattern is formed to include a mesh structure.

22. The method according to claim 18, wherein, The support pattern is formed to include: A first sub-pattern, the first sub-pattern extending in the first direction; and The second sub-pattern extends in the second direction. Each of the openings is located at the intersection between a first sub-pattern in the first sub-pattern and a second sub-pattern in the second sub-pattern.

23. The method according to claim 18, wherein, The support pattern is formed such that the opening is continuously arranged in the support pattern except for the through area of ​​the support pattern.

Images