Three-dimensional memory device

Abstract

Embodiments of 3D memory devices and methods of forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including alternating conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, and a source contact above the memory stack and in contact with the P-type doped semiconductor layer. An upper end of each channel structure of the plurality of channel structures is flush with or below a top surface of the P-type doped semiconductor layer.

Description

[0001] This application is a divisional application of the invention patent application filed on May 27, 2020, with application number 202210417278.3 and entitled "Three-dimensional storage device". Technical Field

[0002] Embodiments of this disclosure relate to three-dimensional (3D) storage devices and methods for manufacturing the same. Background Technology

[0003] Improvements in process technology, circuit design, algorithms, and fabrication techniques have enabled planar memory cells to be shrunk to even smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and fabrication technologies become more difficult and costly. Therefore, the storage density for planar memory cells is nearing its upper limit.

[0004] 3D memory architecture can overcome the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals traveling to and from the memory array. Summary of the Invention

[0005] This article discloses embodiments of 3D storage devices and methods for forming the same.

[0006] In one example, a 3D memory device includes a substrate; peripheral circuitry on the substrate; a memory stack above the peripheral circuitry comprising alternating conductive and dielectric layers; a p-type doped semiconductor layer above the memory stack; a plurality of channel structures, each extending vertically through the memory stack into the p-type doped semiconductor layer; and a source contact above the memory stack and in contact with the p-type doped semiconductor layer. The upper end of each of the plurality of channel structures is flush with or below the top surface of the p-type doped semiconductor layer.

[0007] In another example, a 3D memory device includes: a substrate; a memory stack comprising alternating conductive and dielectric layers above the substrate; a P-type doped semiconductor layer above the memory stack; an N-well in the P-type doped semiconductor layer; a plurality of channel structures, each channel structure extending vertically through the memory stack into the P-type doped semiconductor layer; a first source contact above the memory stack and in contact with the P-type doped semiconductor layer; and a second source contact above the memory stack and in contact with the N-well.

[0008] In another example, a 3D memory device includes: a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes: a memory stack comprising alternating conductive and dielectric layers, a p-type doped semiconductor layer, and a plurality of channel structures, each of said channel structures extending vertically through the memory stack into the p-type doped semiconductor layer and electrically connected to the peripheral circuitry. The p-type doped semiconductor layer includes semiconductor plugs extending into the p-type doped semiconductor layer surrounding a portion of each of the plurality of channel structures. The doping concentration of the semiconductor plugs differs from the doping concentration of the remainder of the p-type doped semiconductor layer. Attached Figure Description

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0010] Figure 1 A side view of a cross-section of an exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0011] Figure 2 A side view of a cross section of another exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0012] Figure 3A –3N illustrates a fabrication process for forming exemplary 3D storage devices according to some embodiments of the present disclosure.

[0013] Figure 4A-4O A fabrication process for forming another exemplary 3D storage device is illustrated according to some embodiments of the present disclosure.

[0014] Figure 5A A flowchart is shown of a method for forming an exemplary 3D storage device according to some embodiments of the present disclosure.

[0015] Figure 5B A flowchart is shown of another method for forming an exemplary 3D storage device according to some embodiments of the present disclosure.

[0016] Figure 6A A flowchart of a method for forming another exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0017] Figure 6B A flowchart is shown of another method for forming another exemplary 3D storage device according to some embodiments of the present disclosure.

[0018] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0019] Although specific configurations and arrangements have been discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a wide variety of other applications.

[0020] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an example embodiment," or "some embodiments" in the specification indicates that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when describing a specific feature, structure, or characteristic in conjunction with embodiments, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0021] Generally, terms can be understood at least partly by their use in context. For example, the word "one or more" can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "a," "one," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood to not necessarily convey an exclusive set of factors, and conversely, again at least partly depending on the context, may allow for additional factors that are not necessarily explicitly stated.

[0022] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest terms. “On” means not only being directly on something, but also being contained on something, with an intermediate feature or layer in between. “Above” or “on top of” means not only being contained above or on something, but also being contained above or on something, without an intermediate feature or layer in between (i.e., being directly on something).

[0023] Furthermore, for ease of explanation, spatial relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0024] The term "substrate" as used in this text refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be formed from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0025] As used herein, the term "layer" can refer to a portion of material comprising a region of a certain thickness. A layer may extend over the entire underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor layers and contact layers (in which interconnect lines and / or vertical interconnect channels (via) contacts are formed) and one or more dielectric layers.

[0026] As used herein, the term "nominal / nominally" refers to the expected or target value of a feature or parameter of a component or process operation set during the design phase of a product or process, along with a range of values ​​higher and / or lower than said expected value. This range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" means a given quantity of value that can vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" may indicate that the given quantity of value varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0027] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND memory strings) situated on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate. The term "vertically" as used herein refers to a lateral surface nominally perpendicular to the substrate.

[0028] In some 3D memory devices (e.g., 3D NAND memory devices), gap structures (e.g., gate line gaps (GLS)) are used to provide electrical connections from the front side of the device to the sources of the memory array (e.g., array common source (ACS)). However, the front-side source contacts can affect the electrical performance of the 3D memory device by introducing both leakage current and parasitic capacitance between the word lines and source contacts (even when spacers are present). The formation of spacers also complicates the fabrication process. In addition to affecting electrical performance, gap structures often consist of walled polysilicon and / or metal filling, which can introduce localized stresses, leading to wafer bowing or warping, thereby reducing yield.

[0029] Furthermore, in some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of the channel structure; this is known as sidewall selective epitaxial growth (SEG). Compared to another type of semiconductor plug formed at the bottom of the channel structure (e.g., bottom SEG), the formation of sidewall SEGs avoids etching of the memory film and semiconductor channel at the bottom surface of the channel via (also known as "SONO" vias), thereby increasing the process window, especially when fabricating 3D NAND memory devices using advanced techniques, such as when there are 96 or more levels in the case of a multi-deck architecture. Sidewall SEGs are often formed by replacing the sacrificial layer between the substrate and the stacked bulk structure using sidewall SEGs, which involves multiple deposition and etching processes through the slot opening. However, as the number of stages in 3D NAND memory devices continues to increase, the aspect ratio of the slot openings extending through the stacked structure becomes larger, making deposition and etching processes through the slot openings more challenging and undesirable for forming sidewall SEGs using known methods due to increased costs and decreased yields.

[0030] Various embodiments of this disclosure provide 3D memory devices with back-side source contacts. By moving the source contacts from the front to the back, the cost per memory cell can be reduced because the effective memory cell array area can be increased, and spacer body formation processes can be skipped. Device performance can also be improved, for example, by avoiding leakage current and parasitic capacitance between word lines and source contacts, and by reducing localized stress caused by the front-side gap structure (as source contacts). Sidewall SEGs (e.g., semiconductor plugs) can be formed from the back side of the substrate to avoid any deposition or etching processes on the front side of the substrate by extending through openings in the stacked body structure. Therefore, the complexity and cost of the fabrication process can be reduced, and yield can be increased. Moreover, since the fabrication process of the sidewall SEGs is no longer affected by the aspect ratio of the openings through the stacked body structure, i.e., not limited by the levels of the memory stack, the scalability of the 3D memory device can also be improved.

[0031] In some embodiments, the substrate on which the memory stack is formed is removed from the back side, thereby exposing the channel structure prior to the formation of the sidewall SEG. Therefore, the choice of substrate can be extended to, for example, dummy wafers to reduce costs, or to silicon-on-insulator (SOI) wafers to simplify the fabrication process. Removing the substrate also avoids the challenging problem of thickness uniformity control in known methods using back-side thinning processes.

[0032] This disclosure discloses various 3D memory device architectures and methods for fabricating them, which, for example, have different erasure operation mechanisms to suit different requirements and applications. In some embodiments, the sidewall SEG is a portion of an N-type doped semiconductor layer, thereby enabling gate-induced-drain-leakage (GIDL) erasure by the 3D memory device. In some embodiments, the sidewall SEG is a portion of a P-type doped semiconductor layer, thereby enabling P-well bulk erasing by the 3D memory device.

[0033] Figure 1 A side view of a cross-section of an exemplary 3D memory device 100 according to some embodiments of the present disclosure is shown. In some embodiments, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are connected at a bonding interface 106 therebetween. Figure 1 As shown, the first semiconductor structure 102 may include a substrate 101, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable material.

[0034] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuitry 108 on a substrate 101. It should be noted that, in Figure 1 Includes x shaft and y The axis is used to further illustrate the spatial relationships of components in a 3D memory device 100 having a substrate 101. The substrate 101 includes axes along... x Two lateral surfaces (e.g., top and bottom surfaces) extending laterally in the direction (i.e., the lateral direction). As used herein, when the substrate is in y When a component (e.g., a layer or device) of a semiconductor device (e.g., a 3D memory device 100) is positioned "above," "on top of," or "below" another component (e.g., a layer or device) along the direction of the lowest plane of the semiconductor device, the orientation of the component is determined by the direction of the semiconductor device (e.g., a 3D memory device 100).y The direction (i.e., the vertical direction) is determined relative to the substrate of the semiconductor device (e.g., substrate 101). The same concept will be used throughout this disclosure to describe spatial relationships.

[0035] In some embodiments, peripheral circuitry 108 is configured to control and sense the 3D memory device 100. Peripheral circuitry 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 100, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of said circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 108 can include transistors formed "on" substrate 101, wherein all or part of the transistors are formed in the semiconductor layer 101 (e.g., below the top surface of substrate 101) and / or directly on substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) can also be formed in substrate 101. According to some embodiments, transistors are high-speed thanks to advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It should be understood that in some embodiments, peripheral circuitry 108 may further include any other circuitry compatible with advanced logic processes, including logic circuitry such as processors and programmable logic devices (PLDs) or memory circuitry such as static random access memory (SRAM) and dynamic RAM (DRAM).

[0036] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 to transmit electrical signals to and from the peripheral circuitry 108. The interconnect layer may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect access (via) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-process (BEOL) interconnects. The interconnect layer may further include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which the interconnects and via contacts may be formed. That is, the interconnect layer may include interconnects and via contacts in multiple ILD layers. The interconnects and via contacts in the interconnect layer may be encapsulated in conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof.

[0037] like Figure 1 As shown, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 located at the bonding interface 106 and above the interconnect layer and peripheral circuitry 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric material electrically isolating the bonding contacts 111. The bonding contacts 111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 110 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 111 in the bonding layer 110 and the surrounding dielectric material may be used for hybrid bonding.

[0038] Similarly, such as Figure 1 As shown, the second semiconductor structure 104 of the 3D memory device 100 may also include a bonding layer 112 located at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric material electrically isolating the bonding contacts 113. The bonding contacts 113 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 112 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 113 in the bonding layer 112 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 113 are in contact with the bonding contacts 111 at the bonding interface 106.

[0039] As detailed below, the second semiconductor structure 104 can be bonded to the top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 110 and 112 as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness comprising the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0040] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 for transmitting electrical signals. This interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in the interconnect layer may be encapsulated in a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0041] In some embodiments, the 3D memory device 100 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings. For example... Figure 1 As shown, the second semiconductor structure 104 of the 3D memory device 100 may include an array of channel structures 124 that function as an array of NAND memory strings. Figure 1As shown, each channel structure 124 may extend vertically through multiple pairs, each pair including a conductive layer 116 and a dielectric layer 118. Alternating conductive layers 116 and dielectric layers 118 form part of a memory stack 114. The number of pairs of conductive layers 116 and dielectric layers 118 in the memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the 3D memory device 100. It should be understood that in some embodiments, the memory stack 114 may have a multi-level architecture (not shown) comprising multiple memory levels stacked one on top of the other. The number of pairs of conductive layers 116 and dielectric layers 118 in each memory level may be the same or different.

[0042] The memory stack 114 may include a plurality of alternating conductive layers 116 and dielectric layers 118. The conductive layers 116 and dielectric layers 118 in the memory stack 114 may alternate in the vertical direction. In other words, except for the layers located at the top or bottom of the memory stack 114, each conductive layer 116 may be adjacent to two dielectric layers 118 on both sides, and each dielectric layer 118 may be adjacent to two conductive layers 116 on both sides. The conductive layers 116 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer 116 may include a gate electrode (gate line) surrounded by a binder layer and a gate dielectric layer. The gate electrode of the conductive layer 116 may extend laterally as a word line, terminating at one or more stepped structures of the memory stack 114. The dielectric layers 118 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0043] like Figure 1As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include an N-type doped semiconductor layer 120 above the memory stack 114. The N-type doped semiconductor layer 120 may be an example of a “sidewall SEG” as described above. The N-type doped semiconductor layer 120 may include a semiconductor material, such as silicon. In some embodiments, the N-type doped semiconductor layer 120 comprises polycrystalline silicon formed by a deposition technique, as detailed below. In some embodiments, the N-type doped semiconductor layer 120 comprises single-crystal silicon, such as a device layer of an SOI wafer, as detailed below. The N-type doped semiconductor layer 120 may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and improve the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer 120 may be a polycrystalline silicon layer doped with N-type dopant such as P, Ar, or Sb. In some embodiments, the N-type doped semiconductor layer 120 is a single polysilicon layer having a uniform doping concentration distribution in the vertical direction, as opposed to a polysilicon sublayer having a non-uniform doping concentration at its interfaces (e.g., a sudden change in doping concentration at the interface between two sublayers). It should be understood that the doping concentration of the N-type dopant in the N-type doped semiconductor layer 120 can still vary gradually in the vertical direction, as long as there are no sudden changes in doping concentration that can distinguish between two or more sublayers based on the doping concentration variation.

[0044] In some embodiments, each channel structure 124 includes a channel via filled with a semiconductor layer (e.g., as a semiconductor channel 128) and a composite dielectric layer (e.g., as a storage film 126). In some embodiments, the semiconductor channel 128 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film 126 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. The remaining space of the channel structure 124 may be partially or entirely filled with a capping layer including a dielectric material (e.g., silicon oxide) and / or air gaps. The channel structure 124 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer, the semiconductor channel 128, and the tunneling layer, storage layer, and barrier layer of the storage film 126 are arranged radially from the center of the column to the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 126 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0045] In some embodiments, the channel structure 124 further includes a channel plug 129 located in the bottom portion (e.g., at the lower end) of the channel structure 124. As used herein, when the substrate 101 is placed in the lowest plane of the 3D memory device 100, the “upper end” of the component (e.g., the channel structure 124) is... y The end that is farther from the substrate 101 in the direction, and the "lower end" of the component (e.g., the channel structure 124) is in y The end closer to the substrate 101 in the direction. The channel plug 129 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 serves as the drain of a NAND memory string.

[0046] like Figure 1 As shown, each channel structure 124 can extend vertically through the alternating conductive layers 116 and dielectric layers 118 of the memory stack 114 into the N-type doped semiconductor layer 120. The upper end of each channel structure 124 can be flush with or below the top surface of the N-type doped semiconductor layer 120. That is, according to some embodiments, the channel structure 124 does not extend beyond the top surface of the N-type doped semiconductor layer 120. In some embodiments, the upper end of the memory film 126 is below the upper end of the semiconductor channel 128 in the channel structure 124, such as... Figure 1 As shown. In some embodiments, the upper end of the storage film 126 is below the top surface of the N-type doped semiconductor layer 120, and the upper end of the semiconductor channel 128 is flush with or below the top surface of the N-type doped semiconductor layer 120. For example, as Figure 1 As shown, the storage film 126 may terminate at the bottom surface of the N-type doped semiconductor layer 120, while the semiconductor channel 128 may extend above the bottom surface of the N-type doped semiconductor layer 120, such that the N-type doped semiconductor layer 120 may surround and contact the top portion 127 of the semiconductor channel 128 extending into the N-type doped semiconductor layer 120. In some embodiments, the doping concentration of the top portion 127 of the semiconductor channel 128 extending into the N-type doped semiconductor layer 120 is different from the doping concentration of the rest of the semiconductor channel 128. For example, the semiconductor channel 128 may include undoped polysilicon in addition to the top portion 127, which may include doped polysilicon to improve its conductivity when forming an electrical connection with the surrounding N-type doped semiconductor layer 120.

[0047] In some embodiments, the N-type doped semiconductor layer 120 includes semiconductor plugs 122, each semiconductor plug surrounding and contacting a top portion 127 of a corresponding semiconductor channel 128 of the channel structure 124 extending into and in contact with said top portion 127. According to some embodiments, the semiconductor plugs 122 comprise doped polysilicon, for example, N-type doped polysilicon. The doping concentration of the semiconductor plugs 122 may differ from the doping concentration of the remainder of the N-type doped semiconductor layer 120 because the semiconductor plugs 122 may be formed in a later process after the formation of the remainder of the N-type doped semiconductor layer 120, as described in detail below. In some embodiments, the semiconductor plugs 122 comprise polysilicon (e.g., N-type doped polysilicon), and the remainder of the N-type doped semiconductor layer 120 comprises monocrystalline silicon (e.g., N-type doped monocrystalline silicon). In some embodiments, the semiconductor plug 122 comprises polysilicon (e.g., N-type doped polysilicon), and the remainder of the N-type doped semiconductor layer 120 comprises polysilicon (e.g., N-type doped polysilicon), but with a different doping concentration than that of the semiconductor plug 122.

[0048] Each semiconductor plug 122 may surround and contact the sidewall of the top portion 127 of the corresponding semiconductor channel 128. Therefore, the semiconductor plug 122 in the N-type doped semiconductor layer 120 can function as a "sidewall SEG (e.g., semiconductor plug)" for the channel structure 124, instead of a "bottom SEG (e.g., semiconductor plug)". Furthermore, as detailed below, the semiconductor plug 122 is formed on opposite sides of the memory stack 114, which avoids any deposition or etching processes through openings in the memory stack 114, thereby reducing fabrication complexity and cost and improving yield and vertical scalability. Depending on the relative position of the upper end of the semiconductor channel 128 of each channel structure 124 with respect to the top surface of the N-type doped semiconductor layer 120, the semiconductor plug 122 may also be formed above and in contact with the upper end of the semiconductor channel 128, for example, as... Figure 1 As shown, this occurs when the upper end of the semiconductor channel 128 is below the top surface of the N-type doped semiconductor layer 120. It should be understood that in other examples where the upper end of the semiconductor channel 128 is flush with the top surface of the N-type doped semiconductor layer 120, the semiconductor plug 122 may be formed to surround and contact only the sidewall of the top portion 127 of the semiconductor channel 128.

[0049] However, the N-type doped semiconductor layer 120 surrounding the top portion 127 of the semiconductor channel 128 of the channel structure 124 with semiconductor plugs 122 (e.g., as sidewall SEG) enables GIDL-assisted body bias for erase operations on the 3D memory device 100. The GIDL surrounding the source select gate of the NAND memory string generates hole currents flowing into the NAND memory string to increase the body potential for the erase operation.

[0050] like Figure 1 As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include insulating structures 130, each insulating structure 130 extending vertically through alternating conductive layers 116 and dielectric layers 118 of the memory stack 114. According to some embodiments, unlike the channel structure 124 which extends further into the N-type doped semiconductor layer 120, the insulating structure 130 terminates at the bottom surface of the N-type doped semiconductor layer 120, i.e., it does not extend vertically into the N-type doped semiconductor layer 120. That is, the top surface of the insulating structure 130 may be flush with the bottom surface of the N-type doped semiconductor layer 120. Each insulating structure 130 may also extend laterally, thereby dividing the channel structure 124 into multiple blocks. In other words, the memory stack 114 may be divided into multiple memory blocks by the insulating structures 130, such that an array of channel structures 124 can be allocated to each memory block. Unlike the slit structures in existing 3D NAND memory devices described above that include front-side ACS contacts, according to some embodiments, the insulating structure 130 does not contain any contacts (i.e., it does not function as source contacts), and therefore, no parasitic capacitance and leakage current are introduced with respect to the conductive layer 116 (including word lines). In some embodiments, each insulating structure 130 includes openings (e.g., slits) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 may be filled with silicon oxide.

[0051] Furthermore, as detailed below, since the opening used to form the insulating structure 130 is not used to form the N-type doped semiconductor layer 120 and the semiconductor plug 122 therein (e.g., sidewall SEG), the increased aspect ratio of the opening will not affect the formation of the N-type doped semiconductor layer 120 and the semiconductor plug 122 therein as the number of alternating conductive layers 116 and dielectric layers 118 increases.

[0052] 3D memory device 100 may not include a front source contact, but may include a back source contact 132 located above the memory stack 114 and in contact with the N-type doped semiconductor layer 120, such as... Figure 1As shown. The source contact 132 and the storage stack 114 (and the insulating structure 130 passing through it) can be positioned on opposite sides of the N-type doped semiconductor layer 120 and are therefore considered "back" source contacts. In some embodiments, the source contact 132 is electrically connected to the semiconductor channel 128 of the channel structure 124 via a semiconductor plug 122 of the N-type doped semiconductor layer 120. In some embodiments, the source contact 132 is not laterally aligned with the insulating structure 130, but is closer to the channel structure 124 to reduce the resistance of the electrical connection therebetween. For example, the source contact 132 may be laterally positioned between the insulating structure 130 and the channel structure 124 (e.g., in...). Figure 1 In x (Direction). Source contact 132 may include any suitable type of contact. In some embodiments, source contact 132 includes a through-hole contact. In some embodiments, source contact 132 includes a laterally extending wall-like contact. Source contact 132 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by a binder layer (e.g., titanium nitride (TiN)).

[0053] like Figure 1 As shown, the 3D memory device 100 may further include a BEOL interconnect layer 133 located above and electrically connected to the source contacts 132 to enable pad take-off, for example, to transmit electrical signals between the 3D memory device 100 and external circuitry. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on an N-type doped semiconductor layer 120 and a redistribution layer 136 on the ILD layers 134. According to some embodiments, the upper end of the source contacts 132 is flush with the top surface of the ILD layers 134 and the bottom surface of the redistribution layer 136, and the source contacts 132 extend vertically through the ILD layers 134 into the N-type doped semiconductor layer 120. The ILD layers 134 in the interconnect layer 133 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in interconnect layer 133 may contain a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, redistribution layer 136 comprises Al. In some embodiments, interconnect layer 133 further includes a passivation layer 138 as the outermost layer for passivation and protection of the 3D memory device 100. Portions of redistribution layer 136 may be exposed from passivation layer 138 to serve as contact pads 140. That is, interconnect layer 133 of 3D memory device 100 may also include contact pads 140 for wire bonding and / or bonding with interposers.

[0054] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 extending through the N-type doped semiconductor layer 120. According to some embodiments, since the N-type doped semiconductor layer 120 may be a thinned substrate, such as a device layer of an SOI wafer, contacts 142 and 144 are through-silicon contacts (TSCs). In some embodiments, contact 142 extends through the N-type doped semiconductor layer 120 and the ILD layer 134 to contact the redistribution layer 136, such that the N-type doped semiconductor layer 120 is electrically connected to contact 142 via the source contact 132 and the redistribution layer 136 of the interconnect layer 133. In some embodiments, contact 144 extends through the N-type doped semiconductor layer 120 and the ILD layer 134 to contact contact pads 140. Each of contacts 142 and 144 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by a binder layer (e.g., TiN). In some embodiments, at least contact 144 further includes a spacer (e.g., a dielectric layer) to electrically isolate contact 144 from N-type doped semiconductor layer 120.

[0055] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148, each extending vertically outside the memory stack 114. Each peripheral contact 146 or 148 may have a depth greater than the memory stack 114 to extend vertically from the bonding layer 112 to the N-type doped semiconductor layer 120 in a peripheral region outside the memory stack 114. In some embodiments, peripheral contact 146 is below and in contact with contact 142, such that the N-type doped semiconductor layer 120 is electrically connected to peripheral circuitry 108 in the first semiconductor structure 102 at least through source contact 132, interconnect layer 133, contact 142, and peripheral contact 146. In some embodiments, peripheral contact 148 is below and in contact with contact 144, such that peripheral circuitry 108 in the first semiconductor structure 102 is electrically connected to contact pads 140 for pad routing at least through contact 144 and peripheral contact 148. Peripheral contacts 146 and 148 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0056] like Figure 1As shown, the 3D memory device 100 also includes various local contacts (also referred to as "C1") as part of an interconnect structure that directly contact the structure within the memory stack 114. In some embodiments, these local contacts include channel local contacts 150, each channel local contact being below and contacting the lower end of a corresponding channel structure 124. Each channel local contact 150 may be electrically connected to bit line contacts (not shown) to implement bit line fan-out. In some embodiments, the local contacts further include word line local contacts 152, each word line local contact being below and contacting the corresponding conductive layer 116 (including the word line) at a stepped structure of the memory stack 114 for word line fan-out. The local contacts (such as channel local contacts 150 and word line local contacts 152) may be electrically connected to the peripheral circuitry 108 of the first semiconductor structure 102 at least via bonding layers 112 and 110. Each of the local contacts (such as channel local contact 150 and word line local contact 152) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0057] Figure 2 A cross-sectional side view of another exemplary 3D memory device 200 according to some embodiments of the present disclosure is shown. In some embodiments, the 3D memory device 200 is a bonded chip including a first semiconductor structure 202 and a second semiconductor structure 204 stacked on top of the first semiconductor structure 202. According to some embodiments, the first semiconductor structure 202 and the second semiconductor structure 204 are connected at a bonding interface 206 therebetween. Figure 2 As shown, the first semiconductor structure 202 may include a substrate 201, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0058] The first semiconductor structure 202 of the 3D memory device 200 may include peripheral circuitry 208 on a substrate 201. In some embodiments, the peripheral circuitry 208 is configured to control and sense the 3D memory device 200. The peripheral circuitry 208 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 200, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of said circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry 208 may include transistors formed "on" the substrate 201, wherein all or part of the transistors are formed in the semiconductor layer 201 (e.g., below the top surface of the substrate 201) and / or directly on the substrate 201. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) may also be formed in the substrate 201. According to some embodiments, transistors are high-speed thanks to advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It should be understood that in some embodiments, peripheral circuitry 208 may further include any other circuitry compatible with advanced logic processes, including logic circuitry such as processors and PLDs, or memory circuitry such as SRAM and DRAM.

[0059] In some embodiments, the first semiconductor structure 202 of the 3D memory device 200 further includes an interconnect layer (not shown) above the peripheral circuitry 208 to transmit electrical signals to and from the peripheral circuitry 208. The interconnect layer may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and via contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more ILD layers (also referred to herein as “IMD layers”), in which the interconnects and via contacts may be formed. That is, the interconnect layer may include interconnects and via contacts in multiple ILD layers. The interconnects and via contacts in the interconnect layer may be encapsulated in a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0060] like Figure 2As shown, the first semiconductor structure 202 of the 3D memory device 200 may further include a bonding layer 210 located at the bonding interface 206 and above the interconnect layer and peripheral circuitry 208. The bonding layer 210 may include a plurality of bonding contacts 211 and a dielectric material electrically isolating the bonding contacts 211. The bonding contacts 211 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 210 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 211 in the bonding layer 210 and the surrounding dielectric material may be used for hybrid bonding.

[0061] Similarly, such as Figure 2 As shown, the second semiconductor structure 204 of the 3D memory device 200 may further include a bonding layer 212 located at the bonding interface 206 and above the bonding layer 210 of the first semiconductor structure 202. The bonding layer 212 may include a plurality of bonding contacts 213 and a dielectric material electrically isolating the bonding contacts 213. The bonding contacts 213 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 212 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 213 in the bonding layer 212 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 213 are in contact with the bonding contacts 211 at the bonding interface 206.

[0062] As detailed below, the second semiconductor structure 204 can be bonded to the top of the first semiconductor structure 202 in a face-to-face manner at the bonding interface 206. In some embodiments, the bonding interface 206 is disposed between the bonding layers 210 and 212 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 206 is the location where the bonding layers 212 and 210 meet and bond. In practice, the bonding interface 206 can be a layer of a certain thickness comprising the top surface of the bonding layer 210 of the first semiconductor structure 202 and the bottom surface of the bonding layer 212 of the second semiconductor structure 204.

[0063] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an interconnect layer (not shown) above the bonding layer 212 for transmitting electrical signals. This interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in the interconnect layer may be encapsulated in a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0064] In some embodiments, the 3D memory device 200 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings. For example... Figure 2 As shown, the second semiconductor structure 204 of the 3D memory device 200 may include an array of channel structures 224 that function as an array of NAND memory strings. Figure 2 As shown, each channel structure 224 extends vertically through multiple pairs, each pair including a conductive layer 216 and a dielectric layer 218. Alternating conductive layers 216 and dielectric layers 218 form part of a memory stack 214. The number of pairs of conductive layers 216 and dielectric layers 218 in the memory stack 214 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the 3D memory device 200. It should be understood that in some embodiments, the memory stack 214 may have a multi-level architecture (not shown) comprising multiple memory levels stacked one on top of the other. The number of pairs of conductive layers 216 and dielectric layers 218 in each memory level may be the same or different.

[0065] The memory stack 214 may include a plurality of alternating conductive layers 216 and dielectric layers 218. The conductive layers 216 and dielectric layers 218 in the memory stack 214 may alternate in the vertical direction. In other words, except for the layers located at the top or bottom of the memory stack 214, each conductive layer 216 may be adjacent to two dielectric layers 218 on both sides, and each dielectric layer 218 may be adjacent to two conductive layers 216 on both sides. The conductive layers 216 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer 216 may include a gate electrode (gate line) surrounded by a binder layer and a gate dielectric layer. The gate electrode of the conductive layer 216 may extend laterally as a word line, terminating at one or more stepped structures of the memory stack 214. The dielectric layers 218 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0066] like Figure 2 As shown, the second semiconductor structure 204 of the 3D memory device 200 may further include a P-type doped semiconductor layer 220 above the memory stack 114. The P-type doped semiconductor layer 220 may be an example of a “sidewall SEG” as described above. The P-type doped semiconductor layer 220 may include a semiconductor material, such as silicon. In some embodiments, the P-type doped semiconductor layer 220 comprises polycrystalline silicon formed by a deposition technique, as detailed below. In some embodiments, the P-type doped semiconductor layer 220 comprises monocrystalline silicon, such as a device layer of an SOI wafer, as detailed below. The P-type doped semiconductor layer 220 may be doped with any suitable P-type dopant, such as boron (B), gallium (Ga), or aluminum (Al), to create a deficiency of valence electrons in the intrinsic semiconductor, also known as “holes.” For example, the P-type doped semiconductor layer 220 may be a polycrystalline silicon layer doped with P-type dopant such as P, Ar, or Sb. In some embodiments, the P-type doped semiconductor layer 220 is a single polysilicon layer having a uniform doping concentration distribution in the vertical direction, as opposed to a polysilicon sublayer having multiple sublayers with non-uniform doping concentrations at their interfaces (e.g., a sudden change in doping concentration at the interface between two sublayers). It should be understood that the doping concentration of the P-type dopant in the P-type doped semiconductor layer 220 can still vary gradually in the vertical direction, as long as there are no sudden changes in doping concentration that can distinguish between two or more sublayers based on the doping concentration variation.

[0067] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an N-well 221 in the p-type doped semiconductor layer 220. The N-well 221 may be doped with any suitable N-type dopant, such as P, Ar, or Sb, which contribute free electrons and improve the conductivity of the intrinsic semiconductor. In some embodiments, the N-well 221 is doped from the bottom surface of the p-type doped semiconductor layer 220. It should be understood that the N-well 221 may extend vertically throughout the entire thickness of the p-type doped semiconductor layer 220, i.e., to the top surface of the p-type doped semiconductor layer 220, or vertically throughout a portion of the entire thickness of the p-type doped semiconductor layer 220.

[0068] In some embodiments, each channel structure 224 includes a channel via filled with a semiconductor layer (e.g., as a semiconductor channel 228) and a composite dielectric layer (e.g., as a storage film 226). In some embodiments, the semiconductor channel 228 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film 226 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. The remaining space of the channel structure 224 may be partially or entirely filled with a capping layer including a dielectric material (e.g., silicon oxide) and / or air gaps. The channel structure 224 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer, the semiconductor channel 228, and the tunneling layer, storage layer, and barrier layer of the storage film 226 are arranged radially from the center of the column to the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 226 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0069] In some embodiments, the channel structure 224 further includes a channel plug 227 located in the bottom portion of the channel structure 224 (e.g., at the lower end). As used herein, when the substrate 201 is placed in the lowest plane of the 3D memory device 200, the “upper end” of the component (e.g., the channel structure 224) is... y The end that is farther from the substrate 201 in the direction, and the "lower end" of the component (e.g., the channel structure 224) is in y The end closer to the substrate 201 in the direction. The channel plug 227 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 227 serves as the drain of a NAND memory string.

[0070] like Figure 2As shown, each channel structure 224 can extend vertically through the alternating conductive layers 216 and dielectric layers 218 of the memory stack 214 into the p-type doped semiconductor layer 220. The upper end of each channel structure 224 can be flush with or below the top surface of the p-type doped semiconductor layer 220. That is, according to some embodiments, the channel structure 224 does not extend beyond the top surface of the p-type doped semiconductor layer 220. In some embodiments, the upper end of the memory film 226 is below the upper end of the semiconductor channel 228 in the channel structure 224, such as... Figure 2 As shown. In some embodiments, the upper end of the storage film 226 is below the top surface of the p-type doped semiconductor layer 220, and the upper end of the semiconductor channel 228 is flush with or below the top surface of the p-type doped semiconductor layer 220. For example, as Figure 2 As shown, the storage film 226 may terminate at the bottom surface of the p-type doped semiconductor layer 220, while the semiconductor channel 228 may extend above the bottom surface of the p-type doped semiconductor layer 220, such that the p-type doped semiconductor layer 220 may surround and contact the top portion 229 of the semiconductor channel 228 extending into the p-type doped semiconductor layer 220. In some embodiments, the doping concentration of the top portion 229 of the semiconductor channel 228 extending into the p-type doped semiconductor layer 220 is different from the doping concentration of the rest of the semiconductor channel 228. For example, the semiconductor channel 228 may include undoped polysilicon except for the top portion 229, and the top portion 229 may include doped polysilicon to improve its conductivity when forming an electrical connection with the surrounding p-type doped semiconductor layer 220.

[0071] In some embodiments, the P-type doped semiconductor layer 220 includes semiconductor plugs 222, each semiconductor plug 222 surrounding and contacting a top portion 229 of a corresponding semiconductor channel 228 of the channel structure 224 extending into and contacting the top portion 229. According to some embodiments, the semiconductor plugs 222 comprise doped polysilicon, for example, P-type doped polysilicon. The doping concentration of the semiconductor plugs 222 may differ from the doping concentration of the remainder of the P-type doped semiconductor layer 220 because the semiconductor plugs 222 may be formed in a later process after the formation of the remainder of the P-type doped semiconductor layer 220, as described in detail below. In some embodiments, the semiconductor plugs 222 comprise polysilicon (e.g., P-type doped polysilicon), and the remainder of the P-type doped semiconductor layer 220 comprises monocrystalline silicon (e.g., P-type doped monocrystalline silicon). In some embodiments, the semiconductor plug 222 comprises polysilicon (e.g., P-type doped polysilicon), and the remainder of the P-type doped semiconductor layer 220 comprises polysilicon (e.g., P-type doped polysilicon), but has a doping concentration different from that of the semiconductor plug 222.

[0072] Each semiconductor plug 222 may surround and contact the sidewall of the top portion 229 of the corresponding semiconductor channel 228. Therefore, the semiconductor plug 222 in the P-type doped semiconductor layer 220 can function as a "sidewall SEG (e.g., semiconductor plug)" for the channel structure 224, instead of a "bottom SEG (e.g., semiconductor plug)". Furthermore, as detailed below, the formation of the semiconductor plug 222 occurs on opposite sides of the memory stack 214, which avoids any deposition or etching processes through openings in the memory stack 214, thereby reducing fabrication complexity and cost and improving yield and vertical scalability. Depending on the relative position of the upper end of the semiconductor channel 228 of each channel structure 224 with respect to the top surface of the P-type doped semiconductor layer 220, the semiconductor plug 222 may also be formed above and in contact with the upper end of the semiconductor channel 228, for example, as... Figure 2 As shown, this occurs when the upper end of the semiconductor channel 228 is below the top surface of the P-type doped semiconductor layer 220. It should be understood that in other examples where the upper end of the semiconductor channel 228 is flush with the top surface of the P-type doped semiconductor layer 220, the semiconductor plug 222 may be formed to surround and contact only the sidewall of the top portion 229 of the semiconductor channel 228.

[0073] However, the P-type doped semiconductor layer 220 surrounding the top portion 229 of the semiconductor channel 228 of the channel structure 224 with a semiconductor plug 222 (e.g., as a sidewall SEG) enables P-well bulk erase operations for the 3D memory device 200. The design of the 3D memory device 200 disclosed herein enables the separation of hole current paths and electron current paths used for forming erase and read operations, respectively. In some embodiments, the 3D memory device 200 is configured to form an electron current path between an electron source (e.g., N-well 221) and the semiconductor channel 228 of the channel structure 224 to provide electrons to the NAND memory string during a read operation according to some embodiments. Conversely, the 3D memory device 200 is configured to form a hole current path between a hole source (e.g., the P-type doped semiconductor layer 220) and the semiconductor channel 228 of the channel structure 224 to provide holes to the NAND memory string during a P-well bulk erase operation according to some embodiments.

[0074] like Figure 2As shown, the second semiconductor structure 204 of the 3D memory device 200 may further include insulating structures 230, each insulating structure 230 extending vertically through alternating conductive layers 216 and dielectric layers 218 of the memory stack 214. According to some embodiments, unlike the channel structure 224 which extends further into the p-doped semiconductor layer 220, the insulating structure 230 terminates at the bottom surface of the p-doped semiconductor layer 220, i.e., it does not extend vertically into the p-doped semiconductor layer 220. That is, the top surface of the insulating structure 230 may be flush with the bottom surface of the p-doped semiconductor layer 220. Each insulating structure 230 may also extend laterally to divide the channel structure 224 into multiple blocks. That is, the memory stack 214 may be divided into multiple memory blocks by the insulating structures 230, such that an array of channel structures 224 can be allocated to each memory block. Unlike the slit structures in existing 3D NAND memory devices described above that include front-side ACS contacts, according to some embodiments, the insulating structure 230 does not contain any contacts (i.e., it does not function as source contacts), and therefore, no parasitic capacitance and leakage current are introduced with respect to the conductive layer 216 (including word lines). In some embodiments, each insulating structure 230 includes openings (e.g., slits) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 230 may be filled with silicon oxide.

[0075] Furthermore, as detailed below, since the opening used to form the insulating structure 230 is not used to form the P-type doped semiconductor layer 220 and the semiconductor plug 222 therein (e.g., sidewall SEG), the increased aspect ratio of the opening will not affect the formation of the P-type doped semiconductor layer 220 and the semiconductor plug 222 therein as the number of alternating conductive layers 216 and dielectric layers 218 increases.

[0076] 3D memory device 100 may not include front source contacts, but may include back source contacts 231 and 232 located above memory stack 214 and in contact with N-well 221 and P-type doped semiconductor layer 220, respectively, as shown below. Figure 1As shown. Source contacts 231 and 232, along with the storage stack 214 (and the insulating structure 230 passing through it), can be positioned on opposite sides of the P-type doped semiconductor layer 220 and are thus considered "back" source contacts. In some embodiments, the source contact 232, contacting the P-type doped semiconductor layer 220, is electrically connected to the semiconductor channel 228 of the channel structure 224 via a semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 231, contacting the N-well 221, is electrically connected to the semiconductor channel 228 of the channel structure 224 via a semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 232 is not laterally aligned with the insulating structure 230 and is close to the channel structure 224 to reduce the resistance of the electrical connection therebetween. It should be understood that although the source contact 231 is as described above... Figure 2 As shown, the source contact 231 is laterally aligned with the insulating structure 230. However, in some examples, the source contact 231 may not be laterally aligned with the insulating structure 230, but may instead be close to the channel structure 224 (e.g., laterally positioned between the insulating structure 230 and the channel structure 224) to also reduce the resistance of the electrical connection therebetween. As described above, source contacts 231 and 232 can be used to separately control the electronic current and hole current during read and erase operations, respectively. Source contacts 231 and 232 can include any suitable type of contact. In some embodiments, source contacts 231 and 232 include through-hole contacts. In some embodiments, source contacts 231 and 232 include laterally extending wall-like contacts. Source contacts 231 and 232 can include one or more conductive layers, such as metal layers (e.g., W, Co, Cu, or Al) or silicide layers surrounded by a binder layer (e.g., titanium nitride (TiN)).

[0077] like Figure 2As shown, the 3D memory device 100 may further include a BEOL interconnect layer 233 located above and electrically connected to the source contacts 231 and 232 to enable pad take-off, for example, to transmit electrical signals between the 3D memory device 200 and external circuitry. In some embodiments, the interconnect layer 233 includes one or more ILD layers 234 on a P-type doped semiconductor layer 220 and a redistribution layer 236 on the ILD layer 234. The upper ends of the source contacts 231 or 232 are flush with the top surface of the ILD layer 234 and the bottom surface of the redistribution layer 236. The source contacts 231 and 232 may be electrically separated by the ILD layer 234. In some embodiments, the source contacts 232 extend vertically through the ILD layer 234 into the P-type doped semiconductor layer 220 to establish an electrical connection with the P-type doped semiconductor layer 220. In some embodiments, the source contact 231 extends vertically through the ILD layer 234 and the P-type doped semiconductor layer 220 into the N-well 221 to make an electrical connection with the N-well. The source contact 231 includes spacers (e.g., dielectric layers) surrounding its sidewalls to electrically isolate it from the P-type doped semiconductor layer 220. The redistribution layer 236 may include two electrically separated interconnects: a first interconnect 236-1 contacting the source contact 232 and a second interconnect 236-2 contacting the source contact 231.

[0078] The ILD layer 234 in interconnect layer 233 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The redistribution layer 236 in interconnect layer 233 may contain a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, redistribution layer 236 includes Al. In some embodiments, interconnect layer 233 further includes a passivation layer 238 as the outermost layer for passivation and protection of the 3D memory device 200. A portion of redistribution layer 236 may be exposed from passivation layer 238 to serve as contact pads 240. That is, interconnect layer 233 of 3D memory device 200 may also include contact pads 240 for wire bonding and / or bonding with interposers.

[0079] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes contacts 242, 243, and 244 extending through the p-type doped semiconductor layer 220. According to some embodiments, since the p-type doped semiconductor layer 220 may be a thinned substrate, such as a device layer of an SOI wafer, contacts 242, 243, and 244 are TSCs (Thin Sinks). In some embodiments, contact 242 extends through the p-type doped semiconductor layer 220 and the ILD layer 234 to contact the first interconnect 236-1 of the redistribution layer 236, such that the p-type doped semiconductor layer 220 is electrically connected to contact 242 via source contact 232 and the first interconnect 236-1 of interconnect layer 233. In some embodiments, contact 243 extends through the p-type doped semiconductor layer 220 and the ILD layer 234 to contact the second interconnect 236-2 of the redistribution layer 236, such that the N-well 221 is electrically connected to contact 243 via source contact 231 and the second interconnect 236-2 of interconnect layer 233. In some embodiments, contact 244 extends through p-type doped semiconductor layer 220 and ILD layer 234 to contact contact pad 240. Each of contacts 242, 243, and 244 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least each of contacts 243 and 244 further includes a spacer (e.g., a dielectric layer) to electrically separate contacts 243 and 244 from p-type doped semiconductor layer 220.

[0080] In some embodiments, the 3D memory device 200 further includes peripheral contacts 246, 247, and 248, each extending vertically outside the memory stack 214. Each peripheral contact 246, 247, or 248 may have a depth greater than the depth of the memory stack 214 to extend vertically from the bonding layer 212 to the p-type doped semiconductor layer 220 in a peripheral region outside the memory stack 214. In some embodiments, peripheral contact 246 is below and in contact with contact 242, such that the p-type doped semiconductor layer 220 is electrically connected to peripheral circuitry 208 in the first semiconductor structure 202 at least through source contact 232, first interconnect 236-1 of interconnect layer 233, contact 242, and peripheral contact 246. In some embodiments, peripheral contact 247 is below and in contact with contact 243, such that N-well 221 is electrically connected to peripheral circuitry 208 in the first semiconductor structure 202 at least through source contact 231, second interconnect 236-2 of interconnect layer 233, contact 243, and peripheral contact 247. That is, the electronic and hole currents for read and erase operations can be separately controlled by peripheral circuitry 208 through different electrical connections. In some embodiments, peripheral contact 248 is below and in contact with contact 244, such that peripheral circuitry 208 in the first semiconductor structure 202 is electrically connected to contact pad 240 for pad routing at least through contact 244 and peripheral contact 248. Each of peripheral contacts 246, 247, and 248 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0081] like Figure 2As shown, the 3D memory device 200 also includes various local contacts (also referred to as "C1") as part of an interconnect structure, which directly contact the structure in the memory stack 214. In some embodiments, the local contacts include channel local contacts 250, each channel local contact 250 being below and contacting the lower end of a corresponding channel structure 224. Each channel local contact 250 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 252, each word line local contact 252 being below and contacting the corresponding conductive layer 216 (including the word line) at a stepped structure of the memory stack 214 for word line fan-out. The local contacts (such as channel local contacts 250 and word line local contacts 252) may be electrically connected to the peripheral circuitry 208 of the first semiconductor structure 202 at least through bonding layers 212 and 210. Each of the local contacts (such as channel local contact 250 and word line local contact 252) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0082] Figure 3A –3N illustrates a fabrication process for forming exemplary 3D storage devices according to some embodiments of the present disclosure. Figure 5A A flowchart of a method 500 for forming an exemplary 3D storage device according to some embodiments of the present disclosure is shown. Figure 5B A flowchart of another method 501 for forming an exemplary 3D storage device according to some embodiments of the present disclosure is shown. Figure 3A-3N , Figure 5A and Figure 5B Examples of 3D storage devices depicted include Figure 1 The 3D storage device 100 depicted in the image. [The image will be used for...] Figure 3A-3N , Figure 5A and Figure 5B Described together. It should be understood that the operations shown in methods 500 and 501 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations described. Figure 5A and Figure 5B The execution is performed in the order shown.

[0083] refer to Figure 5A Method 500 begins with operation 502, in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate. Figure 3GAs shown, multiple transistors are formed on a silicon substrate 350 using various processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 350 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet etching and / or dry etching and thin film deposition. Peripheral circuitry 352 can be formed on the silicon substrate 350 for the transistors.

[0084] like Figure 3G As shown, a bonding layer 348 is formed above the peripheral circuit 352. The bonding layer 348 includes bonding contacts electrically connected to the peripheral circuit 352. To form the bonding layer 348, one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, are used to deposit an ILD layer; wet etching and / or dry etching (e.g., reactive ion etching (RIE)) are then used, followed by one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof), to form bonding contacts through the ILD layer.

[0085] A channel structure extending vertically through the memory stack and the N-type doped semiconductor layer can be formed above the second substrate. Method 500 proceeds to operation 504, as follows: Figure 5A As shown, in this operation, a sacrificial layer, an N-type doped semiconductor layer, and a dielectric stack are sequentially formed on a second substrate. The second substrate may be a silicon substrate. It should be understood that since the second substrate will be removed from the final product, it may be a portion of a dummy wafer (e.g., a carrier substrate) made of any suitable material to reduce the cost of the second substrate; for example, the material may be glass, sapphire, plastic, silicon, and only a few examples are given here. In some embodiments, the substrate is a carrier substrate, the sacrificial layer comprises a dielectric material, the N-type doped semiconductor layer comprises polycrystalline silicon, and the dielectric stack comprises alternating stacked dielectric layers and stacked sacrificial layers. In some embodiments, the stacked dielectric layers and stacked sacrificial layers are deposited alternately on the N-type doped semiconductor layer to form the dielectric stack.

[0086] like Figure 3AAs shown, a sacrificial layer 304 is formed on a carrier substrate 302, and an N-type doped semiconductor layer 306 is formed on the sacrificial layer 304. The N-type doped semiconductor layer 306 may comprise polysilicon doped with an N-type dopant such as P, As, or Sb. The sacrificial layer 304 may comprise any suitable sacrificial material, which may be selectively removed later and is different from the material of the N-type doped semiconductor layer 306. In some embodiments, the sacrificial layer 304 comprises a dielectric material such as silicon oxide or silicon nitride. According to some embodiments, to form the sacrificial layer 304, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, are used to deposit silicon oxide or silicon nitride on the carrier substrate 302. In some embodiments, to form the N-type doped semiconductor layer 306, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, are used to deposit polysilicon on the sacrificial layer 304, followed by ion implantation and / or thermal diffusion to dope the deposited polysilicon with an N-type dopant such as P, As, or Sb. In some embodiments, in order to form an N-type doped semiconductor layer 306, in-situ doping of an N-type dopant such as P, As, or Sb is performed when polysilicon is deposited on the sacrificial layer 304.

[0087] like Figure 3B As shown, a dielectric stack 308 comprising multiple pairs of first dielectric layers (hereinafter referred to as "stacked sacrificial layers" 312) and second dielectric layers (hereinafter referred to as "stacked dielectric layers" 310, and together with the former as "dielectric layer pairs") is formed on an N-type doped semiconductor layer 306. According to some embodiments, the dielectric stack 308 comprises alternating stacked sacrificial layers 312 and stacked dielectric layers 310. The stacked dielectric layers 310 and stacked sacrificial layers 312 may be alternately deposited on the N-type doped semiconductor layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some embodiments, each stacked dielectric layer 310 comprises a silicon oxide layer, and each stacked sacrificial layer 312 comprises a silicon nitride layer. The dielectric stack 308 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 3B As shown, a stepped structure can be formed on the edge of the dielectric stack 308. This stepped structure can be formed by performing multiple so-called "trimming-etching" cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. Due to the repeated trimming-etching cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloping edges and a top dielectric layer pair shorter than the bottom dielectric layer pair, such as... Figure 3B As shown.

[0088] Method 500 proceeds to operation 506, such as... Figure 5A As shown, in this operation, a channel structure is formed that extends vertically through the dielectric stack and the N-type doped semiconductor layer. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the N-type doped semiconductor layer and stopping at the sacrificial layer is etched, and a storage film and a semiconductor channel are sequentially deposited along the sidewalls of the channel hole.

[0089] like Figure 3B As shown, a via is an opening extending vertically through the dielectric stack 308 and the N-type doped semiconductor layer 306. In some embodiments, multiple openings are formed such that each opening becomes a location for growing a separate channel structure 314 in subsequent processes. In some embodiments, the fabrication process for forming the vias of the channel structure 314 includes wet etching and / or dry etching, such as deep RIE (DRIE). The sacrificial layer 304 can act as an etching stop layer for controlling gouging variation between different vias. For example, etching of the vias can be stopped by the sacrificial layer 304 without further extending into the carrier substrate 302. That is, according to some embodiments, the lower end of each via (and corresponding channel structure 314) is located between the top and bottom surfaces of the sacrificial layer 304.

[0090] like Figure 3B As shown, a memory film comprising a barrier layer 317, a storage layer 316, and a tunneling layer 315, and a semiconductor channel 318 are subsequently formed along the sidewalls and bottom surface of the channel via in the listed order. In some embodiments, the barrier layer 317, the storage layer 316, and the tunneling layer 315 are first deposited along the sidewalls and bottom surface of the channel via in the listed order using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film. The semiconductor channel 318 can then be formed by depositing a semiconductor material, such as polycrystalline silicon (e.g., undoped polycrystalline silicon), over the tunneling layer 315 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polycrystalline silicon layer (“SONO” structure) are subsequently deposited to form the barrier layer 317, the storage layer 316, the tunneling layer 315, and the semiconductor channel 318 of the memory film.

[0091] like Figure 3BAs shown, a capping layer is formed in and above the semiconductor channel 318 within the channel hole to completely or partially fill the channel hole (e.g., with or without air gaps). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug is then formed in the top portion of the channel hole. In some embodiments, portions of the storage film, semiconductor channel 318, and capping layer on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A groove can then be formed in the top portion of the channel hole by wet etching and / or dry etching of the portions of the semiconductor channel 318 and capping layer in the top portion of the channel hole. A channel plug can then be formed by depositing a semiconductor material, such as polysilicon, using one or more thin-film deposition processes, such as CVD, PVD, ALD, or any combination thereof. This forms a channel structure 314 that passes through the dielectric stack 308 and the N-type doped semiconductor layer 306. Depending on the depth to which the etch of each channel hole by the sacrificial layer 304 stops, the channel structure 314 may extend further into the sacrificial layer 304 or stop at the interface between the sacrificial layer 304 and the N-type doped semiconductor layer 306. However, the channel structure 314 may not extend further into the carrier substrate 302.

[0092] Method 500 proceeds to operation 508, such as... Figure 5A As shown, in this operation, a so-called "gate replacement" process is used, for example, to replace the dielectric stack with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. In some embodiments, in order to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack and stopping at the N-type doped semiconductor layer is etched, and through the opening, a stacked conductive layer is used instead of a stacked sacrificial layer to form a memory stack comprising alternating stacked dielectric layers and stacked conductive layers.

[0093] like Figure 3C As shown, the slot 320 is an opening that extends vertically through the dielectric stack 308 and terminates at the N-type doped semiconductor layer 306. In some embodiments, the fabrication process for forming the slot 320 includes wet etching and / or dry etching, such as DRIE. Subsequently, gate replacement can be performed through the slot 320 to utilize the memory stack 330 in place of the dielectric stack 308 (e.g., Figure 3E (As shown).

[0094] like Figure 3D As shown, the stacked sacrificial layer 312 is first removed via the gap 320 (as shown). Figure 3CAs shown, lateral grooves 322 are formed. In some embodiments, alternating lateral grooves 322 are created between stacked dielectric layers 310 by removing the stacked sacrificial layer 312 through an etchant applied via slot 320. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 312 relative to the stacked dielectric layer 310.

[0095] like Figure 3E As shown, a stacked conductive layer 328 (including a gate electrode and an adhesive layer) is deposited into a lateral groove 322 through a gap 320 (as shown). Figure 3D In some embodiments, a gate dielectric layer 322 is deposited into a lateral recess 322 prior to the stacked conductive layer 328, such that the stacked conductive layer 328 is deposited on the gate dielectric layer 322. The stacked conductive layer 328, such as a metal layer, can be deposited using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer 332, such as a high-k dielectric layer, is also formed along the sidewalls of the slot 320 and at the bottom of the slot 320. According to some embodiments, this forms a memory stack 330 comprising alternating stacked conductive layers 328 and stacked dielectric layers 310, instead of a dielectric stack 308 (…). Figure 3D (as shown in the image).

[0096] Method 500 proceeds to operation 510, such as Figure 5A As shown, in this operation, an insulating structure is formed that extends vertically through the memory stack. In some embodiments, to form this insulating structure, after the memory stack is formed, one or more dielectric materials are deposited into the opening to fill it. Figure 3E As shown, an insulating structure 336 is formed that extends vertically through the memory stack 330, ending on the top surface of the N-type doped semiconductor layer 306. One or more dielectric materials (e.g., silicon oxide) can be deposited into the gaps 320 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to completely or partially fill the gaps 320 (with or without air gaps), thereby forming the insulating structure 336. In some embodiments, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide).

[0097] like Figure 3FAs shown, after forming the insulating structure 336, local contacts including channel local contacts 334 and word line local contacts 342, as well as peripheral contacts 338 and 340, are formed. A local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material (such as silicon oxide or silicon nitride) on top of the memory stack 330 using one or more thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. Contact openings through the local dielectric layer (and any other ILD layer) can be etched using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340.

[0098] like Figure 3F As shown, a bonding layer 346 is formed above the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and wet etching and / or dry etching (e.g., RIE) are used, followed by one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form bonding contacts through the ILD layer.

[0099] Method 500 proceeds to operation 512, such as Figure 5A As shown, in this operation, the first and second substrates are bonded face-to-face, such that the memory stack is above the peripheral circuitry. The bonding includes hybrid bonding. For example... Figure 3G As shown, the carrier substrate 302 and components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed therethrough) are flipped upside down. According to some embodiments, a downward-facing bonding layer 346 is bonded to an upward-facing bonding layer 348, i.e., face-to-face, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in the bonding layer 346 are aligned and contacted with the bonding contacts in the bonding layer 348, such that the memory stack 330 and the channel structure 314 formed therethrough can be electrically connected to and above the peripheral circuitry 352.

[0100] Method 500 proceeds to operation 514, such as... Figure 5A As shown, in this operation, the second substrate and sacrificial layer are removed to expose the ends of the channel structure. Removal can be performed from the back side of the second substrate. Figure 3H As shown, the carrier substrate 302 and the sacrificial layer 304 are removed from the back side (e.g.) Figure 3G (As shown), to expose the upper end of the channel structure 314. The carrier substrate 302 can be completely removed using CMP, polishing, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 is stripped. Removal of the carrier substrate 302 can be stopped by the underlying sacrificial layer 304 because they are made of different materials to ensure thickness uniformity. In some embodiments where the carrier substrate 302 comprises silicon and the sacrificial layer 304 comprises silicon oxide, CMP is used to remove the carrier substrate 302, which can automatically stop at the interface between the carrier substrate 302 and the sacrificial layer 304.

[0101] Subsequently, the sacrificial layer 304 can be selectively removed using wet etching with a suitable etchant (e.g., hydrofluoric acid) without etching the underlying N-type doped semiconductor layer 306. As described above, since the channel structure 314 does not extend beyond the sacrificial layer 304 into the carrier substrate 302, the removal of the carrier substrate 302 does not affect the channel structure 314. Removal of the sacrificial layer 304 can expose the upper end of the channel structure 314. In some embodiments where the channel structure 314 extends into the sacrificial layer 304, selective etching of the sacrificial layer 304, which includes silicon oxide, also removes the portion of the barrier layer 317, including silicon oxide, above the top surface of the N-type doped semiconductor layer 306, but the memory layer 316, including silicon nitride, and other layers surrounding the memory layer 316 (e.g., tunneling layer 315) remain intact.

[0102] Method 500 proceeds to operation 516, such as... Figure 5A As shown, in this operation, a semiconductor plug is used to replace the portion of the channel structure adjacent to the N-type doped semiconductor layer. In some embodiments, in order to replace the portion of the channel structure adjacent to the N-type doped semiconductor layer with a semiconductor plug, the portion of the storage film adjacent to the N-type doped semiconductor layer is removed to form a groove surrounding the portion of the semiconductor channel. This portion of the semiconductor channel is doped, and polysilicon is deposited in the groove to form a semiconductor plug surrounding and in contact with the doped portion of the semiconductor channel.

[0103] like Figure 3I As shown, the portion of the storage layer 316 adjacent to the N-type doped semiconductor layer 306 is removed (e.g.) Figure 3H(As shown). In some embodiments, wet etching is used to selectively remove the memory layer 316, which includes silicon nitride, using a suitable etchant such as phosphoric acid, without etching the N-type doped semiconductor layer 306, which includes polysilicon. The etching of the memory layer 316 can be controlled by controlling the etching time and / or etching rate so that the etching does not further affect the remaining portion of the memory layer 316 surrounded by the memory stack 330.

[0104] like Figure 3J As shown, portions of the barrier layer 317 and tunneling layer 315 adjacent to the N-type doped semiconductor layer 306 are removed to form a recess 357 surrounding the top portion of the semiconductor channel 318 adjacent to the N-type doped semiconductor layer 306. In some embodiments, wet etching is used with a suitable etchant, such as hydrofluoric acid, to selectively remove the barrier layer 317 and tunneling layer 315, which include silicon oxide, without etching the N-type doped semiconductor layer 306 and semiconductor channel 318, which include polysilicon. The etching of the barrier layer 317 and tunneling layer 315 can be controlled by controlling the etching time and / or etching rate so that the etching does not further affect the remaining portions of the barrier layer 317 and tunneling layer 315 surrounded by the memory stack 330. Therefore, according to some embodiments, the top portion of the storage film (including barrier layer 317, storage layer 316, and tunneling layer 315) of the channel structure 314 adjacent to the N-type doped semiconductor layer 306 is removed to form a groove 357, exposing the top portion of the semiconductor channel 318. In some embodiments, the top portion of the semiconductor channel 318 exposed by the groove 357 is doped to improve its conductivity. For example, a tilted ion implantation process can be performed to dope the top portion of the semiconductor channel 318 (e.g., including polysilicon) exposed by the groove 357 to a desired doping concentration using any suitable dopant.

[0105] like Figure 3K As shown, in groove 357 (e.g.) Figure 3J As shown, a semiconductor plug 359 is formed in the channel structure 314 to surround and contact the doped top portion of the semiconductor channel 318. Therefore, according to some embodiments, the semiconductor plug 359 is thus used to replace the top portion of the channel structure 314 adjacent to the N-type doped semiconductor layer 306 (as shown). Figure 3H(As shown). In some embodiments, to form the semiconductor plug 359, polysilicon is deposited into the trench 357 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to fill the trench 357, followed by a CMP process to remove any excess polysilicon above the top surface of the N-type doped semiconductor layer 306. In some embodiments, in-situ doping of the semiconductor plug 359 is performed during the deposition of polysilicon into the trench 357 using an N-type dopant such as P, As, or Sb. Since the semiconductor plug 359 and the N-type doped semiconductor layer 306 may comprise the same material, such as polysilicon, and have the same thickness (after the CMP process), the semiconductor plug 359 can be considered part of the N-type doped semiconductor layer 306. However, according to some embodiments, since the semiconductor plug 359 is formed in the remaining portion of the N-type doped semiconductor layer 306 (e.g., as shown in the diagram), the semiconductor plug 359 is considered part of the N-type doped semiconductor layer 306. Figure 3A It is formed in a later process after (as shown in the diagram), so regardless of whether the semiconductor plug 359 is in-situ doped, the doping concentration of the semiconductor plug 359 is different from the doping concentration of the rest of the N-type doped semiconductor layer 306.

[0106] As described above, the semiconductor plug 359 in the N-type doped semiconductor layer 306 can serve as a sidewall SEG for the channel structure 314. In known methods for forming sidewall SEGs, a gap 320 extending through the dielectric stack 308 with a large aspect ratio (e.g., Figure 3D The etching and deposition processes (as shown) are performed, and unlike the known methods, when the carrier substrate 302 is removed, semiconductor plugs 359 can be formed from opposite sides of the dielectric stack 308 / memory stack 330, unaffected by the level of the dielectric stack 308 / memory stack 330 and the aspect ratio of the gap 320. By avoiding the problems introduced by the higher aspect ratio of the gap 320, fabrication complexity and cost can be reduced, and yield can be improved. Furthermore, vertical scalability can be improved (e.g., by increasing the number of levels in the dielectric stack 308 / memory stack 330).

[0107] Method 500 proceeds to operation 518, such as... Figure 5A As shown, in this operation, the source contacts are formed above the memory stack and in contact with the N-type doped semiconductor layer. Figure 3LAs shown, one or more ILD layers 356 are formed on an N-type doped semiconductor layer 306. The ILD layer 356 can be formed by depositing a dielectric material on the top surface of the N-type doped semiconductor layer 306 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Source contact openings 358 can be formed through the ILD layer 356 into the N-type doped semiconductor layer 306. In some embodiments, the source contact openings 358 are formed using wet etching and / or dry etching (e.g., RIE). In some embodiments, the source contact openings 358 further extend into the top portion of the N-type doped semiconductor layer 306. The etching process through the ILD layer 356 can continue to etch portions of the N-type doped semiconductor layer 306. In some embodiments, after etching through the ILD layer 356, portions of the N-type doped semiconductor layer 306 are etched using separate etching processes.

[0108] like Figure 3M As shown, on the back side of the N-type doped semiconductor layer 306, at the source contact opening 358 ( Figure 3L (As shown in the diagram) a source contact 364 is formed. According to some embodiments, the source contact 364 is located above the memory stack 330 and contacts the N-type doped semiconductor layer 306. In some embodiments, one or more conductive materials are deposited into the source contact opening 358 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill the source contact opening 358 with a binder layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, may then be performed to remove excess conductive material, such that the top surface of the source contact 364 is flush with the top surface of the ILD layer 356.

[0109] Method 500 proceeds to operation 520, such as... Figure 5A As shown, in this operation, an interconnect layer is formed above and in contact with the source contacts. In some embodiments, a contact is formed through the N-type doped semiconductor layer and in contact with the interconnect layer, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contacts and the interconnect layer.

[0110] like Figure 3NAs shown, a redistribution layer 370 is formed above and in contact with the source contact 364. In some embodiments, the redistribution layer 370 is formed by depositing a conductive material (e.g., Al) on the top surface of the ILD layer 356 and the source contact 364 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A passivation layer 372 may be formed on the redistribution layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. According to some embodiments, an interconnect layer 376 comprising the ILD layer 356, the redistribution layer 370, and the passivation layer 372 is thus formed.

[0111] like Figure 3L As shown, contact openings 360 and 361 are formed, each extending through the ILD layer 356 and the N-type doped semiconductor layer 306. In some embodiments, the contact openings 360 and 361 through the ILD layer 356 and the N-type doped semiconductor layer 306 are formed using wet etching and / or dry etching (e.g., RIE). In some embodiments, the contact openings 360 and 361 are patterned using photolithography to align with peripheral contacts 338 and 340, respectively. Etching of the contact openings 360 and 361 may stop at the upper ends of the peripheral contacts 338 and 340 to expose the peripheral contacts 338 and 340. Figure 3L As shown, spacers 362 are formed along the sidewalls of contact openings 360 and 361 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to electrically separate the N-type doped semiconductor layer 306. In some embodiments, etching of the source contact opening 358 is performed after the spacers 362 are formed, such that the spacers 362 are not formed along the sidewalls of the source contact opening 358, thereby increasing the contact area between the source contact 364 and the N-type doped semiconductor layer 306.

[0112] like Figure 3M As shown, contact openings 360 and 361 are formed on the back side of the N-type doped semiconductor layer 306 (e.g., ...). Figure 3LContacts 366 and 368 (shown) are shown. According to some embodiments, contacts 366 and 368 extend vertically through the ILD layer 356 and the N-type doped semiconductor layer 306. Contacts 366 and 368, as well as the source contact 364, can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings 360 and 361 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill contact openings 360 and 361 with a binder layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material, such that the top surfaces of contacts 366 and 368 (and the top surface of the source contact 364) are flush with the top surface of the ILD layer 356. In some embodiments, since contact openings 360 and 361 are aligned with peripheral contacts 338 and 340 respectively, contacts 366 and 368 are also above and in contact with peripheral contacts 338 and 340 respectively.

[0113] like Figure 3N As shown, a redistribution layer 370 is also formed above and in contact with contact 366. Therefore, the N-type doped semiconductor layer 306 can be electrically connected to the peripheral contact 338 via the source contact 364, the redistribution layer 370 of the interconnect layer 376, and contact 366. In some embodiments, the N-type doped semiconductor layer 306 is electrically connected to the peripheral circuit 352 via the source contact 364, interconnect layer 376, contact 366, peripheral contact 338, and bonding layers 346 and 348.

[0114] like Figure 3N As shown, contact pads 374 are formed on and in contact with contacts 368. In some embodiments, the portion of the passivation layer 372 covering the contact 368 is removed by wet etching and / or dry etching to expose a portion of the underlying redistribution layer 370 to form the contact pads 374. Therefore, the contact pads 374 for pad routing can be electrically connected to the peripheral circuitry 352 via the contacts 368, the peripheral contacts 340, and the bonding layers 346 and 348.

[0115] It should be understood that an SOI wafer can be used instead of the second substrate, sacrificial layer, and N-type doped semiconductor layer described above in method 500. This SOI wafer includes a manipulation layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer, as described below with respect to method 501. For ease of description, details of similar operations between methods 500 and 501 are not repeated. Reference Figure 5BMethod 501 begins with operation 502, in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate.

[0116] Method 501 proceeds to operation 503, such as Figure 5B As shown, in this operation, the device layer of the SOI wafer is doped using an N-type dopant. The SOI wafer may include a manipulation layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer comprises silicon oxide, and the device layer comprises single-crystal silicon. Figure 3A As shown, the SOI wafer 301 includes a manipulation layer 302 (corresponding to the carrier substrate 302 in method 500 described above), a buried oxide layer 304 (corresponding to the sacrificial layer 304), and a device layer 306 (corresponding to the N-type doped semiconductor layer 306). The device layer 306 can be doped with an N-type dopant such as P, As, or Sb using ion implantation and / or thermal diffusion to become an N-type doped device layer 306. It should be understood that the descriptions above relating to the carrier substrate 302, the sacrificial layer 304, and the N-type doped semiconductor layer 306 can be similarly applied to the manipulation layer 302, the buried oxide layer 304, and the doped device layer 306 of the SOI wafer 301, respectively, for a better understanding of method 501 below, and therefore will not be repeated for the sake of simplicity.

[0117] Method 501 proceeds to operation 505, such as... Figure 5B As shown, in this operation, a dielectric stack is formed on the doped device layer of the SOI wafer. This dielectric stack may include alternating stacked dielectric layers and stacked sacrificial layers. Method 501 proceeds to operation 507, as follows: Figure 5B As shown, in this operation, a channel structure is formed that extends vertically through the dielectric stack and the doped device layer. In some embodiments, to form this channel structure, a channel hole is formed that extends vertically through the dielectric stack and the doped device layer, stopping at a buried oxide layer, and a storage film and a semiconductor channel are sequentially deposited along the sidewalls of the channel hole. Method 501 proceeds to operation 508, as follows. Figure 5B As shown, in this operation, a memory stack is used instead of a dielectric stack so that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to use the memory stack instead of the dielectric stack, an opening extending vertically through the dielectric stack is etched, the opening stopping at the doped device layer, and through the opening, a stacked conductive layer is used instead of a stacked sacrificial layer to form a memory stack comprising alternating stacked dielectric layers and stacked conductive layers. Method 501 proceeds to operation 510, as follows. Figure 5BAs shown, in this operation, an insulating structure is formed that extends vertically through the storage stack. In some embodiments, to form the insulating structure, after the storage stack is formed, one or more dielectric materials are deposited into the opening to fill it.

[0118] Method 501 proceeds to operation 513, such as Figure 5B As shown, in this operation, the first substrate and the SOI wafer are bonded face-to-face, such that the memory stack is above the peripheral circuitry. The bonding includes hybrid bonding. Method 501 proceeds to operation 515, as follows: Figure 5B As shown, in this operation, the manipulation layer and buried oxide layer of the SOI wafer are removed to expose the ends of the channel structure. Method 501 proceeds to operation 517, as follows. Figure 5B As shown, in this operation, a semiconductor plug is used to replace the portion of the channel structure adjacent to the doped device layer. In some embodiments, in order to replace the portion of the channel structure adjacent to the doped device layer with a semiconductor plug, the portion of the storage film adjacent to the doped device layer is etched to form a trench surrounding the portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited in the trench to form a semiconductor plug surrounding and in contact with the portion of the doped semiconductor channel.

[0119] Method 501 proceeds to operation 519, such as Figure 5B As shown, in this operation, a source contact is formed above the memory stack and in contact with the doped device layer. Method 501 proceeds to operation 520, as follows: Figure 5B As shown, in this operation, an interconnect layer is formed above and in contact with the source contact. In some embodiments, the contact is formed to pass through the doped device layer and in contact with the interconnect layer, such that the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

[0120] Figure 4A-4O A fabrication process for forming another exemplary 3D storage device is illustrated according to some embodiments of the present disclosure. Figure 6A A flowchart of a method 600 for forming another exemplary 3D storage device according to some embodiments of the present disclosure is shown. Figure 6B A flowchart of another method 601 for forming another exemplary 3D storage device according to some embodiments of the present disclosure is shown. Figure 4A -4O、 Figure 6A and Figure 6B Examples of 3D storage devices depicted include Figure 2 The 3D storage device 200 depicted in the image. [The image will be used for...] Figure 4A-4O , Figure 6A and Figure 6BDescribed together. It should be understood that the operations shown in methods 600 and 601 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations described. Figure 6A and Figure 6B The execution is performed in the order shown.

[0121] refer to Figure 6A Method 600 begins with operation 602, in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate. Figure 4G As shown, multiple transistors are formed on a silicon substrate 450 using various processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 450 by ion implantation and / or thermal diffusion, serving as, for example, source and / or drain regions of transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 450 by wet etching and / or dry etching and thin film deposition. The transistors are capable of forming peripheral circuitry 452 on the silicon substrate 450.

[0122] like Figure 4G As shown, a bonding layer 448 is formed above the peripheral circuit 452. The bonding layer 448 includes bonding contacts electrically connected to the peripheral circuit 452. To form the bonding layer 448, one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, are used to deposit the ILD layer; wet etching and / or dry etching (e.g., RIE) are used, followed by one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof), to form the bonding contacts through the ILD layer.

[0123] A channel structure extending vertically through the memory stack and the P-type doped semiconductor layer with an N-well can be formed above the second substrate. Method 600 proceeds to operation 604, as follows. Figure 6AAs shown, in this operation, a sacrificial layer on a second substrate, a P-type doped semiconductor layer with an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are sequentially formed. The second substrate may be a silicon substrate. It should be understood that since the second substrate will be removed from the final product, the second substrate may be a portion of a pseudo-wafer (e.g., a carrier substrate) made of any suitable material to reduce the cost of the second substrate; for example, the material may be glass, sapphire, plastic, silicon, and only a few examples are given here. In some embodiments, the substrate is a carrier substrate, the sacrificial layer comprises a dielectric material, the P-type doped semiconductor layer comprises polycrystalline silicon, and the dielectric stack comprises alternating stacked dielectric layers and stacked sacrificial layers. In some embodiments, the stacked dielectric layers and stacked sacrificial layers are deposited alternately on the P-type doped semiconductor layer to form the dielectric stack. In some embodiments, prior to forming the dielectric stack, a portion of the P-type doped semiconductor layer is doped with an N-type dopant to form an N-well.

[0124] like Figure 4A As shown, a sacrificial layer 404 is formed on a carrier substrate 402, and a P-type doped semiconductor layer 406 is formed on the sacrificial layer 404. The P-type doped semiconductor layer 406 may comprise a polycrystalline silicon layer doped with a P-type dopant such as B, Ga, or Al. The sacrificial layer 404 may comprise any suitable sacrificial material that may be selectively removed later and is different from the material of the P-type doped semiconductor layer 406. In some embodiments, the sacrificial layer 404 comprises a dielectric material such as silicon oxide or silicon nitride. According to some embodiments, to form the sacrificial layer 404, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, are used to deposit silicon oxide or silicon nitride on the carrier substrate 402. In some embodiments, to form the P-type doped semiconductor layer 406, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, are used to deposit polycrystalline silicon on the sacrificial layer 404, followed by ion implantation and / or thermal diffusion to dope the deposited polycrystalline silicon with a P-type dopant such as B, Ga, or Al. In some embodiments, in order to form a P-type doped semiconductor layer 406, in-situ doping of a P-type dopant such as B, Ga, or Al is performed when polysilicon is deposited on the sacrificial layer 404.

[0125] like Figure 4AAs shown, a portion of the P-type doped semiconductor layer 406 is doped with an N-type dopant such as P, As, or Sb to form an N-well 407 in the P-type doped semiconductor layer 406. In some embodiments, the N-well 407 is formed using ion implantation and / or thermal diffusion. The ion implantation and / or thermal diffusion processes can be controlled to control the thickness of the N-well 407, allowing it to penetrate the entire thickness of the P-type doped semiconductor layer 406 or a portion of the P-type doped semiconductor layer 406.

[0126] like Figure 4B As shown, a dielectric stack 408 comprising multiple pairs of first dielectric layers (hereinafter referred to as "stacked sacrificial layers" 412) and second dielectric layers (hereinafter referred to as "stacked dielectric layers" 410, and together with the former as "dielectric layer pairs") is formed on a p-type doped semiconductor layer 406. According to some embodiments, the dielectric stack 408 comprises alternating stacked sacrificial layers 412 and stacked dielectric layers 410. The stacked dielectric layers 410 and stacked sacrificial layers 412 may be alternately deposited on the p-type doped semiconductor layer 406 above the carrier substrate 402 to form the dielectric stack 408. In some embodiments, each stacked dielectric layer 410 comprises a silicon oxide layer, and each stacked sacrificial layer 412 comprises a silicon nitride layer. The dielectric stack 408 may be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 4B As shown, a stepped structure can be formed on the edge of the dielectric stack 408. This stepped structure can be formed by performing multiple so-called "trimming-etching" cycles on the dielectric layer pairs of the dielectric stack 408 toward the carrier substrate 402. Due to the repeated trimming-etching cycles applied to the dielectric layer pairs of the dielectric stack 408, the dielectric stack 408 can have one or more sloping edges and a top dielectric layer pair shorter than the bottom dielectric layer pair, such as... Figure 4B As shown.

[0127] Method 600 proceeds to operation 606, such as... Figure 6A As shown, in this operation, a channel structure is formed that extends vertically through the dielectric stack and the P-type doped semiconductor layer. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the P-type doped semiconductor layer and stopping at the sacrificial layer is etched, and a storage film and a semiconductor channel are sequentially deposited along the sidewalls of the channel hole.

[0128] like Figure 4BAs shown, a via is an opening extending vertically through the dielectric stack 408 and the p-type doped semiconductor layer 406. In some embodiments, multiple openings are formed such that each opening becomes a location for growing a separate channel structure 414 in subsequent processes. In some embodiments, the fabrication process for forming the vias of the channel structure 414 includes wet etching and / or dry etching, such as DRIE. The sacrificial layer 404 can act as an etch stop layer for controlling the trench variation between different vias. For example, etching of the vias can be stopped by the sacrificial layer 404 without further extending into the carrier substrate 402. That is, according to some embodiments, the lower end of each via (and corresponding channel structure 414) is located between the top and bottom surfaces of the sacrificial layer 404.

[0129] like Figure 4B As shown, a memory film comprising a barrier layer 417, a storage layer 416, and a tunneling layer 415, and a semiconductor channel 418 are subsequently formed along the sidewalls and bottom surface of the channel via in the listed order. In some embodiments, the barrier layer 417, the storage layer 416, and the tunneling layer 415 are first deposited along the sidewalls and bottom surface of the channel via in the listed order using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film. The semiconductor channel 418 can then be formed by depositing a semiconductor material, such as polycrystalline silicon (e.g., undoped polycrystalline silicon), over the tunneling layer 415 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polycrystalline silicon layer (“SONO” structure) are subsequently deposited to form the barrier layer 417, the storage layer 416, the tunneling layer 415, and the semiconductor channel 418 of the memory film.

[0130] like Figure 4BAs shown, a capping layer is formed in and above the semiconductor channel 418 within the channel hole to completely or partially fill the channel hole (e.g., with or without air gaps). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug is then formed in the top portion of the channel hole. In some embodiments, portions of the storage film, semiconductor channel 418, and capping layer on the top surface of the dielectric stack 408 are removed and planarized by CMP, wet etching, and / or dry etching. A groove can then be formed in the top portion of the channel hole by wet etching and / or dry etching of the portions of the semiconductor channel 418 and capping layer in the top portion of the channel hole. A channel plug can then be formed by depositing a semiconductor material, such as polysilicon, using one or more thin-film deposition processes, such as CVD, PVD, ALD, or any combination thereof. This forms a channel structure 414 that passes through the dielectric stack 408 and the p-type doped semiconductor layer 406. Depending on the depth to which the etch of each channel hole by the sacrificial layer 404 stops, the channel structure 414 may extend further into the sacrificial layer 404 or stop at the interface between the sacrificial layer 404 and the p-type doped semiconductor layer 406. However, the channel structure 414 may not extend further into the carrier substrate 402.

[0131] Method 600 proceeds to operation 608, such as... Figure 6A As shown, in this operation, a so-called "gate replacement" process is used, for example, to replace the dielectric stack with a memory stack, such that the channel structure extends vertically through the memory stack and the P-type doped semiconductor layer. In some embodiments, in order to replace the dielectric stack with the memory stack, an opening extending vertically through the dielectric stack and stopping at the P-type doped semiconductor layer is etched, and through the opening, a stacked conductive layer is used instead of a stacked sacrificial layer to form a memory stack comprising alternating stacked dielectric layers and stacked conductive layers.

[0132] like Figure 4C As shown, the slot 420 is an opening that extends vertically through the dielectric stack 408 and terminates at the p-type doped semiconductor layer 406. In some embodiments, the fabrication process for forming the slot 420 includes wet etching and / or dry etching, for example, DRIE. Although as Figure 4C As shown, slot 420 is aligned with N-well 407; however, it should be understood that in other examples, slot 420 may not be aligned with N-well 407. Gate substitution can then be performed through slot 420 to utilize memory stack 430 instead of dielectric stack 408 (e.g., Figure 4E (As shown).

[0133] like Figure 4D As shown, the stacked sacrificial layer 412 is first removed via the gap 420 (as shown). Figure 4C As shown, lateral grooves 422 are formed. In some embodiments, alternating lateral grooves 422 are created between stacked dielectric layers 410 by removing the stacked sacrificial layer 412 through an etchant applied via slot 420. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 412 relative to the stacked dielectric layer 410.

[0134] like Figure 4E As shown, a stacked conductive layer 428 (including a gate electrode and an adhesive layer) is deposited into a lateral groove 422 through a gap 420 (as shown). Figure 3D In some embodiments, a gate dielectric layer 422 is deposited into a lateral recess 422 prior to the stacked conductive layer 428, such that the stacked conductive layer 428 is deposited on the gate dielectric layer 422. The stacked conductive layer 428, such as a metal layer, can be deposited using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer 432, such as a high-k dielectric layer, is also formed along the sidewalls of the slot 420 and at the bottom of the slot 420. According to some embodiments, this forms a memory stack 430 comprising alternating stacked conductive layers 428 and stacked dielectric layers 410, instead of a dielectric stack 408 (…). Figure 4D (as shown in the image).

[0135] Method 600 proceeds to operation 610, such as Figure 6A As shown, in this operation, an insulating structure is formed that extends vertically through the memory stack. In some embodiments, to form this insulating structure, after the memory stack is formed, one or more dielectric materials are deposited into the opening to fill it. Figure 4E As shown, an insulating structure 436 is formed that extends vertically through the memory stack 430, ending on the top surface of the p-type doped semiconductor layer 406. One or more dielectric materials (e.g., silicon oxide) can be deposited into the gaps 420 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to completely or partially fill the gaps 420 (with or without air gaps), thereby forming the insulating structure 436. In some embodiments, the insulating structure 436 includes a gate dielectric layer 432 (e.g., including a high-k dielectric) and a dielectric capping layer 434 (e.g., including silicon oxide).

[0136] like Figure 4FAs shown, after forming the insulating structure 436, local contacts including channel local contacts 434 and word line local contacts 442, as well as peripheral contacts 438, 439, and 440, are formed. A local dielectric layer can be formed on the memory stack 430 by depositing a dielectric material (such as silicon oxide or silicon nitride) on top of the memory stack 430 using one or more thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. Contact openings through the local dielectric layer (and any other ILD layer) can be etched using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the channel local contacts 444, word line local contacts 442, and peripheral contacts 438, 439, and 440.

[0137] like Figure 4F As shown, a bonding layer 446 is formed above the channel local contact 444, the word line local contact 442, and the peripheral contacts 438, 439, and 440. The bonding layer 446 includes bonding contacts electrically connected to the channel local contact 444, the word line local contact 442, and the peripheral contacts 438, 439, and 440. To form the bonding layer 446, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and wet etching and / or dry etching (e.g., RIE) are used, followed by one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the bonding contacts through the ILD layer.

[0138] Method 600 proceeds to operation 612, such as Figure 6A As shown, in this operation, the first and second substrates are bonded face-to-face, such that the memory stack is above the peripheral circuitry. The bonding includes hybrid bonding. For example... Figure 4G As shown, the carrier substrate 402 and components formed thereon (e.g., the memory stack 430 and the channel structure 414 formed therethrough) are flipped upside down. According to some embodiments, a downward-facing bonding layer 446 is bonded to an upward-facing bonding layer 448, i.e., face-to-face, thereby forming a bonding interface 454 between the carrier substrate 402 and the silicon substrate 450. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in the bonding layer 446 are aligned and contacted with the bonding contacts in the bonding layer 448, such that the memory stack 430 and the channel structure 414 formed therethrough can be electrically connected to and above the peripheral circuitry 452.

[0139] Method 600 proceeds to operation 614, such as Figure 6A As shown, in this operation, the second substrate and sacrificial layer are removed to expose the ends of the channel structure. Removal can be performed from the back side of the second substrate. Figure 4H As shown, the carrier substrate 402 and the sacrificial layer 404 are removed from the back side (e.g. Figure 4G (As shown), to expose the upper end of the channel structure 414. The carrier substrate 402 can be completely removed using CMP, polishing, dry etching, and / or wet etching. In some embodiments, the carrier substrate 402 is stripped. Removal of the carrier substrate 402 can be stopped by the underlying sacrificial layer 404 because they are made of different materials to ensure thickness uniformity. In some embodiments where the carrier substrate 402 comprises silicon and the sacrificial layer 404 comprises silicon oxide, CMP is used to remove the carrier substrate 402, which can automatically stop at the interface between the carrier substrate 402 and the sacrificial layer 404.

[0140] Subsequently, the sacrificial layer 404 can be selectively removed using wet etching with a suitable etchant (e.g., hydrofluoric acid) without etching the underlying P-type doped semiconductor layer 406. As described above, since the channel structure 414 does not extend beyond the sacrificial layer 404 into the carrier substrate 402, the removal of the carrier substrate 402 does not affect the channel structure 414. Removal of the sacrificial layer 404 can expose the upper end of the channel structure 414. In some embodiments where the channel structure 414 extends into the sacrificial layer 404, selective etching of the sacrificial layer 404, which includes silicon oxide, also removes the portion of the barrier layer 417, including silicon oxide, above the top surface of the P-type doped semiconductor layer 406, but the memory layer 416, including silicon nitride, and other layers surrounding the memory layer 416 (e.g., tunneling layer 415) remain intact.

[0141] Method 600 proceeds to operation 616, such as Figure 6A As shown, in this operation, a semiconductor plug is used to replace the portion of the channel structure adjacent to the P-type doped semiconductor layer. In some embodiments, in order to replace the portion of the channel structure adjacent to the P-type doped semiconductor layer with a semiconductor plug, the portion of the storage film adjacent to the P-type doped semiconductor layer is removed to form a groove surrounding the portion of the semiconductor channel. This portion of the semiconductor channel is doped, and polysilicon is deposited in the groove to form a semiconductor plug surrounding and in contact with the doped portion of the semiconductor channel.

[0142] like Figure 4I As shown, the portion of the storage layer 416 adjacent to the p-type doped semiconductor layer 406 is removed (e.g.) Figure 4H(As shown). In some embodiments, wet etching is used to selectively remove the memory layer 416, which includes silicon nitride, using a suitable etchant such as phosphoric acid, without etching the P-type doped semiconductor layer 406, which includes polysilicon. The etching of the memory layer 416 can be controlled by controlling the etching time and / or etching rate so that the etching does not further affect the remaining portion of the memory layer 416 surrounded by the memory stack 430.

[0143] like Figure 4J As shown, portions of the barrier layer 417 and tunneling layer 415 adjacent to the P-type doped semiconductor layer 406 are removed to form a recess 457 surrounding the top portion of the semiconductor channel 418 adjacent to the P-type doped semiconductor layer 406. In some embodiments, wet etching is used with a suitable etchant, such as hydrofluoric acid, to selectively remove the barrier layer 417 and tunneling layer 415, which comprise silicon oxide, without etching the P-type doped semiconductor layer 406 and semiconductor channel 418, which comprise polysilicon. The etching of the barrier layer 417 and tunneling layer 415 can be controlled by controlling the etching time and / or etching rate so that the etching does not further affect the remaining portions of the barrier layer 417 and tunneling layer 415 surrounded by the memory stack 430. Therefore, according to some embodiments, the top portion of the storage film (including barrier layer 417, storage layer 416, and tunneling layer 415) of the channel structure 414 adjacent to the P-type doped semiconductor layer 406 is removed to form a recess 457, exposing the top portion of the semiconductor channel 418. In some embodiments, the top portion of the semiconductor channel 418 exposed by the recess 457 is doped to improve its conductivity. For example, a tilted ion implantation process can be performed to dope the top portion of the semiconductor channel 418 (e.g., including polysilicon) exposed by the recess 457 to a desired doping concentration using any suitable dopant.

[0144] like Figure 4K As shown, in groove 457 (e.g.) Figure 4J As shown, a semiconductor plug 459 is formed in the semiconductor channel 418 to surround and contact the doped top portion of the semiconductor channel 418. Therefore, according to some embodiments, the semiconductor plug 459 is thus used to replace the top portion of the channel structure 414 adjacent to the p-type doped semiconductor layer 406 (as shown). Figure 4H(As shown). In some embodiments, to form the semiconductor plug 459, polysilicon is deposited into the trench 457 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to fill the trench 457, followed by a CMP process to remove any excess polysilicon above the top surface of the p-type doped semiconductor layer 406. In some embodiments, in-situ doping of the semiconductor plug 459 is performed during the deposition of polysilicon into the trench 457 using a p-type dopant such as B, Ga, or Al. Since the semiconductor plug 459 and the p-type doped semiconductor layer 406 may comprise the same material, such as polysilicon, and have the same thickness (after the CMP process), the semiconductor plug 459 can be considered as part of the p-type doped semiconductor layer 406. However, according to some embodiments, since the semiconductor plug 459 is formed in the remaining portion of the p-type doped semiconductor layer 406 (e.g., as shown in the diagram), the semiconductor plug 459 is considered as part of the p-type doped semiconductor layer 406. Figure 4A It is formed in a later process after (as shown in the diagram), so regardless of whether the semiconductor plug 459 is in-situ doped, the doping concentration of the semiconductor plug 459 is different from the doping concentration of the rest of the P-type doped semiconductor layer 406.

[0145] As described above, the semiconductor plug 459 in the p-type doped semiconductor layer 406 can serve as a sidewall SEG for the channel structure 414. In known methods for forming a sidewall SEG, a gap 420 extending through the dielectric stack 408 with a large aspect ratio (e.g., Figure 4D The etching and deposition processes (as shown) are performed, and unlike the known methods, when the carrier substrate 402 is removed, semiconductor plugs 459 can be formed from opposite sides of the dielectric stack 408 / memory stack 430, unaffected by the level of the dielectric stack 408 / memory stack 430 and the aspect ratio of the gap 420. By avoiding the problems introduced by the higher aspect ratio of the gap 420, fabrication complexity and cost can be reduced, and yield can be improved. Furthermore, vertical scalability can be improved (e.g., by increasing the number of levels in the dielectric stack 408 / memory stack 430).

[0146] Method 600 proceeds to operation 618, such as Figure 6A As shown, in this operation, a first source contact is formed above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact is formed above the memory stack and in contact with the N-well. Figure 4L As shown, one or more ILD layers 456 are formed on a P-type doped semiconductor layer 406. The ILD layer 456 can be formed by depositing a dielectric material on the top surface of the P-type doped semiconductor layer 406 using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0147] like Figure 4M As shown, a source contact opening 458 can be formed through the ILD layer 456 into the P-type doped semiconductor layer 406. In some embodiments, the source contact opening 458 is formed using wet etching and / or dry etching (e.g., RIE). In some embodiments, the source contact opening 458 further extends into the top portion of the P-type doped semiconductor layer 406. The etching process through the ILD layer 456 can continue etching portions of the P-type doped semiconductor layer 406. In some embodiments, after etching through the ILD layer 456, a separate etching process is used to etch portions of the P-type doped semiconductor layer 406.

[0148] like Figure 4M As shown, a source contact opening 465 can be formed through the ILD layer 456 into the N-well 407. In some embodiments, the source contact opening 465 is formed using wet etching and / or dry etching (e.g., RIE). In some embodiments, the source contact opening 465 further extends into the top portion of the N-well 407. The etching process through the ILD layer 456 can continue etching portions of the N-well 407. In some embodiments, after etching through the ILD layer 456, portions of the N-well 407 are etched using separate etching processes. Etching of the source contact opening 458 can be performed after etching of the source contact opening 465, and vice versa. It should be understood that in some examples, the source contact openings 458 and 465 can be etched using the same etching process to reduce the number of etching processes.

[0149] like Figure 4N As shown, openings 458 and 465, respectively located at the source contact, are formed on the back side of the P-type doped semiconductor layer 406. Figure 4M Contacts 464 and 478 are shown in the diagram. According to some embodiments, source contact 464 is above the memory stack 430 and contacts the p-type doped semiconductor layer 406. According to some embodiments, source contact 478 is above the memory stack 430 and contacts the N-well 407. In some embodiments, one or more conductive materials are deposited into the source contact openings 458 and 465 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill the source contact openings 458 and 465 with a binder layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material, such that the top surfaces of source contacts 464 and 478 are flush with each other and flush with the top surface of the ILD layer 456. It should be understood that in some examples, source contacts 464 and 478 can be formed using the same deposition and CMP processes to reduce the number of fabrication processes.

[0150] Method 600 proceeds to operation 620, such as Figure 6A As shown, in this operation, an interconnect layer is formed above and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect and a second interconnect that are respectively located above and in contact with the first and second source contacts.

[0151] like Figure 4O As shown, a redistribution layer 470 is formed above and in contact with source contacts 464 and 478. In some embodiments, the redistribution layer 470 is formed by depositing a conductive material (e.g., Al) on the top surface of the ILD layer 456 and the source contacts 464 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the redistribution layer 470 is patterned by photolithography and etching processes to form a first interconnect 470-1 above and in contact with source contacts 464 and a second interconnect 470-2 above and in contact with source contacts 478. The first interconnect 470-1 and the second interconnect 470-2 may be electrically isolated from each other. A passivation layer 472 may be formed on the redistribution layer 470. In some embodiments, a passivation layer 472 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. According to some embodiments, this forms an interconnect layer 476 comprising an ILD layer 456, a redistribution layer 470, and the passivation layer 472.

[0152] like Figure 4LAs shown, contact openings 460, 461, and 463 are formed, each extending through the ILD layer 456 and the P-type doped semiconductor layer 406. In some embodiments, the contact openings 460, 461, and 463 are formed through the ILD layer 456 and the P-type doped semiconductor layer 406 using wet etching and / or dry etching (e.g., RIE). In some embodiments, the contact openings 460, 461, and 463 are patterned using photolithography to align with peripheral contacts 438, 440, and 439, respectively. Etching of the contact openings 460, 461, and 463 may stop at the upper ends of the peripheral contacts 438, 439, and 440 to expose the peripheral contacts 438, 440, and 439. Etching of the contact openings 460, 461, and 463 can be performed using the same etching process to reduce the number of etching processes. It should be understood that, due to different etching depths, etching of contact openings 460, 461, and 463 can be performed before etching of source contact opening 465, and vice versa, but not simultaneously.

[0153] like Figure 4M As shown, spacers 462 are formed along the sidewalls of contact openings 460, 461, and 463 and contact opening 465 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to electrically separate the P-type doped semiconductor layer 406. In some embodiments, spacers 462 are formed along the sidewalls of contact openings 460, 461, and 463 and source contact opening 465 using the same deposition process to reduce the number of fabrication processes. In some embodiments, etching of source contact opening 458 is performed after the formation of spacers 462, such that spacers 462 are not formed along the sidewalls of source contact opening 458 to increase the contact area between source contact 464 and P-type doped semiconductor layer 406.

[0154] like Figure 4N As shown, contact openings 460, 461, and 463 are formed on the back side of the P-type doped semiconductor layer 406 (e.g., ...). Figure 4MContacts 466, 468, and 469 (shown) are shown. According to some embodiments, contacts 466, 468, and 469 extend vertically through the ILD layer 456 and the p-type doped semiconductor layer 406. Contacts 466, 468, and 469, as well as source contacts 464 and 478, can be formed using the same deposition process to reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited into contact openings 460, 461, and 463 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill contact openings 460, 461, and 463 with a binder layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material, such that the top surfaces of contacts 466, 468, and 469 (and the top surfaces of source contacts 464 and 478) are flush with the top surface of the ILD layer 456. In some embodiments, since the contact openings 460, 461 and 463 are aligned with the peripheral contacts 438, 440 and 439 respectively, the contacts 466, 468 and 469 are also above the peripheral contacts 438, 440 and 439 and in contact with the peripheral contacts 438, 440 and 439 respectively.

[0155] like Figure 4O As shown, the first interconnect 470-1 of the redistribution layer 470 is formed above and in contact with contact 466. Therefore, the P-type doped semiconductor layer 406 can be electrically connected to the peripheral contact 438 via the source contact 464, the first interconnect 470-1 of the interconnect layer 476, and contact 466. In some embodiments, the P-type doped semiconductor layer 406 is electrically connected to the peripheral circuit 452 via the source contact 464, the first interconnect 470-1 of the interconnect layer 476, contact 466, peripheral contact 438, and bonding layers 446 and 448. Similarly, the second interconnect 470-2 of the redistribution layer 470 is formed above and in contact with contact 469. Therefore, the N-well 407 can be electrically connected to the peripheral contact 438 via the source contact 478, the second interconnect 470-2 of the interconnect layer 476, and contact 469. In some embodiments, the N-well 407 is electrically connected to the peripheral circuit 452 via the source contact 478, the second interconnect 470-2 of the interconnect layer 476, the contact 469, the peripheral contact 439, and the bonding layers 446 and 448.

[0156] like Figure 4OAs shown, contact pads 474 are formed on and in contact with contact 468. In some embodiments, the portion of passivation layer 472 covering contact 468 is removed by wet etching and / or dry etching to expose a portion of the underlying redistribution layer 470 to form contact pads 474. Therefore, contact pads 474 for pad routing can be electrically connected to peripheral circuitry 452 via contact 468, peripheral contact 440, and bonding layers 446 and 448.

[0157] It should be understood that an SOI wafer, comprising a manipulation layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer, can be used instead of the second substrate, sacrificial layer, and P-type doped semiconductor layer described above in method 600, as described below with respect to method 601. For ease of description, details of similar operations between methods 600 and 601 are not repeated. Reference Figure 6B Method 601 begins with operation 602, in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate.

[0158] Method 601 proceeds to operation 603, such as Figure 6B As shown, in this operation, the device layer of the SOI wafer is doped using a P-type dopant. The SOI wafer may include a manipulation layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide, and the device layer includes monocrystalline silicon. Method 601 proceeds to operation 605, as follows: Figure 6B As shown, in this operation, a portion of the doped device layer is doped with an N-type dopant to form an N-well in the doped device layer.

[0159] like Figure 4A As shown, the SOI wafer 401 includes a manipulation layer 402 (corresponding to the carrier substrate 402 in method 600 described above), a buried oxide layer 404 (corresponding to the sacrificial layer 404), and a device layer 406 (corresponding to the P-type doped semiconductor layer 406). The device layer 406 can be doped with a P-type dopant, such as P, As, or Sb, using ion implantation and / or thermal diffusion to become a P-type doped device layer 406. A portion of the doped device layer 406 can be further doped with an N-type dopant, such as B, Ga, or Al, using ion implantation and / or thermal diffusion to form an N-well 407. It should be understood that the description above relating to the carrier substrate 402, the sacrificial layer 404, and the P-type doped semiconductor layer 406 can be similarly applied to the manipulation layer 402, the buried oxide layer 404, and the doped device layer 406 of the SOI wafer 401, respectively, for a better understanding of method 601 below, and will therefore not be repeated for simplicity.

[0160] Method 601 proceeds to operation 607, such as... Figure 6B As shown, in this operation, a dielectric stack is formed on the doped device layer of the SOI wafer. This dielectric stack may include alternating stacked dielectric layers and stacked sacrificial layers. Method 601 proceeds to operation 609, as follows: Figure 6B As shown, in this operation, a channel structure is formed that extends vertically through the dielectric stack and the doped device layer. In some embodiments, to form this channel structure, a channel hole is formed that extends vertically through the dielectric stack and the doped device layer, stopping at a buried oxide layer, and a storage film and a semiconductor channel are sequentially deposited along the sidewalls of the channel hole. Method 601 proceeds to operation 608, as follows. Figure 6B As shown, in this operation, a memory stack is used instead of a dielectric stack so that the channel structure extends vertically through the memory stack and the doped device layer. In some embodiments, to use the memory stack instead of the dielectric stack, an opening extending vertically through the dielectric stack is etched, the opening stopping at the doped device layer, and through the opening, a stacked conductive layer is used instead of a stacked sacrificial layer to form a memory stack comprising alternating stacked dielectric layers and stacked conductive layers. Method 601 proceeds to operation 610, as follows. Figure 6B As shown, in this operation, an insulating structure is formed that extends vertically through the storage stack. In some embodiments, to form the insulating structure, after the storage stack is formed, one or more dielectric materials are deposited into the opening to fill it.

[0161] Method 601 proceeds to operation 613, such as Figure 6B As shown, in this operation, the first substrate and the SOI wafer are bonded face-to-face, such that the memory stack is above the peripheral circuitry. The bonding includes hybrid bonding. Method 601 proceeds to operation 615, as follows: Figure 6B As shown, in this operation, the manipulation layer and buried oxide layer of the SOI wafer are removed to expose the ends of the channel structure. Method 601 proceeds to operation 617, as follows. Figure 6B As shown, in this operation, a semiconductor plug is used to replace the portion of the channel structure adjacent to the doped device layer. In some embodiments, in order to replace the portion of the channel structure adjacent to the doped device layer with a semiconductor plug, the portion of the storage film adjacent to the doped device layer is etched to form a trench surrounding the portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited in the trench to form a semiconductor plug surrounding and in contact with the portion of the doped semiconductor channel.

[0162] Method 601 proceeds to operation 619, such as Figure 6BAs shown, in this operation, a first source contact is formed above the memory stack and in contact with the doped device layer, and a second source contact is formed above the memory stack and in contact with the N-well. Method 601 proceeds to operation 621, as follows. Figure 6B As shown, in this operation, an interconnect layer is formed above and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect above and in contact with the first source contact, and a second interconnect above and in contact with the second source contact. In some embodiments, a first contact is formed through the doped device layer and in contact with the first interconnect, such that the doped device layer is electrically connected to the first contact through the first source contact and the first interconnect. In some embodiments, a second contact is formed through the doped device layer and in contact with the second interconnect, such that the N-well is electrically connected to the second contact through the second source contact and the second interconnect.

[0163] According to one aspect of this disclosure, a 3D memory device includes: a substrate; peripheral circuitry on the substrate; a memory stack comprising alternating conductive and dielectric layers above the peripheral circuitry; a P-type doped semiconductor layer above the memory stack; a plurality of channel structures, each of the channel structures extending vertically through the memory stack into the P-type doped semiconductor layer; and a source contact above the memory stack and in contact with the P-type doped semiconductor layer. The upper end of each of the plurality of channel structures is flush with or below the top surface of the P-type doped semiconductor layer.

[0164] In some embodiments, the 3D memory device further includes an N-well in a P-type doped semiconductor layer and a second source contact above the memory stack and in contact with the N-well.

[0165] In some embodiments, the 3D storage device further includes an interconnect layer above the first source contact and the second source contact. According to some embodiments, the interconnect layer includes a first interconnect contacting the first source contact and a second interconnect contacting the second source contact.

[0166] In some embodiments, the 3D memory device further includes a first contact extending through the P-type doped semiconductor layer. According to some embodiments, the P-type doped semiconductor layer is electrically connected to peripheral circuitry at least through a first source contact, a first interconnect, and a first contact. In some embodiments, the 3D memory device further includes a second contact extending through the P-type doped semiconductor layer. According to some embodiments, the N-well is electrically connected to peripheral circuitry at least through a second source contact, a second interconnect, and a second contact.

[0167] In some embodiments, the 3D memory device further includes a third contact extending through a p-type doped semiconductor layer. According to some embodiments, the interconnect layer includes contact pads electrically connected to the third contact.

[0168] In some embodiments, the P-type doped semiconductor layer comprises polycrystalline silicon.

[0169] In some embodiments, the P-type doped semiconductor layer comprises single-crystal silicon.

[0170] In some embodiments, each channel structure in the channel structure includes a memory film and a semiconductor channel, and the upper end of the memory film is below the upper end of the semiconductor channel.

[0171] In some embodiments, the upper end of the storage film is below the top surface of the P-type doped semiconductor layer, and the upper end of the semiconductor channel is flush with or below the top surface of the P-type doped semiconductor layer.

[0172] In some embodiments, the portion of the semiconductor channel extending into the P-type doped semiconductor layer comprises doped polysilicon.

[0173] In some embodiments, the P-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel, and the doping concentration of the semiconductor plug is different from the doping concentration of the rest of the P-type doped semiconductor layer.

[0174] In some embodiments, the 3D memory device further includes an insulating structure that extends vertically through the memory stack and laterally to divide the plurality of channel structures into a plurality of blocks.

[0175] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0176] In some embodiments, the top surface of the insulating structure is flush with the bottom surface of the P-type doped semiconductor layer.

[0177] In some embodiments, the 3D memory device further includes a bonding interface between the peripheral circuitry and the memory stack.

[0178] According to another aspect of this disclosure, a 3D memory device includes: a substrate; a memory stack comprising alternating conductive and dielectric layers above the substrate; a P-type doped semiconductor layer above the memory stack; an N-well in the P-type doped semiconductor layer; a plurality of channel structures, each of the channel structures extending vertically through the memory stack into the P-type doped semiconductor layer; a first source contact above the memory stack and in contact with the P-type doped semiconductor layer; and a second source contact above the memory stack and in contact with the N-well.

[0179] In some embodiments, the upper end of each of the plurality of channel structures is flush with or below the top surface of the P-type doped semiconductor layer.

[0180] In some embodiments, each of the plurality of channel structures includes a memory film and a semiconductor channel, wherein the upper end of the memory film is below the upper end of the semiconductor channel.

[0181] In some embodiments, the upper end of the storage film is below the top surface of the P-type doped semiconductor layer, and the upper end of the semiconductor channel is flush with or below the top surface of the P-type doped semiconductor layer.

[0182] In some embodiments, the portion of the semiconductor channel extending into the P-type doped semiconductor layer comprises doped polysilicon.

[0183] In some embodiments, the P-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel, and the doping concentration of the semiconductor plug is different from the doping concentration of the rest of the P-type doped semiconductor layer.

[0184] In some embodiments, the semiconductor plug comprises polysilicon, and the remainder of the P-type doped semiconductor layer comprises polysilicon.

[0185] In some embodiments, the semiconductor plug comprises polycrystalline silicon, and the remainder of the P-type doped semiconductor layer comprises monocrystalline silicon.

[0186] In some embodiments, the 3D memory device further includes an insulating structure that extends vertically through the memory stack and laterally to divide the plurality of channel structures into a plurality of blocks.

[0187] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0188] In some embodiments, the top surface of the insulating structure is flush with the bottom surface of the P-type doped semiconductor layer.

[0189] In some embodiments, the 3D memory device further includes peripheral circuitry above the substrate and a bonding interface between the peripheral circuitry and the memory stack.

[0190] According to another aspect of this disclosure, a 3D memory device includes: a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes: a memory stack comprising alternating conductive and dielectric layers, a p-type doped semiconductor layer, and a plurality of channel structures, each of said channel structures extending vertically through the memory stack into the p-type doped semiconductor layer and electrically connected to the peripheral circuitry. The p-type doped semiconductor layer includes a semiconductor plug extending into the p-type doped semiconductor layer surrounding a portion of each of the plurality of channel structures. The doping concentration of the semiconductor plug differs from the doping concentration of the remainder of the p-type doped semiconductor layer.

[0191] In some embodiments, the second semiconductor structure further includes an insulating structure that extends vertically through the memory stack and laterally to divide the plurality of channel structures into a plurality of blocks.

[0192] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0193] In some embodiments, the insulating structure does not extend vertically into the P-type doped semiconductor layer.

[0194] In some embodiments, the second semiconductor structure further includes a first source contact in contact with a P-type doped semiconductor layer and a second source contact in contact with an N-well.

[0195] In some embodiments, the second semiconductor structure further includes an interconnect layer, the interconnect layer including a first interconnect in contact with a first source contact and a second interconnect in contact with a second source contact.

[0196] In some embodiments, the second semiconductor structure further includes a first contact extending through the P-type doped semiconductor layer. According to some embodiments, the P-type doped semiconductor layer is electrically connected to a peripheral circuit at least through a first source contact, a first interconnect, and a first contact. In some embodiments, the second semiconductor structure further includes a second contact extending through the P-type doped semiconductor layer. According to some embodiments, the N-well is electrically connected to a peripheral circuit at least through a second source contact, a second interconnect, and a second contact.

[0197] In some embodiments, each channel structure in the channel structure does not extend beyond the P-type doped semiconductor layer.

[0198] In some embodiments, the semiconductor plug comprises polysilicon, and the remainder of the P-type doped semiconductor layer comprises polysilicon.

[0199] In some embodiments, the semiconductor plug comprises polycrystalline silicon, and the remainder of the P-type doped semiconductor layer comprises monocrystalline silicon.

[0200] The foregoing description of specific embodiments thus reveals the general essence of this disclosure. Those skilled in the art, with their knowledge and skills, can readily modify and / or adjust such specific embodiments for various applications without departing from the general principles of this disclosure, without extensive experimentation. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and their equivalents. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes; therefore, those skilled in the art should interpret the terminology or terminology of this specification in accordance with the teachings and guidance provided.

[0201] The embodiments of this disclosure have been described above using functional building blocks to illustrate implementations of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0202] The summary and abstract sections may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0203] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) storage device, comprising: A stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction; Semiconductor layer; One or more second dielectric layers, wherein the semiconductor layer is located between the one or more second dielectric layers and the stacked structure in the first direction; A channel structure that extends along the first direction through the stacked structure and is connected to the semiconductor layer; A first source contact passes through one or more second dielectric layers and is connected to the semiconductor layer, with a portion of the first source contact extending into the semiconductor layer. 2.The three-dimensional (3D) memory device of claim 1, wherein, It also includes a substrate and peripheral circuitry formed on the substrate, the stacked structure being located between the semiconductor layer and the substrate along the first direction.

3. The three-dimensional (3D) memory device of claim 1, wherein, The channel structure includes a semiconductor channel and a memory film, the memory film surrounding the semiconductor channel, the semiconductor channel being exposed from the memory film and connected to the semiconductor layer.

4. The three-dimensional (3D) storage device according to claim 3, characterized in that, The semiconductor channel includes a first portion and a second portion along the first direction, the first portion being located between the semiconductor layer and the second portion, the first portion being in contact with the semiconductor layer, and the doping concentration of the first portion being different from the doping concentration of the second portion.

5. The three-dimensional (3D) storage device according to claim 3, characterized in that, The semiconductor channel contacts the semiconductor layer at one end face in the first direction, and the semiconductor channel also contacts the semiconductor layer in a second direction, which is perpendicular to the first direction.

6. The three-dimensional (3D) storage device according to claim 3, characterized in that, The semiconductor channel is located at one end of the semiconductor layer in the first direction, and is higher than the storage film at one end of the conductor layer in the first direction.

7. The three-dimensional (3D) storage device according to claim 3, characterized in that, The storage film is lower than the semiconductor layer at the end closest to the conductor layer in the first direction.

8. The three-dimensional (3D) storage device according to claim 1, characterized in that, It also includes a first interconnect layer, wherein the one or more second dielectric layers are located between the first interconnect layer and the semiconductor layer along a first direction, and the first interconnect layer is connected to the first source contact.

9. The three-dimensional (3D) storage device according to claim 8, characterized in that, It also includes a first contact structure that passes through the one or more second dielectric layers and the semiconductor layer along a first direction, the first contact structure being spaced apart from the semiconductor layer and connected to the first interconnect layer.

10. The three-dimensional (3D) storage device according to claim 9, characterized in that, Also includes: A second contact structure extending along the first direction, the second contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in a second direction, the second direction being perpendicular to the first direction; The third interconnect layer, wherein the second contact structure is located between the first contact structure and the third interconnect layer, and the second contact structure is connected to both the first contact structure and the third interconnect layer.

11. The three-dimensional (3D) storage device according to claim 2, characterized in that, The semiconductor layer includes a portion extending beyond the stacked structure along a second direction perpendicular to the first direction, and further includes: A third contact structure, wherein the third contact structure and the portion of the third contact structure located outside the stacked structure, passing through the one or more second dielectric layers and the semiconductor layer along the first direction, are spaced apart from the semiconductor layer; A fourth contact structure extending along the first direction, the fourth contact structure being spaced apart from the stacked structure in the second direction, the fourth contact structure being connected to the first contact structure and the peripheral circuit respectively.

12. The three-dimensional (3D) storage device according to claim 1, characterized in that, The semiconductor layer includes an N-type or P-type doped semiconductor layer.

13. The three-dimensional (3D) storage device according to claim 1, characterized in that, Also includes: The second source contact is electrically isolated from the first source contact and passes through the one or more second dielectric layers and is connected to the semiconductor layer.

14. The three-dimensional (3D) storage device according to claim 13, characterized in that, Also includes: The second interconnect layer, wherein one or more second dielectric layers are located between the second interconnect layer and the semiconductor layer along the first direction, and the second interconnect layer is connected to the second source contact.

15. The three-dimensional (3D) storage device according to claim 1, characterized in that, Also includes: An insulating structure extends through the stacked structure along the first direction and contacts the semiconductor layer, the insulating structure being electrically insulated from the semiconductor layer.

16. A three-dimensional (3D) storage device, comprising: A stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction; A semiconductor layer extending beyond the stacked structure along a second direction perpendicular to the first direction; One or more second dielectric layers, wherein the semiconductor layer is located between the one or more second dielectric layers and the stacked structure in the first direction; A channel structure that extends along the first direction through the stacked structure and is connected to the semiconductor layer; A third contact structure, wherein the third contact structure and the portion of the third contact structure located outside the stacked structure, passing through the one or more second dielectric layers and the semiconductor layer along the first direction, are spaced apart from the semiconductor layer; The peripheral circuit, wherein the stacked structure is located between the semiconductor layer and the peripheral circuit along the first direction, and the third contact structure is coupled to the peripheral circuit.

17. The three-dimensional (3D) storage device according to claim 16, characterized in that, Also includes: A fourth contact structure extending along the first direction, the fourth contact structure being spaced apart from the stacked structure in the second direction; A third interconnect layer is located between the fourth contact structure and the peripheral circuit in the first direction. The fourth contact structure is connected to both the third interconnect layer and the third contact structure. The third interconnect layer is connected to the peripheral circuit.

18. The three-dimensional (3D) storage device according to claim 16, characterized in that, It also includes an insulating structure that passes through the stacked structure along the first direction and contacts the semiconductor layer, the insulating structure being insulated from the semiconductor layer.

19. The three-dimensional (3D) storage device according to claim 16, characterized in that, It also includes a third dielectric layer, which is located between the third contact structure and the semiconductor layer.

20. The three-dimensional (3D) storage device according to claim 16, characterized in that, It also includes a first source contact that passes through the one or more second dielectric layers and is connected to the semiconductor layer, with a portion of the source contact extending into the semiconductor layer.

21. The three-dimensional (3D) storage device according to claim 16, characterized in that, The channel structure includes a semiconductor channel and a memory film, the memory film surrounding the semiconductor channel, the semiconductor channel being exposed from the memory film and connected to the semiconductor layer.

22. The three-dimensional (3D) storage device according to claim 21, characterized in that, The semiconductor channel includes a first portion and a second portion along the first direction, the first portion being located between the semiconductor layer and the second portion, the first portion being in contact with the semiconductor layer, and the doping concentration of the first portion being different from the doping concentration of the second portion.

23. The three-dimensional (3D) storage device according to claim 21, characterized in that, The semiconductor channel contacts the semiconductor layer at one end face in the first direction, and the semiconductor channel also contacts the semiconductor layer in a second direction, which is perpendicular to the first direction.

24. The three-dimensional (3D) storage device according to claim 21, characterized in that, The semiconductor channel is located at one end of the semiconductor layer in the first direction, and is higher than the storage film at one end of the conductor layer in the first direction.

25. The three-dimensional (3D) storage device according to claim 21, characterized in that, The storage film is lower than the semiconductor layer at the end closest to the conductor layer in the first direction.

26. The three-dimensional (3D) storage device according to claim 20, characterized in that, It also includes a first interconnect layer, wherein the one or more second dielectric layers are located between the first interconnect layer and the semiconductor layer along a first direction, and the first interconnect layer is connected to the first source contact.

27. The three-dimensional (3D) storage device according to claim 26, characterized in that, It also includes a first contact structure that passes through the one or more second dielectric layers and the semiconductor layer along a first direction and is connected to the first interconnect layer, wherein the first contact structure is spaced apart from the semiconductor layer.

28. The three-dimensional (3D) storage device according to claim 27, characterized in that, It also includes a second contact structure extending along the first direction, the second contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in a second direction, the second direction being perpendicular to the first direction, and the second contact structure being connected to the first contact structure and the peripheral circuit respectively.

29. The three-dimensional (3D) storage device according to claim 16, characterized in that, The semiconductor layer includes an N-type or P-type doped semiconductor layer.

30. The three-dimensional (3D) storage device according to claim 16, characterized in that, Also includes: The second source contact is electrically isolated from the first source contact and passes through the one or more second dielectric layers and is connected to the semiconductor layer.

31. The three-dimensional (3D) storage device according to claim 30, characterized in that, Also includes: The second interconnect layer, wherein one or more second dielectric layers are located between the second interconnect layer and the semiconductor layer along a first direction, and the second interconnect layer is connected to the second source contact.

32. A three-dimensional (3D) storage device, comprising: A stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction; Semiconductor layer; One or more second dielectric layers, wherein the semiconductor layer is located between the one or more second dielectric layers and the stacked structure in the first direction; A channel structure that extends along the first direction through the stacked structure and is connected to the semiconductor layer; A first source contact passes through the one or more second dielectric layers and is connected to the semiconductor layer; A first contact structure is provided, which passes through the one or more second dielectric layers and the semiconductor layer along the first direction. The first contact structure is spaced apart from the semiconductor layer and coupled to the first source contact.

33. The three-dimensional (3D) storage device according to claim 32, characterized in that, It also includes a first interconnect layer, wherein the one or more second dielectric layers are located between the first interconnect layer and the semiconductor layer along a first direction, and the first interconnect layer is connected to the first source contact and the first contact structure, respectively.

34. The three-dimensional (3D) storage device according to claim 32, characterized in that, A second contact structure extending along the first direction, the second contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in a second direction, the second direction being perpendicular to the first direction; The third interconnect layer, the second contact structure is located between the third interconnect layer and the first contact structure in the first direction, and the second contact structure is connected to the third interconnect layer and the first contact structure respectively.

35. The three-dimensional (3D) storage device according to claim 32, characterized in that, It also includes a second source contact that is electrically isolated from the first source contact, and the second source contact passes through the one or more second dielectric layers and extends into the semiconductor layer.

36. The three-dimensional (3D) storage device according to claim 35, characterized in that, Also includes: The second interconnect layer, wherein one or more second dielectric layers are located between the second interconnect layer and the semiconductor layer along a first direction, and the second interconnect layer is connected to the second source contact.

37. The three-dimensional (3D) storage device according to claim 32, characterized in that, The semiconductor layer extends beyond the stacked structure along a second direction perpendicular to the first direction. The three-dimensional memory device further includes a third contact structure that passes through the one or more second dielectric layers and the semiconductor layer along the first direction, and the third contact structure is spaced apart from the semiconductor layer. A fourth contact structure extending along the first direction, the fourth contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in the second direction, the fourth contact structure being connected to the third contact structure and the peripheral circuit respectively.

38. The three-dimensional (3D) storage device according to claim 32, characterized in that, The third contact structure is made of the same material as the first contact structure.

39. The three-dimensional (3D) storage device according to claim 32, characterized in that, It also includes an insulating structure that passes through the stacked structure along the first direction and contacts the semiconductor layer, the insulating structure being electrically isolated from the semiconductor layer.

40. The three-dimensional (3D) storage device according to claim 32, characterized in that, It also includes a third dielectric layer, which is located between the first contact structure and the semiconductor layer.

41. The three-dimensional (3D) storage device according to claim 32, characterized in that, It also includes a substrate and peripheral circuitry formed on the substrate, the stacked structure being located between the semiconductor layer and the substrate along the first direction, and the second contact structure being electrically connected to the peripheral circuitry.

42. The three-dimensional (3D) storage device according to claim 32, characterized in that, The channel structure includes a semiconductor channel and a memory film, the memory film surrounding the semiconductor channel, the semiconductor channel being exposed from the memory film and connected to the semiconductor layer.

43. The three-dimensional (3D) storage device according to claim 42, characterized in that, The semiconductor channel includes a first portion and a second portion along the first direction, the first portion being located between the semiconductor layer and the second portion, the first portion being in contact with the semiconductor layer, and the doping concentration of the first portion being different from the doping concentration of the second portion.

44. The three-dimensional (3D) storage device according to claim 42, characterized in that, The semiconductor channel contacts the semiconductor layer at one end face in the first direction, and the semiconductor channel also contacts the semiconductor layer in a second direction, which is perpendicular to the first direction.

45. The three-dimensional (3D) storage device according to claim 42, characterized in that, The semiconductor channel is located at one end of the semiconductor layer in the first direction, and is higher than the storage film at one end of the conductor layer in the first direction.

46. ​​The three-dimensional (3D) storage device according to claim 42, characterized in that, The storage film is lower than the semiconductor layer at the end closest to the conductor layer in the first direction.

47. The three-dimensional (3D) storage device according to claim 32, characterized in that, The semiconductor layer includes an N-type or P-type doped semiconductor layer.

48. A three-dimensional (3D) storage device, comprising: A stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction; Semiconductor layer; One or more second dielectric layers, wherein the semiconductor layer is located between the one or more second dielectric layers and the stacked structure in the first direction; A channel structure extending through the stacked structure along a first direction, the channel structure including a semiconductor channel and a memory film, the memory film surrounding the semiconductor channel, the semiconductor channel contacting the semiconductor layer at one end face in the first direction, and the semiconductor channel also contacting the semiconductor layer in a second direction perpendicular to the first direction; A first source contact passes through the one or more second dielectric layers and is connected to the semiconductor layer.

49. The three-dimensional (3D) storage device according to claim 48, characterized in that, The semiconductor channel includes a first portion and a second portion along the first direction, the first portion being located between the semiconductor layer and the second portion, the first portion being in contact with the semiconductor layer, and the doping concentration of the first portion being different from the doping concentration of the second portion.

50. The three-dimensional (3D) storage device according to claim 48, characterized in that, The semiconductor channel is located at one end of the semiconductor layer in the first direction, and is higher than the storage film at one end of the conductor layer in the first direction.

51. The three-dimensional (3D) storage device according to claim 48, characterized in that, The storage film is lower than the semiconductor layer at the end closest to the conductor layer in the first direction.

52. The three-dimensional (3D) storage device according to claim 48, characterized in that, It also includes a substrate and peripheral circuitry formed on the substrate, the stacked structure being located between the semiconductor layer and the substrate along the first direction.

53. The three-dimensional (3D) storage device according to claim 48, characterized in that, It also includes a first interconnect layer, wherein the one or more second dielectric layers are located between the first interconnect layer and the semiconductor layer along a first direction, and the first interconnect layer is connected to the first source contact.

54. The three-dimensional (3D) storage device according to claim 53, characterized in that, It also includes a first contact structure that passes through the one or more second dielectric layers and the semiconductor layer along a first direction, the first contact structure being spaced apart from the semiconductor layer and connected to the first interconnect layer.

55. The three-dimensional (3D) storage device according to claim 54, characterized in that, Also includes: A second contact structure extending along the first direction, the second contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in a second direction, the second direction being perpendicular to the first direction; The third interconnect layer, wherein the second contact structure is located between the first contact structure and the third interconnect layer, and the second contact structure is connected to both the first contact structure and the third interconnect layer.

56. The three-dimensional (3D) storage device according to claim 52, characterized in that, The semiconductor layer includes a portion extending beyond the stacked structure along a second direction perpendicular to the first direction, and further includes: A third contact structure, wherein the third contact structure and the portion of the third contact structure located outside the stacked structure, passing through the one or more second dielectric layers and the semiconductor layer along the first direction, are spaced apart from the semiconductor layer; A fourth contact structure extending along the first direction, the fourth contact structure being spaced apart from the stacked structure in the second direction, the fourth contact structure being connected to the first contact structure and the peripheral circuit respectively.

57. The three-dimensional (3D) storage device according to claim 48, characterized in that, The semiconductor layer includes an N-type or P-type doped semiconductor layer.

58. The three-dimensional (3D) storage device according to claim 48, characterized in that, Also includes: The second source contact is electrically isolated from the first source contact and passes through the one or more second dielectric layers and is connected to the semiconductor layer.

59. The three-dimensional (3D) storage device according to claim 58, characterized in that, Also includes: The second interconnect layer, wherein one or more second dielectric layers are located between the second interconnect layer and the semiconductor layer along the first direction, and the second interconnect layer is connected to the second source contact.

60. The three-dimensional (3D) storage device according to claim 48, characterized in that, Also includes: An insulating structure extends through the stacked structure along the first direction and contacts the semiconductor layer, the insulating structure being electrically insulated from the semiconductor layer.

61. A three-dimensional (3D) storage device, comprising: A stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction; A semiconductor layer, wherein the semiconductor layer is located on one side of the stacked structure in the first direction; A channel structure extending along a first direction through the stacked structure and connected to the semiconductor layer, the channel structure including a semiconductor channel and a memory film, the memory film surrounding the semiconductor channel, the semiconductor channel including a first portion and a second portion along the first direction, the first portion being located between the semiconductor layer and the second portion, the first portion being in contact with the semiconductor layer, and the doping concentration of the first portion being different from the doping concentration of the second portion.

62. The three-dimensional (3D) storage device according to claim 61, characterized in that, It also includes one or more second dielectric layers, wherein the semiconductor layer is located between the one or more second dielectric layers and the stacked structure in the first direction; A first source contact passes through the one or more second dielectric layers and is connected to the semiconductor layer.

63. The three-dimensional (3D) storage device according to claim 61, characterized in that, The semiconductor channel is located at one end of the semiconductor layer in the first direction, and is higher than the storage film at one end of the conductor layer in the first direction.

64. The three-dimensional (3D) storage device according to claim 61, characterized in that, The storage film is lower than the semiconductor layer at the end closest to the conductor layer in the first direction.

65. The three-dimensional (3D) storage device according to claim 61, characterized in that, It also includes a substrate and peripheral circuitry formed on the substrate, the stacked structure being located between the semiconductor layer and the substrate along the first direction.

66. The three-dimensional (3D) storage device according to claim 62, characterized in that, It also includes a first interconnect layer, wherein the one or more second dielectric layers are located between the first interconnect layer and the semiconductor layer along a first direction, and the first interconnect layer is connected to the first source contact.

67. The three-dimensional (3D) storage device according to claim 66, characterized in that, It also includes a first contact structure that passes through the one or more second dielectric layers and the semiconductor layer along a first direction, the first contact structure being spaced apart from the semiconductor layer and connected to the first interconnect layer.

68. The three-dimensional (3D) storage device according to claim 67, characterized in that, Also includes: A second contact structure extending along the first direction, the second contact structure being located on one side of the stacked structure and spaced apart from the stacked structure in a second direction, the second direction being perpendicular to the first direction; The third interconnect layer, wherein the second contact structure is located between the first contact structure and the third interconnect layer, and the second contact structure is connected to both the first contact structure and the third interconnect layer.

69. The three-dimensional (3D) storage device according to claim 65, characterized in that, The semiconductor layer includes a portion extending beyond the stacked structure along a second direction perpendicular to the first direction, and further includes: A third contact structure, wherein the third contact structure and the portion of the third contact structure located outside the stacked structure, passing through the one or more second dielectric layers and the semiconductor layer along the first direction, are spaced apart from the semiconductor layer; A fourth contact structure extending along the first direction, the fourth contact structure being spaced apart from the stacked structure in the second direction, the fourth contact structure being connected to the first contact structure and the peripheral circuit respectively.

70. The three-dimensional (3D) storage device according to claim 61, characterized in that, The semiconductor layer includes an N-type or P-type doped semiconductor layer.

71. The three-dimensional (3D) storage device according to claim 62, characterized in that, Also includes: The second source contact is electrically isolated from the first source contact and passes through the one or more second dielectric layers and is connected to the semiconductor layer.

72. The three-dimensional (3D) storage device according to claim 71, characterized in that, Also includes: The second interconnect layer, wherein one or more second dielectric layers are located between the second interconnect layer and the semiconductor layer along the first direction, and the second interconnect layer is connected to the second source contact.

73. The three-dimensional (3D) storage device according to claim 61, characterized in that, Also includes: An insulating structure extends through the stacked structure along the first direction and contacts the semiconductor layer, the insulating structure being electrically insulated from the semiconductor layer.

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