Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package is provided, including: a first semiconductor chip; a second semiconductor chip disposed above the first semiconductor chip; a first seed film disposed on at least a portion of a first surface of the first semiconductor chip facing the second semiconductor chip; a second seed film disposed on the first seed film; a first barrier film disposed on the second seed film; a third seed film disposed on a lower portion of a second surface of the second semiconductor chip facing the first surface in a first direction intersecting the first surface; a fourth seed film disposed on a lower portion of the third seed film; a second barrier film disposed on a lower portion of the fourth seed film; a bonding film disposed between the first barrier film and the second barrier film; and a fill layer disposed between the first semiconductor chip and the second semiconductor chip and configured to surround the first seed film, the second seed film, the first barrier film, the third seed film, the fourth seed film, the second barrier film, and the bonding film.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0012360, filed with the Korean Intellectual Property Office on January 31, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiment relates to a semiconductor package and a method of manufacturing the semiconductor package. Background Technology

[0003] With the development of the electronics industry, the demand for high-performance, high-speed, and miniaturized electronic components is increasing. In response to this trend, methods such as stacking multiple semiconductor chips on a single package interconnect structure or stacking packages on packages can be used. For example, package-in-package (PIP) or package-on-package (POP) semiconductor packages can be used.

[0004] Meanwhile, as semiconductor packaging becomes increasingly integrated, methods are being used to vertically stack and bond semiconductor chips. Summary of the Invention

[0005] On the one hand, it provides a semiconductor package with improved bonding performance.

[0006] On the one hand, it provides a minimized semiconductor package.

[0007] On the one hand, a semiconductor package with improved high-speed performance is provided.

[0008] The technical tasks to be achieved in this example embodiment are not limited to those described above, and those skilled in the art can infer other technical tasks from the following example embodiments.

[0009] In one aspect, a semiconductor package is disclosed, comprising: a first semiconductor chip; a second semiconductor chip disposed above the first semiconductor chip; a first seed film disposed on at least a portion of a first surface of the first semiconductor chip facing the second semiconductor chip; a second seed film disposed on the first seed film; a first barrier film disposed on the second seed film; a third seed film disposed in a first direction intersecting the first surface of the first semiconductor chip at a lower portion of a second surface of the second semiconductor chip facing the first surface of the first semiconductor chip; a fourth seed film disposed at a lower portion of the third seed film; a second barrier film disposed at a lower portion of the fourth seed film; a bonding film disposed between the first barrier film and the second barrier film; and a filler layer disposed between the first semiconductor chip and the second semiconductor chip, and further disposed around the first seed film, the second seed film, the first barrier film, the third seed film, the fourth seed film, the second barrier film, and the bonding film.

[0010] According to one aspect, a semiconductor package is provided, comprising: a first semiconductor chip; a second semiconductor chip disposed above the first semiconductor chip; a first seed film disposed on at least a portion of a first surface of the first semiconductor chip facing the second semiconductor chip; a second seed film disposed on the first seed film; a first barrier film disposed on the second seed film; a third seed film disposed in a first direction intersecting the first surface, below a second surface of the second semiconductor chip facing the first surface; a fourth seed film disposed below the third seed film; a second barrier film disposed below the fourth seed film; a bonding film disposed between the first barrier film and the second barrier film; and a filler layer disposed between the first semiconductor chip and the second semiconductor chip, and configured to surround the first seed film, the second seed film, the first barrier film, the third seed film, the fourth seed film, the second barrier film, and the bonding film.

[0011] According to another aspect, a semiconductor package is provided, comprising: a buffer chip; a plurality of semiconductor chips stacked in a first direction intersecting an upper surface of the buffer chip and including a through-hole extending in the first direction; a plurality of bonding portions disposed in each of the spaces between the buffer chip and the plurality of semiconductor chips and electrically connected to the through-hole; and a filling layer disposed in each of the spaces between the buffer chip and the plurality of semiconductor chips and disposed around the plurality of bonding portions, wherein each of the plurality of bonding portions includes a first seed film, a second seed film, a first barrier film, a bonding film, a second barrier film, a fourth seed film, and a third seed film stacked sequentially in the first direction, wherein the second seed film, the fourth seed film, and the bonding film comprise the same metallic material, wherein the first barrier film and the second barrier film comprise metallic materials different from the metallic materials of the second seed film, the fourth seed film, and the bonding film, wherein the bonding film comprises nanotwinned copper, and wherein at least a portion of a side surface of the bonding film is coplanar with a side surface of the first barrier film.

[0012] According to one aspect, a semiconductor package is provided, comprising: a buffer chip; a plurality of semiconductor chips stacked in a first direction intersecting an upper surface of the buffer chip and including a through-hole extending in the first direction; a plurality of bonding portions disposed in each of a space between the buffer chip and the plurality of semiconductor chips and electrically connected to the through-hole; and a filling layer disposed in each of the space between the buffer chip and the plurality of semiconductor chips and configured to surround the plurality of bonding portions. Each of the plurality of bonding portions includes a first seed film, a second seed film, a first barrier film, a bonding film, a second barrier film, a fourth seed film, and a third seed film sequentially stacked in the first direction, wherein the second seed film, the fourth seed film, and the bonding film comprise the same metallic material, the first barrier film and the second barrier film comprise metallic materials different from the metallic materials of the second seed film, the fourth seed film, and the bonding film, the bonding film comprises nanotwinned copper, and at least a portion of a side surface of the bonding film is coplanar with a side surface of the first barrier film.

[0013] According to another aspect, a semiconductor package is provided, comprising: a first semiconductor chip; a second semiconductor chip disposed above the first semiconductor chip; a first seed film disposed on at least a portion of a first surface of the first semiconductor chip facing the second semiconductor chip; a second seed film disposed on the first seed film; a first barrier film disposed on the second seed film; a third seed film disposed in a first direction intersecting the first surface of the first semiconductor chip below a second surface of the second semiconductor chip facing the first surface of the first semiconductor chip; a fourth seed film disposed below the third seed film; a second barrier film disposed below the fourth seed film; a bonding film disposed between the first barrier film and the second barrier film; and a filler layer comprising a non-conductive film (NCF) and configured to fill the space between the first semiconductor chip and the second semiconductor chip, wherein the first seed film and the third seed film comprise titanium, wherein the second seed film and the fourth seed film comprise copper, wherein the first barrier film and the second barrier film comprise nickel, and wherein the bonding film comprises nanotwinned copper.

[0014] According to one aspect, a semiconductor package is provided, comprising: a first semiconductor chip; a second semiconductor chip disposed above the first semiconductor chip; a first seed film disposed on at least a portion of a first surface of the first semiconductor chip facing the second semiconductor chip; a second seed film disposed on the first seed film; a first barrier film disposed on the second seed film; a third seed film disposed below a second surface of the second semiconductor chip facing the first surface in a first direction intersecting the first surface; a fourth seed film disposed below the third seed film; a second barrier film disposed below the fourth seed film; a bonding film disposed between the first barrier film and the second barrier film; and a filler layer comprising a non-conductive film (NCF) and configured to fill the space between the first semiconductor chip and the second semiconductor chip. The first and third seed films comprise titanium, the second and fourth seed films comprise copper, the first and second barrier films comprise nickel, and the bonding film comprises nanotwinned copper.

[0015] According to one aspect, a method of manufacturing a semiconductor package is provided, the method comprising: forming a first pre-seed film configured to cover a first surface of a first semiconductor chip; forming a second pre-seed film on the first pre-seed film; forming a photomask on the second pre-seed film; forming a bonding portion patterned hole by patterning the photomask, the bonding portion patterned hole being configured to expose the second pre-seed film; forming a first blocking film and a first portion in the bonding portion patterned hole; removing the photomask; forming a first seed film and a second seed film by patterning the first pre-seed film and the first pre-seed film using the first blocking film and the first portion; and forming a second seed film on a second semiconductor chip. A third pre-seed film is formed on the second surface, the third pre-seed film being configured to cover the second surface; a fourth pre-seed film is formed on the third pre-seed film; a photomask is formed on the fourth pre-seed film; a bonding portion patterned hole is formed by patterning the photomask, the bonding portion patterned hole being configured to expose the fourth pre-seed film; a second blocking film and a second portion are formed in the bonding portion patterned hole; the photomask is removed; the third and fourth pre-seed films are formed by patterning the third and fourth pre-seed films using the second blocking film and the second portion; the first and second surfaces are bonded using a non-conductive film (NCF); and the first and second portions are bonded.

[0016] Specific details of other examples and embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0017] These and / or other aspects and features of the exemplary embodiments will become apparent and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0019] Figure 2 yes Figure 1 A magnified view of part P;

[0020] Figure 3 yes Figure 1 A magnified view of part P, used to describe a semiconductor package according to another example embodiment;

[0021] Figure 4 yes Figure 1 A magnified view of part P, used to describe a semiconductor package according to another example embodiment;

[0022] Figure 5 yes Figure 1 A magnified view of part P, used to describe a semiconductor package according to another example embodiment;

[0023] Figure 6 yes Figure 1 A magnified view of part P, used to describe a semiconductor package according to another example embodiment;

[0024] Figure 7 yes Figure 1 A magnified view of part P, used to describe a semiconductor package according to another example embodiment;

[0025] Figures 8 to 16 It shows the process of manufacturing. Figure 1 A diagram illustrating intermediate operations of a semiconductor packaging method. Detailed Implementation

[0026] Before describing this disclosure in detail, the terms or words used in this specification and claims should not be construed as limited to their ordinary or dictionary meanings. Furthermore, these terms or words should be interpreted as having meanings and concepts consistent with the technical spirit of this disclosure, based on the principle that the inventor can appropriately define the concepts of terms in order to best interpret the inventor's invention. The exemplary embodiments described in this specification and the configurations shown in the accompanying drawings are merely the most preferred embodiments of this disclosure and do not necessarily represent the entirety of the technical spirit of this disclosure. Therefore, various equivalents and modifications may exist at the time of this disclosure.

[0027] In the following description, unless the context clearly indicates otherwise, singular expressions also include plural expressions. It will be understood that when an element (e.g., a first element) is "(operably or communicatively) coupled to" or "connected to" another element (e.g., a second element), the element may be directly coupled to the other element, or there may be an intermediate element (e.g., a third element) between the element and the other element. The terms "having," "may have," "comprising," and "may include," as used herein, indicate the presence of a corresponding feature (e.g., an element such as a number, function, operation, or component) and do not exclude the presence of other features.

[0028] In this disclosure, unless the context clearly indicates otherwise, singular expressions also include plural expressions. Furthermore, the terms "first," "second," etc., can be used to describe various components. However, components are not limited by these terms, and these terms can be used for the purpose of distinguishing one component from another. Within the scope of the technical concept of this disclosure, a first component can be named a second component. Similarly, a second component can be named a first component. Furthermore, for clarity of description, the shape and size of components may be exaggerated.

[0029] Furthermore, in the following description, terms such as top, top, bottom, side, front, and rear are based on the orientation shown in the accompanying drawings. If the orientation of the object changes, it can be expressed in different ways. For clarity, the shape and size of the elements in the accompanying drawings may be exaggerated.

[0030] In addition, expressions such as "at least one of a, b and c" include only "a", only "b", only "c", "a and b", "a, b and c" and other variations.

[0031] In the following description, exemplary embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0032] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment. Figure 2 yes Figure 1 A magnified view of part P.

[0033] refer to Figure 1 and Figure 2 The semiconductor package may include a buffer chip 50, a plurality of semiconductor chips (a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300 and a fourth semiconductor chip 400), a bonding portion 500 and a bonding portion 500a, and a molding film 600.

[0034] According to some example embodiments, a buffer chip 50 may be disposed beneath multiple semiconductor chips (a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400). The buffer chip 50 may be electrically connected to the multiple semiconductor chips (a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400). The multiple semiconductor chips (a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400) may exchange electrical signals with external devices through the buffer chip 50.

[0035] According to some example embodiments, the buffer chip 50 may be a semiconductor device integrated circuit (IC), in which hundreds or even millions of semiconductor devices are integrated into a single chip. In example embodiments, the buffer chip 50 may be a logic chip. The buffer chip 50 may be an application processor, such as a microprocessor, analog device, digital signal processor, or microcontroller. In another example embodiment, the buffer chip 50 may be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), or cryptographic processor, but the buffer chip 50 is not limited thereto. In another example embodiment, the buffer chip 50 may be a memory chip, such as volatile memory (e.g., dynamic random access memory (DRAM)) or non-volatile memory (e.g., ROM or flash memory).

[0036] According to some example embodiments, the buffer chip 50 can be an interconnect structure for packaging. For example, the buffer chip 50 can be a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, it is apparent that the buffer chip 50 can be an interconnect structure for a wafer-level package (WLP) manufactured at the wafer level. The buffer chip 50 can be a semiconductor chip containing semiconductor devices. The buffer chip 50 can serve as a support substrate for a semiconductor package.

[0037] According to some example embodiments, the buffer chip 50 may be, but is not limited to, a glass substrate, a ceramic substrate, or a plastic substrate. For example, the buffer chip 50 may include a resin impregnated in a core material (e.g., glass fiber (glass cloth or glass fiber fabric)) having inorganic fillers (e.g., prepreg, Ajinomoto laminate (ABF), FR-4, or bismaleimide triazine (BT)).

[0038] According to some example embodiments, the buffer chip 50 may include, for example, bulk silicon or silicon-on-insulator (SOI). In another example embodiment, the buffer chip 50 may be a silicon substrate. In yet another example embodiment, the buffer chip 50 may include silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the buffer chip 50 is not limited thereto.

[0039] According to some example embodiments, the buffer chip 50 may include conductive regions, such as doped wells or doped structures. The buffer chip 50 may have various device isolation structures such as shallow trench isolation (STI) structures.

[0040] According to some example embodiments, the buffer chip 50 may include a body portion 51, a lower pad 52, and an upper pad 53.

[0041] According to some example embodiments, when the buffer chip 50 is a PCB, the main body portion 51 may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. The buffer chip 50 may include at least one material selected from tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, BT, hot melt adhesive, cyanate ester, and liquid crystal polymer.

[0042] According to some example embodiments, the body portion 51 may include a photoimaging dielectric. For example, the body portion 51 may include a photoimaging polymer. The photoimaging polymer may be formed of at least one of, for example, photoimaging polyimide, polybenzoxazole, phenol-based polymer, and benzocyclobutene-based polymer. In another example embodiment, the body portion 51 may be formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0043] Although not shown, the surface of the main body portion 51 may be covered by an upper insulating film and a lower insulating film. The upper and lower insulating films protect the substrate interconnect structures and other structures within the main body portion 51 from external impacts or moisture. The upper and lower insulating films may include solder resist. However, the example embodiment is not limited thereto.

[0044] According to some example embodiments, the lower pad 52 may be disposed on the lower part of the main body portion 51. The upper pad 53 may contact the bonding portion 500 disposed on the lower part of the first semiconductor chip 100.

[0045] Although not shown, a substrate interconnect structure may be disposed within the body portion 51. The substrate interconnect structure may include wiring layers and interconnect vias connecting each wiring layer. For example, the substrate interconnect structure may be a multilayer structure with two or more interconnect layers or two or more interconnect vias alternately stacked. For example, the interconnect layers may extend in a second direction D2 or a third direction D3. Interconnect vias may connect interconnect layers spaced apart in a first direction D1.

[0046] According to some example embodiments, the substrate interconnect structure may include a conductive material. For example, the substrate interconnect structure may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but the substrate interconnect structure is not limited thereto.

[0047] According to some example embodiments, external connection terminals 55 may be formed on the lower portion of buffer chip 50. External connection terminals 55 may be disposed on lower pad 52. External connection terminals 55 may contact lower pad 52. External connection terminals 55 may include solder balls or solder bumps. External connection terminals 55 may be, for example, spherical or elliptical in shape, but are not limited thereto. The number, spacing, arrangement, and shape of external connection terminals 55 are not limited to those shown in the figures, and it will be apparent that their number, spacing, arrangement, and shape may vary depending on the design. External connection terminals 55 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but are not limited thereto.

[0048] According to some example embodiments, the external connection terminal 55 can electrically connect the buffer chip 50 to an external device. Therefore, the external connection terminal 55 can provide electrical signals to the buffer chip 50, or the external connection terminal 55 can provide electrical signals from the buffer chip 50 to an external device. For example, the external connection terminal 55 can receive signals input to multiple semiconductor chips 10A, 10B, 10C, and 10D. The external connection terminal 55 can also receive signals output from multiple semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400).

[0049] According to some example embodiments, each of the plurality of semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) can be a logic chip or a memory chip. All of the plurality of semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) can be the same type of memory chip, or they can be a combination of different types of memory chips. For example, all of the plurality of semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) can be volatile memory chips, such as DRAM or static random access memory (SRAM). In another example embodiment, all of the plurality of semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) can be non-volatile memory chips, such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM). In another example embodiment, all of the plurality of semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300 and fourth semiconductor chip 400) can be high-bandwidth memory (HBM).

[0050] According to some example embodiments, some of the multiple semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) may be memory chips, while other semiconductor chips may be logic chips. For example, some of the multiple semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) may be microprocessors, analog components, digital signal processors, or application processors.

[0051] According to some example embodiments, a plurality of semiconductor chips may include a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400. The first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 may be stacked on a buffer chip 50 in a first direction D1 (e.g., a vertical direction). The first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 may be electrically connected to each other via a bonding portion 500, or may be electrically connected to the buffer chip 50.

[0052] According to some example embodiments, multiple semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) and buffer chip 50 can be attached to each other via NCF. Fill layer 150 may contain NCF. For example, fill layer 150 may be disposed between first semiconductor chip 100 and buffer chip 50. Fill layer 150 may be disposed between first semiconductor chip 100 and second semiconductor chip 200. Fill layer 150 may be disposed between second semiconductor chip 200 and third semiconductor chip 300, and between third semiconductor chip 300 and fourth semiconductor chip 400.

[0053] According to some example embodiments, the fill layer 150 may fill the space between the first semiconductor chip 100 and the second semiconductor chip 200. Hereinafter, "fill space" may include filling the entire space or filling less than the entire space. The fill layer 150 may cover the first surface S1 of the first semiconductor chip 100 and the second surface S2 of the second semiconductor chip 200. The fill layer 150 may also protrude outward from the side surfaces of the first semiconductor chip 100 and the second semiconductor chip 200. For example, the width of the fill layer 150 in the second direction D2 or the third direction D3 may be greater than the width of the first semiconductor chip 100 and the width of the second semiconductor chip 200. The second direction D2 may be a direction intersecting the first direction D1 and parallel to the first surface S1. The third direction D3 may be a direction intersecting the first direction D1 and parallel to the first surface S1. The third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. The fill layer 150 may be a single layer. The fill layer 150 may be disposed around the bonding portion 500 or may be configured to surround the bonding portion 500. The filler layer 150 can cover the side surface of the joint portion 500.

[0054] although Figure 1 The illustration shows four stacked semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400), but the example embodiment is not limited thereto. For example, a semiconductor package may contain a different number (e.g., one or two) of stacked semiconductor chips.

[0055] According to some example embodiments, the first semiconductor chip 100 may include a first semiconductor substrate 110, a first semiconductor device layer 120, and a first via 130. The first semiconductor chip 100 may be connected to the buffer chip 50 via a bonding portion 500.

[0056] According to some example embodiments, the first semiconductor substrate 110 may be, for example, bulk silicon or SOI. In another example embodiment, the first semiconductor substrate 110 may be a silicon substrate. In yet another example embodiment, the first semiconductor substrate 110 may include silicon germanium, SGOI, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the first semiconductor substrate 110 is not limited thereto.

[0057] According to some example embodiments, the first semiconductor substrate 110 may include conductive regions, such as doped wells or doped structures. The first semiconductor substrate 110 may have various device isolation structures, such as STI structures.

[0058] According to some example embodiments, a first semiconductor device layer 120 may be disposed on the lower portion of a first semiconductor substrate 110. The first semiconductor device layer 120 may include multiple individual devices and interlayer insulating films. Individual devices may include various microelectronic devices. For example, they may include metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-insulator-semiconductor (CMOS) transistors), system-on-a-system (LSI) circuits, image sensors such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, RRAM, CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active devices, and / or passive devices.

[0059] According to some example embodiments, individual devices of the first semiconductor device layer 120 may be electrically connected to conductive regions formed within the first semiconductor substrate 110. Individual devices of the first semiconductor device layer 120 may be electrically isolated from other adjacent individual devices via an insulating film. The first semiconductor device layer 120 may include a first interconnect structure 140 that electrically connects at least two or more of the plurality of individual devices to the conductive regions of the first semiconductor substrate 110.

[0060] According to some example embodiments, the first interconnect structure 140 may include metal interconnect layers and via plugs. For example, the first interconnect structure 140 may be a multilayer structure in which two or more metal interconnect layers and two or more via plugs are stacked alternately.

[0061] Although not shown, a passivation film may be formed on the lower portion of the first semiconductor device layer 120 to protect the first interconnect structure 140 and other structures within the first semiconductor device layer 120 from external impacts or moisture. The passivation film may cover the lower portion of the first semiconductor device layer 120 and may expose the side of the first interconnect structure 140 connected to the bonding portion 500.

[0062] According to some example embodiments, the first via 130 may penetrate the first semiconductor substrate 110. The first via 130 may extend downward from the upper surface of the first semiconductor substrate 110. The first via 130 may be connected to a first interconnect structure 140 disposed in the first semiconductor device layer 120.

[0063] According to some example embodiments, the first via 130 may include a barrier film formed on a columnar surface and a buried conductive layer filling the interior of the barrier film. The barrier film may include at least one of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB, but is not limited thereto. The buried conductive layer may include, but is not limited to, at least one of Cu, Cu alloys such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, W alloys, Ni, Ru, and Co.

[0064] According to some example embodiments, an insulating film may be disposed between the first semiconductor substrate 110 and the first via 130. The insulating film may include, but is not limited to, oxide films, nitride films, carbon films, polymers, or combinations thereof.

[0065] According to some example embodiments, a second semiconductor chip 200 may be disposed on a first semiconductor chip 100. The second semiconductor chip 200 may include a second semiconductor substrate 210, a second semiconductor device layer 220, a second via 230, and a second interconnect structure 240. The second semiconductor chip 200 may be electrically connected to the first semiconductor chip 100 via a bonding portion 500 disposed between the first semiconductor chip 100 and the second semiconductor chip 100.

[0066] According to some example embodiments, a third semiconductor chip 300 may be disposed on a second semiconductor chip 200. The third semiconductor chip 300 may include a third semiconductor substrate 310, a third semiconductor device layer 320, a third via 330, and a third interconnect structure 340. The third semiconductor chip 300 may be electrically connected to the second semiconductor chip 200 through a bonding portion 500 disposed between the second semiconductor chip 200 and the third semiconductor chip 200.

[0067] According to some example embodiments, a fourth semiconductor chip 400 may be disposed on a third semiconductor chip 300. The fourth semiconductor chip 400 may include a fourth semiconductor substrate 410, a fourth semiconductor device layer 420, and a fourth interconnect structure 440. The fourth semiconductor chip 400 may be electrically connected to the third semiconductor chip 300 via a bonding portion 500 disposed between the fourth semiconductor chip 300 and the first semiconductor chip 100. Unlike the first to third semiconductor chips 300, the fourth semiconductor chip 400 may not include vias.

[0068] According to some example embodiments, the descriptions of the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 are substantially the same as the descriptions of the first semiconductor chip 100, therefore the descriptions of the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 are omitted.

[0069] Figure 1 The illustration shows first semiconductor device layers 120 to 420 respectively disposed on the lower portions of first semiconductor substrates 110 to 410, but the example embodiment is not limited thereto. For example, first semiconductor device layer 120 may be disposed on the lower portion of first semiconductor substrate 110, while second semiconductor device layer 220 may be disposed on second semiconductor substrate 210. In this case, second semiconductor substrate 210 and first semiconductor substrate 110 may face each other. In another example embodiment, third semiconductor device layer 320 may be disposed on third semiconductor substrate 310, while fourth semiconductor device layer 420 may be disposed on the lower portion of fourth semiconductor substrate 410. In this case, third semiconductor device layer 320 and fourth semiconductor device layer 420 may face each other. The arrangement of multiple semiconductor chips (first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400) along the first direction D1 may vary depending on the example embodiment.

[0070] According to some example embodiments, bonding portions 500 and 500a may be disposed between the buffer chip 50 and the first semiconductor chip 100 to the fourth semiconductor chip 400. Bonding portion 500a may be disposed between the buffer chip 50 and the first semiconductor chip 100. Bonding portion 500 may be disposed in the space of each of the first semiconductor chip 100 to the fourth semiconductor chip 400. Since bonding portion 500a is substantially the same as bonding portion 500, the following description is based on bonding portion 500. It is shown that bonding portion 500a disposed between the buffer chip 50 and the first semiconductor chip 100 does not include the first seed film 511, the second seed film 521, and the first barrier film 531. However, the example embodiments are not limited thereto. For example, bonding portion 500a disposed between the buffer chip 50 and the first semiconductor chip 100 may include the first seed film 511, the second seed film 521, and the first barrier film 531.

[0071] According to some example embodiments, a bonding portion 500 may be disposed between the first semiconductor chip 100 and the second semiconductor chip 200 in a first direction D1. The bonding portion 500 can electrically connect the first semiconductor chip 100 and the second semiconductor chip 200. For example, the bonding portion 500 can electrically connect a first via 130 of the first semiconductor chip 100 and a second interconnect structure 240 of the second semiconductor chip 200.

[0072] According to some example embodiments, the bonding portion 500 may include a first seed film 511, a second seed film 521, a third seed film 512, a fourth seed film 522, a first barrier film 531, a second barrier film 532, and a bonding film 540. The first seed film 511, the second seed film 521, the third seed film 512, the fourth seed film 522, the first barrier film 531, the second barrier film 532, and the bonding film 540 may be disposed relative to each other in a first direction D1. The first seed film 511, the second seed film 521, the first barrier film 531, the bonding film 540, the second barrier film 532, the fourth seed film 522, and the third seed film 512 may be stacked in the first direction D1.

[0073] According to some example embodiments, a first seed film 511 may be disposed on a first semiconductor chip 100. The first seed film 511 may be disposed on a first surface S1 of the first semiconductor chip 100. The first seed film 511 may cover at least a portion of the first surface S1 of the first semiconductor chip 100. The first seed film 511 may be disposed between the first semiconductor chip 100 and a second seed film 521. The first surface S1 of the first semiconductor chip 100 may be the surface facing the second semiconductor chip 200. The first seed film 511 may include at least one selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In some example embodiments, the first seed film 511 may include titanium (Ti).

[0074] According to some example embodiments, a second seed film 521 may be disposed on the first seed film 511. The second seed film 521 may cover the first seed film 511. The second seed film 521 may be disposed between the first seed film 511 and the first barrier film 531. The second seed film 521 may include at least one selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The second seed film 521 may contain a different material than the first seed film 511. In some example embodiments, the second seed film 521 may include copper (Cu).

[0075] According to some example embodiments, the width of the first seed film 511 in the second direction D2 and the width of the second seed film 521 in the second direction D2 may be the same. The side surfaces 511SS of the first seed film 511 and the side surfaces 521SS of the second seed film 521 may be disposed on the same plane. The side surfaces 511SS of the first seed film 511 and the side surfaces 521SS of the second seed film 521 may be aligned in the first direction D1.

[0076] According to some example embodiments, a third seed film 512 may be disposed on the lower portion of the second semiconductor chip 200. The third seed film 512 may be disposed on the lower portion of the second surface S2 of the second semiconductor chip 200. The third seed film 512 may cover at least a portion of the second surface S2 of the second semiconductor chip 200. The third seed film 512 may be disposed on a fourth seed film 522. The third seed film 512 may cover the fourth seed film 522. The third seed film 512 may be disposed between the second semiconductor chip 200 and the fourth seed film 522. The second surface S2 of the second semiconductor chip 200 may be the surface facing the first semiconductor chip 100. The third seed film 512 may include at least one material selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The third seed film 512 may contain the same material as the first seed film 511. In some example embodiments, the third seed film 512 may include titanium (Ti).

[0077] According to some example embodiments, a fourth seed film 522 may be disposed on the second barrier film 532. The fourth seed film 522 may cover the second barrier film 532. The fourth seed film 522 may be disposed on the lower portion of the third seed film 512. The fourth seed film 522 may be disposed between the third seed film 512 and the second barrier film 532. The fourth seed film 522 may include at least one material selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The fourth seed film 522 may contain the same material as the second seed film 521. In some example embodiments, the fourth seed film 522 may include copper (Cu).

[0078] According to some example embodiments, the width of the third seed film 512 in the second direction D2 and the width of the fourth seed film 522 in the second direction D2 may be the same. The side surfaces 512SS of the third seed film 512 and 522SS of the fourth seed film 522 may be disposed on the same plane. The side surfaces 512SS of the third seed film 512 and 522SS of the fourth seed film 522 may be aligned in the first direction D1.

[0079] According to some example embodiments, a first barrier film 531 may be disposed on a second seed film 521. The first barrier film 531 may cover the second seed film 521. The first barrier film 531 may be disposed between the second seed film 521 and the bonding film 540. The first barrier film 531 may inhibit material diffusion between the second seed film 521 and the bonding film 540. The first barrier film 531 may include at least one selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The first barrier film 531 may include a metallic material different from the first seed film 511 and the second seed film 521. In some example embodiments, the first barrier film 531 may include nickel (Ni).

[0080] According to some example embodiments, the width of the first blocking film 531 in the second direction D2 may be the same as the width of the first seed film 511 and the width of the second seed film 521. The side surface 531SS of the first blocking film 531 may be disposed in the same plane as the side surface 511SS of the first seed film 511 and the side surface 521SS of the second seed film 521. The side surface 531SS of the first blocking film 531 may be aligned with the side surface 511SS of the first seed film 511 and the side surface 521SS of the second seed film 521 in the first direction D1.

[0081] According to some example embodiments, the width of the first barrier film 531 in the second direction D2 may be the same as the width of the bonding film 540. The side surface 531SS of the first barrier film 531 may be disposed in the same plane as at least a portion of the side surface 540SS of the bonding film 540. The side surface 531SS of the first barrier film 531 may be aligned with the side surface 540SS of the bonding film 540 in the first direction D1.

[0082] According to some example embodiments, a second barrier film 532 may be disposed on the bonding film 540. The second barrier film 532 may cover the bonding film 540. The second barrier film 532 may be disposed on the lower portion of the fourth seed film 522. The second barrier film 532 may be disposed between the fourth seed film 522 and the bonding film 540. The second barrier film 532 may suppress material diffusion between the fourth seed film 522 and the bonding film 540. The second barrier film 532 may include at least one material selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). The second barrier film 532 may contain the same material as the first barrier film 531. In some example embodiments, the second barrier film 532 may include nickel (Ni).

[0083] According to some example embodiments, the width of the second barrier film 532 in the second direction D2 may be the same as the width of the third seed film 512 and the width of the fourth seed film 522. The side surface 532SS of the second barrier film 532 may be disposed in the same plane as the side surfaces 512SS of the third seed film 512 and the fourth seed film 522. The side surface 532SS of the second barrier film 532 may be aligned with the side surfaces 512SS of the third seed film 512 and the fourth seed film 522 in the first direction D1.

[0084] According to some example embodiments, the width of the second barrier film 532 in the second direction D2 may be the same as the width of the bonding film 540. At least a portion of the side surface 532SS of the second barrier film 532 may be disposed in the same plane as the side surface 540SS of the bonding film 540. The side surface 532SS of the second barrier film 532 may be aligned with the side surface 540SS of the bonding film 540 in the first direction D1.

[0085] According to some example embodiments, the bonding film 540 may be disposed between the first barrier film 531 and the second barrier film 532. The bonding film 540 may be disposed on the first barrier film 531. The bonding film 540 may be disposed on the lower portion of the second barrier film 532. The bonding film 540 may include at least one material selected from, for example, titanium (Ti), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In some example embodiments, the bonding film 540 may include copper (Cu). In some example embodiments, the bonding film 540 may include nanotwinned copper.

[0086] According to some example embodiments, at least a portion of the side surface 540SS of the bonding membrane 540 may be coplanar with the side surface 511SS of the first seed membrane 511 and the side surface 521SS of the second seed membrane 521. The side surface 540SS of the bonding membrane 540 may be aligned with the side surface 511SS of the first seed membrane 511 and the side surface 521SS of the second seed membrane 521 in a first direction D1. At least a portion of the side surface 540SS of the bonding membrane 540 may be coplanar with the side surface 512SS of the third seed membrane 512 and the side surface 522SS of the fourth seed membrane 522. At least a portion of the side surface 540SS of the bonding membrane 540 may be coplanar with the side surface 531SS of the first barrier membrane 531 or the side surface 532SS of the second barrier membrane 532.

[0087] According to some example embodiments, in the first direction D1, the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 can be the same as each other. In the first direction D1, each of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 can be less than the thickness TH540 of the bonding film 540.

[0088] According to some exemplary embodiments, in the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, and TH531 of the first barrier film 531 may be less than the thickness TH540 of the bonding film 540. In the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 may be less than the thickness TH540 of the bonding film 540. However, the exemplary embodiments are not limited to this. In the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 can be greater than or equal to the thickness TH540 of the bonding film 540.

[0089] According to some example embodiments, the joining portion 500 may be surrounded by a filler layer 150, or the filler layer 150 may be disposed around the joining portion 500. The side surfaces 511SS of the first seed film 511, the second seed film 521, the third seed film 512SS, the fourth seed film 522SS, the first barrier film 531SS, the second barrier film 532SS, and the joining film 540SS may be in contact with the filler layer 150. The side surfaces 511SS of the first seed film 511, the second seed film 521SS, the third seed film 512SS, the fourth seed film 522SS, the first barrier film 531SS, the second barrier film 532SS, and the joining film 540SS may be covered by the filler layer 150.

[0090] According to some example embodiments, in the thermocompression bonding (TCB) method, bumps are used to bond multiple semiconductor chips. In thermocompression bonding, the heat compression can cause the bumps to protrude laterally. Therefore, there is a limitation to reducing the spacing between the multiple bumps below a threshold. In hybrid bonding methods, metal pads are directly bonded to metal pads, and insulating films with embedded metal pads are directly bonded to each other to bond multiple semiconductor chips. When bonding multiple semiconductor chips by hybrid bonding, the bonding strength between the insulating film and the metal pads may be weak.

[0091] According to some example embodiments, the bonding film 540 can improve the bonding strength by including nanotwinned copper. Nanotwinned copper can improve the bonding stability when copper is directly bonded to copper, including the (111) crystal plane. Because the bonding strength of the bonding film 540 is excellent, the first semiconductor chip 100 and the second semiconductor chip 200 can be bonded without using bumps. Since the gap between the bonding films 540 can be relatively reduced compared to bumps, the high-speed performance of the semiconductor package can be improved by increasing the number of bonding portions 500.

[0092] According to some example embodiments, when multiple semiconductor chips are joined using a bonding portion 500 with improved bonding strength, including nanotwinned copper, the gap between the multiple semiconductor chips in the first direction D1 can be reduced compared to bonding using bumps. Therefore, semiconductor packaging can be miniaturized.

[0093] According to some example embodiments, the filler layer 150 can protect the bonding portion 500, which can improve bonding stability. Furthermore, since the filler layer 150 directly bonds the first surface S1 of the first semiconductor chip 100 and the second surface S2 of the second semiconductor chip 200, the bonding strength between the first semiconductor chip 100 and the second semiconductor chip 200 can be improved.

[0094] According to some example embodiments, a molding film 600 may be formed on the buffer chip 50. The molding film 600 may cover the filler layer 150 and the first semiconductor chip 100 to the fourth semiconductor chip 400. The molding film 600 may contain a polymer, such as a resin. For example, the molding film 600 may include, but is not limited to, an epoxy molding compound (EMC).

[0095] According to some example embodiments, a molding film 60 may not be provided between the buffer chip 50 and the first semiconductor chip 100 to the fourth semiconductor chip 400. Specifically, since the filling layer 150 fills the space between the buffer chip 50 and the first semiconductor chip 100 to the fourth semiconductor chip 400, that is, it fills the space between the buffer chip 50 and the first semiconductor chip 100, and also fills the space between the first semiconductor chip 100 and the fourth semiconductor chip 400, a molding film 600 may not be provided between the buffer chip 50 and the first semiconductor chip 100 to the fourth semiconductor chip 400.

[0096] Figure 3 yes Figure 1 A magnified view of portion P, used to illustrate a semiconductor package according to another example embodiment. To illustrate a semiconductor package according to some other example embodiments, the description is primarily based on references to... Figure 1 and Figure 2 The differences in semiconductor packaging are described.

[0097] refer to Figure 3Each of the thicknesses TH531 of the first barrier film 531 and TH532 of the second barrier film 532 may differ from any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. Each of the thicknesses TH531 of the first barrier film 531 and TH532 of the second barrier film 532 may be greater than any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. For example, the thickness TH531 of the first barrier film 531 may be greater than any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. The thickness TH532 of the second barrier film 532 can be greater than any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. The thicknesses TH531 of the first barrier film 531 and TH532 of the second barrier film 532 can be the same. However, the exemplary embodiment is not limited to this. For example, the thicknesses TH531 of the first barrier film 531 and TH532 of the second barrier film 532 can be different from each other.

[0098] According to some example embodiments, in the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, and TH531 of the first barrier film 531 can be less than the thickness TH540 of the bonding film 540. In the first direction D1, the sum of the thicknesses TH512 of the third seed film 512, TH522 of the fourth seed film 522, and TH532 of the second barrier film 532 can be less than the thickness TH540 of the bonding film 540. In the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 can be less than the thickness TH540 of the bonding film 540.

[0099] Figure 4 yes Figure 1 A magnified view of portion P, used to illustrate a semiconductor package according to another example embodiment. To illustrate a semiconductor package according to some other example embodiments, the description is primarily based on references to... Figure 1 and Figure 2 The differences in semiconductor packaging are described.

[0100] refer to Figure 4 Each of the thicknesses TH531 of the first barrier film 531 and TH532 of the second barrier film 532 can be less than the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. For example, the thickness TH531 of the first barrier film 531 can be less than any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522. The thickness TH532 of the second barrier film 532 can be less than any one of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, and TH522 of the fourth seed film 522.

[0101] According to some example embodiments, in the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, and TH531 of the first barrier film 531 can be less than the thickness TH540 of the bonding film 540. In the first direction D1, the sum of the thicknesses TH512 of the third seed film 512, TH522 of the fourth seed film 522, and TH532 of the second barrier film 532 can be less than the thickness TH540 of the bonding film 540. In the first direction D1, the sum of the thicknesses TH511 of the first seed film 511, TH521 of the second seed film 521, TH512 of the third seed film 512, TH522 of the fourth seed film 522, TH531 of the first barrier film 531, and TH532 of the second barrier film 532 can be less than the thickness TH540 of the bonding film 540.

[0102] Figure 5 yes Figure 1 A magnified view of portion P, used to illustrate a semiconductor package according to another example embodiment. To illustrate a semiconductor package according to some other example embodiments, the description is primarily based on references to... Figure 1 and Figure 2 The differences in semiconductor packaging are described.

[0103] refer to Figure 5 The side surface 540SS of the bonding membrane 540 may have a slope. For example, the width of the bonding membrane 540 in the second direction D2 may not be constant.

[0104] According to some example embodiments, the bonding film 540 may include a first portion 541 and a second portion 542. The side surfaces of the first portion 541 and the second portion 542 may have different tilt angles relative to the first surface S1. For example, the side surfaces of the first portion 541 and the second portion 542 may be symmetrical in a first direction D1.

[0105] According to some example embodiments, as the first portion 541 moves closer to the second surface S2 from the first surface S1, the width of the first portion 541 may increase in the second direction D2 or the third direction D3. As the first portion 541 gets closer to the first semiconductor chip 100, the width of the first portion 541 may decrease in the second direction D2. The first portion 541 may be disposed on the first barrier film 531. The first portion 541 may be disposed between the first barrier film 531 and the second portion 542.

[0106] According to some example embodiments, as the second portion 542 moves closer to the second surface S2 from the first surface S1, the width of the second portion 542 may decrease in the second direction D2 or the third direction D3. As the second portion 542 gets closer to the second semiconductor chip 200, the width of the second portion 542 may decrease in the second direction D2. The second portion 542 may be disposed on the lower portion of the second barrier film 532. The second portion 542 may be disposed between the first portion 541 and the second barrier film 532.

[0107] According to some example embodiments, the bonding membrane 540 may include a point where the first portion 541 and the second portion 542 are connected. At this point, the width of the bonding membrane 540 may be maximized in either the second direction D2 or the third direction D3.

[0108] According to some example embodiments, the side surface 531SS of the first barrier film 531 may have an inclination. For example, the width of the first barrier film 531 may not be constant in the second direction D2. As the first barrier film 531 moves closer to the second surface S2 from the first surface S1, the width of the first barrier film 531 may increase in the second direction D2 or the third direction D3. The side surface 531SS of the first barrier film 531 may be coplanar with the side surface of the first portion 541 of the bonding film 540. The inclination angle of the side surface 531SS of the first barrier film 531 relative to the first surface S1 may be the same as the inclination angle of the side surface of the first portion 541 of the bonding film 540 relative to the first surface S1.

[0109] According to some example embodiments, the side surface 532SS of the second barrier film 532 may have an inclination. For example, the width of the second barrier film 532 in the second direction D2 may not be constant. As the second barrier film 532 moves closer to the second surface S2 from the first surface S1, the width of the second barrier film 532 may decrease in the second direction D2 or the third direction D3. The side surface 532SS of the second barrier film 532 may be coplanar with the side surface of the second portion 542 of the bonding film 540. The inclination angle of the side surface 532SS of the second barrier film 532 relative to the first surface S1 may be the same as the inclination angle of the side surface of the second portion 542 of the bonding film 540 relative to the first surface S1.

[0110] According to some example embodiments, in a cross-section including the first direction D1 and the second direction D2, the first barrier film 531 and the first portion 541 of the bonding film 540 may have an inverted trapezoidal shape. In a cross-section including the first direction D1 and the second direction D2, the second barrier film 532 and the second portion 542 of the bonding film 540 may have a trapezoidal shape. The slope of the first barrier film 531 and the first portion 541 of the bonding film 540, and the slope of the second barrier film 532 and the second portion 542 of the bonding film 540, may be formed due to the patterning characteristics during the manufacturing of semiconductor packages.

[0111] According to some example embodiments, the maximum width of the bonding film 540 in the second direction D2 can be greater than the widths of the first seed film 511, the second seed film 521, the third seed film 512, and the fourth seed film 522. For example, the width of the bonding film 540 can be increased at the point where the first portion 541 and the second portion 542 are connected. Because the bonding film 540 has a larger width, the bonding strength between the first semiconductor chip 100 and the second semiconductor chip 200 through the bonding portion 500 can be improved. Furthermore, the bonding portion 500 can reduce the resistance to electrical signal transmission between the first semiconductor chip 100 and the second semiconductor chip 200.

[0112] Figure 6 yes Figure 1 A magnified view of portion P, used to illustrate a semiconductor package according to another example embodiment. To illustrate a semiconductor package according to some other example embodiments, the description is primarily based on references to... Figure 1 and Figure 2 The differences in semiconductor packaging are described.

[0113] refer to Figure 6The bonding membrane 540 may include a first portion 541 and a second portion 542. The first portion 541 may be offset relative to the second portion 542 in a second direction D2. The offset of the first portion 541 relative to the second portion 542 may indicate that the first portion 541 and the second portion 542 are arranged in a stepped manner, without completely overlapping or aligning in the first direction D1.

[0114] According to some example embodiments, a first portion 541 may be disposed on a first barrier membrane 531. The first portion 541 may be in contact with the first barrier membrane 531. The first portion 541 may be aligned with the first seed membrane 511, the second seed membrane 521, and the first barrier membrane 531. The side surface 541SS of the first portion 541 may be coplanar with the side surface 511SS of the first seed membrane 511, the side surface 521SS of the second seed membrane 521, and the side surface 531SS of the first barrier membrane 531.

[0115] According to some example embodiments, the second portion 542 may be disposed on the lower part of the second barrier membrane 532. The second portion 542 may be in contact with the second barrier membrane 532. The second portion 542 may be aligned with the third seed membrane 512, the fourth seed membrane 522, and the second barrier membrane 532. The side surface 542SS of the second portion 542 may be coplanar with the side surface 512SS of the third seed membrane 512, the side surface 522SS of the fourth seed membrane 522, and the side surface 532SS of the second barrier membrane 532.

[0116] According to some example embodiments, in the second direction D2, the width of the first portion 541 and the width of the second portion 542 may be the same. The first portion 541 and the second portion 542 may not completely overlap in the first direction D1, but may only partially overlap and not overlap with the remaining portions. The side surfaces 541SS of the first portion 541 and 542SS of the second portion 542 may not be aligned on the same plane. The side surfaces 541SS of the first portion 541 and 542SS of the second portion 542 may have steps.

[0117] According to some example embodiments, the first seed film 511, the second seed film 521, and the first barrier film 531 may overlap with the first portion 541 of the bonding film 540 in the first direction D1. The third seed film 512, the fourth seed film 522, and the second barrier film 532 may overlap with the second portion 542 of the bonding film 540 in the first direction D1. The first seed film 511, the second seed film 521, and the first barrier film 531 may not completely overlap with the third seed film 512, the fourth seed film 522, and the second barrier film 532 in the first direction D1. The first seed film 511, the second seed film 521, and the first barrier film 531 may be offset relative to the third seed film 512, the fourth seed film 522, and the second barrier film 532 in the second direction D2.

[0118] According to some example embodiments, even if misalignment occurs between the first portion 541 and the second portion 542 when bonding the first semiconductor chip 100 and the second semiconductor chip 200, excellent bonding strength and stable bonding are provided because the first portion 541 and the second portion 542 contain nanotwinned copper.

[0119] Figure 6 The first part 541 and the second part 542 are shown to be separate, but the first part 541 and the second part 542 can also be formed as one unit. For example, the boundary between the first part 541 and the second part 542 may not be discernible.

[0120] Figure 7 yes Figure 1 A magnified view of portion P, used to illustrate a semiconductor package according to another example embodiment. To illustrate a semiconductor package according to some other example embodiments, the description is primarily based on references to... Figure 1 and Figure 2 The differences in semiconductor packaging are described.

[0121] refer to Figure 7 The bonding film 540 may include a first portion 541 and a second portion 542. In the second direction D2, the widths of the first portion 541 and the second portion 542 may be different. In the second direction D2, the width of the first portion 541 may be greater than the width of the second portion 542. The second portion 542, having a smaller width in the second direction D2, may completely overlap with the first portion 541 in the first direction D1. The side surface 542SS of the second portion 542 may be disposed inward relative to the side surface 541SS of the first portion 541. The side surface 541SS of the first portion 541 may be disposed outward more than the side surface 542SS of the second portion 542.

[0122] According to some example embodiments, a first portion 541 may be disposed on a first barrier membrane 531. The first portion 541 may be in contact with the first barrier membrane 531. The first portion 541 may be aligned with the first seed membrane 511, the second seed membrane 521, and the first barrier membrane 531. The side surface 541SS of the first portion 541 may be coplanar with the side surface 511SS of the first seed membrane 511, the side surface 521SS of the second seed membrane 521, and the side surface 531SS of the first barrier membrane 531.

[0123] According to some example embodiments, the second portion 542 may be disposed on the lower part of the second barrier membrane 532. The second portion 542 may be in contact with the second barrier membrane 532. The second portion 542 may be aligned with the third seed membrane 512, the fourth seed membrane 522, and the second barrier membrane 532. The side surface 542SS of the second portion 542 may be coplanar with the side surface 512SS of the third seed membrane 512, the side surface 522SS of the fourth seed membrane 522, and the side surface 532SS of the second barrier membrane 532.

[0124] According to some example embodiments, the second portion 542 may completely overlap with the first portion 541 in the first direction D1. Only a portion of the first portion 541 may overlap with the second portion 542 in the first direction D1, while other portions may not overlap with the second portion 542 in the first direction D1.

[0125] According to some example embodiments, the first seed film 511, the second seed film 521, and the first barrier film 531 may overlap with the first portion 541 of the bonding film 540 in the first direction D1. The third seed film 512, the fourth seed film 522, and the second barrier film 532 may overlap with the second portion 542 of the bonding film 540 in the first direction D1. In the second direction D2, the width of the first seed film 511, the width of the second seed film 521, and the width of the first barrier film 531 may be greater than the width of the third seed film 512, the width of the fourth seed film 522, and the width of the second barrier film 532.

[0126] According to some example embodiments, the distance between a side surface 541SS of one first portion 541 of each of two adjacent joint portions 500 in the second direction D2 and the other side surface 541SS of the other first portion 541 can be less than the distance between a side surface 542SS of one second portion 542 of each of two adjacent joint portions 500 in the second direction D2 and the other side surface 542SS of the other second portion 542. The distance between a side surface 511SS of one first seed membrane 511 of each of two adjacent joint portions 500 in the second direction D2 and the other side surface 511SS of the other first seed membrane 511, the distance between a side surface 521SS of one second seed membrane 521 of each of two adjacent joint portions 500 in the second direction D2 and the other side surface 521SS of the other second seed membrane 521, and the distance between a side surface 531SS of one first barrier membrane 531 of each of two adjacent joint portions 500 in the second direction D2 and the other side surface 531SS of the other first barrier membrane 531 can be... The distance between a side surface 512SS of a third seed membrane 512 and the other side surface 512SS of another third seed membrane 512 in each of two adjacent joint portions 500 in the second direction D2, the distance between a side surface 522SS of a fourth seed membrane 522 and the other side surface 522SS of another fourth seed membrane 522 in each of two adjacent joint portions 500 in the second direction D2, and the distance between a side surface 532SS of a second barrier membrane 532 and the other side surface 532SS of another second barrier membrane 532 in each of two adjacent joint portions 500 in the second direction D2.

[0127] According to some example embodiments, even if misalignment occurs between the first portion 541 and the second portion 542 when bonding the first semiconductor chip 100 and the second semiconductor chip 200, a stable bonding can be performed because the width of the first portion 541 is greater than the width of the second portion 542.

[0128] Figure 7 The first part 541 and the second part 542 are shown to be separate, but the first part 541 and the second part 542 can also be formed as one unit. For example, the boundary between the first part 541 and the second part 542 may not be discernible.

[0129] Figures 8 to 16 It shows the process of manufacturing. Figure 1 The diagram illustrates intermediate operations of a semiconductor packaging method. In the following text, the term "pre" may refer to an intermediate structure prior to its formation as the final structure.

[0130] refer to Figure 8 The third pre-seed film 512P and the fourth pre-seed film 522P can be sequentially formed on the second surface S2 of the first semiconductor chip 100. The first surface S1 of the first semiconductor chip 100 can be one side of the first semiconductor substrate 110. The second surface S2 of the first semiconductor chip 100 can be one side of the first semiconductor device layer 120.

[0131] According to some example embodiments, a third pre-seed film 512P and a fourth pre-seed film 522P may cover the entire second surface S2. The third pre-seed film 512P may be formed on the second surface S2. The fourth pre-seed film 522P may be formed on the third pre-seed film 512P. For example, the third pre-seed film 512P may contain titanium (Ti), and the fourth pre-seed film 522P may contain copper (Cu).

[0132] refer to Figure 9 The photomask 25 can be formed on the fourth pre-seed film 522P. The photomask 25 can cover the entire fourth pre-seed film 522P. For example, the photomask 25 can include a photoresist material.

[0133] refer to Figure 10 The photomask 25 can be patterned to form a bonding portion patterned hole 500H. The bonding portion patterned hole 500H can be formed by removing at least a portion of the photomask 25. The surface of the fourth pre-seed film 522P can be partially exposed within the bonding portion patterned hole 500H.

[0134] refer to Figure 11 The second barrier film 532 and the second portion 542 can be formed in Figure 10 The joint portion is within the patterned hole 500H. The second barrier film 532 and the second portion 542 can be filled. Figure 10 The joining portion of the patterned hole 500H. The second barrier film 532 and the second portion 542 can be sequentially formed in the... Figure 10 The bonding portion is within the patterned hole 500H. The second barrier film 532 may cover a portion of the fourth pre-seed film 522P. The second portion 542 may cover the second barrier film 532. For example, the second barrier film 532 may contain nickel (Ni), and the second portion 542 may contain nanotwinned copper.

[0135] According to some example embodiments, the second barrier membrane 532 and the second portion 542 can be coupled with... Figure 10 The photomask 25 contacts the pattern hole 500H in the joint portion. The side surface of the second blocking film 532 and the side surface of the second portion 542 that contacts the photomask 25 can be disposed on the same plane.

[0136] refer to Figure 12It can remove Figure 11 The photomask 25 in the middle. The surface of the fourth pre-seed film 522P can be exposed in areas other than the areas where the second blocking film 532 and the second part 542 are formed.

[0137] refer to Figure 13 The second blocking film 532 and the second part 542 can be used as masks for patterning. Figure 12 The third pre-seed membrane 512P and Figure 12 The fourth pre-seed film 522P is included. The third seed film 512 and the fourth seed film 522 can be formed to be aligned with the second barrier film 532 and the second portion 542. The side surface of each of the third seed film 512 and the fourth seed film 522 patterned using the second barrier film 532 and the second portion 542 as masks can be coplanar with the side surface of the second barrier film 532 and the side surface of the second portion 542.

[0138] refer to Figure 14 The first seed film 511, the second seed film 521, the first barrier film 531, and the first portion 541 can be formed on the first surface S1 of the first semiconductor chip 100. This can be compared with a reference... Figures 8 to 13 The third seed film 512, the fourth seed film 522, the second barrier film 532, and the second portion 542 are formed in the same manner as the first seed film 511, the second seed film 521, the first barrier film 531, and the first portion 541. For example, the first seed film 511 may contain titanium (Ti), and the second seed film 521 may contain copper (Cu). The first barrier film 531 may contain nickel (Ni), and the first portion 541 may contain nanotwinned copper.

[0139] refer to Figure 15 The bonding device 30 can be used to bond the first semiconductor chip 100 and the second semiconductor chip 200. The bonding device 30 can apply heat and pressure to bond the first semiconductor chip 100 and the second semiconductor chip 200. The bonding device 30 can apply pressure to the first semiconductor chip 100 and the second semiconductor chip 200 along a first direction D1.

[0140] According to some example embodiments, the second semiconductor chip 200 may include a first seed film 511, a second seed film 521, a first barrier film 531, and a first portion 541 formed on a first surface S1, and a third seed film 512, a fourth seed film 522, a second barrier film 532, and a second portion 542 formed on a second surface S2. For example, the first seed film 511, the second seed film 521, the first barrier film 531, and the first portion 541 are formed on the first surface S1 of the first semiconductor chip 100, and the third seed film 512, the fourth seed film 522, the second barrier film 532, and the second portion 542 are formed on the second surface S2 of the first semiconductor chip 100 (see reference). Figures 8 to 14 As described, the first seed film 511, the second seed film 521, the first barrier film 531 and the first portion 541 can be formed on the first surface S1 of the second semiconductor chip 200, and the third seed film 512 and the fourth seed film 522, the second barrier film 532 and the second portion 542 can be formed on the second surface S2 of the second semiconductor chip 200.

[0141] According to some example embodiments, the first surface S1 of the first semiconductor chip 100 and the second surface S2 of the second semiconductor chip 200 can be aligned to face each other. However, the example embodiments are not limited to this. Obviously, the second surface S2 of the first semiconductor chip 100 and the first surface S1 of the second semiconductor chip 200 can be aligned to face each other.

[0142] According to some example embodiments, the prefill layer 150P can be disposed between the first surface S1 of the first semiconductor chip 100 and the second surface S2 of the second semiconductor chip 200. The prefill layer 150P can be NCF. The first seed film 511, the second seed film 521, the first barrier film 531, and the first portion 541 formed on the first surface S1 of the first semiconductor chip 100 can be aligned with the third seed film 512, the fourth seed film 522, the second barrier film 532, and the second portion 542 formed on the second surface S2.

[0143] refer to Figure 16 It can be joined Figure 15 Part 1, 541 and Figure 15 The second part 542 forms the bonding film 540 and the bonding portion 500. It contains nano-twinned copper. Figure 15 Part 1, 541 and Figure 15 The second part 542 has the same grain size, so the bonding strength can be good. Figure 15 Part 1 541 and Figure 15 The boundary of the second part 542 joint may be difficult to discern. For example, the joint membrane 540 may appear to be integral. Through jointing... Figure 15 Part 1, 541 and Figure 15 The bonding film 540 formed by the second part 542, the first seed film 511, the second seed film 521, the first barrier film 531, the third seed film 512, the fourth seed film 522 and the second barrier film 532 can be electrically connected. The first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected through the bonding portion 500.

[0144] According to some example embodiments, the joint can be protected by using a filler layer 150. Figure 15 Part 1, 541 and Figure 15 The bonding portion 500 is formed during the second part 542 process. Furthermore, since the filler layer 150 fills the space between the first semiconductor chip 100 and the second semiconductor chip 200, the bonding can be made more robust. Figure 15 The pressure applied by the bonding device 30 when bonding the first semiconductor chip 100 and the second semiconductor chip 200 allows the filler layer 150 to protrude further outward from the side surfaces of the first semiconductor chip 100 and the second semiconductor chip 200.

[0145] In addition, refer to Figure 1 For reference Figures 8 to 14 The first semiconductor chip 100 and the second semiconductor chip 200 can be joined in the same manner as described above, and the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 can also be joined in the same manner using the joining portion 500. The buffer chip 50 and the first semiconductor chip 100 can also be joined in the same manner.

[0146] Figures 8 to 14 The illustration shows that a third seed film 512, a fourth seed film 522, a second barrier film 532, and a second portion 542 are first formed on the second surface S2 of the first semiconductor chip 100, and then a first seed film 511, a second seed film 521, a first barrier film 531, and a first portion 541 are formed on the first surface S1. However, the example embodiment is not limited to this. For example, it is obvious that the first seed film 511, the second seed film 521, the first barrier film 531, and the first portion 541 can be formed first on the first surface S1, and then the third seed film 512, the fourth seed film 522, the second barrier film 532, and the second portion 542 can be formed on the second surface S2.

[0147] Various embodiments of this disclosure have been described in detail above. However, it will be apparent to those skilled in the art that the scope of this disclosure is not limited thereto, and various modifications and variations can be made without departing from the technical spirit of this disclosure as set forth in the claims. Furthermore, the above example embodiments can be implemented by deleting some elements, and each example embodiment can be implemented in combination with each other.

Claims

1. A semiconductor package, comprising: First semiconductor chip; The second semiconductor chip is disposed above the first semiconductor chip; A first seed film is disposed on at least a portion of a first surface of the first semiconductor chip that faces the second semiconductor chip; The second seed membrane is disposed on the first seed membrane; A first barrier membrane is disposed on the second seed membrane; A third seed film is disposed on the lower part of the second surface of the second semiconductor chip facing the first surface of the first semiconductor chip in a first direction intersecting with the first surface of the first semiconductor chip; A fourth seed membrane is disposed below the third seed membrane; The second barrier membrane is disposed below the fourth seed membrane; A bonding membrane is disposed between the first barrier membrane and the second barrier membrane; as well as A filling layer is disposed between the first semiconductor chip and the second semiconductor chip, and is further disposed around the first seed film, the second seed film, the first barrier film, the third seed film, the fourth seed film, the second barrier film and the bonding film.

2. The semiconductor package according to claim 1, wherein, The bonding film comprises nanotwinned copper.

3. The semiconductor package according to claim 1, wherein, The first seed membrane and the third seed membrane are made of the same material.

4. The semiconductor package according to claim 1, wherein, At least a portion of the side surface of the bonding membrane is configured to be coplanar with the side surfaces of the first seed membrane and the second seed membrane.

5. The semiconductor package according to claim 1, wherein, The filling layer further protrudes outward from the side surfaces of the first semiconductor chip and the second semiconductor chip.

6. The semiconductor package according to claim 1, wherein, The filling layer covers the first surface of the first semiconductor chip and the second surface of the second semiconductor chip.

7. The semiconductor package according to claim 1, wherein, The filling layer includes a non-conductive film NCF.

8. The semiconductor package according to claim 1, wherein, The filling layer is a single-layer film.

9. The semiconductor package according to claim 1, wherein, In the first direction, the thickness of the first seed film, the thickness of the second seed film, and the thickness of the first barrier film are all less than the thickness of the bonding film.

10. The semiconductor package according to claim 1, wherein, In the first direction, the sum of the thickness of the first seed film, the thickness of the second seed film, and the thickness of the first barrier film is less than the thickness of the bonding film.

11. The semiconductor package according to claim 1, wherein, The bonding membrane includes: The first part is in contact with the first barrier membrane; and The second part is in contact with the second barrier membrane and connected to the first part. The side surfaces of the first part and the second part have steps.

12. The semiconductor package of claim 11, wherein, In a second direction intersecting the first direction and parallel to the first surface of the first semiconductor chip, the width of the first portion and the width of the second portion are equal, and The first portion is offset relative to the second portion in the second direction.

13. The semiconductor package of claim 11, wherein, In a second direction that intersects the first direction and is parallel to the first surface of the first semiconductor chip, the width of the first portion is greater than the width of the second portion, and The second part completely overlaps with the first part in the first direction.

14. The semiconductor package according to claim 1, wherein, The first barrier film comprises a metal material that is different from the metal material of the first seed film and the metal material of the second seed film.

15. The semiconductor package according to claim 1, wherein, The side surfaces of the first seed membrane and the second seed membrane are coplanar.

16. A semiconductor package, comprising: Buffer chip; Multiple semiconductor chips are stacked in a first direction intersecting the upper surface of the buffer chip, and include through-holes extending in the first direction; Multiple bonding portions are disposed in each of the spaces between the buffer chip and the multiple semiconductor chips, and are electrically connected to the via; as well as A filler layer is disposed in each of the spaces between the buffer chip and the plurality of semiconductor chips, and is disposed around the plurality of bonding portions. Each of the plurality of joining portions includes a first seed film, a second seed film, a first barrier film, a joining film, a second barrier film, a fourth seed film, and a third seed film sequentially stacked in the first direction. The second seed film, the fourth seed film, and the bonding film all comprise the same metallic material. The first barrier film and the second barrier film comprise metal materials different from the metal materials of the second seed film, the fourth seed film, and the bonding film. The bonding film comprises nanotwinned copper, and Wherein, at least a portion of the side surface of the bonding film is coplanar with the side surface of the first barrier film.

17. The semiconductor package of claim 16, wherein, At least a portion of the side surface of the bonding membrane is coplanar with the side surface of the second barrier membrane.

18. The semiconductor package of claim 16, wherein, In the first direction, each of the thicknesses of the first seed film, the second seed film, the first barrier film, the third seed film, the fourth seed film, and the second barrier film is less than the thickness of the bonding film.

19. The semiconductor package of claim 16, wherein, The plurality of semiconductor chips include high-bandwidth memory.

20. A semiconductor package, comprising: First semiconductor chip; The second semiconductor chip is disposed above the first semiconductor chip; A first seed film is disposed on at least a portion of a first surface of the first semiconductor chip that faces the second semiconductor chip; The second seed membrane is disposed on the first seed membrane; A first barrier membrane is disposed on the second seed membrane; A third seed film is disposed on the lower part of the second surface of the second semiconductor chip facing the first surface of the first semiconductor chip in a first direction intersecting with the first surface of the first semiconductor chip; A fourth seed membrane is disposed below the third seed membrane; The second barrier membrane is disposed below the fourth seed membrane; A bonding membrane is disposed between the first barrier membrane and the second barrier membrane; as well as A filler layer, comprising a non-conductive NCF film, is configured to fill the space between the first semiconductor chip and the second semiconductor chip. The first seed film and the third seed film comprise titanium. The second and fourth seed films comprise copper. Wherein, the first barrier film and the second barrier film comprise nickel, and The bonding film includes nanotwinned copper.

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