Hbt device with selective in-situ re-doped emitter and method of making the same

Abstract

The application discloses an HBT device with a selectively in-situ re-doped epitaxial emitter and a manufacturing method thereof, and the device manufacturing method comprises the following steps: providing a first SEG self-aligned front structure; forming a base region and an E-B junction isolation medium on the first self-aligned front structure; using a single-crystal-poly-crystal mixed thin film with a Cl-containing Si-based CVD precursor gas source for epitaxial in-situ re-doping as an emitter thin film; performing a rapid thermal annealing process; and performing a metallization process to obtain the HBT device. In the application, the epitaxy is performed by using the Cl-containing Si-based precursor gas source, so that the poly-crystal nucleation process of the Si source in the gas phase and on the surface of the E-B junction isolation medium can be effectively inhibited, and the emitter holes formed at the single-crystal-poly-crystal interface can be completely eliminated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication, and in particular relates to an HBT device with a selective in-situ heavily doped epitaxial emitter and its fabrication method. Background Technology

[0002] High-end, specialized analog circuit devices are manufactured using high-speed, advanced SiGe HBT (heterojunction bipolar transistor) technology with characteristic frequencies exceeding 200 GHz. The emitter layer of the SiGe HBT directly affects the device's characteristic frequency. f T Compared to traditional implantation and diffusion doping methods, in-situ doping can effectively reduce the thermal budget of the emitter layer and subsequent processes, improving device yield and process stability. A typical polycrystalline silicon in-situ phosphorus doping design process has been applied to SiGe HBT emitter manufacturing, but the resulting emitter material has high resistance, and the device's characteristic frequency... f T Low performance ceiling. Currently, in high-end SiGe chip manufacturing, advanced process technology for in-situ heavy As-doped emitters can produce heavy As-doped, low-resistivity emitter single-crystal silicon, which has been widely used in advanced SiGe BiCMOS manufacturing processes. However, as device process nodes continue to shrink, serious problems such as emitter seam formation at the single-crystal-polycrystalline interface, emitter punch-through, and short circuits in the device's EB (emitter-base) junction have emerged, which severely affect device yield. Summary of the Invention

[0003] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide an HBT device with a selective in-situ heavily doped epitaxial emitter and a method for fabricating the same.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter includes the following steps: S100, Provide a first SEG self-alignment front structure with a base region window; S200. An HBT base region and an EB junction isolation medium are formed on the first SEG self-aligned pre-structure to obtain a second SEG self-aligned pre-structure. S300. Using a single-crystal-polycrystalline mixed-crystal thin film with Cl-containing Si-based CVD precursor gas source epitaxial in situ heavily doped as an emitter thin film on the second SEG self-aligned pre-structure, a first sample is obtained. S400. Perform a rapid thermal annealing process on the first sample to obtain the second sample; S500. Perform a metallization process on the second sample to obtain an HBT device.

[0005] Furthermore, the first HBT device front structure includes a substrate and a Si collector epitaxial layer, a TEOS layer and a polysilicon outer base region sequentially disposed on the substrate. A first window is formed on the TEOS layer, and a second window is formed on the polysilicon outer base region at a position corresponding to the first window (making the first window and the second window connected). The first window and the second window together form the base region window.

[0006] Furthermore, step S100 includes the following sub-steps: S110, Select a first SEG self-alignment front structure; S120. Perform standard RCA cleaning on the first SEG self-aligned pre-structure. S130. Place the cleaned first SEG self-aligned pre-structure in the reaction chamber for SICONI pretreatment.

[0007] Furthermore, step S200 includes the following sub-steps: S210. An HBT base region is formed in the base region window of the first SEG self-aligned front structure by selectively epitaxial base region thin film. S220. An EB junction isolation medium is deposited on the upper surface of the first SEG self-aligned front structure and the sidewall of the base region window (i.e., the sidewall of the second window).

[0008] Furthermore, the base region thin film is a single-crystal SiGe thin film; and / or The structure of the EB junction isolation medium is SIN / OX / SIN.

[0009] Furthermore, in step S400, the temperature of the rapid thermal annealing process is 800–900 °C, and the annealing time is 5–15 s.

[0010] Furthermore, in step S300, the heavily doped single-crystal-polycrystalline mixed film is a heavily doped As-Si mixed film; a heavily doped single-crystal As-Si film is rapidly epitaxially grown on the HBT base region using a Si-based CVD precursor gas source containing Cl, while a heavily doped polycrystalline As-Si film is selectively and slowly deposited on the EB junction isolation medium to form a heavily doped As-Si mixed film.

[0011] Furthermore, in step S300, the Si-based CVD precursor gas source containing Cl used during epitaxy includes a Si source precursor gas source and a doping gas. The Si source precursor gas source is a DCS, and the doping gas is a 1% AsH3 mixed with H2 gas. The epitaxy pressure is 100-150 Torr, and the temperature is stabilized at 630-700 °C.

[0012] Furthermore, in step S300, the Si-based CVD precursor gas source containing Cl used during epitaxy also includes an auxiliary precursor gas source to ensure the epitaxial growth rate, wherein the auxiliary precursor gas source is SiH4.

[0013] A selective in-situ heavily doped epitaxial emitter HBT device is fabricated using the selective in-situ heavily doped epitaxial emitter HBT device fabrication method described in any of the preceding items.

[0014] In this invention, by employing a Si-based CVD precursor gas source containing Cl, the polycrystalline nucleation process of the Si source in the gas phase and at the surface of the EB junction isolation dielectric can be effectively suppressed. This balances the growth rates of single-crystal As-Si films and polycrystalline As-Si films, completely eliminating emitter voids formed at the single-crystal-polycrystalline interface. Simultaneously, the increased proportion of single-crystal As-Si film thickness effectively reduces the resistivity of the emitter film, significantly improving the overall electrical performance of the HBT device. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the structure with emitter pores when using a traditional CVD precursor deposition process.

[0016] Figure 2 This is a flowchart of an embodiment of the method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter according to the present invention.

[0017] Figure 3 This is a schematic diagram of the first SEG self-aligned pre-structure.

[0018] Figure 4 This is a schematic diagram of the structure after the HBT base region is formed on the first SEG self-aligned pre-structure.

[0019] Figure 5 This is a schematic diagram of the second SEG self-aligned pre-structure.

[0020] Figure 6 This is a schematic diagram of the structure of the first sample.

[0021] The reference numerals in the accompanying drawings are as follows: First SEG self-aligned front structure 100; Substrate 110; Si collector epitaxial layer 120; TEOS layer 130; Polysilicon outer base region 140; Base region window 150; First window 151; Second window 152; Second SEG self-aligned front structure 200; HBT base region 210; EB junction isolation medium 220; First sample 300; Emitter thin film 310; Single crystal As-Si thin film 311; Polycrystalline As-Si thin film 312; Emitter hole 320. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0023] As semiconductor processes advance towards refinement and high performance, the advanced technology of in-situ heavy doping of emitters with arsenic (As) has gradually replaced the traditional phosphorus doping process and has been widely adopted in the manufacturing of high-end SiGe chips. This process uses As as the heavy doping element. As has high activation efficiency and high carrier concentration in silicon materials, enabling the fabrication of heavily doped, low-resistivity emitter single-crystal silicon, effectively improving the characteristic frequency of SiGe HBT devices. f T With its current driving capability, it meets the high-performance requirements of advanced SiGeBiCMOS manufacturing processes, providing technical support for the research and development and production of high-end SiGe chips.

[0024] However, as device process nodes continue to shrink, when the HBT manufacturing process node drops to 0.13 μm and below, the device's structural size shrinks significantly, and the emitter's self-alignment window also decreases, bringing many technical challenges to emitter fabrication. Please see [link to relevant documentation]. Figure 1 Among these issues, the most prominent problems include: the easy formation of emitter holes 320 at the single-crystal-polycrystalline interface. Emitter holes 320 disrupt the structural integrity of the emitter, hindering carrier transport and increasing the risk of device leakage; the emitter is prone to punch-through, meaning the depletion layer between the emitter and base is connected, causing the device to malfunction; and the EB (emitter-base) junction is prone to short circuits, directly leading to device failure. These problems, combined, severely impact the production yield of SiGe HBT devices, restricting the large-scale application of high-end SiGe chips at process nodes of 0.13μm and below, and becoming a critical technical bottleneck that urgently needs to be addressed in the development of advanced SiGe HBT processes.

[0025] Please seeFigure 2 , Figure 2 This is a flowchart illustrating an embodiment of the method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter according to the present invention. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter in this embodiment includes the following steps: S100. Provide a first SEG (Selective Epitaxial Growth) pre-structure 100 with a base region window 150. The first SEG self-aligned pre-structure 100 is the basic carrier for the entire HBT device fabrication. Its surface cleanliness directly affects the fabrication quality of subsequent structures such as the HBT base region 210 and emitter film 310. The base region window 150 is the growth region of the HBT base region 210. To ensure that the first SEG self-aligned pre-structure 100 meets the requirements of subsequent processes, this step may specifically include the following sub-steps: S110, please refer to Figure 3 A first SEG self-aligned pre-structure 100 is selected. Specifically, the first SEG self-aligned pre-structure 100 includes a substrate 110 and a Si collector epitaxial layer 120, a TEOS layer 130, and a polysilicon outer base region 140 sequentially stacked on the substrate 110. The substrate 110 serves as the supporting foundation for the entire device and is preferably a high-purity single-crystal silicon substrate to ensure the structural stability of the device. The Si collector epitaxial layer 120 is used to subsequently form the collector of the HBT device, providing a carrier collection channel. The TEOS layer 130 is a silicon dioxide insulating layer formed by tetraethyl orthosilicate deposition, used to achieve electrical isolation between the Si collector epitaxial layer 120 and the polysilicon outer base region 140, preventing leakage between them. A first window 151 is formed on the TEOS layer 130 through photolithography and etching processes, and a second window 152 is formed on the polysilicon outer base region 140 at the position corresponding to the first window 151 through photolithography and etching processes. The first window 151 and the second window 152 are connected, and together they form the base region window 150, providing an accurate growth area for the subsequent selective epitaxial growth of the HBT base region 210.

[0026] S120. Perform standard RCA cleaning on the first SEG self-aligned pre-structure 100. During the fabrication process, the surface of the first SEG self-aligned pre-structure 100 will be contaminated with organic matter, metal ions, particulate impurities, and other pollutants. These contaminants will affect the epitaxial quality of the subsequent HBT base region 210. Therefore, a standard RCA cleaning process is required to thoroughly clean the first SEG self-aligned pre-structure 100. RCA cleaning is a standard semiconductor wafer cleaning method proposed by RCA Corporation. It mainly removes organic matter, metal ions, and particulate impurities from the surface of the first SEG self-aligned pre-structure 100 through a multi-step chemical cleaning process. After cleaning, it is rinsed with high-purity deionized water and dried to ensure the interface quality of subsequent processes. This cleaning method is a conventional and mature technology in the semiconductor field, and its specific cleaning parameters and operating procedures will not be elaborated here.

[0027] S130. The cleaned first SEG self-aligned pre-structure 100 is placed in the reaction chamber for SICONI pretreatment. After standard RCA cleaning, although most contaminants have been removed from the surface of the first SEG self-aligned pre-structure 100, there may still be minor interface defects, affecting the bonding force between the subsequent HBT base region 210 and the first SEG self-aligned pre-structure 100, as well as the crystal quality of the epitaxial layer. Therefore, SICONI (Silicon Carbon Nitride Interface) pretreatment is required. This process is a conventional pretreatment process used to optimize interface performance in semiconductor device fabrication. By introducing a specific reactive gas into the reaction chamber, a thin and uniform silicon carbon nitride interface layer is formed on the surface of the first SEG self-aligned pre-structure 100, thereby repairing interface defects, improving interface flatness, and enhancing the bonding force between the subsequent epitaxial layer and the substrate, laying a good foundation for the selective epitaxial growth of the HBT base region 210. The specific process and parameters are conventional techniques well known to those skilled in the art and will not be described in detail here.

[0028] S200: An HBT base region 210 and an EB junction isolation dielectric 220 are formed on the first SEG self-aligned pre-structure 100 to obtain a second SEG self-aligned pre-structure 200. This step is a crucial step in the formation of the main structure of the HBT device. The HBT base region 210, as an important region for carrier transport in the device, directly affects the current gain and high-frequency performance of the device due to its crystal quality and thickness uniformity. The EB junction isolation dielectric 220 is used to achieve electrical isolation between the HBT base region 210 and the subsequent emitter film 310, avoiding leakage between them and ensuring the electrical stability of the device. To ensure the fabrication quality of the HBT base region 210 and the EB junction isolation dielectric 220, this step may specifically include the following sub-steps: S210, please refer to Figure 4In the base region window 150 (specifically the first window 151) of the first SEG self-aligned pre-structure 100, the HBT base region 210 is formed by selectively epitaxially growing a base region thin film. The selective epitaxy process can precisely control the growth area of ​​the base region thin film, ensuring the positional accuracy and structural integrity of the HBT base region 210. In this embodiment, the base region thin film is a single-crystal SiGe thin film. SiGe material has excellent heterojunction characteristics, and compared with traditional Si-based base regions, it can effectively improve the current gain and cutoff frequency of the HBT device, meeting the high-performance requirements of the HBT device.

[0029] S220, please refer to Figure 5 An EB junction isolation dielectric 220 is deposited on the upper surface of the first SEG self-aligned front structure 100 (i.e., the surface of the polysilicon outer base region 140) and the sidewall of the base region window 150 (i.e., the sidewall of the second window 152). The deposition process can employ chemical vapor deposition (CVD) to ensure uniform coverage and consistent thickness of the EB junction isolation dielectric 220, thereby effectively forming isolation and preventing electrical short circuits or leakage. In this embodiment, the EB junction isolation dielectric 220 has a three-layer composite structure of SIN / OX / SIN. The SIN (silicon nitride) layer has excellent insulation properties and the ability to block impurity diffusion. The OX (silicon dioxide) layer serves as an intermediate buffer layer, enhancing the bonding strength of the three-layer structure. Compared to a single insulating layer, the three-layer composite structure offers superior insulation performance and structural stability, better ensuring the electrical performance and long-term reliability of the HBT device.

[0030] S300, please refer to Figure 6 A first sample 300 is obtained by using a Si-based CVD precursor gas source epitaxially heavily doped single-crystal-polycrystalline mixed-crystal thin film containing Cl as the emitter thin film 310 on the second SEG self-aligned pre-structure 200. The emitter thin film 310 is used for carrier injection in HBT devices. Its doping concentration, crystal quality, and surface flatness directly determine the switching speed and current driving capability of the device. The use of an in-situ heavily doped single-crystal-polycrystalline mixed-crystal structure can balance good contact between the emitter and the HBT base region 210 and the integration density of the device. In this embodiment, the heavily doped single-crystal-polycrystalline mixed-crystal thin film is a heavily doped As-Si mixed-crystal thin film. Using arsenic (As) as the heavily doped element can effectively increase the carrier concentration of the emitter thin film 310 and reduce the emitter resistivity. The nominal thickness of the As-Si mixed crystal thin film can be about 100 nm. This thickness can balance the electrical performance of the emitter and the integration of the device, avoiding the increase in device size due to excessive thickness or the decrease in carrier transport efficiency due to excessive thinness.

[0031] The emitter film 310 specifically includes a single-crystal As-Si film 311 formed on the surface of the HBT base region 210 and a polycrystalline As-Si film 312 covering the single-crystal As-Si film 311 and the surface of the EB junction isolation medium 220. Its formation principle is as follows: A heavily doped single-crystal As-Si film 311 is rapidly epitaxially deposited on the single-crystal SiGe surface of the HBT base region 210 using a Si-based CVD precursor gas source containing Cl. The lattice matching between single-crystal SiGe and single-crystal As-Si ensures a tight interface bond and few defects. Simultaneously, a heavily doped polycrystalline As-Si film 312 is selectively and slowly deposited on the surface of the EB junction isolation medium 220, thereby forming a structurally complete and high-performance heavily doped As-Si mixed-crystal film, i.e., the emitter film 310.

[0032] In this step, the Si-based CVD precursor gas source used for epitaxy includes a Si source precursor gas source and a doping gas. The Si source precursor gas source is the main raw material for forming the As-Si mixed-crystal thin film. The Si source precursor gas source is preferably DCS (Dichlorosilane, chemical formula SiH2Cl2). The doping gas is AsH3 gas with 1% H2 mixture. During epitaxy, process parameters are strictly controlled: the epitaxy pressure is 100–150 Torr, and the temperature is stabilized at 630–700℃. For example, the epitaxy pressure can be approximately 100 Torr, 110 Torr, 120 Torr, 130 Torr, 140 Torr, 150 Torr, etc., and the temperature can be stabilized at approximately 630℃, 640℃, 650℃, 660℃, 670℃, 680℃, 690℃, 700℃, etc.

[0033] By using a Cl-containing DCS as the Si source precursor gas source, its advantage lies in effectively suppressing the polycrystalline nucleation process of the Si source in the gas phase and on the surface of the EB junction isolation medium 220. Since the ratio of silicon to chlorine in the DCS is fixed at 1:2, the introduction of chlorine gas of this ratio can further optimize the nucleation suppression effect, effectively suppressing the formation of pores, so that the growth rates of the single-crystal As-Si film 311 and the polycrystalline As-Si film 312 reach a balance, thereby avoiding the formation of pore structures (i.e., emitter pores 320) at the single-crystal-polycrystalline interface, ensuring the pore-filling ability of the heavily doped As-Si material, and ensuring the surface flatness and structural integrity of the emitter film 310. At the same time, this process can also increase the thickness ratio of the single-crystal As-Si film 311. The single-crystal structure has a lower resistivity than the polycrystalline structure, thereby reducing the overall resistivity of the emitter film 310 and improving the overall electrical performance of the HBT device. Finally, a heavily doped HBT device emitter film 310 with a flat surface, high doping concentration, and high crystal quality can be directly obtained through epitaxy.

[0034] However, in practical applications, it has been found that when only DCS is used as the Si source precursor gas source, the decomposition rate of the Si source is slow, resulting in extremely slow growth of the As-Si mixed-crystal thin film. This significantly prolongs the process cycle, reduces production efficiency, and increases manufacturing costs, failing to meet the demands of large-scale mass production. Therefore, in this embodiment, the Si-based CVD precursor gas source used in epitaxy also includes an auxiliary precursor gas source, namely SiH4 (silane). As a highly active silicon source, SiH4 has a fast decomposition rate. By introducing SiH4 into the Si-based CVD precursor gas source, the growth rate of silicon can be greatly increased without affecting the crystal quality and doping uniformity of the emitter thin film 310, effectively shortening the process cycle and improving production efficiency. Simultaneously, it can also help balance the growth rates of single-crystal As-Si thin films 311 and polycrystalline As-Si thin films 312, further optimizing the structure and performance of the emitter thin film 310.

[0035] S400. Perform a rapid thermal annealing (RTP) process on the first sample 300 to obtain the second sample. During the epitaxial growth process, the emitter film 310 in the first sample 300 may develop a small number of lattice defects, and the doped arsenic element may not be fully activated, potentially leading to suboptimal electrical performance of the emitter film 310. Therefore, the first sample 300 needs to be processed using a rapid thermal annealing process. In this step, the temperature of the rapid thermal annealing process is controlled between 800 and 900°C, for example, approximately 800°C, 820°C, 840°C, 860°C, 880°C, 900°C, etc., preferably approximately 850°C; the annealing time is controlled between 5 and 15 seconds, for example, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds, 10 seconds, 11 seconds, 12 seconds, 13 seconds, 14 seconds, 15 seconds, etc., preferably approximately 10 seconds. These process parameters can fully activate the arsenic doping, improve the carrier concentration and conductivity of the emitter film 310, effectively repair lattice defects generated during epitaxy, optimize the crystal quality of the emitter film 310, and avoid excessive diffusion of arsenic due to excessive temperature or time, thus ensuring the junction depth accuracy between the HBT base region 210 and the emitter film 310 and guaranteeing the stability of the device's electrical performance.

[0036] S500. Perform a metallization process compatible with standard CMOS procedures on the second sample to obtain an HBT device. The purpose of the metallization process is to form metal electrodes on the surface of the second sample, enabling electrical connection between the device and external circuits. To reduce the difficulty and cost of device integration manufacturing and facilitate the integration of the HBT device with other CMOS devices, this step adopts a metallization process compatible with standard CMOS procedures, which may include sub-steps such as metal layer deposition, photolithography, etching, and annealing, thereby ultimately completing the fabrication of the HBT device.

[0037] In this embodiment, by employing a Cl-containing CVD precursor gas source DCS, the polycrystalline nucleation process of the Si source in the gas phase and on the surface of the EB junction isolation medium 220 can be effectively suppressed. By precisely adjusting the Si / Cl ratio, the growth rates of the single-crystal As-Si thin film 311 and the polycrystalline As-Si thin film 312 are balanced, completely eliminating the emitter void 320 formed at the single-crystal-polycrystalline interface. Simultaneously, the increased thickness of the single-crystal As-Si thin film 311 effectively reduces the resistivity of the emitter thin film 310, significantly improving the overall electrical performance of the HBT device. This embodiment uses a one-step epitaxial manufacturing method with a Cl-containing CVD precursor, eliminating the need for subsequent additional doping processes, directly obtaining an As-doped HBT device emitter thin film 310 with a smooth surface, high doping concentration, and high crystal quality, simplifying the process steps. Overall, this embodiment features a simple manufacturing process, low cost, and ease of implementation, making it directly applicable to production practice and possessing the potential for large-scale promotion. By tackling key challenges in the As in-situ doping extension process technology, the characteristic frequency of the SiGe HBT can be guaranteed. f T With a speed exceeding 260 GHz, it effectively solves the problem of high-end SiGe BiCMOS chips, fills the gap in my country's SiGe BiCMOS process manufacturing field, and has important industrial application value and national strategic significance.

[0038] Please continue reading. Figure 6 This invention also discloses a selective in-situ heavily doped epitaxial emitter HBT device. This HBT device can be fabricated using the selective in-situ heavily doped epitaxial emitter HBT device fabrication method described in any of the above embodiments. The emitter film 310 of this HBT device has a smooth surface, high doping concentration, and high crystal quality. Furthermore, the single-crystal As-Si film 311 of the HBT device has a tight interface with the HBT base region 210 with few defects, and the polycrystalline As-Si film 312 achieves large-area coverage of the emitter, balancing the device's electrical performance and integration density. Simultaneously, the heavy arsenic doping effectively reduces the emitter resistivity, improves the device's switching speed and current drive capability, and ensures the device's electrical stability.

[0039] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter, characterized in that, Includes the following steps: S100, Provide a first SEG self-alignment front structure with a base region window; S200: An HBT base region and EB (base-emitter) junction isolation medium are formed on the first SEG self-aligned front structure to obtain a second SEG self-aligned front structure; S300. Using a single-crystal-polycrystalline mixed-crystal thin film with Cl-containing Si-based precursor gas source epitaxial in situ heavily doped as an emitter thin film on the second SEG self-aligned pre-position structure, a first sample is obtained. S400. Perform a rapid thermal annealing process on the first sample to obtain the second sample; S500. Perform a metallization process on the second sample to obtain an HBT device.

2. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 1, characterized in that: The first HBT device front structure includes a substrate and a Si collector epitaxial layer, a TEOS layer, a polysilicon outer base region, and a SiGe SEG inner base region sequentially disposed on the substrate. A first window is formed on the TEOS layer, and a second window is formed on the polysilicon outer base region at the position corresponding to the first window (making the first window and the second window connected). The first window and the second window together form the base region window.

3. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 1, characterized in that, Step S100 includes the following sub-steps: S110, Select a first SEG self-alignment front structure; S120. Perform standard RCA cleaning on the first SEG self-aligned pre-structure. S130. Place the cleaned first SEG self-aligned pre-structure in the reaction chamber for SICONI pretreatment.

4. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 1, characterized in that, Step S200 includes the following sub-steps: S210. An HBT base region is formed in the base region window of the first SEG self-aligned front structure by selectively epitaxial base region thin film. S220. An EB junction isolation medium is deposited on the upper surface of the first SEG self-aligned front structure and the sidewall of the base region window (i.e., the sidewall of the second window).

5. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 4, characterized in that: The base region thin film is a single-crystal SiGe thin film; and / or the structure of the EB junction isolation medium is SIN / OX / SIN.

6. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 1, characterized in that: In step S400, the temperature of the rapid thermal annealing process is 800–900 °C, and the annealing time is 5–15 s.

7. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in any one of claims 1 to 6, characterized in that: In step S300, the heavily doped single-crystal-polycrystalline mixed film is a heavily doped As-Si mixed film; a heavily doped single-crystal As-Si film is rapidly epitaxially grown on the HBT base region using a Si-based CVD precursor gas source containing Cl, while a heavily doped polycrystalline As-Si film is selectively and slowly deposited on the EB junction isolation medium to form a heavily doped As-Si mixed film.

8. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 7, characterized in that: In step S300, the Si-based CVD precursor gas source containing Cl used in epitaxy includes a Si source precursor gas source and a doping gas. The Si source precursor gas source is a DCS, and the doping gas is a 1% AsH3 mixed with H2 gas. The epitaxy pressure is 100-150 Torr, and the temperature is stable at 630-700 °C.

9. The method for fabricating an HBT device with a selective in-situ heavily doped epitaxial emitter as described in claim 8, characterized in that: In step S300, the Si-based CVD precursor gas source containing Cl used in epitaxy also includes an auxiliary precursor gas source, which is SiH4.

10. A selective in-situ heavily doped epitaxial emitter HBT device, characterized in that: The HBT device is fabricated using the selective in-situ heavily doped epitaxial emitter fabrication method as described in any one of claims 1 to 9.

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