A high-voltage SiC IGBT device with low electromagnetic interference noise and a preparation method thereof

Abstract

This invention relates to the field of silicon carbide insulated gate bipolar transistor (SiC IGBT) technology, and particularly to a low electromagnetic interference noise high-voltage SiC IGBT device and its fabrication method. The SiC IGBT device comprises, from bottom to top: P + Collector region; N-type buffer region; N-type drift region; P-type shielding region; gate; N-type carrier storage layer; P-base region; P ‑ District; P + District; N + This invention proposes a novel SiC IGBT structure with an adaptive hole extraction channel, which, during the transient processes of turn-on and turn-off, is driven by P + Holes injected from the collector can be transmitted through P ‑ The hole extraction channel formed in the region is directly extracted by the emitter, reducing hole accumulation at the bottom of the gate, decreasing gate displacement current, and suppressing electromagnetic interference noise. When the device is in the on state, P ‑ When the region is depleted by the positive voltage applied by the gate, the hole extraction channel is closed, which can increase the carrier concentration on the emitter side and enhance the conductivity modulation effect.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide insulated gate bipolar transistor (SiC IGBT) technology, and particularly to a low electromagnetic interference noise high-voltage SiC IGBT device and its fabrication method. Background Technology

[0002] Silicon carbide insulated gate bipolar transistors (SiC IGBTs), as representatives of bipolar power devices, have advantages such as low on-resistance, fast switching speed and high blocking voltage, and are highly favored in applications such as smart grids, new energy vehicles and rail transit.

[0003] However, as a high-frequency power device, SiC IGBT has a switching speed much higher than that of traditional Si IGBT. The excessively fast turn-on speed causes the voltage and current of the device to change drastically in a short period of time, resulting in large dv / dt and dI / dt during the switching transient. Under the influence of parasitic capacitance and inductance in the circuit, this generates serious electromagnetic interference noise, affecting the normal performance of SiC IGBT.

[0004] To address the EMI noise problem caused by high-frequency switching in SiC IGBTs, the industry has proposed several solutions: First, using filters to block the conduction of noise from the interference source. Second, using simplified packaging structures and optimized electrode wiring to reduce parasitic inductance. Third, controlling the di / dt and dv / dt of the device through circuitry. However, these optimization solutions have significant limitations. These methods of reducing EMI noise through external circuitry not only increase circuit complexity and device losses but also raise manufacturing costs and may affect the system's operating state, making it difficult to fundamentally reduce EMI noise caused by parasitic parameters. In contrast, addressing EMI at the device level is a more direct and efficient approach.

[0005] Therefore, in order to promote the widespread application of SiC IGBTs in the high voltage and high frequency fields, it is of great practical significance to study its device structure and performance optimization. Summary of the Invention

[0006] This invention provides a high-voltage SiC IGBT device with low electromagnetic interference noise and its fabrication method. The purpose is to solve the problem that existing SiC IGBTs have large dv / dt and dI / dt during the switching transient, which causes electromagnetic interference and affects the working performance.

[0007] To achieve the above objectives, the present invention provides a low electromagnetic interference noise high-voltage SiC IGBT device, comprising, from bottom to top: P + Collector region; N-type buffer; set in P +Above the collector region and covering its entire horizontal plane; N-type drift zone; positioned above the N-type buffer zone and covering its entire horizontal plane; P-type shielding zone; positioned above the N-type drift zone, but not completely covering the horizontal plane of the N-type drift zone; The N-type carrier storage layer is partially disposed above the N-type drift region, completely covering the horizontal plane of the N-type drift region that is not covered by the P-type shielding region; the other part is disposed above the P-type shielding region, not completely covering the horizontal plane of the P-type shielding region. Gate; disposed above the P-type shielding region, and horizontally adjacent to the N-type carrier storage layer disposed above the N-type drift region; The P-base region is located above the N-type carrier storage layer above the N-type drift region, and has an L-shaped structure, with its bottom surface completely covering the horizontal plane of the N-type carrier storage layer above the N-type drift region. P - The region is located above the P-type shielding region and horizontally between the N-type carrier storage layer and the gate. P + Area; partly located in P - Above the P-type shielding region and the N-type carrier storage layer, covering the horizontal plane of both; another part is disposed above the P-base region, filling the recessed top surface of its L-shaped structure; the P-type shielding region... + The top surface of the region is flush with the gate. N + The region; is located above the top surface of the L-shaped protrusion in the P-base region; the N + The top surface of the region is flush with the gate.

[0008] Preferably, the gate is made of polysilicon, and a gate oxide layer is deposited on its outer side, the thickness of which is 0.05-0.08 μm; the gate height is 2 ± 0.2 μm.

[0009] Preferably, the N-type buffer has a thickness of 3±1 μm and a doping concentration of 8×10⁻⁶. 16 cm -3 -1×10 17 cm -3 The thickness of the N-type drift region is 100-180 μm, and the doping concentration is 4.5 × 10⁻⁶. 14 cm -3 -5×10 14 cm -3 .

[0010] Preferably, the thickness of the N-type carrier storage layer above the N-type drift region is 0.5-0.9 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 -4×10 16 cm-3 The thickness of the N-type carrier storage layer above the P-type shielding region is 2 ± 0.2 μm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 -4×10 16 cm -3 The thickness of the P-type shielding region is 0.7±0.2μm, and the doping concentration is 5×10⁻⁶. 18 cm -3 -9×10 18 cm -3 The width is consistent with the distance from the adjacent edge of the gate and the N-type carrier storage layer to the other boundary of the SiC IGBT device, and more preferably 3μm; Preferably, the P - The region has a depth of 2±0.2 μm and a width of 0.1-0.3 μm; the doping concentration is 1×10⁻⁶. 16 cm -3 -3×10 16 cm -3 The L-shaped structure of the P-based region has a depth of 0.7-0.9 μm at its higher position and a doping concentration of 1×10⁻⁶. 17 cm -3 -3×10 17 cm -3 The P + The region has a depth of 0.3-0.4 μm, a width of 0.7 μm, and a doping concentration of 2 × 10⁻⁶. 19 cm -3 -4×10 19 cm -3 The N + The region depth is 0.3-0.4 μm, and the doping concentration is 1×10⁻⁶. 19 -2×10 19 cm -3 .

[0011] Preferably, the SiC IGBT device further includes: ILD dielectric layer; disposed on the gate, P + District and N + Above the top surface of the Qiping area; Contact holes; the contact holes are respectively located on the gate and P + District and N + The contact hole is filled with tungsten metal and penetrates the ILD dielectric layer at the corresponding position on the horizontal plane of the area. Emitter, gate, and collector; a passivation layer is disposed between the emitter and the gate.

[0012] Preferably, the thickness of the ILD dielectric layer is 0.6-1 μm, the depth of the contact hole is 0.9-1.1 μm, and the thickness of the tungsten metal is 4 ± 0.4 μm. The emitter and gate have a thickness of 4±0.4μm, and the passivation layer is SiON with a horizontal thickness of 1±0.1μm. The current collector comprises titanium-nickel-silver metal layers with thicknesses of 1±0.1μm, 2±0.2μm, and 10±1μm, respectively.

[0013] Under the same technical concept, the present invention also provides a method for fabricating a high-voltage SiC IGBT device with low electromagnetic interference noise, comprising the following steps: S1, in P + On the collector region substrate, an N-type buffer zone is epitaxially grown by chemical vapor deposition. The process conditions are: temperature 1600-1670℃, pressure 80-120mbar, reaction gases SiH4 and C3H8, carrier gas high-purity H2, and N-type impurity source nitrogen. S2. Epitaxially grow an N-type drift region on an N-type buffer zone; S3. Epitaxially grow an N-type carrier storage layer on the N-type drift region; S4. P-type shielding trenches are etched on the N-type carrier storage layer using ICP under the obstruction of photoresist. The main etching gas is SF6, and the P-type shielding region is formed epitaxially by trench filling technology. S5. Continue to epitaxially grow another part of the N-type carrier storage layer on the P-type shielding region; S6. Etch gate trenches on the N-type carrier storage layer, and grow a 50-80 nm thick gate oxide layer using low-pressure chemical vapor deposition at a temperature of 1000-1050℃ and a pressure of 0.8-1.5 mbar, with TEOS and O2 as the reactant gases and N2 as the carrier gas. Then, deposit a 2-2.5 μm thick polysilicon on the gate oxide as the gate. The polysilicon deposition process conditions are: temperature of 500-600℃, reactant gases of silane and phosphine, and helium as the carrier gas. Finally, planarize the excess polysilicon on the surface using CMP. S7. Three-step aluminum ion implantation to form P under the obstruction of photoresist. - P-base region and P-base region; S8, Three-step aluminum ion implantation to form P + District and N + The zone was annealed at 950℃ for 30 minutes.

[0014] Preferably, the preparation method further includes the following steps after S8: S9, using physical vapor deposition process on the gate, P + District and N + An ILD dielectric layer is grown above the top surface of the area. S10. Etch contact holes on the ILD dielectric layer, sputter tungsten metal to fill the contact holes, and then remove the tungsten metal from the surface by a dry etching process. S11. Sputter a 4μm thick Al metal onto the ILD dielectric layer, then etch the Al metal to form a 4μm deep metal trench under the obstruction of photoresist, then deposit a 1μm thick SiON dielectric on the surface to form a passivation layer to isolate the emitter metal and the gate metal, and anneal at 450°C to form an ohmic contact between the emitter and gate contact metals. S12, titanium-nickel-silver ingots are successively evaporated using a metal evaporator, at P + Titanium-nickel-silver metal with thicknesses of 1 μm, 2 μm, and 10 μm is grown on the back side of the collector region to form the collector.

[0015] Preferably, before depositing the gate using the low-pressure chemical vapor deposition process described in S6, the process further includes the following steps: first, growing a 0.05 μm sacrificial oxygen layer by dry oxygen oxidation at a temperature of 1050°C and removing it by BOE to remove burrs from the sidewalls of the gate trench; then, depositing gate oxide using a dry oxygen process to form a gate oxide layer.

[0016] The above-described solution of the present invention has the following beneficial effects: (1) This invention proposes a novel SiC IGBT structure with an adaptive hole extraction channel, which, during the transient processes of turn-on and turn-off, is driven by P + Holes injected from the collector can be transmitted through P - The hole extraction channel formed in the region is directly extracted by the emitter, reducing hole accumulation at the bottom of the gate, decreasing gate displacement current, and suppressing electromagnetic interference noise. When the device is in the on state, P - When the region is depleted by the positive voltage applied by the gate, the hole extraction channel is closed, which can increase the carrier concentration on the emitter side and enhance the conductivity modulation effect. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the SiC IGBT device of the present invention; Figure 2-10 This is a schematic diagram of the fabrication process of the SiC IGBT device of the present invention; Figure 11 The gate displacement current (I) of the structure proposed in this invention G_dis A schematic diagram comparing the characteristics with those of a traditional high-voltage SiC IGBT structure. Compared to the traditional structure, the gate displacement current of the structure proposed in this invention is significantly and effectively suppressed.

[0018] Among them, 1, P +1. Collector region; 2. N-type buffer zone; 3. N-type drift region; 4. P-type shielding region; 5. N-type carrier storage layer; 6. Gate; 7. P-type base region; 8. P-type base region. - District; 9, P + District; 10, N + 11. ILD dielectric layer; 12. Contact hole. Detailed Implementation

[0019] To make the technical problems, solutions, and advantages of this invention clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] Example 1 A high-voltage SiC IGBT device with low electromagnetic interference noise is shown in the schematic diagram below. Figure 1 As shown; from bottom to top including: P + Collector region 1; thickness 2-4 μm, doping concentration 8 × 10⁻⁶ 16 cm -3 -1×10 17 cm -3 ; N-type buffer 2; set in P + Above and covering the entire horizontal plane of collector region 1; thickness 3±1μm, doping concentration 8×10⁻⁶. 16 cm -3 -1×10 17 cm -3 N-type drift region 3; positioned above N-type buffer zone 2 and covering its entire horizontal plane; thickness 100-180 μm, doping concentration 4.5 × 10⁻⁶. 14 cm -3 ; The N-type carrier storage layer 5 above the N-type drift region 3 has a thickness of 0.7 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 The N-type carrier storage layer 5 above the P-type shielding region 4 has a thickness of 2 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 ; P-type shielding region 4; positioned above N-type drift region 3, but not completely covering the horizontal plane of N-type drift region 3; P-type shielding region 4 has a thickness of 0.7 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 Width is 3µm; Gate 6 is located above the P-type shielding region 4 and is horizontally adjacent to the N-type carrier storage layer 5. Gate 6 is made of polysilicon and is covered with a gate oxide layer with a thickness of 0.05 μm. Gate 6 has a height of 2 μm.

[0024] The N-type carrier storage layer 5 is partially disposed above the N-type drift region 3, completely covering the horizontal surface of the N-type drift region 3 that is not covered by the P-type shielding region 4; the other part is disposed above the P-type shielding region 4, not completely covering the horizontal surface of the P-type shielding region 4. P-base region 7; located above the N-type carrier storage layer 5 above the N-type drift region 3, in an L-shaped structure, with its bottom surface completely covering the horizontal plane of the N-type carrier storage layer 5 above the N-type drift region 3; the higher part of the L-shaped structure of P-base region 7 has a depth of 0.8 μm and a doping concentration of 2 × 10⁻⁶. 17 cm -3 ; P - Region 8; positioned above the P-type shielding region 4, horizontally located between the N-type carrier storage layer 5 and the gate 6; P - Region 8 has a depth of 2 μm and a width of 0.1–0.3 μm; the doping concentration is 2 × 10⁻⁶. 16 cm -3 The height is consistent with gate 6 P + Section 9; some areas are located in P -Above region 8 and the N-type carrier storage layer 5 above the P-type shielding region 4, covering their horizontal plane; another part is disposed above the P-base region 7, filling the recessed top surface of its L-shaped structure; the P + The top surface of region / is flush with gate 6; P + Region 9 has a depth of 0.3 μm and a doping concentration of 4 × 10⁻⁶. 19 cm -3 ; N + Zone 10; located above the top surface of the L-shaped protrusion in P-base zone 7; N + The top surface of region 10 is flush with gate 6, N + Region 10 has a depth of 0.4 μm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 .

[0025] ILD dielectric layer 11; disposed at gate 6, P + Zones 9 and N + Above the top surface of section 10, level with the surrounding surface; Contact hole 12; Contact holes 12 are located at gate 6 and P respectively. + Zones 9 and N + The corresponding position of the horizontal plane of zone 10 penetrates the ILD dielectric layer 11, and the contact hole 12 is filled with tungsten metal. Emitter, gate, and collector; a passivation layer is disposed between the emitter and the gate.

[0026] This invention relates to the fabrication of the SiC IGBT device. Among them, 1, P + 1. Collector region; 2. N-type buffer zone; 3. N-type drift region; 4. P-type shielding region; 5. N-type carrier storage layer; 6. Gate; 7. P-type base region; 8. P-type base region. - District; 9, P + District; 10, N + 11. ILD dielectric layer; 12. Contact hole.

[0027] A method for fabricating a high-voltage SiC IGBT device structure with low electromagnetic interference noise is illustrated in the schematic diagram below. Figure 2-10 Specifically, it includes the following steps: 1. An N-type buffer layer with a thickness of 2-4 μm and a doping concentration of 8 × 10⁻⁶ is epitaxially grown on a P+ substrate. 16 cm -3 -1×10 17 cm -3 .

[0028] 2: An N-type drift region is epitaxially grown on the N-type buffer layer, with a thickness of 100-180 μm and a doping concentration of 4.5 × 10⁻⁶. 14 cm-3 .

[0029] 3: Continue epitaxial growth of an N-type carrier storage layer on the N-drift region, with a thickness of 0.7 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 .

[0030] 4: A 0.7 μm deep P-shield trench was etched on the N-type carrier storage layer, and a doping concentration of 5 × 10⁻⁶ was formed epitaxially using trench filling technology. 18 cm -3 The P-shield region has a width of 3µm.

[0031] 5: Continue epitaxial growth of an N-type carrier storage layer with a thickness of 2 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 .

[0032] 6. Gate trenches with depths and widths of 2 μm and 1.4 μm, respectively, were etched on the N-type carrier storage layer. Then, a 0.05 μm sacrificial oxide layer was grown by dry oxidation at 1050 °C and removed by BOE to remove burrs from the trench sidewalls. Next, a 0.05 μm gate oxide layer was deposited using a dry oxidation process. Finally, an 8 μm layer of polysilicon was deposited on the gate oxide layer using low-pressure chemical vapor deposition, and excess polysilicon was planarized using CMP.

[0033] 7: Under the obstruction of photoresist, three-step aluminum ion implantation resulted in a depth and concentration of 2 μm and 2 × 10⁻⁶, respectively. 16 cm -3 P - The region was then subjected to three steps of aluminum ion implantation to form a depth and concentration of 0.8 μm and 2 × 10⁻⁶ m, respectively. 17 cm -3 The P-well region.

[0034] 8: The three-step aluminum ion implantation resulted in a depth and concentration of 0.3 μm and 4 × 10⁻⁶, respectively. 19 cm -3 P + The active region is then implanted with nitrogen ions in three steps to form a depth and concentration of 0.4 μm and 2 × 10⁻⁶ m, respectively. 19 cm -3 N + The active region is then annealed at 950℃ for 30 minutes to activate the injected ions and repair lattice damage.

[0035] 9: A 0.8 μm ILD dielectric layer was grown using physical vapor deposition.

[0036] 10: Etch a 1.2μm deep contact hole on the ILD dielectric layer, then sputter a 4μm thick tungsten metal to fill the contact hole, and then remove the tungsten metal from the surface by a dry etching process.

[0037] 11: A 4μm thick Al metal layer is sputtered on the front side, and then the Al metal is etched to form a 4μm deep metal trench under the constraint of photoresist. A 10μm thick SiON dielectric layer is then deposited on the surface to isolate the emitter metal and the gate metal. Annealing is performed at 450°C to form an ohmic contact between the emitter and gate contact metals. Finally, titanium-nickel-silver ingots are successively evaporated using a metal evaporation machine to grow titanium-nickel-silver metal layers with thicknesses of 1μm, 2μm, and 10μm on the back side of the wafer to form the collector metal.

[0038] Figure 11 The gate displacement current (I) of the structure proposed in this invention G_dis A schematic diagram comparing the characteristics of the proposed structure with those of a traditional high-voltage SiC IGBT. Compared to the traditional structure, the gate displacement current of the proposed structure is significantly and effectively suppressed. (The SiC IGBT capacitance characteristics were tested according to GB / T 29332-2012, with the gate and emitter shorted, and a DC bias of 0 V to the rated voltage applied to the collector. A 1 MHz small-signal AC test was used to measure the reverse transfer capacitance Crss.) g_dis = Crss dV CE / The gate displacement current is obtained by dt.

Claims

1. A high-voltage SiC IGBT device with low electromagnetic interference noise, characterized in that, From bottom to top, including: P + Collector region (1); N-type buffer (2); set in P + Above the collector region (1) and covering its entire horizontal plane; N-type drift zone (3); set above N-type buffer zone (2) and covering its entire horizontal plane; P-type shielding area (4); set above N-type drift area (3), not completely covering the horizontal plane of N-type drift area (3); The N-type carrier storage layer (5) is partially disposed above the N-type drift region (3), completely covering the horizontal surface of the N-type drift region (3) that is not covered by the P-type shielding region (4); the other part is disposed above the P-type shielding region (4), not completely covering the horizontal surface of the P-type shielding region (4). Gate (6); disposed above the P-type shielding region (4), and horizontally adjacent to the N-type carrier storage layer (5) disposed above the N-type drift region (3); P-base region (7); set above the N-type carrier storage layer (5) above the N-type drift region (3), in an L-shaped structure, with the bottom surface completely covering the horizontal surface of the N-type carrier storage layer (5) above the N-type drift region (3); P - Region (8); located above the P-type shielding region (4), horizontally between the N-type carrier storage layer (5) and the gate (6); P + Zone (9); some areas are located in P - Above the N-type carrier storage layer (5) above the P-type shielding region (8) and the P-type shielding region (4), covering the horizontal plane of both; another part is set above the P-base region (7), filling the recessed top surface of its L-shaped structure; the P + The top surface of region (9) is flush with the gate (6); N + Region (10); disposed above the upper top surface of the L-shaped protrusion of the P-base region (7); the N + The top surface of region (10) is flush with the gate (6).

2. The SiC IGBT device as described in claim 1, characterized in that, The gate (6) is made of polysilicon and is coated with a gate oxide layer on its outer side. The thickness of the gate oxide layer is 0.05-0.08μm. The height of the gate (6) is 2±0.2μm.

3. The SiC IGBT device as described in claim 1, characterized in that, The N-type buffer (2) has a thickness of 3±1μm and a doping concentration of 8×10⁻⁶. 16 cm -3 -1×10 17 cm -3 The N-type drift region (3) has a thickness of 100-180 μm and a doping concentration of 4.5 × 10⁻⁶ μm. 14 cm -3 -5×10 14 cm -3 .

4. The SiC IGBT device as described in claim 1, characterized in that, The thickness of the N-type carrier storage layer (5) above the N-type drift region (3) is 0.7 ± 0.2 μm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 -4×10 16 cm -3 The thickness of the N-type carrier storage layer (5) above the P-type shielding region (4) is 2 ± 0.2 μm, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 -4×10 16 cm -3 The thickness of the P-type shielding region (4) is 0.7±0.2μm, and the doping concentration is 5×10⁻⁶. 18 cm -3 -9×10 18 cm -3 The width is consistent with the distance from the adjacent side of the gate (6) and the N-type carrier storage layer (5) to the other side boundary of the SiC IGBT device.

5. The SiC IGBT device as described in claim 1, characterized in that, The P - Region (8) has a depth of 2±0.2μm and a width of 0.1-0.3μm; the doping concentration is 1×10⁻⁶. 16 cm -3 -3×10 16 cm -3 The L-shaped structure of the P-base region (7) has a depth of 0.7-0.9 μm at its higher position and a doping concentration of 1×10⁻⁶. 17 cm -3 -3×10 17 cm -3 The P + Region (9) has a depth of 0.3-0.4 μm, a width of 0.7 μm, and a doping concentration of 2 × 10⁻⁶. 19 cm -3 -4×10 19 cm -3 The N + Region (10) has a depth of 0.3 μm-0.4 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 -2×10 19 cm -3 .

6. The SiC IGBT device as described in claim 1, characterized in that, The SiC IGBT device also includes: ILD dielectric layer (11); disposed at gate (6), P + Zone (9) and N + Above the flush top surface of area (10); Contact holes (12); the contact holes (12) are respectively located at the gate (6) and P + Zone (9) and N + The ILD dielectric layer (11) is penetrated at the corresponding position of the horizontal surface of the area (10), and the contact hole (12) is filled with tungsten metal; Emitter, gate, and collector; a passivation layer is disposed between the emitter and the gate.

7. The SiC IGBT device as described in claim 6, characterized in that, The thickness of the ILD dielectric layer (11) is 0.6-1 μm, the depth of the contact hole (12) is 0.9-1.1 μm, and the thickness of the tungsten metal is 4 ± 0.4 μm. The emitter and gate have a thickness of 4±0.4μm, and the passivation layer is SiON with a thickness of 1±0.1μm; The current collector comprises titanium-nickel-silver metal layers with thicknesses of 1±0.1μm, 2±0.2μm, and 10±1μm, respectively.

8. A method for fabricating a low electromagnetic interference noise high-voltage SiC IGBT device, characterized in that, Includes the following steps: S1, in P + On the substrate of collector region (1), an N-type buffer zone (2) is epitaxially grown by chemical vapor deposition; the process conditions are: temperature is 1600-1670℃, pressure is 80-120mbar, reaction gas is SiH4 and C3H8, carrier gas is high-purity H2, and N-type impurity source is nitrogen. S2. An N-type drift region (3) is epitaxially grown on the N-type buffer zone (2); S3. An N-type carrier storage layer (5) is epitaxially grown on the N-type drift region (3); S4. P-type shielding trenches are etched on the N-type carrier storage layer (5) under the obstruction of photoresist using ICP. The main etching gas is SF6, and the P-type shielding region (4) is formed by epitaxial growth through trench filling technology. S5. Continue to epitaxially grow another part of the N-type carrier storage layer (5) on the P-type shielding region (4); S6. Etch gate trenches on the N-type carrier storage layer (5), and grow a 50-80 nm thick gate oxide layer by low-pressure chemical vapor deposition at a temperature of 1000-1050℃, a pressure of 0.8-1.5 mbar, a reaction gas of TEOS and O2, and a carrier gas of N2. Then deposit a 2-2.5 μm thick polysilicon on the gate oxide as the gate (6). The process conditions for depositing polysilicon are: temperature of 500-600℃, reaction gas of silane and phosphine, carrier gas of helium, and then use CMP to planarize the excess polysilicon on the surface. S7. Under the obstruction of photoresist, three-step aluminum ion implantation forms a concentration of 1×10⁻⁶. 16 cm -3 -3×10 16 cm -3 P - Zone (8) and 1×10 17 cm -3 -3×10 17 cm -3 P-base region (7); S8, the three-step aluminum ion implantation formation concentration is 2×10 19 cm -3 -4×10 19 cm -3 P + Zone (9) and 1×10 19 cm -3 -2×10 19 cm -3 N + Zone (10) was annealed at 950℃ for 30 minutes.

9. The preparation method according to claim 8, characterized in that, The preparation method further includes the following steps after S8: S9, using physical vapor deposition process on the gate (6), P + Zone (9) and N + An ILD dielectric layer (11) is grown above the flush top surface of region (10). S10. Etch contact holes (12) on the ILD dielectric layer (11), sputter tungsten metal to fill contact holes (12), and then remove the tungsten metal on the surface by dry etching process; S11. Sputter Al metal with a thickness of 4±0.4μm on the ILD dielectric layer (11), then etch the Al metal to form a metal trench with a depth of 4±0.4μm under the block of photoresist, then deposit SiON dielectric with a thickness of 1±0.1μm on the surface to form a passivation layer, which isolates the emitter metal and the gate metal, and anneal at a temperature of 450°C to form an ohmic contact between the emitter and the gate contact metal; S12, titanium-nickel-silver ingots are successively evaporated using a metal evaporator, at P + Titanium-nickel-silver metal with thicknesses of 1±0.1μm, 2±0.2μm and 10±1μm is grown on the back side of the collector region (1) to form a collector.

10. The preparation method according to claim 8, characterized in that, Before depositing the gate (6) via the low-pressure chemical vapor deposition process described in S6, The process includes the following steps: at a temperature of 1000-1050℃, a 0.05-0.08μm sacrificial oxygen layer is first grown by dry oxygen oxidation and removed by BOE to remove burrs on the sidewall of the gate trench; then, a dry oxygen process is used to deposit gate oxide to form a gate oxide layer.

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