A preparation method for improving withstand voltage performance of an LDMOS device and the LDMOS device

Abstract

The application discloses a preparation method for improving the withstand voltage performance of an LDMOS device and the LDMOS device, which comprises the following steps performed on a semiconductor substrate in sequence: silicon nitride deposition after a shallow trench isolation and field implantation process, high-voltage gate photoetching and / or etching, high-voltage gate gate oxide layer deposition, silicon nitride removal, sacrifice oxide layer deposition, well implantation, gate oxide layer deposition and polysilicon deposition. The application improves the better withstand voltage performance by increasing the thickness of the step oxide and adjusting the process sequence and parameters of the deposited sacrifice oxide layer, reduces the occurrence of wafer misalignment, meets the withstand voltage demand of customers for products, provides better product performance, and the improvements fully meet the strict requirements for the withstand voltage performance of products, meanwhile, the application provides products with more excellent performance and more stable quality, and enhances the competitiveness of the products in the market.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing an LDMOS device with improved breakdown voltage performance and an LDMOS device. Specifically, it can be applied to logic elements, mixed-signal elements, embedded memory, BCD (Bipolar-CMOS-DMOS), trench MOSFETs, and high-voltage components (such as PMICs) and related products and processes. Background Technology

[0002] Currently, the BCD (Bipolar-Complementary Metal-Oxide-Diffused Metal-Oxide-Semiconductor) process employs a stepped oxide structure (high-voltage gate process) to improve the breakdown voltage of lateral double-diffused metal-oxide-semiconductor (LDMOS). This process uses silicon nitride (SIN) as a hard mask layer; however, silicon nitride has significant stress. If this stress is not released through subsequent heat treatment, it can lead to misalignment in the device.

[0003] When customers use array devices to achieve high-voltage withstand capabilities, this misalignment will become a weak point, directly affecting the device's voltage withstand capability.

[0004] To address these issues, existing technologies need to be improved to minimize product costs, enhance product competitiveness, and better meet user needs. Summary of the Invention

[0005] The main objective of this invention is to provide a method for preparing LDMOS devices with improved breakdown voltage performance and an LDMOS device in general. By increasing the thickness of the stepped oxide layer and adjusting the process sequence and parameters for depositing the sacrificial oxide layer, better breakdown voltage performance is achieved, while reducing the occurrence of wafer misalignment. This meets customer requirements for product breakdown voltage and provides better product performance. These improvements fully meet the stringent requirements for product breakdown voltage performance and provide products with superior performance and more stable quality, thereby enhancing the product's competitiveness in the market.

[0006] According to one aspect of the present invention, a method for fabricating an improved LDMOS device with high voltage withstand capability is provided, comprising the following steps performed sequentially on a semiconductor substrate: silicon nitride deposition after shallow trench isolation and field implantation processes, high voltage gate lithography and / or etching, high voltage gate oxide deposition, silicon nitride removal, sacrificial oxide deposition, well implantation, gate oxide deposition, and polysilicon deposition.

[0007] According to one embodiment of the present invention, the deposition thickness of the high-voltage gate oxide layer is 900~1000 Å.

[0008] According to one embodiment of the present invention, the deposition thickness of the sacrificial oxide layer is 100~120 Å.

[0009] According to one embodiment of the present invention, the sacrificial oxide layer is deposited under high temperature conditions.

[0010] According to one embodiment of the present invention, the reaction temperature for sacrificial oxide layer deposition is >1000°C.

[0011] According to one embodiment of the present invention, the reaction temperature for sacrificial oxide layer deposition is >1100°C.

[0012] According to one embodiment of the present invention, the sacrificial oxide layer deposition includes deposition in a furnace tube, followed by the introduction of oxygen to generate silicon dioxide.

[0013] According to one embodiment of the present invention, the fabrication method further includes depositing a stress buffer layer between the high-voltage gate oxide layer and the semiconductor substrate.

[0014] According to one embodiment of the present invention, the deposition includes adding rare earth elements to perform the deposition.

[0015] According to another aspect of the present invention, an LDMOS device is provided, which is fabricated using any of the methods mentioned in the above technical solutions.

[0016] In a deep trench isolation structure and its manufacturing method according to an embodiment of the present invention, by increasing the thickness of the stepped oxide and adjusting the process sequence and parameters for depositing the sacrificial oxide layer, better withstand voltage performance is achieved, while reducing the occurrence of wafer misalignment, thus meeting customer requirements for product withstand voltage and providing better product performance. Through the above process optimization, not only is the product's withstand voltage performance improved, enabling reliable operation in complex electrical environments, but the occurrence of wafer misalignment is also reduced, ensuring high-quality product manufacturing. This series of improvements fully meets the stringent requirements for product withstand voltage performance, while providing products with superior performance and more stable quality, enhancing the product's competitiveness in the market.

[0017] This invention is specifically applicable to logic elements, mixed-signal elements, embedded memory, BCD (Bipolar-CMOS-DMOS), trench MOSFETs, and high-voltage components (such as PMICs) and related products and processes. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some implementation examples of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A process flow diagram of a method for fabricating an improved LDMOS device with voltage withstand capability according to an exemplary embodiment of the present invention is shown; Figure 2 A process flow diagram of the fabrication method of LDMOS devices in the prior art is shown. Detailed Implementation

[0020] The following detailed description of the embodiments is intended to exemplify the principles of the present invention, but should not be construed as limiting the scope of the invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0021] These embodiments are provided to make this disclosure thorough and complete, and to fully express the scope of the invention to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​set forth in these embodiments should be interpreted as merely exemplary and not as limiting.

[0022] It should be noted that, in the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] It should also be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention depending on the specific circumstances. When a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device.

[0024] All terms used in this invention have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0026] like Figure 1 As shown, the present invention provides a method for improving the breakdown voltage performance of LDMOS devices, which includes the following steps performed sequentially on a semiconductor substrate: silicon nitride deposition after shallow trench isolation and field implantation processes, high voltage gate lithography and / or etching, high voltage gate oxide deposition, silicon nitride removal, sacrificial oxide deposition, well implantation, gate oxide deposition, and polysilicon deposition.

[0027] In the fabrication method for improving the withstand voltage performance of LDMOS devices according to embodiments of the present invention, a significant improvement in the withstand voltage performance of the product was successfully achieved by increasing the thickness of the stepped oxide and adjusting the process sequence and key parameters for depositing the sacrificial oxide layer. This improvement not only greatly enhances the stability and reliability of the device under high-voltage environments but also effectively reduces the occurrence rate of wafer misalignment during the manufacturing process, thereby ensuring the consistency and high quality of the final product. These optimization measures closely align with customers' stringent requirements for product withstand voltage performance, not only meeting their urgent needs in high-voltage applications but also further improving the overall performance of the product, bringing customers a superior user experience and higher satisfaction. In summary, these technological advancements not only solidify our leading position in the industry but also provide strong support for the diversified needs of the market.

[0028] In some specific embodiments, the deposition thickness of the high-voltage gate oxide layer is 900~1000 Å, preferably 970 Å.

[0029] This thickness of gate oxide layer can effectively regulate the electric field distribution in the high-voltage gate region. Under high-voltage operating conditions, an excessively thin oxide layer may lead to excessively high electric field strength, causing problems such as breakdown; while when the thickness is between 900 and 1000 Å, the electric field can be uniformly distributed, avoiding the electric field concentration in local areas, reducing the risk of electric field breakdown, ensuring stable operation of the device under high voltage, and improving the electrical reliability of the device.

[0030] Based on the above embodiments, the deposition thickness of the sacrificial oxide layer is 100~120 Å, preferably 110 Å.

[0031] In subsequent semiconductor manufacturing processes, such as ion implantation, the silicon wafer surface is susceptible to damage from high-energy particle impacts. A 110 Å thick sacrificial oxide layer can act as a buffer layer, effectively absorbing and dispersing this energy, reducing damage to the silicon substrate, ensuring the integrity of the internal crystal structure of the silicon wafer, and thus guaranteeing the performance and reliability of semiconductor devices.

[0032] During photolithography, etching, and other processes, impurities from the external environment may be adsorbed onto the silicon wafer surface. A sacrificial oxide layer of appropriate thickness can act as an isolation layer, preventing impurities from diffusing into the silicon wafer and avoiding adverse effects on the electrical properties of the semiconductor, such as preventing leakage current caused by impurities, thereby improving the yield and stability of the device.

[0033] A sacrificial oxide layer of suitable thickness can form a good transition between silicon and other subsequently grown materials (such as silicon nitride), enhancing the bonding force between interfaces. This helps improve the stability of multilayer structures, prevents problems such as interface delamination during subsequent processes or device use, and improves device reliability and lifespan.

[0034] In some specific embodiments, the sacrificial oxide layer is deposited under high-temperature conditions. High temperatures facilitate a more complete oxidation reaction, resulting in a denser sacrificial oxide layer. Atoms at high temperatures exhibit greater activity, enabling more thorough diffusion and bonding, thereby reducing porosity and defects in the oxide layer and forming a more compact structure. This provides better protection against impurity diffusion and the intrusion of external substances, enhancing the protective performance of the underlying material.

[0035] During high-temperature deposition, the crystal structure of the oxide layer can be better adjusted and optimized. Atoms have sufficient energy to rearrange themselves, forming a more stable and regular crystal structure, which helps to improve the mechanical properties and chemical stability of the oxide layer, enabling it to better withstand various stresses and chemical reactions in subsequent processes.

[0036] Based on the above embodiments, the reaction temperature for sacrificial oxide layer deposition is >1000℃. At temperatures above 1000℃, the atoms on the substrate material surface are extremely active, enabling the formation of stronger chemical bonds between them and the deposited oxide layer atoms. Taking a metal substrate as an example, the metal-oxygen bonds formed between metal atoms and oxygen atoms are even stronger, significantly enhancing the bonding force between the oxide layer and the substrate. During subsequent machining or use, the oxide layer is less likely to detach or peel off, ensuring the integrity and stability of the material surface.

[0037] In some specific embodiments, the reaction temperature for sacrificial oxide layer deposition is >1100°C. Oxide layers formed at temperatures above 1100°C have a more compact and ordered atomic arrangement and a more stable crystal structure. This gives the oxide layer a stronger ability to block the diffusion of various impurities and ions, and in subsequent processing, it can more effectively prevent the penetration and diffusion of impurities, protecting the performance of the substrate material from being affected.

[0038] Based on the above embodiments, the sacrificial oxide layer deposition includes deposition in a furnace tube, where oxygen is introduced to generate silicon dioxide. The silicon dioxide sacrificial oxide layer deposited in the furnace tube can fill the tiny pits and defects on the substrate surface, making the surface smoother. Taking silicon wafers as an example, the roughness of the originally rough silicon wafer surface can be significantly reduced after growing the silicon dioxide sacrificial oxide layer, from tens of nanometers to a few nanometers or even lower. This provides more ideal surface conditions for subsequent processes such as photolithography, which is beneficial for improving the resolution of photolithography and the accuracy of pattern transfer.

[0039] In some specific embodiments, the fabrication method further includes depositing a stress buffer layer between the high-voltage gate oxide layer and the semiconductor substrate. The stress buffer layer can adjust the stress state of the semiconductor substrate, altering its band structure. For some semiconductor materials, such as silicon, a suitable stress state can reduce the effective mass of charge carriers, thereby increasing the mobility of charge carriers in the semiconductor. Taking n-type silicon as an example, the tensile stress introduced by the stress buffer layer can increase the mobility of electrons in the conduction band, thereby increasing the device's on-state current and switching speed, and improving the overall performance of the device.

[0040] Based on the above embodiments, the deposition process includes the addition of rare earth elements. The addition of rare earth elements improves the surface hardness and toughness of the material, thereby enhancing its wear resistance. Taking steel as an example, the addition of lanthanum (La) forms a layer of rare earth compound with high hardness and good wear resistance on the material surface, significantly reducing the wear rate and improving the material's service life under frictional conditions.

[0041] The present invention also proposes an LDMOS device, which is fabricated using any of the above technical solutions.

[0042] like Figure 2 As shown, in the prior art, the BCD (Bipolar-Complementary Metal-Oxide-Dual-Diffused Metal-Oxide-Semiconductor) process uses a stepped oxide structure (high-voltage gate process) to improve the breakdown voltage of lateral dual-diffused metal-oxide-semiconductor (LDMOS). This process uses silicon nitride (SIN) as a hard mask layer; however, silicon nitride has significant stress. If this stress is not released through subsequent heat treatment, it can lead to misalignment in the device.

[0043] In this application, in the field of semiconductor manufacturing, by increasing the thickness of the stepped oxide and finely adjusting the process sequence and parameters for depositing the sacrificial oxide layer, significant beneficial effects can be achieved for the product.

[0044] Firstly, in terms of withstand voltage performance, increasing the thickness of the stepped oxide layer allows it to withstand higher voltage surges, effectively dispersing the electric field intensity and preventing excessive concentration of the electric field in localized areas that could lead to insulation breakdown. Simultaneously, precisely adjusting the process sequence and parameters for depositing the sacrificial oxide layer results in a tighter and more stable bond between the sacrificial oxide layer and the stepped oxide layer, as well as other material layers, further enhancing the overall insulation performance. This synergistic effect gives the product superior withstand voltage capability, enabling stable operation in higher voltage environments and significantly improving its withstand voltage performance to meet the demands of modern electronic equipment for high-voltage operating environments.

[0045] Secondly, the optimized process played a crucial role in reducing wafer misalignment. Properly adjusting the deposition sequence of the sacrificial oxide layer allows for better control of stress distribution in each layer during deposition, reducing wafer deformation and misalignment caused by uneven stress. Precise parameter settings, such as deposition temperature and gas flow rate, ensure uniform material deposition on the wafer surface, avoiding wafer position shifts due to localized deposition rate differences. These measures effectively reduced the probability of wafer misalignment, improving the precision and consistency of wafer manufacturing.

[0046] The above are exemplary embodiments disclosed in this invention. The order of the disclosed embodiments is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. However, it should be noted that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the disclosed embodiments of this invention (including the claims) is limited to these examples. Various changes and modifications can be made without departing from the scope defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular.

[0047] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of the different aspects of the invention as described above exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for preparing an LDMOS device with improved breakdown voltage performance, characterized in that, The process includes the following steps performed sequentially on a semiconductor substrate: silicon nitride deposition after shallow trench isolation and field implantation, high-voltage gate lithography and / or etching, high-voltage gate oxide deposition, silicon nitride removal, sacrificial oxide deposition, trap implantation, gate oxide deposition, and polysilicon deposition.

2. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The deposition thickness of the high-voltage gate oxide layer is 900~1000 Å.

3. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The thickness of the sacrificial oxide layer is 100~120 Å.

4. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The sacrificial oxide layer is deposited under high temperature conditions.

5. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The reaction temperature for the deposition of the sacrificial oxide layer is >1000℃.

6. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The reaction temperature for the deposition of the sacrificial oxide layer is >1100℃.

7. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The sacrificial oxide layer deposition involves deposition in a furnace tube, followed by the introduction of oxygen to generate silicon dioxide.

8. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The fabrication method also includes depositing a stress buffer layer between the high-voltage gate oxide layer and the semiconductor substrate.

9. The method for preparing an improved LDMOS device according to claim 1, characterized in that, The deposition process involves adding rare earth elements.

10. An LDMOS device, characterized in that, It is prepared by any one of the methods described in claims 1-9.

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