Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure including a first stack structure and a second stack structure. The first stack structure includes first metal gate structures and first channel layers arranged alternately with the first metal gate structures. The second stack structure is separated from the first stack structure and includes second metal gate structures and second channel layers arranged alternately with the second metal gate structures. The first stack structure has a first number of the first channel layers. The second stack structure has a second number of the second channel layers. The first number is different from the second number. Embodiments of the present disclosure also relate to a semiconductor structure and a method of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other forms of electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation region above the first surface, wherein the isolation region includes an insulating material having a dielectric constant between 3 and 5; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a plurality of first sheets and the second stacked structure includes a plurality of second sheets; forming a first gate structure and a second gate structure above the first stacked structure and the second stacked structure, wherein the first gate structure and the second gate structure respectively enclose the plurality of first sheets and the plurality of second sheets; forming a first epitaxial structure and a second epitaxial structure in a recess of the substrate on an opposite side of the second stacked structure; forming an etch stop layer above the respective first epitaxial structure and the second epitaxial structure; forming a dielectric layer above the respective etch stop layer; forming a first opening by recessing the substrate from the second surface; and filling the first opening with a first dielectric material.

[0005] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation structure above the first surface; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a first sacrificial layer and a first channel layer alternately arranged with the first sacrificial layer, and the second stacked structure includes a second sacrificial layer and a second channel layer alternately arranged with the second sacrificial layer; forming a first epitaxial structure and a second epitaxial structure in a recess of the substrate on opposite sides of the first stacked structure, wherein the first epitaxial structure is located between the first stacked structure and the second stacked structure, and portions of the first epitaxial structure and the second epitaxial structure are suspended above the isolation structure; forming a first source / drain epitaxial structure above the first epitaxial structure, and A second source / drain epitaxial structure is formed above the second epitaxial structure; the upper portions of the first source / drain epitaxial structure and the second source / drain epitaxial structure are converted into metal silicides; source / drain contacts electrically coupled to the first source / drain epitaxial structure and the second source / drain epitaxial structure are formed on the corresponding metal silicides; the first sacrificial layer and the second sacrificial layer are replaced with a first dielectric layer and a conductive layer; a first opening is formed by etching the conductive layer closest to the second surface of the substrate and the first stack structure from the second surface, wherein the first opening is located between the first epitaxial structure and the second epitaxial structure; a second opening is formed through the first opening by etching through the bottommost channel layer in the first channel layer, wherein the second opening is connected to the first opening; and the first opening and the second opening are filled with a first dielectric material.

[0006] Some embodiments of this application provide a semiconductor structure, including: a first stacked structure including a first metal gate structure and a first channel layer alternately arranged with the first metal gate structure; a second stacked structure separated from the first stacked structure and including a second metal gate structure and a second channel layer alternately arranged with the second metal gate; a drain epitaxial structure and a source epitaxial structure disposed on opposite sides of the first stacked structure, wherein the drain epitaxial structure is located between the first stacked structure and the second stacked structure, and the source epitaxial structure is located on the side of the second stacked structure opposite to the drain epitaxial structure; a first contact etch stop layer and a second contact etch stop layer. The first contact etch stop layer is disposed above the drain epitaxial structure, and the second contact etch stop layer is disposed above the source epitaxial structure; a first dielectric layer and a second dielectric layer are disposed above the first contact etch stop layer and the second dielectric layer is disposed above the second contact etch stop layer; a drain contact extends through the first dielectric layer and is electrically coupled to the drain epitaxial structure; a source contact extends through the second dielectric layer and is electrically coupled to the source epitaxial structure, wherein the first stack structure has a first number of first channel layers, the second stack structure has a second number of second channel layers, and the first number is different from the second number. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6B , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12 to 14 , Figures 15A to 15D and Figures 16A to 16D According to some embodiments of this disclosure Figure 1 A schematic cross-sectional diagram illustrating the sequential operations of the methods in the diagram.

[0010] Figure 5C , Figure 6A and Figure 7A According to some embodiments of this disclosure Figure 1 A schematic 3D diagram illustrating some operations of the methods described.

[0011] Figure 17 This illustrates some embodiments of the present disclosure for continued use. Figure 1 The flowchart of the method in [the document / section].

[0012] Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figures 22B to 22D , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A , Figure 31B and Figures 32A to 32C According to some embodiments of this disclosure Figure 17 A schematic cross-sectional diagram illustrating the sequential operations of the methods in the diagram.

[0013] Figure 33 This is a use of some embodiments according to the present disclosure. Figure 1 The methods and Figure 17 A schematic 3D diagram of a semiconductor structure formed by the method described in the diagram.

[0014] Figure 34A and Figure 34B It includes some embodiments according to this disclosure. Figure 33 A simplified circuit diagram of one or more semiconductor devices in a semiconductor structure.

[0015] Figures 35A to 35C It includes some embodiments according to this disclosure. Figure 34A Semiconductor devices or Figure 34BA schematic diagram of a semiconductor device chip or semiconductor structure.

[0016] Figure 36 This illustrates that parasitic capacitances according to some embodiments of the present disclosure can be similar to... Figure 16C The diagram illustrates the possible locations within a uniform sheet / nanosheet semiconductor structure. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. In some embodiments, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In some embodiments, the spatial relative terms are intended to cover orientations of the device that differ from those depicted in the figures during use or operation. The device may be oriented in other ways (rotated 100 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0019] While the numerical ranges and parameters illustrating the broad scope of embodiments of this disclosure are approximate, the numerical values ​​described in specific embodiments are reported as precisely as possible. However, any numerical value inherently includes some error that is necessarily caused by normal deviations found in the corresponding test measurements. Furthermore, as used herein, the terms “substantially,” “about,” and “approximately” generally mean values ​​or ranges that would be expected by one of ordinary skill in the art. Alternatively, the terms “substantially,” “about,” and “approximately” mean within an acceptable standard error of the average as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working instances, or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein, such as the amount of material used for them, duration, temperature, operating conditions, ratios of quantities, etc., should be understood to be modified by the terms “substantially,” “about,” or “approximately” in all instances. Therefore, unless indicated to the contrary, the numerical parameters set forth in embodiments of this disclosure and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted at least in light of the number of significant figures reported and by applying common rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise stated.

[0020] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0021] This disclosure relates to semiconductor structures (or integrated circuit structures) and methods of forming them. More specifically, some embodiments of this disclosure relate to semiconductor structures including asymmetric GAA stack structures, which include a varying number of wafers for reducing parasitic capacitance. Furthermore, the reduced number of wafers improves the electrical performance of such semiconductor structures.

[0022] Figure 1 It shows the method for forming Figure 16C and Figure 16D The flowchart of method 200 for semiconductor structure 10. Figure 2 , Figure 3 , Figure 4A, Figure 4B , Figure 5A , Figure 5B , Figure 6B , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12 to 14 , Figures 15A to 15D and Figures 16A to 16D It is shown Figure 1 A schematic cross-sectional view of the sequential operation of method 200. The cross-sectional view can be taken along different directions and along different lines or planes. Figure 5C , Figure 6A and Figure 7A It is shown Figure 1 The diagram shows some operations of method 200. Method 200 can be used to form a GAA transistor device. Method 200 includes multiple operations, and the description and illustrations are not intended to limit the order of the operations.

[0023] exist Figure 1 In operation 201, a substrate 50 is provided, such as Figure 2 As shown in the diagram, substrate 50 has a first surface S1 (also referred to as the front side) and a second surface S2 (also referred to as the back side) opposite to the first surface S1. In some embodiments, the first surface S1 is used to form a transistor, but the embodiments disclosed herein are not limited thereto. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., having p-type or n-type dopants) or undoped. Substrate 50 may be a wafer or a portion of a wafer, such as a silicon (Si) wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide (SiO2) layer, etc. The insulating layer is provided on a substrate that is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 includes: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.; or combinations thereof.

[0024] exist Figure 1 In operation 203, one or more stacked structures 51 are formed on the substrate 50, such as Figure 3As shown in the figure. In some embodiments, multiple deposition and planarization operations are performed on the first surface S1 of the substrate 50 to form a stacked structure 51. The stacked structure 51 includes alternating first semiconductor layers 52 and second semiconductor layers 54. The first semiconductor layers 52 and second semiconductor layers 54 are alternately formed over the substrate 50 along a first direction D1, which may be the thickness direction of the substrate 50. Figure 3 The multiple layers of the first semiconductor layer 52 and the second semiconductor layer 54 shown are merely non-limiting examples. Other numbers of layers are also possible and are fully intended to be included within the scope of embodiments of this disclosure. In some embodiments, the first semiconductor layer 52 is formed of an epitaxial material suitable for forming, for example, a channel region of a p-type FET, such as silicon germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1). In some embodiments, the second semiconductor layer 54 is formed of an epitaxial material, such as silicon, suitable for forming the channel region of, for example, an n-type or p-type FET. The stacked structure 51 is patterned to form the channel region of an NSFET (nanosheet FET) in subsequent operations. In particular, the stacked structure 51 is patterned to form horizontal nanosheets, wherein the channel region of the resulting NSFET comprises a plurality of horizontal nanosheets.

[0025] The stacked structure 51 can be formed by an epitaxial growth operation, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth operation, the growth chamber is cyclically exposed to a first precursor set for selectively growing a first semiconductor layer 52, and then exposed to a second precursor set for selectively growing a second semiconductor layer 54. The first precursor set includes a precursor for a first semiconductor material such as silicon-germanium, and the second precursor set includes a precursor for a second semiconductor material such as silicon. In some embodiments, the first precursor set includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second precursor set includes a silicon precursor but omits the germanium precursor.

[0026] In some embodiments, the second semiconductor layer 54 serves as a channel region for a subsequently formed semiconductor structure, and its thickness is selected based on device performance considerations. In some embodiments, the first semiconductor layer 52 is eventually removed and serves to define the vertical distance between adjacent channel regions for a subsequently formed nanosheet GAA device, and its thickness is selected based on device performance considerations. Therefore, the first semiconductor layer 52 can be referred to as a sacrificial layer, and the second semiconductor layer 54 can be referred to as a channel layer.

[0027] exist Figure 1 In operation 205, the stacked structure 51 and the substrate 50 are patterned to form the fin structure 62, such as Figure 4A and Figure 4B As shown in the image.

[0028] refer to Figure 4A A mask 55 is formed on the stacked structure 51. The mask 55 may be a photoresist pattern or spacer formed using, for example, a self-aligned operation.

[0029] refer to Figure 4B The substrate 50 and the stacked structure 51 are patterned using a single patterning operation, a double patterning operation, or a multiple patterning operation. A mask 55 is used as an etching mask to etch portions of the substrate 50 and the stacked structure 51. The etching can be any acceptable etching operation, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. In some embodiments, the etching is an anisotropic etching operation. After the etching operation, a plurality of fins 60 protruding from the remaining substrate 50 are formed. The fins 60 may be arranged along a second direction D2 perpendicular to a first direction D1. The fins 60 extend along a third direction D3 perpendicular to the first direction D1 and the second direction D2. The remaining portion of the stacked structure 51 forms a plurality of fin-like stacked structures 61, each disposed on a fin 60. In the illustrated embodiment, each of the fin-like stacked structures 61 includes alternating first semiconductor layers 52 and second semiconductor layers 54. The fins 60 and the fin-like stacked structures 61 may be collectively referred to as fin structure 62. The mask 55 is then removed after the fin structure 62 has been formed.

[0030] exist Figure 1 In operation 207, one or more isolation regions 72 are formed above the substrate 50, such as Figures 5A to 5C As shown in the image. Reference Figure 5A An insulating material 70 is deposited over the substrate 50 using, for example, high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or another suitable method. The insulating material 70 fills the gaps between adjacent fins 60. The insulating material 70 may be silicon oxide, silicon nitride, silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low dielectric constant (low k) dielectric such as carbon-doped oxides (e.g., k between about 3 and about 5), an extremely low k dielectric such as porous carbon-doped silicon dioxide (e.g., k less than 3), a polymer such as polyimide, or combinations thereof.

[0031] refer to Figure 5B and Figure 5C , Figure 5B Is along with Figure 5A A schematic cross-sectional view in the same direction as the direction, and Figure 5C yes Figure 5B A schematic perspective view of the structure shown. (See diagram below.) Figure 5B and Figure 5C As shown, a planarization operation, such as chemical mechanical polishing (CMP), is used to remove the portion of insulating material 70 above the top surface of the topmost second semiconductor layer 54. Subsequently, an etch-back operation, for example, is used to recess the insulating material 70 until the top portion of the fin 60 is exposed. The remaining insulating material 70 forms an isolation region 72. The isolation region 72 is disposed between adjacent fins 60. In some embodiments, the isolation region 72 is a shallow trench isolation (STI). In other embodiments, the top surface of the isolation region 72 is higher than or substantially flush with the top surface of the fin 60, such that the fin 60 is completely surrounded by the isolation region 72. The isolation region 72 may have a substantially flat surface, a convex surface, a concave surface, or a combination thereof, as shown.

[0032] exist Figure 1 In operation 209, a pseudo-gate oxide layer 80 is formed above the fin structure 62, such as... Figure 6A and Figure 6B As shown in the image. Figure 6B It is along Figure 6A A schematic cross-sectional view of section A-A' is shown in the figure. In some embodiments, the dummy gate oxide layer 80 is formed by thermal oxidation, CVD, sputtering, atomic layer deposition (ALD), or another suitable method. In some embodiments, the dummy gate oxide layer 80 is formed of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimides, or combinations thereof. In other embodiments, the dummy gate oxide layer 80 is made of a dielectric material having, for example, a high dielectric constant (k value) greater than 9.0. Dielectric materials include metal oxides such as HfO2, HfZrO x HfSiO x HfTiO x HfAlO x Or a combination thereof. The pseudo-gate oxide layer 80 may be conformally formed on the exposed fin structure 62, the exposed surface of the isolation region 72, and the top and sidewalls of the isolation region 72.

[0033] exist Figure 1 In operation 211, multiple pseudo-gate structures 82, 84, and 86 are formed on the isolation region 72, such as Figures 7A to 7C As shown in the image. Figure 7B It is along Figure 7A A schematic cross-sectional view of section B-B' in the diagram, and Figure 7C It is along Figure 7AA schematic cross-sectional view of section C-C' in the diagram. In some embodiments, dummy gate structures 82, 84, and 86 are formed by physical vapor deposition (PVD), CVD, sputtering, or other suitable methods. Dummy gate structures 82, 84, and 86 are formed on a dummy gate oxide layer 80. The top surfaces of dummy gate structures 82, 84, and 86 may be planarized after deposition. In some embodiments, dummy gate structures 82, 84, and 86 are formed from amorphous silicon (a-Si), polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or combinations thereof. Dummy gate structures 82, 84, and 86 are spaced apart from each other and extend along a second direction D2. In some embodiments, dummy gate structures 82, 84, and 86 extend along the second direction D2. Dummy gate structures 82, 84, and 86 enclose different portions of a plurality of fin structures 62. Dummy gate structures 82, 84, and 86 may be referred to as sacrificial gate structures because they will be replaced with metal gate structures in subsequent operations.

[0034] exist Figure 1 In operation 213, gate spacers 85 are formed around the corresponding pseudo-gate structures 82, 84, and 86, such as Figure 8A and Figure 8B As shown in the image. Reference Figure 8A The dummy gate structures 82, 84, and 86 are each partially removed by an etching operation. During the etching operation, portions of the dummy gate oxide layer 80 are removed, thus forming multiple spaced dummy gate oxide layers 80. (See reference...) Figure 8B A dielectric material, such as silicon nitride, is deposited over the dummy gate structures 82, 84, and 86. The dielectric material can be formed using ALD, CVD, sputtering, or another suitable method. Although not specifically shown, the dielectric material is patterned using one or more photolithography and etching operations, thus forming the gate spacer 85. The sidewalls of the remaining dummy gate oxide layer 80 and the sidewalls of the remaining dummy gate structures 82, 84, and 86 are each surrounded by the gate spacer 85. The gate spacer 85 can have a single-layer or multi-layer structure.

[0035] exist Figure 1 In operation 215, the patterned fin structure 62 and the substrate 50 are, as follows: Figure 9As shown in the figure. In some embodiments, an anisotropic etching operation is used to remove portions of the fin structure 62 exposed by the gate spacer 85 and the dummy gate structures 82, 84, and 86. In some embodiments, the anisotropic etching operation is source / drain etching. Source / drain etching can be performed in a variety of ways. For example, source / drain etching can be performed by dry chemical etching using a plasma source and a reactive gas. The plasma source can be inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the reactive gas can be a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, etc.), chloride (Cl2), hydrogen bromide (HBr), oxygen (O2), etc., or combinations thereof. In other embodiments, source / drain etching can be performed by wet chemical etching, such as ammonium peroxide mixtures (APM), NH4OH, tetramethylammonium hydroxide (TMAH), etc., or combinations thereof. In some other embodiments, source / drain etching can be implemented using a combination of dry chemical etching and wet chemical etching.

[0036] In some embodiments, the anisotropic etching operation selectively removes portions of the fin structure 62 without substantially consuming the gate spacer 85, the dummy gate oxide layer 80, and the dummy gate structures 82, 84, and 86. During the anisotropic etching operation, portions of the fin structure 62 are removed. The first semiconductor layer 52 becomes spaced-apart first semiconductor layers 52A, 52B, and 52C, and the second semiconductor layer 54 becomes spaced-apart second semiconductor layers 54A, 54B, and 54C. In some embodiments, the anisotropic etching operation also recesses portions of the substrate 50 exposed by the first semiconductor layers 52A, 52B, and 52C and the second semiconductor layers 54A, 54B, and 54C. In other embodiments, etching operations other than the anisotropic etching operation used to etch the fin structure 62 are used to recess the substrate 50. A plurality of recesses T10 extending into the substrate 50 are formed. The recesses T10 may have a rounded bottom profile, but in practice, they may have various profiles depending on the etching operation performed.

[0037] exist Figure 1 In operation 217, initial epitaxial structures 90S and 90D are formed in groove T10, respectively, as follows: Figure 10A and Figure 10B As shown in the image. Reference Figure 10A An epitaxial growth operation is performed on the silicon exposed by the trench T10 to form an initial epitaxial structure 90S / 90D. In some embodiments, the initial epitaxial structure 90S / 90D serves as an initial layer for the subsequently formed source / drain epitaxial structures 100S and 100D (see [link to documentation]). Figure 12In some embodiments, the initial epitaxial structure 90S / 90D is epitaxially grown to the extent that it substantially fills or partially fills each of the grooves T10.

[0038] refer to Figure 10B In some embodiments, dielectric layers 92 are formed on the initial epitaxial structures 90S / 90D. In some embodiments, dielectric layers 92 are formed by CVD, ALD, or another suitable method. In some embodiments, dielectric layers 92 are formed of a low-k dielectric, such as SiO2, SiN, SiCN, or SiOCN. Dielectric layers 92 can be used to protect the subsequently formed source / drain epitaxial structures 100S / 100D from, for example, etching operations. In other embodiments, dielectric layers 92 are not present. That is, the formation of dielectric layers 92 is optional.

[0039] exist Figure 1 In operation 219, internal spacers 94 are formed on the sidewalls of the first semiconductor layer 52A, the first semiconductor layer 52B, and the first semiconductor layer 52C, respectively, such as Figure 11A and Figure 11B As shown in the image. Reference Figure 11A In some embodiments, one or more etching operations are used to remove portions of the first semiconductor layer 52A, portions of the first semiconductor layer 52B, and portions of the first semiconductor layer 52C. Selective etching is used to horizontally recess the first semiconductor layers 52A, 52B, and 52C, creating multiple openings H1 on the outer sides of each of the second semiconductor layers 54A, 54B, and 54C. By way of example and not limitation, the first semiconductor layers 52A, 52B, and 52C are made of silicon-germanium, and the second semiconductor layers 54A, 54B, and 54C are made of silicon, allowing for selective etching of the first semiconductor layers 52A, 52B, and 52C. In some embodiments, selective etching includes etching a silicon-germanium ammonium hydroxide-hydrogen peroxide-water mixture at a rate faster than that used to etch silicon. Therefore, the second semiconductor layers 54A, 54B, and 54C extend laterally beyond the opposite end faces of the first semiconductor layers 52A, 52B, and 52C, respectively.

[0040] refer to Figure 11B Dielectric materials are formed on the sidewalls of the remaining first semiconductor layer 52A, the remaining first semiconductor layer 52B, and the remaining first semiconductor layer 52C, respectively. In some embodiments, the dielectric material includes a silicon nitride-based material, such as SiN, silicon oxynitride, silicon carbonitride (SiOCN), silicon carbonitride (SiCN), or combinations thereof. The dielectric material can be formed using ALD, CVD, or another suitable method.

[0041] After each opening H1 is filled with dielectric material, one or more etching operations are used to trim the dielectric material outside the sidewalls of the second semiconductor layers 54A, 54B and 54C, thus forming the internal spacer 94.

[0042] exist Figure 1 In operation 221, a source / drain epitaxial structure 100S / 100D is formed above the substrate 50, such as... Figure 12 As shown in the figure. In some embodiments, the source / drain epitaxial structure 100S / 100D is formed using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or other suitable methods. In embodiments where dielectric layer 92 is present, the source / drain epitaxial structure 100S / 100D is formed laterally from the second semiconductor layers 54A, 54B, and 54C. In embodiments where dielectric layer 92 is absent, the source / drain epitaxial structure 100S / 100D is formed laterally from the second semiconductor layers 54A, 54B, and 54C, and upward from the initial epitaxial structure 90S / 90D. In some embodiments, the source / drain epitaxial structure 100S / 100D is formed of a material comprising silicon and germanium. The material gradually increases in size and fills the gaps between adjacent fin structures 62. The source / drain epitaxial structure 100S / 100D can have various profiles. Figure 12 The outlines of the source / drain epitaxial structures 100S / 100D shown in the figures below are merely illustrative. The source / drain epitaxial structures 100S / 100D may have surfaces protruding from the respective end faces of the second semiconductor layers 54A, 54B, and 54C, and may have multiple small planes.

[0043] The source / drain epitaxial structure 100S / 100D can be in-situ doped during epitaxial growth by introducing dopant including p-type dopant (such as boron or BF2) or n-type dopant (such as phosphorus or arsenic). If the source / drain epitaxial structure 100S / 100D is not in-situ doped, an implantation operation is performed to dope the source / drain epitaxial structure 100S / 100D. In some embodiments, the source / drain epitaxial structure 100S / 100D in an n-type transistor comprises SiP, while those in a p-type transistor comprise SiGeB, GeSnB, and / or SiGeSnB. After the source / drain epitaxial structure 100S / 100D is formed, an annealing operation can be performed to activate the p-type or n-type dopant in the source / drain epitaxial structure 100S / 100D. The annealing operation can be, for example, rapid thermal annealing (RTA), laser annealing, millisecond thermal annealing (MSA), etc.

[0044] In some embodiments, the lattice constant of the source / drain epitaxial structure 100S / 100D is different from the lattice constant of the second semiconductor layers 54A, 54B, and 54C, thereby allowing the channel regions in the second semiconductor layers 54A, 54B, and 54C to be strained or stressed by the source / drain epitaxial structure 100S / 100D to improve the mobility of charge carriers such as electrons.

[0045] exist Figure 1 In operation 223, a contact etch stop layer (CESL) 102 is formed above the corresponding source / drain epitaxial structure 100S / 100D, such as... Figure 13 As shown in the figure. In some embodiments, a dielectric material such as SiN, SiON, SiCN, SiOCN, or combinations thereof is conformally deposited on the source / drain epitaxial structure 100S / 100D, the gate spacer 85, and the dummy gate structures 82, 84, and 86. The dielectric material can be formed using plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), ALD, or other suitable methods. In some embodiments, the contact etch stop layer 102 can be a stress layer.

[0046] exist Figure 1 In operation 225, a dielectric layer 110 is formed above the corresponding contact etch stop layer 102, such as... Figure 14 As shown in the diagram. In some embodiments, a dielectric material such as silicon oxide, silicon nitride, PSG, BSG, BPSG, USG, or combinations thereof is deposited on the contact etch stop layer 102, the gate spacer 85, and the dummy gate structures 82, 84, and 86. The dielectric material can be formed using CVD, PECVD, FCVD, spin coating, or another suitable method. Other insulating materials formed by any acceptable method can be used. A planarization operation such as CMP can be used to remove excess portions of the dielectric material of the contact etch stop layer 102 and the dielectric layer 110 above the top surfaces of the gate spacer 85 and the dummy gate structures 82, 84, and 86, thus forming the dielectric layer 110. The top surfaces of the dummy gate structures 82, 84, and 86 are exposed through the dielectric layer 110 and are flush with the top surfaces of the contact etch stop layer 102 and the dielectric layer 110.

[0047] exist Figure 1 In operation 227, a polysilicon gate (RPG) replacement operation is performed, such as... Figures 15A to 15D As shown in the image. Reference Figure 15AOne or more etching operations are used to remove the dummy gate structures 82, 84, and 86 and the dummy gate oxide layer 80. After forming a plurality of gate trenches O1 between the gate spacers 85, another etching operation is used to remove the first semiconductor layers 52A, 52B, and 52C. The etching operation may be referred to as a silicon removal operation. In some embodiments, the silicon removal operation includes using a solution selective for silicon. For example, TMAH may be used in such an operation. In some embodiments, the silicon removal operation selectively etches the first semiconductor layers 52A, 52B, and 52C while substantially not consuming the second semiconductor layers 54A, 54B, and 54C. After removing the first semiconductor layers 52A, 52B, and 52C, a plurality of openings O2 are formed between the internal spacers 94. At this stage, the second semiconductor layers 54A, 54B, and 54C become horizontal nanosheets suspended above the substrate 50. The second semiconductor layers 54A, 54B, and 54C are located between the source / drain epitaxial structure 100S / 100D and other source / drain epitaxial structure pairs (not shown). The second semiconductor layers 54A, 54B, and 54C can be interchangeably referred to as nanostructures (or alternatively, nanowire structures, nanosheet structures, etc., depending on their geometry). The nanosheet structures can be collectively referred to as the channel region.

[0048] refer to Figure 15B A gate dielectric layer 118 is conformally deposited on the exposed portions of the second semiconductor layers 54A, 54B, and 54C, and in the openings O2 formed by removing the first semiconductor layers 52A, 52B, and 52C. Furthermore, some of the gate dielectric layers 118 are formed in trenches O1 between the gate spacers 85. The gate dielectric layers 118 are formed using thermal oxidation, ALD, CVD, molecular beam deposition (MBD), or another suitable method. In some embodiments, the gate dielectric layers 118 are formed of a high-k dielectric (a material having a k value greater than about 7.0), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO2), hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), or combinations thereof. In some embodiments, the gate dielectric layers 118 cover the sidewalls of the inner spacer 94 and the sidewalls of the second semiconductor layers 54A, 54B, and 54C, such as... Figure 15B As shown in the image.

[0049] refer to Figure 15C One or more conductive materials are deposited over substrate 50 to form gate layer 122. The conductive material is formed using sputtering, PVD, CVD, ALD, or another suitable method. The conductive material is deposited into openings O1 and O2 and conformally formed over gate dielectric layer 118.

[0050] refer to Figure 15D , Figure 15DIt is along Figure 15C A cross-sectional view of section D-D' in the diagram. In some embodiments, the gate layer 122 includes a plurality of gate electrodes 122A, 122B, and 122C that are parallel to each other, but... Figure 15D Only gate electrode 122B is shown. Second semiconductor layers 54A, 54B, and 54C are wrapped by gate electrodes 122A, 122B, and 122C, respectively. In some embodiments, gate electrodes 122A, 122B, and 122C are multilayer structures. Each of gate electrodes 122A, 122B, and 122C may include multiple layers, such as a barrier layer, a work function layer, and a conductive layer. For example, the barrier layer may be conformally formed on the gate dielectric layer 118. The barrier layer is made of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. The work function layer may be conformally formed on the barrier layer. Exemplary p-type work function materials (which may also be referred to as p-type work function metals) include TiN, TaN, Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function materials (which may also be referred to as n-type work function metals) include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A conductive layer may be formed on the work function layer and fill the gaps left by the work function layer. The conductive layer is made of W, Cu, Co, Al, Ni, Ta, Ti, Mo, Pd, Pt, Ru, Ir, Ag, Au, etc., or combinations thereof.

[0051] Gate electrodes 122A, 122B, and 122C, and their respective gate dielectric layers 118, can be collectively referred to as gate structure 125. Gate structure 125 and second semiconductor layers 54A, 54B, and 54C (i.e., nanosheets) are arranged alternately along a first direction D1. In some embodiments, internal spacers 94 are disposed on opposite sides of a gate structure 125.

[0052] exist Figure 1 In operation 229, source / drain contacts 130 are formed above the corresponding source / drain epitaxial structures 100S / 100D, such as... Figures 16A to 16D As shown in the image. Reference Figure 16A An etching operation is used to remove portions of the dielectric layer 110 and the contact etch stop layer 102 to form an opening O10 exposing the underlying source / drain epitaxial structure 100S / 100D. Although the contact etch stop layer 102 is present, portions of the source / drain epitaxial structure 100S / 100D may be consumed during the etching operation.

[0053] refer to Figure 16BA silicide operation is performed on the source / drain epitaxial structure 100S / 100D. In some embodiments, the silicide operation transforms the upper portion of the source / drain epitaxial structure 100S / 100D into a metal silicide 128. The metal silicide 128 is used to improve the adhesion or conductivity between the source / drain epitaxial structure 100S / 100D and the subsequently deposited conductive material.

[0054] refer to Figure 16C One or more conductive materials are deposited on the metal silicide 128 and the source / drain epitaxial structure 100S / 100D to form source / drain contacts 130. The conductive materials include W, Cu, Co, Al, Ni, Ta, Ti, Mo, Pd, Pt, Ru, Ir, Ag, Au, etc., or combinations thereof. The source / drain contacts 130 penetrate the dielectric layer 110 and the contact etch stop layer 102 and extend to the source / drain epitaxial structure 100S / 100D. The source / drain contacts 130 are electrically coupled to the source / drain epitaxial structure 100S / 100D. The source / drain contacts 130 formed above the source epitaxial structure 100S can be referred to as source contacts 130, and the source / drain contacts 130 formed above the drain epitaxial structure 100D can be referred to as drain contacts 130. At this stage, a semiconductor structure 10 is formed.

[0055] Figure 16D It is along Figure 16C The diagram shows a combined cross-sectional view of three parallel sections E-E', F-F', and G-G'. In some embodiments, the gate structure 125 encloses second semiconductor layers 54A, 54B, and 54C. Source / drain epitaxial structures 100S / 100D are formed on opposite sides of the gate structure 125. Furthermore, source / drain contacts 130 are formed on opposite sides of the gate structure 125.

[0056] Figure 17 It shows the process for continuing to form. Figure 16C and Figure 16D The flowcharts for method 200 and method 300 of semiconductor structure 10 are shown. Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figures 22B to 22D , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A , Figure 31B and Figures 32A to 32C It is shown Figure 17 A schematic cross-sectional view of the sequential operations of method 300. The cross-sectional view can be taken along different directions and along different lines or planes. Method 300 includes multiple operations, and the description and illustration are not intended to be a limitation on the order of the operations.

[0057] exist Figure 17 In operation 301, the portion of substrate 50 and gate electrode 122B is removed, such as... Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B As shown in the figure. In some embodiments, the semiconductor structure 10 is flipped for subsequent operation; however, for ease of understanding, the semiconductor structure 10 is not shown as flipped.

[0058] refer to Figure 18A and Figure 18B In some embodiments, a patterned photoresist 40 is formed on the second surface S2 of the substrate 50. The patterned photoresist 40 has one or more spaced openings O40, depending on design requirements. In some embodiments, the openings O40 are within the coverage area of ​​one of the fin structures 62. For example, the openings O40 are aligned with the fin structure 62 including the gate electrode 122B and the second semiconductor layer 54B. In some embodiments, the patterned photoresist 40 is used as an etching mask to perform multiple etching operations on the second surface S2 of the substrate 50. The etching operations may include dry etching, RIE, or combinations thereof. In some embodiments, one etching operation is used to remove a portion of the substrate 50 and another etching operation is used to remove a portion of the isolation region 72, but the embodiments disclosed herein are not limited thereto. The order of the etching operations is not limited. Etching operations may be performed until the bottommost gate dielectric layer 118 is exposed through the opening O50. In some embodiments, the opening O50 tapers gradually from the second surface S2 to the first surface S1. In some embodiments, the opening O50 is separated from the source / drain epitaxial structure 100S / 100D.

[0059] refer to Figure 19A and Figure 19BIn some embodiments, an etching operation is used to extend the opening O50 by removing a lower portion of the bottommost gate dielectric layer 118. The etching operation may include dry etching, RIE, or a combination thereof. The etching operation enlarges the opening O50, and the gate electrode 122B is exposed through the enlarged opening O50.

[0060] refer to Figure 20A and Figure 20B In some embodiments, an etching operation is used to further extend the opening O50 by removing a portion of the gate electrode 122B. The etching operation may include dry etching, RIE, or a combination thereof. The etching operation further enlarges the opening O50, and the upper portion of the bottommost gate dielectric layer 118 is exposed through the enlarged opening O50.

[0061] refer to Figure 21A and Figure 21B In some embodiments, an etching operation is used to further extend the opening O50 by removing the upper portion of the bottommost gate dielectric layer 118. The etching operation may include dry etching, RIE, or a combination thereof. The etching operation further enlarges the opening O50, and the bottommost second semiconductor layer 54B is exposed through the enlarged opening O50.

[0062] exist Figure 17 In operation 303, one of the second semiconductor layers 54B is removed, such as... Figures 22A to 22D As shown in the image. Reference Figure 22A and Figure 22B In some embodiments, an etching operation is used to remove the bottom second semiconductor layer 54B through opening O50. In some embodiments, the etching operation may include wet etching, atomic layer etching (ALE), lateral etching, or a combination thereof. When the bottom second semiconductor layer 54B is removed, opening O52 is formed. Opening O52 is connected to opening O50. The patterned photoresist 40 is then removed.

[0063] refer to Figure 22C and Figure 22D , Figure 22C Is along with Figure 22B A cross-sectional view in the same direction as the direction of the view, and Figure 22D yes Figure 22C A top view. In some embodiments, during the removal of the bottommost second semiconductor layer 54B, additional etching operations are used to further remove portions of the gate electrode 122B and the substrate 50. Therefore, the width W52 of the opening O52 can be increased, depending on design requirements. In some embodiments, the width W52 of the opening O52 is substantially uniform. Because both the gate electrode 122B and the substrate 50 are conductors, removing the conductor portions of the semiconductor structure 10 can reduce parasitic capacitances that may be generated when the semiconductor structure 10 is in operation. Figure 22DThe top view shows the portion O52 of the gate electrode 122B that could be further removed to reduce parasitic capacitance. Figure 22D Subsequently, an M0 metal line 132 electrically connected to the source / drain contact 130 can be formed above the source / drain contact 130.

[0064] exist Figure 17 In operation 305, a dielectric layer 140 is formed in openings O50 and O52, such as Figure 23A and Figure 23B As shown in the diagram. The dielectric layer 140 can be formed using CVD, PECVD, FCVD, spin coating, or another suitable method. In some embodiments, the dielectric layer 140 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, or combinations thereof. The dielectric material is deposited on the second surface S2 of the substrate 50 until the openings O50 and O52 are completely filled with the dielectric material. The dielectric material can be planarized using a planarization operation such as CMP, thus forming the dielectric layer 140.

[0065] exist Figure 17 In operation 307, a mesa removal operation is performed on the semiconductor structure 10, such as... Figure 24A and Figure 24B As shown in the diagram. In some embodiments, the mesa removal operation refers to the complete removal of the substrate 50 and optionally the removal of the isolation region 72. In some embodiments, multiple etching operations are performed on the second surface S2 of the substrate 50. In such embodiments, the etchant of the etching operations is selective for the materials of the substrate 50 and the isolation region 72. The etching operations may include dry etching, RIE, or combinations thereof. For example, one etching operation may be used to remove the substrate 50 and another etching operation may be used to remove the isolation region 72, but the embodiments disclosed herein are not limited thereto. The order of the etching operations is not limited. After the mesa removal operation, the bottommost gate dielectric layer 118 and the initial epitaxial structure 90S / 90D are exposed.

[0066] exist Figure 17 In operation 309, a dielectric refilling operation is performed on the semiconductor structure 10, such as... Figure 25A and Figure 25B As shown in the diagram. In some embodiments, additional dielectric material is deposited in the region where the substrate 50 initially exists. Thus, the dielectric material covers the bottommost gate dielectric layer 118 and the initial epitaxial structure 90S / 90D. The dielectric material can be planarized using a planarization operation such as CMP. For convenience, the resulting dielectric layer is also designated as 140. The dielectric layer 140 may have a substantially flat surface S140.

[0067] exist Figure 17In operation 311, a conductive member 152 is formed connected to the source epitaxial structure 100S (or source epitaxial structure 100D, but this embodiment only uses source epitaxial structure 100S as an example), such as Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A and Figure 30B As shown in the image. Reference Figure 26A and Figure 26B A patterned photoresist 42 is formed on the surface S140 of the dielectric layer 140. The patterned photoresist 42 has one opening O42 or multiple spaced openings O42, depending on design requirements. In some embodiments, the opening O42 is aligned with the source epitaxial structure 100S from a top viewpoint.

[0068] refer to Figure 27A and Figure 27B One or more etching operations are performed on the surface S140 of the dielectric layer 140 using patterned photoresist 42 as an etching mask. The etching operations may include dry etching, RIE, or a combination thereof. In some embodiments, one etching operation is used to remove a portion of the dielectric layer 140 located within the coverage area of ​​the source epitaxial structure 100S, and another etching operation is used to remove the initial epitaxial structure 90S and the dielectric layer 92 above the initial epitaxial structure 90S, but the embodiments disclosed herein are not limited thereto. The etching operations may continue until the source epitaxial structure 100S is exposed by the opening O60.

[0069] refer to Figure 28A and Figure 28B A silicide operation is performed on the source epitaxial structure 100S. In some embodiments, the silicide operation transforms the lower portion of the source epitaxial structure 100S into silicide 148. Silicide 148 is used to improve the adhesion or conductivity between the source epitaxial structure 100S and the subsequently deposited conductive material.

[0070] refer to Figure 29A and Figure 29B A liner layer 150 is conformally formed in the opening O60. In some embodiments, the liner layer 150 is formed by CVD, ALD, or another suitable method. In some embodiments, the liner layer 150 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, or combinations thereof. Although not specifically shown, one or more barrier layers may be formed on the liner layer 150. The barrier layers are made of titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof.

[0071] refer to Figure 30A and Figure 30B One or more conductive materials are deposited in the opening O60 and above the pad layer 150. The conductive materials include W, Cu, Co, Al, Ni, Ta, Ti, Mo, Pd, Pt, Ru, Ir, Ag, Au, etc., or combinations thereof. Excess conductive material can be removed using a planarization operation such as CMP, thus forming the conductive member 152. The conductive member 152 is correspondingly electrically connected to the source epitaxial structure 100S. According to some embodiments, the conductive member 152 is a conductive via.

[0072] exist Figure 17 In operation 313, the initial epitaxial structure 90D is replaced with dielectric layer 160, as follows: Figure 31A , Figure 31B and Figures 32A to 32C As shown in the image. Reference Figure 31A and Figure 31B One or more etching operations are performed on the surface S140 of the dielectric layer 140. Etching operations may include dry etching, RIE, or combinations thereof. In some embodiments, one etching operation is used to remove a portion of the dielectric layer 140, and another etching operation is used to remove the initial epitaxial structure 90D and the dielectric layer 92 above the initial epitaxial structure 90D, but the embodiments disclosed herein are not limited thereto. Etching operations may be performed until the drain epitaxial structure 100D is exposed. Thus, a plurality of openings O62 are formed. In some embodiments, the drain epitaxial structure 100D is exposed by one of the openings O62.

[0073] refer to Figure 32A and Figure 32B A dielectric material is deposited in the opening O62 using methods such as CVD, ALD, or another suitable method. The dielectric material can be silicon oxide, silicon nitride, SiON, FSG, PSG, BSG, BPSG, USG, etc., or combinations thereof. The dielectric material can be planarized using a planarization operation such as CMP, thus forming a dielectric layer 160. At this stage, a semiconductor structure 20 is formed. In some embodiments, the semiconductor structure 20 uses... Figure 1 Method 200 and subsequent Figure 17 The semiconductor structure 20 is formed using method 300. In some embodiments, a back-side power delivery (BPD) is used to supply power to the semiconductor structure 20 via the conductive member 152. The conductive member 152 may be referred to as a back-side via or a back-side power rail (BPR). The dielectric layer 160 may be referred to as a back-side interlayer dielectric (B-ILD) layer. In some embodiments, when the conductive member 152 is electrically connected to a power supply, the padding layer 150 is used to prevent short circuits when current flows through the conductive member 152.

[0074] refer to Figure 32CIn embodiments where portions of the gate electrode 122B and substrate 50 are further removed, the resulting gaps are filled with more dielectric material to form a dielectric layer 140.

[0075] Figure 33 This is a schematic perspective view of semiconductor structure 20. In some embodiments, semiconductor structure 20 includes fin structures with different numbers of channel regions (nanosheets). In some embodiments, fin structure 62 has N second semiconductor layers, such as second semiconductor layers 54A or 54C, and fin structure 64 has N-1 second semiconductor layers, such as second semiconductor layer 54B. In such embodiments, fin structure 62 has N nanosheets, and fin structure 64 has N-1 nanosheets. Fin structure 64 includes one less nanosheet than fin structure 62. Semiconductor structure 20 may be referred to as a hybrid sheet structure including N-1 nanosheets and N nanosheets. In some embodiments, semiconductor structure 20 includes a hybrid sheet structure comprising K nanosheets and N nanosheets, where K is not equal to N. Furthermore, fin structure 62 includes M gate structures 125 located between N nanosheets, and fin structure 64 includes M-1 gate structures 125 located between N-1 nanosheets. That is, fin structure 64 includes one less metal gate than fin structure 62. Fin structures 62 and 64 may be adjacent to or far apart from each other, for example, in different cells or regions of a shared semiconductor structure, depending on design requirements. In some embodiments, fin structures 62 and 64 are separated by a source epitaxial structure 100S or a drain epitaxial structure 100D. In other embodiments, fin structures 62 and 64 are separated by a plurality of source / drain epitaxial structures 100S / 100D.

[0076] Figure 34A and Figure 34B These include Figure 33A simplified circuit diagram of one or more semiconductor devices 1A and 1B in semiconductor structure 20 is shown. Semiconductor device 1A includes a first circuit R1 connected to a second circuit R2. According to some embodiments, semiconductor device 1A includes a critical path in the second circuit R2. To achieve a better trade-off between power and speed, the transistors used to form the critical path, or the transistors in the second circuit R2, are implemented using a fin structure 62, while the transistors in the first circuit R1 are implemented using a fin structure 64. This is because, on the one hand, the transistors implemented using fin structure 62 include a larger number of channel regions than the channel regions of fin structure 64, and therefore the transistors implemented using fin structure 62 can have larger channel currents to achieve a higher operating speed than the transistors implemented using fin structure 64. By means of fin structure 62, the operating speed of the speed-sensitive critical path can be increased, and the overall speed of semiconductor device 1A can be improved accordingly. Therefore, fin structure 62 is suitable for use in the second circuit R2. On the other hand, the transistor implemented using fin structure 64 can have a smaller channel current than fin structure 62, thus saving more power than the transistor implemented using fin structure 64 without significantly affecting the operating speed of semiconductor device 1A, and is therefore suitable for use in the first circuit R1. That is, semiconductor device 1A includes some transistors with a larger number of channel regions (nanofes) and some transistors with a smaller number of channel regions (nanofes), and therefore a better trade-off between speed and power consumption can be achieved for semiconductor device 1A. Therefore, semiconductor device 1A has a hybrid fin-plate structure.

[0077] Similarly, semiconductor device 1B includes a third circuit R3 connected to the fourth circuit R4. In some embodiments, the third circuit R3 includes one or more fin structures 64, and the fourth circuit R4 includes one or more fin structures 62. According to some embodiments, semiconductor device 1B includes a critical path in the third circuit R3. To achieve a better trade-off between power and speed, the transistors forming the critical path, or the transistors in the third circuit R3, are implemented using fin structures 62, while the transistors in the fourth circuit R4 are implemented using fin structures 64. Therefore, semiconductor device 1B includes some transistors with a larger number of channel regions (nanofes) and some transistors with a smaller number of channel regions (nanofes), and thus a better trade-off between speed and power can be achieved for semiconductor device 1B. Therefore, semiconductor device 1A has a hybrid plate-fin structure. Therefore, semiconductor device 1B has a hybrid plate-fin structure.

[0078] Figures 35A to 35C It includes Figure 34A Semiconductor device 1A or Figure 34BA schematic diagram of the chip or semiconductor structure of semiconductor device 1B is shown. Semiconductor device 1A or 1B includes one or more first chips C1 and one or more second chips C2. The first chip C1 may be a system-on-a-chip (SoC), and the second chip C2 may be a central processing unit (CPU) chip, but the embodiments disclosed herein are not limited thereto.

[0079] refer to Figure 35A In some embodiments, the arrangement separating the fin structure 64 (having a smaller number of nanosheets) and the fin structure 62 (having a larger number of nanosheets) is based on different chips or cells. In some embodiments, the first chip C1 includes only circuits having characteristics similar to the first circuit R1 or the fourth circuit R4, each of which includes transistors implemented with the fin structure 64, and the second chip C2 includes only circuits having characteristics similar to the second circuit R2 or the third circuit R3, each of which includes the fin structure 62. That is, the first chip C1 includes only transistors having a smaller number (e.g., N-1) of channel regions, and the second chip C2 includes only transistors having a larger number (e.g., N) of channel regions.

[0080] refer to Figure 35B In some embodiments, the arrangement separating the fin structures 64 (having a smaller number of nanosheets) and fin structures 62 (having a larger number of nanosheets) is based on different circuit blocks of a chip or cell. In some embodiments, the first chip C1 and the second chip C2 each include multiple circuit blocks B1 and B2. Circuit block B1 of the first chip C1 includes circuitry with fin structures 64, similar to the first circuit R1, and circuit block B2 of the first chip C1 includes circuitry with fin structures 62, similar to the second circuit R2. Similarly, block B1 of the second chip C2 includes circuitry with fin structures 64, similar to the first circuit R1, and block B2 of the second chip C2 includes circuitry with fin structures 62, similar to the second circuit R2. In other words, the transistors in each circuit block B1 or B2 of the first chip C1 or the second chip C2 are implemented using all fin structures 62 or all fin structures 64.

[0081] refer to Figure 35CIn some embodiments, the arrangement separating the fin structure 64 (having N-1 nanosheets) and the fin structure 62 (having a larger number of nanosheets) is based on different transistors. In some embodiments, a single block B1 or B2 of the first chip C1 or the second chip C2 includes multiple transistors T1 and T2. In some embodiments, transistor T1 includes fin structure 62, and transistor T2 includes fin structure 64. In such embodiments, adjacent or closely arranged transistors may include different numbers of channel regions (nanofashes). In other embodiments, the first chip C1 or the second chip C2 includes a transistor with fin structure 62 and a transistor with fin structure 64 in a single block B1 of the first chip C1 or the second chip C2.

[0082] Capacitance is a measure of the ability to store electrical charge. Parasitic capacitance is an unavoidable and generally unwanted capacitance that exists between parts of an electronic component or circuit due to their proximity to each other. When two conductive or semiconductive materials are arranged close to each other while being insulated, an electric field may be generated between them, allowing charge to accumulate on the conductive or semiconductive materials by inserting an insulating material between them.

[0083] Figure 36 This illustrates that parasitic capacitance may exist in similar... Figure 16CThe diagram illustrates possible locations within the uniform nanosheet semiconductor structure of the semiconductor structure 10 shown. A first parasitic capacitance PC1 may exist between the gate electrodes 122A, 122B, and 122C between the gate spacer 85 and the channel regions 54A, 54B, and 54C, or between the gate electrodes 122A, 122B, and 122C adjacent to the source epitaxial structure 100S or the drain epitaxial structure 100D. A second parasitic capacitance PC2 may exist between the gate electrodes 122A, 122B, and 122C and the adjacent source epitaxial structure 100S or the drain epitaxial structure 100D via an intermediate internal spacer 94, wherein the gate electrodes 122A, 122B, and 122C are located between the source epitaxial structure 100S and the drain epitaxial structure 100D. The third parasitic capacitance PC3 may exist between a lightly doped region (not shown separately) and adjacent gate electrodes 122A, 122B, and 122C. The lightly doped region is located at both ends of the channel regions 54A, 54B, and 54C near the source epitaxial structure 100S and the drain epitaxial structure 100D. The fourth parasitic capacitance PC4 may exist between the gate electrodes 122A, 122B, and 122C and adjacent source epitaxial structure 100S or drain epitaxial structure 100D through the intermediate channel regions 54A, 54B, and 54C. The gate electrodes 122A, 122B, and 122C are located between the source epitaxial structure 100S and the drain epitaxial structure 100D. The fifth parasitic capacitance PC5 may exist between the gate electrodes 122A, 122B, and 122C and the underlying substrate 50, with the gate electrodes 122A, 122B, and 122C located between the source epitaxial structure 100S and the drain epitaxial structure 100D. The sixth parasitic capacitance PC6 may exist through the dielectric layer 92 between the source epitaxial structure 100S or the drain epitaxial structure 100D and the underlying substrate 50 or the initial epitaxial structures 90D and 90S.

[0084] refer to Figure 32A The proposed hybrid semiconductor structure 20 and Figure 16CThe difference in the uniform wafer semiconductor structure 10 shown is that the bottommost gate electrode 122B closest to the substrate 50 and its adjacent channel region 54B are removed and replaced by a dielectric layer 140. Furthermore, the substrate 50 is also replaced by the dielectric layer 140. Due to the removal of the gate electrode 122B, the channel region 54B, and the substrate 50, the amounts of the first parasitic capacitance PC1, the second parasitic capacitance PC2, the third parasitic capacitance PC3, the fourth parasitic capacitance PC4, the fifth parasitic capacitance PC5, and the sixth parasitic capacitance PC6 can be reduced, respectively. According to some embodiments, given that the total number of channels in the uniform wafer semiconductor structure 10 is set to three, the reduction in the parasitic capacitance of the first parasitic capacitance PC1 and the second parasitic capacitance PC2 in the proposed hybrid wafer semiconductor structure 20 can be as much as 1 / 3. Furthermore, according to some embodiments, given that the total number of channels in the uniform wafer semiconductor structure 10 is set to three, the reduction in the parasitic capacitance of the third parasitic capacitance PC3 and the fourth parasitic capacitance PC4 in the proposed hybrid wafer semiconductor structure 20 can reach less than about 1 / 3. According to some embodiments, the parasitic capacitances of the fifth parasitic capacitance PC5 and the sixth parasitic capacitance PC6 for the proposed hybrid semiconductor structure 20 are essentially eliminated due to the removal of the substrate 50. Therefore, the proposed hybrid semiconductor structure 20 can improve power efficiency by reducing power consumption caused by parasitic capacitances.

[0085] This disclosure presents a semiconductor structure with a hybrid wafer configuration and a method for forming such a semiconductor structure. The proposed hybrid wafer configuration offers advantages. Parasitic capacitance is significantly reduced due to the removal of conductive and semiconductive materials. For example, the parasitic capacitance of the semiconductor structure is reduced when one of the substrate or the metal gate is removed. Furthermore, the nanosheet semiconductor structure provides design flexibility for fin structures with different numbers of nanosheets (channel numbers). Thus, speed-sensitive circuits can be implemented with fin structures having a larger number of channels to improve speed, while power-sensitive circuits can be implemented with fin structures having a smaller number of channels to save power. A better power-speed tradeoff can be achieved, and system performance can be enhanced without sacrificing too much power. Therefore, the power efficiency of the semiconductor structure can be further improved. In addition, the formation of the back-side power rails can be performed during substrate removal. Therefore, manufacturing time and cost can be managed more economically. Furthermore, the removal operations of the gate electrode, channel region, and substrate are performed from the second surface (back side) of the semiconductor structure. The layout and circuit design of the semiconductor structure on the first surface (front side) remain unchanged. Therefore, the original well-proven circuit layout on the front side can be reused in the design of the proposed semiconductor structure. This can further reduce the design cycle and cost.

[0086] One aspect of this disclosure provides a method for forming a semiconductor structure. The method includes: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation region above the first surface, wherein the isolation region includes an insulating material having a dielectric constant between about 3 and about 5; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a plurality of first wafers and the second stacked structure includes a plurality of second wafers; forming a first gate structure and a second gate structure above the first stacked structure and the second stacked structure, wherein the first gate structure and the second gate structure respectively enclose the plurality of first wafers and the plurality of second wafers; forming a first epitaxial structure and a second epitaxial structure in a recess in the substrate on an opposite side of the second stacked structure; forming an etch stop layer above the respective first epitaxial structure and the respective second epitaxial structure; forming a dielectric layer above the respective etch stop layer; forming a first opening by recessing the substrate from the second surface; and filling the first opening with a first dielectric material.

[0087] Another aspect of this disclosure provides a method for forming a semiconductor structure. The method includes: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation structure above the first surface; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a first sacrificial layer and a first channel layer alternately arranged with the first sacrificial layer, and the second stacked structure includes a second sacrificial layer and a second channel layer alternately arranged with the second sacrificial layer; forming a first epitaxial structure and a second epitaxial structure in a recess in the substrate on opposite sides of the first stacked structure, wherein the first epitaxial structure is located between the first stacked structure and the second stacked structure, and portions of the first and second epitaxial structures are suspended above the isolation structure; forming a first source / drain epitaxial structure above the first epitaxial structure, and forming a second source / drain epitaxial structure above the second epitaxial structure. A second source / drain epitaxial structure is formed above the first epitaxial structure; the upper portions of the first and second source / drain epitaxial structures are converted into metal silicides; source / drain contacts electrically coupled to the first and second source / drain epitaxial structures are formed on the respective silicides; the first and second sacrificial layers are replaced with a first dielectric layer and a conductive layer; a first opening is formed by etching the conductive layer closest to the second surface of the substrate and the first stack structure from the second surface, wherein the first opening is located between the first and second epitaxial structures; a second opening is formed by etching through the first opening through the bottommost one of the first channel layers, wherein the second opening is connected to the first opening; and the first and second openings are filled with a first dielectric material.

[0088] Another aspect of the embodiments of this disclosure provides a semiconductor structure. The semiconductor structure includes: a first stacked structure including a first metal gate structure and a first channel layer alternately arranged with respect to the first metal gate structure; a second stacked structure separated from the first stacked structure and including a second metal gate structure and a second channel layer alternately arranged with respect to the second metal gate structure; a drain epitaxial structure and a source epitaxial structure disposed on opposite sides of the first stacked structure, wherein the drain epitaxial structure is located between the first and second stacked structures, and the source epitaxial structure is located on the side of the second stacked structure opposite to the drain epitaxial structure; a first contact etch stop layer and a second contact etch stop layer, the first contact etch stop layer being disposed above the drain epitaxial structure and the second contact etch stop layer being disposed above the source epitaxial structure; a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed above the first contact etch stop layer and the second dielectric layer being disposed above the second contact etch stop layer; a drain contact extending through the first dielectric layer and electrically coupled to the drain epitaxial structure; and a source contact extending through the second dielectric layer and electrically coupled to the source epitaxial structure. The first stacked structure has a first number of first channel layers, and the second stacked structure has a second number of second channel layers, wherein the first number and the second number are different.

[0089] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation region above the first surface, wherein the isolation region includes an insulating material having a dielectric constant between 3 and 5; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a plurality of first sheets and the second stacked structure includes a plurality of second sheets; forming a first gate structure and a second gate structure above the first stacked structure and the second stacked structure, wherein the first gate structure and the second gate structure respectively enclose the plurality of first sheets and the plurality of second sheets; forming a first epitaxial structure and a second epitaxial structure in a recess of the substrate on an opposite side of the second stacked structure; forming an etch stop layer above the respective first epitaxial structure and the second epitaxial structure; forming a dielectric layer above the respective etch stop layer; forming a first opening by recessing the substrate from the second surface; and filling the first opening with a first dielectric material.

[0090] In some embodiments, the method further includes: forming a first source / drain epitaxial structure and a second source / drain epitaxial structure over the first epitaxial structure and the second epitaxial structure, respectively, wherein the first source / drain epitaxial structure and the second source / drain epitaxial structure are in contact with the sidewalls of the second wafer. In some embodiments, the first opening is located between the first epitaxial structure and the second epitaxial structure. In some embodiments, the first opening is separated from the first source / drain epitaxial structure and the second source / drain epitaxial structure. In some embodiments, the method further includes: removing the substrate to expose at least the first epitaxial structure, the second epitaxial structure, and the first gate structure. In some embodiments, the method further includes: depositing a second dielectric material to cover the first epitaxial structure, the second epitaxial structure, and the first gate structure. In some embodiments, the method further includes: removing portions of the second dielectric material and the second epitaxial structure to form a second opening exposing the second source / drain structure; and filling the second opening with a conductive material to form a conductive member. In some embodiments, the method further includes: removing portions of the second dielectric material and the second epitaxial structure to form a second opening exposing the second source / drain structure; conformally forming a pad layer in the second opening and along the inner sidewall of the second dielectric material; and filling the second opening with a conductive material to form a conductive member. In some embodiments, the method further includes: forming a hole by removing the bottommost one of the second sheets exposed by the first opening, wherein the first dielectric material further fills the hole.

[0091] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate including a first surface and a second surface opposite to the first surface; forming an isolation structure above the first surface; forming a first stacked structure and a second stacked structure protruding from the first surface, wherein the first stacked structure includes a first sacrificial layer and a first channel layer alternately arranged with the first sacrificial layer, and the second stacked structure includes a second sacrificial layer and a second channel layer alternately arranged with the second sacrificial layer; forming a first epitaxial structure and a second epitaxial structure in a recess of the substrate on opposite sides of the first stacked structure, wherein the first epitaxial structure is located between the first stacked structure and the second stacked structure, and portions of the first epitaxial structure and the second epitaxial structure are suspended above the isolation structure; forming a first source / drain epitaxial structure above the first epitaxial structure, and A second source / drain epitaxial structure is formed above the second epitaxial structure; the upper portions of the first source / drain epitaxial structure and the second source / drain epitaxial structure are converted into metal silicides; source / drain contacts electrically coupled to the first source / drain epitaxial structure and the second source / drain epitaxial structure are formed on the corresponding metal silicides; the first sacrificial layer and the second sacrificial layer are replaced with a first dielectric layer and a conductive layer; a first opening is formed by etching the conductive layer closest to the second surface of the substrate and the first stack structure from the second surface, wherein the first opening is located between the first epitaxial structure and the second epitaxial structure; a second opening is formed through the first opening by etching through the bottommost channel layer in the first channel layer, wherein the second opening is connected to the first opening; and the first opening and the second opening are filled with a first dielectric material.

[0092] In some embodiments, the first opening exposes internal spacers of the conductive layer surrounding the first stacked structure. In some embodiments, forming the first opening includes using dry etching or reactive ion etching (RIE), and forming the second opening includes using wet etching, atomic layer etching (ALE), or lateral etching. In some embodiments, the first opening tapers gradually from the second surface to the first surface, and the second opening has a substantially uniform width. In some embodiments, the method further includes: removing the substrate; covering the first epitaxial structure, the second epitaxial structure, and the first dielectric material with a second dielectric material; removing portions of the second dielectric material and the second epitaxial structure to form a third opening; and filling the third opening with a conductive material to form a conductive member. In some embodiments, the conductive member is electrically connected to the second source / drain structure.

[0093] Some embodiments of this application provide a semiconductor structure, including: a first stacked structure including a first metal gate structure and a first channel layer alternately arranged with the first metal gate structure; a second stacked structure separated from the first stacked structure and including a second metal gate structure and a second channel layer alternately arranged with the second metal gate; a drain epitaxial structure and a source epitaxial structure disposed on opposite sides of the first stacked structure, wherein the drain epitaxial structure is located between the first stacked structure and the second stacked structure, and the source epitaxial structure is located on the side of the second stacked structure opposite to the drain epitaxial structure; a first contact etch stop layer and a second contact etch stop layer. The first contact etch stop layer is disposed above the drain epitaxial structure, and the second contact etch stop layer is disposed above the source epitaxial structure; a first dielectric layer and a second dielectric layer are disposed above the first contact etch stop layer and the second dielectric layer is disposed above the second contact etch stop layer; a drain contact extends through the first dielectric layer and is electrically coupled to the drain epitaxial structure; a source contact extends through the second dielectric layer and is electrically coupled to the source epitaxial structure, wherein the first stack structure has a first number of first channel layers, the second stack structure has a second number of second channel layers, and the first number is different from the second number.

[0094] In some embodiments, the first quantity is equal to the second quantity minus one. In some embodiments, the bottommost metal gate structure of the first metal gate structure is located at a level higher than the bottommost metal gate structure of the second metal gate structure. In some embodiments, the semiconductor structure further includes: a conductive member electrically connected from the side of the bottommost metal gate structure of the first metal gate structure to the source structure. In some embodiments, the semiconductor structure further includes: a third dielectric layer covering the bottommost metal gate structure of the first metal gate structure and laterally surrounding the conductive member; and a fourth dielectric layer covering the third dielectric layer and laterally surrounding the conductive member.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A substrate is provided that includes a first surface and a second surface opposite to the first surface; An isolation region is formed above the first surface, wherein the isolation region comprises an insulating material having a dielectric constant between 3 and 5; A first stacked structure and a second stacked structure are formed protruding from the first surface, wherein the first stacked structure includes a plurality of first pieces, and the second stacked structure includes a plurality of second pieces; A first gate structure and a second gate structure are formed above the first stacked structure and the second stacked structure, wherein the first gate structure and the second gate structure respectively enclose the plurality of first wafers and the plurality of second wafers; A first epitaxial structure and a second epitaxial structure are formed in a groove in the substrate on opposite sides of the second stacked structure; An etch stop layer is formed above the corresponding first epitaxial structure and second epitaxial structure; A dielectric layer is formed above the corresponding etch stop layer; A first opening is formed by recessing the substrate from the second surface; and The first opening is filled with the first dielectric material.

2. The method according to claim 1, further comprising: A first source / drain epitaxial structure and a second source / drain epitaxial structure are formed above the first epitaxial structure and the second epitaxial structure, respectively, wherein the first source / drain epitaxial structure and the second source / drain epitaxial structure are connected to the sidewall of the second wafer.

3. The method according to claim 2, wherein, The first opening is located between the first epitaxial structure and the second epitaxial structure.

4. The method according to claim 2, wherein, The first opening is separated from the first source / drain epitaxial structure and the second source / drain epitaxial structure.

5. The method according to claim 2, further comprising: The substrate is removed to expose at least the first epitaxial structure, the second epitaxial structure, and the first gate structure.

6. The method according to claim 5, further comprising: A second dielectric material is deposited to cover the first epitaxial structure, the second epitaxial structure, and the first gate structure.

7. The method of claim 6, further comprising: Remove portions of the second dielectric material and the second epitaxial structure to form a second opening that exposes the second source / drain structure; as well as The second opening is filled with a conductive material to form a conductive component.

8. The method according to claim 7, further comprising: Remove portions of the second dielectric material and the second epitaxial structure to form a second opening that exposes the second source / drain structure; A liner layer is conformally formed in the second opening and along the inner sidewall of the second dielectric material; as well as The second opening is filled with a conductive material to form a conductive component.

9. A method for forming a semiconductor structure, comprising: A substrate is provided that includes a first surface and a second surface opposite to the first surface; An isolation structure is formed above the first surface; A first stack structure and a second stack structure protruding from the first surface are formed, wherein the first stack structure includes a first sacrificial layer and a first channel layer arranged alternately with the first sacrificial layer, and the second stack structure includes a second sacrificial layer and a second channel layer arranged alternately with the second sacrificial layer. A first epitaxial structure and a second epitaxial structure are formed in a groove of the substrate on opposite sides of the first stacked structure, wherein the first epitaxial structure is located between the first stacked structure and the second stacked structure, and portions of the first epitaxial structure and the second epitaxial structure are suspended above the isolation structure. A first source / drain epitaxial structure is formed above the first epitaxial structure, and a second source / drain epitaxial structure is formed above the second epitaxial structure; The upper portions of the first source / drain epitaxial structure and the second source / drain epitaxial structure are converted into metal silicides; Source / drain contacts are formed on the corresponding metal silicides and electrically coupled to the first source / drain epitaxial structure and the second source / drain epitaxial structure, respectively; The first sacrificial layer and the second sacrificial layer are replaced with a first dielectric layer and a conductive layer; A first opening is formed by etching the conductive layer of the substrate and the first stack structure closest to the second surface from the second surface, wherein the first opening is located between the first epitaxial structure and the second epitaxial structure; A second opening is formed through the first opening by etching through the bottommost trench layer in the first trench layer, wherein the second opening is connected to the first opening; and The first opening and the second opening are filled with a first dielectric material.

10. A semiconductor structure, comprising: The first stacked structure includes a first metal gate structure and a first channel layer arranged alternately with the first metal gate structure; The second stacked structure is separated from the first stacked structure and includes a second metal gate structure and a second channel layer arranged alternately with the second metal gate. A drain epitaxial structure and a source epitaxial structure are disposed on opposite sides of the first stacked structure, wherein the drain epitaxial structure is located between the first stacked structure and the second stacked structure, and the source epitaxial structure is located on the side of the second stacked structure opposite to the drain epitaxial structure. A first contact etch stop layer and a second contact etch stop layer are disposed above the drain epitaxial structure and the second contact etch stop layer is disposed above the source epitaxial structure. A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed above the first contact etch stop layer, and the second dielectric layer is disposed above the second contact etch stop layer; A drain contact extends through the first dielectric layer and is electrically coupled to the drain epitaxial structure; A source contact extends through the second dielectric layer and is electrically coupled to the source epitaxial structure, wherein... The first stacked structure has a first number of first channel layers. The second stacked structure has a second number of second channel layers, and The first quantity is different from the second quantity.

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