A method for growing gallium nitride heterojunction based on silicon carbide substrate and products

Abstract

The application discloses a kind of based on silicon carbide substrate growth gallium nitride heterojunction epitaxial method and product, belong to semiconductor device technical field.The method includes: by high temperature pyrolysis process and form single layer or double layer graphene on semi-insulating 4H-SiC substrate surface;After forming hexagonal hole array by patterning, N ion implantation is carried out to control the surface energy of SiC in hole, and then etching is carried out to remove implantation damage layer and mask;Subsequently, graphene is fluorinated into high resistance fluorinated graphene, and finally AlN nucleation layer and GaN channel layer are epitaxially grown.AlN is preferentially nucleated on the SiC surface in the hole, and fast lateral merging is realized by means of the low migration barrier of fluorinated graphene surface, obtaining a high-quality flat AlN nucleation layer at a relatively thin thickness, thereby the traditional GaN buffer layer can be cancelled, the epitaxial structure is simplified, and the crystal quality and device performance are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an epitaxial method for growing gallium nitride heterojunctions on silicon carbide substrates. Background Technology

[0002] AlGaN / GaN high electron mobility transistors (HEMTs), with their wide bandgap, high breakdown electric field, high saturation electron drift velocity, and excellent two-dimensional electron gas transport characteristics, have become core devices for next-generation high-frequency, high-power microwave applications, demonstrating irreplaceable application value in fields such as 5G / 6G communication base stations, satellite communication payloads, and military phased array radar. Limited by the size and cost bottlenecks of GaN single-crystal substrates, heteroepitaxial technology remains the mainstream route for current industrialization. Among candidate substrates such as sapphire, silicon, and silicon carbide, the semi-insulating 4H-SiC substrate is recognized as the optimal substrate for fabricating high-performance GaN HEMTs due to its high thermal conductivity, high resistivity, and relatively small lattice mismatch with GaN, and has already achieved large-scale mass production of 6-inch and even 8-inch wafers.

[0003] Metal-organic chemical vapor deposition (MOCVD), as the mainstream industrial technology for epitaxial growth of group III nitride semiconductors, dominates the fabrication of GaN-based devices due to its large-area uniformity, high growth rate, and precise composition and thickness control. Epitaxial growth of GaN-based HEMT structures on 4H-SiC substrates typically involves complex multilayer heteroepitaxial processes, with the core objective of achieving high mobility and high areal density two-dimensional electron gas channels while controlling defect density. Due to the significant lattice mismatch and difference in thermal expansion coefficients between GaN and 4H-SiC, directly epitaxially growing GaN on the SiC surface will generate a high density of through-dislocations, severely degrading the breakdown characteristics and reliability of the device. Therefore, substrate surface treatment, nucleation layer design, and buffer layer optimization have become key technical aspects in this field.

[0004] Existing technical solutions mainly revolve around substrate pretreatment, low-temperature nucleation layers, high-temperature nucleation layers, and buffer layer structures. Regarding substrate pretreatment, the industry commonly uses high-temperature hydrogen annealing to remove surface oxides and impurities, or trimethylaluminum (TMAl) pre-lay technology to improve surface wettability. In recent years, some researchers have proposed using nitrogen ions (N... + Injecting nano- to micro-scale surface vacancies into the SiC surface introduces these vacancies as preferred nucleation sites for AlN, thereby suppressing the traditional island-like nucleation mode, promoting layered growth, achieving a flat AlN / SiC interface, and reducing the nucleation energy barrier.

[0005] In the nucleation layer technology route, low-temperature AlN or GaN nucleation layers (growth temperature 400-900°C) are used. oC, thickness typically 20-50nm) combined with high-temperature annealing process (>1000) o C) is the most mature solution for industrial application. Its advantages lie in its mature process and ability to effectively reduce lattice mismatch stress. However, point defects and interface states in the nucleation layer significantly affect the subsequent epitaxial quality. In contrast, high-temperature AlN nucleation layers (growth temperature > 1000°C) o (C, thickness 50-100 nm) Because the lattice mismatch between AlN and SiC is small (about 1%), higher crystal quality can be obtained and the leakage current of the buffer layer can be effectively suppressed, but higher requirements are placed on the uniformity of the thermal field and stress control of the equipment.

[0006] To further relieve stress and reduce the density of penetrating dislocations, researchers also developed graded-component Al... x Ga 1-x The N(x-gradient) buffer layer or AlN / AlGaN superlattice buffer layer structure achieves stress gradient relaxation by gradually adjusting the lattice constant. However, this scheme has a complex growth process, is difficult to control repeatability, and the additional number of interfaces may introduce thermal resistance, which is not conducive to the thermal management of the device under high frequency and high power conditions.

[0007] In recent years, remote epitaxy or van der Waals epitaxy based on two-dimensional materials has provided a new technical path for SiC-based GaN epitaxy. This technology utilizes two-dimensional materials such as graphene as a weak coupling interface between the SiC substrate and the epitaxial layer, theoretically significantly reducing dislocation density caused by lattice mismatch and endowing the epitaxial layer with peelable properties, thus enabling flexible electronics and heterogeneous integration applications. However, this technology still faces severe challenges: the atomic-level cleanliness and lattice orientation control of the epitaxial initiation interface are extremely demanding; the preparation and interface integration processes for large-area, high-quality graphene are not yet mature; the weak van der Waals coupling interface may introduce additional thermal resistance and electrical isolation problems; and the overall process cost is high and the yield is low. Currently, it is mainly in the laboratory research stage and is still significantly far from industrial application.

[0008] In summary, although significant progress has been made in SiC-based GaN epitaxy, simplifying the epitaxial structure, reducing thermal resistance, and improving process reliability while ensuring crystal quality remain pressing technical challenges. Particularly in high-performance microwave device applications, reducing epitaxial layer thickness, optimizing interface characteristics, and suppressing buffer layer leakage current are crucial for improving device frequency characteristics and power-added efficiency. Summary of the Invention

[0009] In view of the above, the purpose of this invention is to provide an epitaxial method and product for growing gallium nitride heterojunctions based on silicon carbide substrates. This method can obtain a flat AlN nucleation layer at a relatively thin thickness, eliminate the need for gallium nitride buffer layer epitaxy, improve epitaxial production efficiency, enhance the epitaxial quality of subsequent gallium nitride, and help improve the heat dissipation and voltage withstand performance of subsequent gallium nitride HEMT devices during operation.

[0010] To achieve the above-mentioned objectives, this invention provides an epitaxial growth method for gallium nitride heterojunctions based on silicon carbide substrates, comprising the following steps: Step 1: Take an uncut, horizontal, semi-insulating 4H-SiC substrate and form up to three layers of graphene on the surface of the 4H-SiC substrate through a high-temperature pyrolysis process; Step 2: The substrate obtained in Step 1 is patterned by using photolithography and a mask to form multiple periodically arranged hexagonal holes on the graphene surface. Step 3: Perform N-ion implantation on the substrate obtained in Step 2 to regulate the surface energy of the SiC surface within the hexagonal holes, thereby optimizing subsequent AlN nucleation. Step 4: Etch the substrate obtained in Step 3 to remove the implanted damage layer and expose the graphene and SiC surface inside the hexagonal holes, and remove the mask. Step 5: Fluoride the surface of the substrate obtained in Step 4 to convert the graphene into highly resistive fluorinated graphene. Step 6: Epitaxially grow an AlN nucleation layer on the substrate obtained in step 5. The AlN preferentially nucleates on the SiC surface within the hexagonal holes and laterally merges on the fluorinated graphene surface to form a continuous AlN nucleation layer. Step 7: Directly epitaxially grow a GaN channel layer on the AlN nucleation layer.

[0011] In step 1, the graphene formed on the surface of the 4H-SiC substrate by the high-temperature pyrolysis process can be a single layer, two layers, or three layers. If more than three layers of multilayer graphene are used, the film stress introduced during the subsequent epitaxial layer growth process will cause the epitaxial layer to detach from the graphene.

[0012] Preferably, the high-temperature pyrolysis process in step 1 employs a silicon background pressure method, including: at temperatures above 1500 °C... o Graphene is generated by thermal decomposition of SiC surface under temperature C and silicon background pressure, and then annealed in hydrogen atmosphere to allow hydrogen atoms to insert between the graphene and SiC substrate, transforming the covalently bonded graphene into a quasi-free state of up to three layers of graphene with weak van der Waals force. This method can effectively control the number of layers and obtain high mobility.

[0013] More preferably, the silicon background pressure method includes: placing the substrate in a high-temperature furnace and heating it to 1500-1600°C. o C, in 1×10 -6 -1×10 -5 Graphene is generated by thermal decomposition of SiC surface under a silicon background pressure of mbar; subsequently, it is annealed in a hydrogen atmosphere for 10-30 minutes at an annealing temperature of 900-1000 °C. o The flow rate of C and H2 is 100-200 sccm; the annealing process in this hydrogen atmosphere causes hydrogen atoms to insert between graphene and SiC, forming quasi-free monolayer or bilayer graphene.

[0014] More preferably, the high-temperature pyrolysis process employs an ultra-high vacuum direct pyrolysis method, comprising: placing the substrate under a pressure below 1×10⁻⁶. -4 In an ultra-high vacuum environment of Pa, the temperature is raised to 1200-1500 Pa. o At C, hold at a temperature of 5-20 minutes to anneal the SiC substrate at high temperature, thereby directly graphitizing its surface to form up to three layers of graphene.

[0015] More preferably, the pressure in the ultra-high vacuum chamber of the ultra-high vacuum direct pyrolysis method is lower than 1×10⁻⁶. -5 Pa, pyrolysis temperature is 1400 o C.

[0016] In step 2, the graphene surface obtained in step 1 is patterned using photolithography, and a mask layer (such as Ni or SiO2) with a thickness of 50-200 nm is deposited. Subsequently, reactive ion etching (RIE) or inductively coupled plasma etching (ICP) is used to form periodically arranged hexagonal holes on the graphene surface. The etching gas is an SF6 / O2 mixture with a flow ratio of 10:1-20:1, a power of 50-150 W, and a time of 30-120 s.

[0017] Preferably, the diameter of the hexagonal holes in step 2 is 0.5-1 μm, the center-to-center spacing between adjacent hexagonal holes is 1.0-1.5 μm, and a set of opposite sides of the hexagonal holes are parallel to the [11-20] crystal orientation of the SiC substrate. Hexagonal holes help optimize the growth orientation of the AlN nucleation layer. The diameter of the hexagonal holes has a regulatory effect on the size of the AlN nucleation islands. When the hole diameter is too large, the lateral growth time of AlN after nucleation within the hole is insufficient, making it difficult to form high-quality hexagonal AlN nucleation islands; when the hole diameter is too small, the nucleation islands are too small and too densely distributed, resulting in more grain boundaries during subsequent merging. Similarly, too small a hole spacing leads to an excessively fast lateral merging rate, preventing the crystal planes between nucleation islands from completing orientation twisting in time, and excessively dense spacing also introduces more grain boundaries during the merging stage; while too large a hole spacing results in insufficient lateral growth time for AlN, making it difficult to achieve effective merging of nucleation islands.

[0018] Preferably, in step 3, during N ion implantation, the implantation energy is 40-60 keV and the implantation dose is 5 × 10⁻⁶. 16 cm -2 The injection angle is deviated from the normal by 6-8° to reduce the channeling effect, and the injection temperature is room temperature or 300-500°C. o C. High-temperature implantation can reduce the accumulation of lattice damage.

[0019] Nitrogen ion implantation disrupts the ordered lattice of the substrate surface through high-energy bombardment, forming an amorphous layer and introducing a large number of nitrogen atoms. These nitrogen atoms combine with dangling bonds on the substrate surface in subsequent steps to form more stable nitrides (such as AlN), effectively saturating unsaturated bonds. This chemical passivation significantly reduces the residual bond energy and atomic activity on the surface, thereby lowering the overall surface free energy and providing a more favorable low-energy nucleation interface for epitaxy.

[0020] Preferably, in step 4, ICP dry etching is used, and the gas is a mixture of Cl2 / BCl3 or SF6 / Ar, wherein the flow ratio of Cl2:BCl3 is 10:1-5:1, the flow ratio of SF6 / Ar is 1:2-2:1, the total flow rate is 50-100 sccm, and the etching time is 1-5 minutes, with the specific time depending on the removal of about 5-20 nm of damage layer.

[0021] In step 4, the etching process introduces a large number of dangling bonds into the SiC surface. Specifically, the etching process removes atoms from the SiC surface through physical or chemical action, breaking the existing Si-C covalent bonds. Each removed atom leaves an unpaired electron on the surface, i.e., a dangling bond. For example, ion bombardment or chemical reactions (such as fluorine-based gases) in plasma etching preferentially remove Si or C atoms, disrupting lattice integrity and exposing a large number of unsaturated dangling bonds.

[0022] Preferably, the fluorination treatment in step 5 can be performed using any of the following methods: XeF2 gas-phase fluorination, i.e., placing the substrate in XeF2 vapor at room temperature, pressure 1-10 Torr, reaction time 15 minutes. Fluorination induces graphene to transform into a high-resistivity state. The surface of high-resistivity fluorinated graphene lacks dangling bonds, thereby suppressing interface leakage that may be caused by the presence of the graphene layer in subsequent devices; or CF4 plasma treatment, i.e., using RIE equipment, CF4 flow rate 50-100 sccm, power 50-150 W, treatment time 30-120 s; or F ion implantation, implantation energy 5-20 keV, dose 1×10 14 -1×10 16 cm -2 The injection temperature is from room temperature to 400℃.

[0023] Preferably, in step 6, the growth temperature is 1000-1100℃. o C, the reaction chamber pressure is 50-200 mbar; the aluminum source flow rate is 50-200 µmol / min, and the aluminum source is preferably trimethylaluminum; the nitrogen source flow rate is 1000-3000 sccm, and the nitrogen source is preferably ammonia; the growth time is 5-15 minutes.

[0024] Preferably, the thickness of the AlN nucleation layer in step 6 is 30-80 nm. Compared to highly resistive fluorinated graphene lacking dangling bonds on its surface, AlN preferentially nucleates on the SiC surface within hexagonal pores where the surface energy is modulated by N ion implantation and dangling bonds are increased by etching. After nucleation, the absence of dangling bonds on the surface of the highly resistive fluorinated graphene significantly reduces the migration barrier of Al atoms on the substrate surface. Therefore, lateral merging between AlN islands can be promoted at a relatively thin thickness of 30-80 nm and a relatively low temperature below 1100 °C, thereby obtaining a high-quality AlN nucleation layer with a smooth surface.

[0025] Preferably, in step 7, the growth temperature is 1000-1100℃. o C, the reaction chamber pressure is 100-300 mbar; the gallium source is preferably trimethylgallium, with a gallium source flow rate of 100-400 µmol / min; the nitrogen source is preferably NH3, with a nitrogen source flow rate of 2000-5000 sccm, and the growth time is 5-30 min.

[0026] Preferably, the epitaxial thickness of the GaN channel layer in step 7 can be as low as 50 nm. Since a flat and high-quality AlN nucleation layer is obtained in step 6, effectively alleviating lattice mismatch, there is no need for an epitaxial GaN buffer layer for transition. The GaN channel layer can be directly epitaxially grown on the AlN nucleation layer, and a flat surface can be obtained with a minimum thickness of only 50 nm.

[0027] Furthermore, based on step 7, additional epitaxy layers such as insertion layers, barrier layers, and capping layers can be added, which is no different from conventional methods and will not be limited here.

[0028] To achieve the above-mentioned objectives, this invention also provides a gallium nitride heterojunction, which is grown by the epitaxial method described above.

[0029] Compared with the prior art, the beneficial effects of the present invention include at least the following: This invention successfully manages the nucleation mode of AlN on the silicon carbide surface through patterning of graphene on the SiC substrate surface, selective N ion implantation, and etching processes, achieving precise control over AlN nucleation sites. Through patterned ion implantation and etching, due to the lack of dangling bonds on the graphene surface, AlN preferentially nucleates on the SiC surface within the hexagonal pores treated by ion implantation and etching, thereby precisely controlling the nucleation density, grain size, and grain orientation consistency. After nucleation, the low transition barrier of Al atoms on the graphite surface facilitates the rapid merging of AlN nucleation islands, resulting in a flat AlN nucleation layer with a relatively thin thickness (30-80 nm). This eliminates the need for gallium nitride buffer layer epitaxy, improving epitaxial production efficiency and enhancing the subsequent gallium nitride epitaxial quality. Furthermore, the reduction in the transition buffer layer helps improve the heat dissipation effect during the subsequent fabrication of gallium nitride HEMT devices. Furthermore, by reducing the buffer layer, the conventional gallium nitride buffer layer, which requires doping with Fe and C to achieve high resistance as in traditional processes, is avoided. However, this process still introduces stress dislocations and has some impact on the breakdown voltage. Therefore, it also helps to improve the breakdown voltage capability of HEMTs. At the same time, the use of fluorinated graphene further reduces the interface leakage current that may be caused by the graphene layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of the epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate provided in the embodiment; Figure 2 These are the surface rocking curves provided in Example 1, where (a) is the surface rocking curve of GaN (002) and (b) is the surface rocking curve of GaN (102). Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of this invention.

[0033] The inventive concept of this invention is to achieve low-temperature, thin-layer growth of high-quality AlN nucleation layers by constructing a selective nucleation-rapid lateral merging epitaxial growth mechanism on the surface of a semi-insulating 4H-SiC substrate. This eliminates the need for a traditional GaN buffer layer, simplifies the epitaxial structure of GaN-based HEMTs, and improves the device's breakdown voltage and heat dissipation performance, thereby further enhancing the device's operating performance.

[0034] Figure 1 This is a flowchart of an epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate, as provided in the embodiments, including the following steps: Step 1: Take an un-slanted, horizontally semi-insulating 4H-SiC substrate and form a single layer or few layers (≤3 layers) of graphene on its surface through a high-temperature pyrolysis process. The high-temperature pyrolysis process includes silicon background pressure method and ultra-high vacuum direct pyrolysis method.

[0035] Step 2: The graphene surface obtained in Step 1 is patterned using photolithography, and a mask layer (such as Ni or SiO2) is deposited. Subsequently, hexagonal holes arranged periodically are formed on the graphene surface using reactive ion etching (RIE) or inductively coupled plasma etching (ICP).

[0036] Step 3: Perform N-ion implantation on the substrate obtained in Step 2, and modify only the SiC surface exposed in the hexagonal holes to regulate its surface energy.

[0037] Step 4: Etch the substrate obtained in Step 3 to remove the implanted damage layer and expose the graphene and SiC surface inside the hexagonal holes, while removing the mask layer.

[0038] Step 5: Fluoride the surface of the substrate obtained in Step 4 to convert the graphene into highly resistive fluorinated graphene. Step 6: The fluorinated substrate obtained in step 5 is placed in an MOCVD reaction chamber to epitaxially grow an AlN nucleation layer. AlN preferentially nucleates on the SiC surface within the hexagonal pores and laterally merges on the fluorinated graphene surface to form a continuous nucleation layer.

[0039] Step 7: Directly epitaxially grow a GaN channel layer on the AlN nucleation layer without introducing an additional GaN buffer layer. Based on the above-described extensional method, the following embodiments are provided. Example 1 Step 1 employs a high-temperature pyrolysis process based on silicon background pressure, wherein the temperature is raised to 1500°C. o C, in 5×10 -6 Graphene was generated by thermal decomposition of SiC surface under a silicon background pressure of mbar; subsequently, it was annealed for 15 minutes in a hydrogen atmosphere at a temperature of 950°C. o With a C and H2 flow rate of 150 sccm, monolayer graphene was obtained.

[0040] In step 2, a 100 nm thick SiO2 mask layer is deposited, and periodically arranged hexagonal holes are formed on the surface of the RIE graphene. The etching gas is an SF6 / O2 mixture with a flow ratio of 15:1, a power of 100 W, and a time of 60 s. The diameter of the resulting hexagonal holes is 0.5 μm, the center-to-center spacing of adjacent hexagonal holes is 1.0 μm, and a set of opposite sides of the hexagonal holes are parallel to the [11-20] crystal orientation of the SiC substrate.

[0041] In step 3, during N ion implantation, the implantation energy is 50 keV and the implantation dose is 5 × 10⁻⁶. 16 cm -2 The injection angle deviates from the normal by 7 degrees. o To reduce the channeling effect, the injection temperature is room temperature.

[0042] In step 4, ICP dry etching is used, with Cl2 / BCl3 as the gas, where the Cl2:BCl3 flow ratio is 10:1, the total flow rate is 50 sccm, and the etching time is 2 minutes.

[0043] Step 5 involves gas-phase fluorination with XeF2 under the following conditions: room temperature (25°C). o C), XeF2 vapor pressure 5 Torr, reaction time 15 minutes.

[0044] In step 6, the growth temperature for epitaxially growing the AlN nucleation layer is 1050 °C. o C, reaction chamber pressure is 100 mbar; aluminum source is trimethylaluminum, flow rate is 100 µmol / min; nitrogen source is ammonia, flow rate is 2000 sccm, growth time is 10 minutes.

[0045] In step 7, GaN channel layers are directly epitaxially grown on the AlN nucleation layer at a growth temperature of 1050 °C. o C, reaction chamber pressure was 200 mbar; gallium source was trimethylgallium with a flow rate of 200 µmol / min; nitrogen source was NH3 with a flow rate of 3000 sccm; growth time was 15 min.

[0046] Furthermore, the GaN channel layer described above was fabricated into a HEMT structure (i.e., a GaN HEMT structure), wherein the GaN channel layer thickness was only 300 nm, such as... Figure 2 As shown, the full width at half maximum (FWHM) of the GaN(002) surface X-ray diffraction (XRD) is reduced from 200 arcsec to 70 arcsec in the conventional structure, and the FWHM of the GaN(102) surface is reduced from 350 arcsec to 270 arcsec, resulting in a significant reduction in dislocation density; the root mean square roughness of the surface is less than 0.3 nm, and the device breakdown voltage is improved by 50% compared with the conventional structure.

[0047] Example 2 The difference between Example 2 and Example 1 lies in steps 1, 5, and 6; the remaining steps are the same as in Example 1.

[0048] In step 1, graphene is prepared using an ultra-high vacuum direct pyrolysis method. Specifically, the 4H-SiC substrate is placed under a pressure of 5 × 10⁻⁶. -5 In an ultra-high vacuum chamber with a pressure of Pa, the temperature is raised to 1400°C and held for 10 minutes. Through high-temperature annealing, the SiC surface is directly graphitized to form bilayer graphene. In step 5, CF4 plasma fluorination is used, specifically with RIE equipment, CF4 flow rate 80 sccm, power 100 W, and processing time 60 s; In step 6, the growth temperature is 1020°C (slightly lower than in Example 1), and the other parameters are the same.

[0049] The GaN channel layer prepared in Example 2 has the following performance: GaN(002) half width at half maximum (WHM) of 75 arcsec, (102) half width at half maximum (WHM) of 280 arcsec, and surface roughness of 0.2 nm, which is 45% higher than that of conventional methods.

[0050] Example 3 The difference between Example 3 and Example 1 lies in the AlN growth time and thickness in steps 5 and 6, while the remaining steps are the same as in Example 1.

[0051] In step 5, F ions are implanted for fluorination, with a specific implantation energy of 10 keV and an implantation dose of 1×10⁻⁶. 15 cm -2 Injection temperature: room temperature (25°C); In step 6: the growth temperature was 1080°C, the reaction chamber pressure was 100 mbar, the TMAl flow rate was 120 µmol / min, the NH3 flow rate was 2500 sccm, and the growth time was 6 minutes, resulting in an AlN nucleation layer with a target thickness of approximately 40 nm, which is thinner than that in Example 1.

[0052] The GaN channel layer prepared in Example 3 exhibits the following performance characteristics: GaN(002) half-width at half-maximum (WHM) of 72 arcsec, (102) half-width at half-maximum (WHM) of 285 arcsec, and surface roughness of 0.2 nm, representing a 50% improvement over conventional methods. The thinner AlN layer further reduces thermal resistance and enhances heat dissipation performance.

[0053] Example 4 The difference between this embodiment and Embodiment 1 lies in the injection temperature in step 3 and the growth time in step 6.

[0054] Step 3 employs high-temperature N-ion implantation, specifically with an implantation energy of 50 keV and a dose of 5 × 10⁻⁶. 16 cm -2 The injection angle deviates from the normal by 7°, and the injection temperature is 400°C. High-temperature injection can reduce the accumulation of lattice damage. In step 6, the growth temperature was 1050°C, the reaction chamber pressure was 100 mbar, the TMAl flow rate was 100 µmol / min, the NH3 flow rate was 2000 sccm, and the growth time was 14 minutes, forming an AlN nucleation layer with a target thickness of about 70 nm, and the lateral merging was more complete.

[0055] The GaN channel layer prepared in Example 4 exhibits the following performance characteristics: GaN(002) half-width at half-maximum (WHM) of 70 arcsec, (102) half-width at half-maximum (WHM) of 270 arcsec, and surface roughness of 0.20 nm, representing a 50% improvement over conventional methods. Optimal crystal quality was achieved through high-temperature implantation combined with a thicker AlN nucleation layer.

[0056] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An epitaxial method for growing gallium nitride heterojunctions on silicon carbide substrates, characterized in that, Includes the following steps: Step 1: Take a semi-insulating 4H-SiC substrate and form up to three layers of graphene on the surface of the 4H-SiC substrate through a high-temperature pyrolysis process; Step 2: Pattern the substrate obtained in Step 1 by using photolithography and masking to form multiple periodically arranged hexagonal holes on the graphene surface of the substrate. Step 3: Perform N-ion implantation on the substrate obtained in Step 2 to modulate the surface energy of the SiC surface within the hexagonal holes; Step 4: Etch the substrate obtained in Step 3 to remove the implanted damage layer and expose the graphene and SiC surface inside the hexagonal holes, and remove the mask. Step 5: Fluoride the surface of the substrate obtained in Step 4 to convert the graphene into highly resistive fluorinated graphene. Step 6: Epitaxially grow an AlN nucleation layer on the substrate obtained in step 5. The AlN preferentially nucleates on the SiC surface within the hexagonal holes and laterally merges on the fluorinated graphene surface to form a continuous AlN nucleation layer. Step 7: Directly epitaxially grow a GaN channel layer on the AlN nucleation layer.

2. The epitaxial growth method for gallium nitride heterojunctions based on a silicon carbide substrate according to claim 1, characterized in that, The high-temperature pyrolysis process described in step 1 uses a silicon background pressure method, which includes: placing the substrate in a high-temperature environment and heating it to 1500-1600°C. o C, in 1×10 -6 -1×10 -5 Graphene is generated by thermal decomposition of SiC surface under a silicon background pressure of mbar; subsequently, it is annealed in a hydrogen atmosphere for 10-30 minutes at an annealing temperature of 900-1000 °C. o C and H2 flow rates are 100-200 sccm.

3. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, The high-temperature pyrolysis process described in step 1 employs an ultra-high vacuum direct pyrolysis method, including: placing the substrate under a pressure lower than 1×10⁻⁶. -4 In an ultra-high vacuum environment of Pa, the temperature is raised to 1200-1500 Pa. o At C, hold at a temperature of 5-20 minutes to anneal the SiC substrate at high temperature, thereby directly graphitizing its surface to form up to three layers of graphene.

4. The epitaxial method for growing gallium nitride heterojunctions based on a silicon carbide substrate according to claim 1, characterized in that, The diameter of the hexagonal hole in step 2 is 0.5-1 μm, the center-to-center spacing of adjacent hexagonal holes is 1.0-1.5 μm, and a set of opposite sides of the hexagonal hole is parallel to the [11-20] crystal orientation of the SiC substrate.

5. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, In step 3, during N ion implantation, the implantation energy is 40-60 keV and the implantation dose is 5 × 10⁻⁶. 16 cm -2 The injection angle should deviate from the normal by 6-8°, and the injection temperature should be room temperature or 300-500°C. o C.

6. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, In step 4, ICP dry etching is used, with Cl2 / BCl3 or SF6 / Ar mixed gas. The flow ratio of Cl2:BCl3 is 10:1-5:1, the flow ratio of SF6 / Ar is 1:2-2:1, the total flow rate is 50-100 sccm, and the etching time is based on removing 5-20 nm of damage layer.

7. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, The fluorination treatment in step 5 can be carried out by any of the following methods: gas-phase fluorination of XeF2, at room temperature in XeF2 vapor, pressure 1-10 Torr, reaction time 15 minutes; Alternatively, CF4 plasma treatment can be used, with a CF4 flow rate of 50-100 sccm, a power of 50-150 W, and a treatment time of 30-120 s. Alternatively, F ion implantation can be performed at an implantation energy of 5-20 keV and a dose of 1×10⁻⁶. 14 -1×10 16 cm -2 The injection temperature is from room temperature to 400℃.

8. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, In step 6, the growth temperature is 1000-1100℃. o C, reaction chamber pressure 50-200 mbar; aluminum source flow rate 50-200 µmol / min; nitrogen source flow rate 1000-3000 sccm; growth time 5-15 minutes; The thickness of the AlN nucleation layer is 30-80 nm.

9. The epitaxial method for growing gallium nitride heterojunctions on a silicon carbide substrate according to claim 1, characterized in that, In step 7, the growth temperature is 1000-1100℃. o C, reaction chamber pressure 100-300 mbar; gallium source flow rate 100-400 µmol / min; nitrogen source flow rate 2000-5000 sccm; growth time 5-30 min; The epitaxial thickness of the GaN channel layer is at least 50 nm.

10. A gallium nitride heterojunction, characterized in that, The gallium nitride heterojunction is grown by the epitaxial method described in any one of claims 1-9.

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