Semiconductor device, integrated circuit, and electronic device

Abstract

The application provides a semiconductor device, an integrated circuit and an electronic device, and belongs to the technical field of semiconductors. The semiconductor device comprises a first III-V transistor, a second III-V transistor and a substrate. The substrate comprises a first doped layer and a second doped layer, the first doped layer is of a first doping type, and the second doped layer is of a second doping type. The first III-V transistor is arranged on a first surface of the first doped layer, and the second III-V transistor is arranged on the second doped layer. An interface between the first doped layer and the second doped layer forms a PN junction, and no leakage current occurs between the first III-V transistor and the second III-V transistor. A periphery of the first surface surrounds a normal projection of the first III-V transistor on the substrate, so that no leakage current occurs between the first III-V transistor and the second doped layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, integrated circuit, and electronic device. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) are a new generation of power semiconductor devices. GaNHEMTs, thanks to their excellent high-frequency characteristics, are well-suited for applications such as power switches. A common circuit topology in power switches is a half-bridge circuit with two HEMTs connected in series. To reduce the size and cost of the half-bridge circuit, the two HEMTs are typically integrated on a single substrate. One of the two HEMTs can be a high-side HEMT, and the other a low-side HEMT. The high-side HEMT is electrically connected to the power supply, and the low-side HEMT is electrically connected to ground.

[0003] However, when the high-side HEMT is turned on, leakage current is likely to occur between the high-side HEMT and the low-side HEMT due to the difference in potential between them, which can cause the half-bridge circuit to malfunction. Summary of the Invention

[0004] This application provides a semiconductor device, integrated circuit, and electronic device designed to solve the problem of leakage current easily occurring between a high-side HEMT and a low-side HEMT.

[0005] In a first aspect, embodiments of this application provide a semiconductor device comprising a first III-V transistor, a second III-V transistor, and a substrate. The substrate includes a base, a first doped layer, and a second doped layer. The first and second doped layers are disposed on the base, with the second doped layer connected to the periphery of the first doped layer. The first doped layer includes a first surface facing away from the base, and the second doped layer includes a second surface facing away from the base. The first doped layer is of a first doping type, and the second doped layer is of a second doping type. The first III-V transistor is disposed on the first surface, and the second III-V transistor is disposed on the second surface. A trench is formed between the first and second III-V transistors, located above the transition region at the boundary between the first and second doped layers. The periphery of the first surface, in its orthographic projection onto the base, surrounds the orthographic projection of the first III-V transistor onto the base.

[0006] A PN junction is formed at the boundary between the first and second doped layers. During semiconductor device operation, this PN junction is reverse-biased, and no current flows between the first and second doped layers. Therefore, no leakage current occurs between the first and second III-V transistors, allowing the semiconductor device to function normally. Furthermore, the projection of the periphery of the first surface onto the substrate surrounds the projection of the first III-V transistor onto the substrate; that is, the first III-V transistor does not cover the periphery of the first surface, preventing leakage current between the first III-V transistor and the second doped layer that would otherwise occur due to direct connection between the first III-V transistor and the second doped layer.

[0007] In one embodiment, the first doped layer is a well region, and the second doped layer is an epitaxial layer. The first doped layer is formed by implanting ions into the second doped layer. The periphery of the first doped layer has a first variable doping region, where the doping concentration decreases in the direction from the first doped layer to the second doped layer. The first variable doping region is of a first doping type. If the potential difference between the first doped layer and the second doped layer is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken down. Therefore, by forming the second variable doping region around the periphery of the first doped layer, the second variable doping region increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0008] In an exemplary embodiment, the semiconductor device further includes a dielectric layer disposed above the transition region. The semiconductor device also includes a field plate disposed above the dielectric layer and located in the trench. The dielectric layer further serves to insulate the field plate from the second doped layer. The field plate extends the PN junction beneath it, i.e., the field plate increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0009] In an exemplary embodiment, the orthographic projection of the field plate onto the substrate coincides with the orthographic projection of the first variable-doped region onto the substrate, and the orthographic projection of the periphery of the field plate onto the substrate coincides with the orthographic projection of the first variable-doped region onto the substrate, or the periphery of the field plate protrudes beyond the periphery of the first variable-doped region. The combination of the field plate and the first variable-doped region significantly increases the reverse breakdown voltage of the PN junction, thereby greatly improving the breakdown voltage of the semiconductor device.

[0010] In an exemplary embodiment, the first doped layer is a well region, and the second doped layer is an epitaxial layer. The first doped layer is formed by implanting ions into the second doped layer. The substrate further includes at least one first guard ring, which is disposed within the second doped layer and surrounds the periphery of the first doped layer, spaced apart from the first doped layer. The first guard ring is of a first doping type. If the potential difference between the first doped layer and the second doped layer is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken. Therefore, by forming at least one first guard ring on the periphery of the first doped layer, the first guard ring increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0011] In an exemplary embodiment, the field plate is located above each of the first guard rings and spaced apart from each of the first guard rings by a dielectric layer. The periphery of the field plate protrudes from the periphery of the first guard ring furthest from the first doped layer, further expanding the width of the PN junction around the first guard ring. The combination of the field plate and the first guard rings significantly increases the reverse breakdown voltage of the PN junction, thereby greatly improving the breakdown voltage of the semiconductor device.

[0012] In another embodiment, the first doped layer is an epitaxial layer, and the second doped layer is a well region. The second doped layer is formed by implanting ions into the first doped layer. A second variable doping region is present at the periphery of the first doped layer, with the doping concentration increasing in the direction from the first doped layer to the second doped layer; the second variable doping region is a second doping type. If the potential difference between the first doped layer and the second doped layer is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken down. Therefore, by forming the second variable doping region at the periphery of the first doped layer, the second variable doping region increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0013] In an exemplary embodiment, the semiconductor device further includes a dielectric layer disposed at least on the first surface and the second surface. The semiconductor device also includes a field plate disposed above the dielectric layer and located in the trench. The field plate's orthographic projection onto the substrate coincides with the orthographic projection of the second variable-doped region onto the substrate, or the periphery of the field plate protrudes beyond the periphery of the second variable-doped region. The field plate extends the PN junction beneath it, with the periphery of the field plate located above the second variable-doped region or protruding beyond the periphery of the second variable-doped region. The field plate further expands the width of the PN junction around the periphery of the first doped layer. The combination of the field plate and the second variable-doped region significantly increases the reverse breakdown voltage of the PN junction, greatly improving the breakdown voltage of the semiconductor device.

[0014] In an exemplary embodiment, the first doped layer is an epitaxial layer, and the second doped layer is a well region. The substrate further includes at least one second guard ring, which is disposed within the first doped layer. The projection of each second guard ring onto the substrate is spaced apart from the projection of the first III-V transistor onto the substrate. The second guard ring is also spaced apart from the substrate, and the second guard ring is of a second doping type. The potential difference between the first doped layer and the second doped layer is greater than the reverse breakdown voltage of the PN junction, which would cause the PN junction to undergo reverse breakdown. Therefore, by forming at least one second guard ring within the first doped layer, the second guard ring increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0015] In an exemplary embodiment, the semiconductor device further includes a dielectric layer disposed above the transition region. The semiconductor device also includes a field plate disposed above the dielectric layer and located in the trench. The field plate is located above each of the second guard rings, and the periphery of the field plate protrudes beyond the periphery of the first doped layer. The combination of the field plate and the second guard rings significantly increases the reverse breakdown voltage of the PN junction, thereby greatly improving the breakdown voltage of the semiconductor device.

[0016] In an exemplary embodiment, to prevent the first doped layer from extending below the second semiconductor layer, a portion of the substrate is also formed with the second doped layer by an ion implantation process, wherein the depth of the second doped layer is greater than the depth of the first doped layer.

[0017] In one embodiment, the first III-V transistor includes a first semiconductor layer, a first gate, a first source, and a first drain. The first gate, the first source, and the first drain are disposed on a surface of the first semiconductor layer, and the surface of the first semiconductor layer opposite to the first gate is connected to the first surface. The semiconductor device further includes a first conductor disposed inside the first semiconductor layer, and the first conductor is connected to both the first source and the first doped layer. The first doped layer is electrically connected to the first source through the first conductor.

[0018] In one embodiment, the second III-V transistor includes a second semiconductor layer, a second gate, a second source, and a second drain. The second gate, the second source, and the second drain are disposed on a surface of the second semiconductor layer, and the surface of the second semiconductor layer opposite to the second gate is connected to the second surface. The semiconductor device further includes a second conductor disposed inside the second semiconductor layer, and the second conductor is connected to the second source and the second doped layer, respectively. The second doped layer is electrically connected to a ground terminal through the second conductor and the second source, eliminating the need for additional conductive elements to ground the second doped layer. This saves material, increases the integration density of the semiconductor device, and reduces the design complexity of the peripheral circuit. Furthermore, grounding the second doped layer can reduce parasitic effects and improve circuit stability and reliability. Moreover, by changing the potential of the second source, the potential of the second doped layer can be changed, achieving controllable substrate potential.

[0019] Secondly, embodiments of this application also provide a semiconductor device, the semiconductor device including a first III-V transistor, a second III-V transistor, and a substrate. The substrate includes a base and a doped layer, the base being connected to the periphery of the doped layer. The doped layer 38 includes a first top surface, and the base includes a second top surface, the first top surface and the second top surface having the same orientation. The doped layer is a well region, the doped layer is of a first doping type, and the base is of a second doping type. The first III-V transistor is disposed on the first top surface, the second III-V transistor is disposed on the second top surface, and a trench is formed between the first III-V transistor and the second III-V transistor, the trench being located above the transition region at the junction of the base and the doped layer. The periphery of the first top surface, in its orthographic projection onto the base, encloses the orthographic projection of the first III-V transistor onto the base. The periphery of the doped layer has a first variable doping region, the concentration of the first variable doping region decreasing from the doped layer toward the first variable doping region, the first variable doping region being of a first doping type. Therefore, a PN junction is formed at the interface between the first and second doped layers. When the semiconductor device is operating, this PN junction is reverse biased, and no current flows between the first and second doped layers. No leakage current occurs between the first and second III-V transistors, thus enabling the semiconductor device to function normally. Furthermore, by forming a first variable doping region around the periphery of the doped layers, the width of the PN junction is increased, thereby raising the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device.

[0020] In an exemplary embodiment, the semiconductor device further includes a dielectric layer disposed above the transition region. The semiconductor device also includes a field plate disposed above the dielectric layer and located in the trench. The orthographic projection of the field plate onto the substrate coincides with the orthographic projection of the first variable-doped region onto the substrate, and the orthographic projection of the periphery of the field plate onto the substrate coincides with the orthographic projection of the first variable-doped region onto the substrate, or the periphery of the field plate protrudes beyond the periphery of the first variable-doped region. The dielectric layer also serves to insulate the field plate from the second doped layer. The field plate extends the PN junction beneath it, i.e., the field plate increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device. The combination of the field plate and the first variable-doped region significantly increases the reverse breakdown voltage of the PN junction, greatly improving the breakdown voltage of the semiconductor device.

[0021] Thirdly, embodiments of this application also provide an integrated circuit, which includes an electronic device and the aforementioned semiconductor device, wherein the semiconductor device is electrically connected to the electronic device.

[0022] Fourthly, embodiments of this application also provide an electronic device, which includes a circuit board and the aforementioned integrated circuit, wherein the integrated circuit is disposed on the circuit board and connected to the circuit board. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0024] Figure 1 This is a schematic diagram of the structure of the first electronic device disclosed in the first embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the first embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the integrated circuit structure disclosed in the second embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the circuit structure of the semiconductor device disclosed in this application;

[0029] Figure 6 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0031] Figure 8 for Figure 7 A top view of the first III-V group transistor of the semiconductor device shown;

[0032] Figure 9 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0033] Figure 10 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0034] Figure 11 This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0035] Figure 12 This is a schematic diagram of the seventh layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0036] Figure 13 This is a schematic diagram of the eighth layer structure of the semiconductor device disclosed in the third embodiment of this application;

[0037] Figure 14 This is a schematic diagram of a layer structure of one type of first III-V group transistor disclosed in the embodiments of this application;

[0038] Figure 15 This is a schematic diagram of another type of layer structure of the first III-V group transistor disclosed in the embodiments of this application;

[0039] Figure 16 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0040] Figure 17 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0041] Figure 18 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0042] Figure 19 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0043] Figure 20 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0044] Figure 21 This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the fourth embodiment of this application;

[0045] Figure 22 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the fifth embodiment of this application;

[0046] Figure 23 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the fifth embodiment of this application;

[0047] Figure 24 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the fifth embodiment of this application;

[0048] Figure 25 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the fifth embodiment of this application;

[0049] Figure 26 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the fifth embodiment of this application;

[0050] Figure 27This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Detailed Implementation

[0051] In the description of the embodiments of this application, it is understood that, unless otherwise expressly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after the connection.

[0052] The directional terms mentioned in the embodiments of this application, such as "upper", "lower", "top", "bottom", "inner", "outer", "side", etc., are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0053] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature. The term "multiple" refers to at least two.

[0054] In the embodiments of this application, the terms "parallel," "perpendicular," and "aligned" are used in relation to the current technological level, rather than being absolutely strict mathematical definitions. Slight deviations are permissible; approximations of parallelism, perpendicularity, and alignment are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, with the angle between A and B ranging from 0° to 10°. Similarly, "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, with the angle between A and B ranging from 80° to 100°. Finally, "A and B are aligned" means that A and B are aligned or approximately aligned, with the alignment difference between A and B within 1 nm.

[0055] References to "some embodiments" and the like in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "some embodiments," "in other embodiments," and "in still other embodiments" appearing in different parts of this specification do not necessarily refer to the same embodiments, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically emphasized.

[0056] It is understood that the specific embodiments described herein are merely illustrative of related embodiments and not intended to limit the scope of those embodiments. It is also understood that, for ease of description, the accompanying drawings show only the parts relevant to the embodiments.

[0057] It is understood that, without conflict, the embodiments and features described in this application can be combined with each other.

[0058] The embodiments of this application are described below with reference to the accompanying drawings.

[0059] This application provides an electronic device, which can be a mobile phone, laptop computer, tablet computer, smart TV, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet, smart glasses), in-vehicle device, smart home device, smart city device, terminal device, and other electronic products. This application does not impose any special limitations on the specific type of this electronic device. Please refer to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the first electronic device disclosed in the first embodiment of this application. Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the first embodiment of this application. Figure 1 The electronic device shown is a mobile phone. Figure 2 The electronic device shown is a laptop computer.

[0060] Please see Figure 3 , Figure 3This is a schematic diagram of the integrated circuit structure disclosed in the second embodiment of this application. The aforementioned electronic device includes, but is not limited to, components such as integrated circuit 1, circuit board 2, and power module 3. Integrated circuit 1 is disposed on circuit board 2 and is electrically connected to circuit board 2 via pins. Circuit board 2 can also be electrically connected to an external power supply and power module 3, respectively.

[0061] Integrated circuit 1 is electrically connected to an external power source via circuit board 2, and is also electrically connected to power module 3 via circuit board 2. Integrated circuit 1 receives current from the external power source, rectifies and regulates the voltage of the current, and then outputs the current to power module 3 to supply power to power module 3. Integrated circuit 1 can be a power management chip, and power module 3 can be a display screen, radio frequency module, speaker, camera module, etc., without specific limitations in this application.

[0062] It should be noted that Integrated Circuit 1 can be applied to power transmission and distribution systems, providing low-voltage DC power to industrial equipment. Integrated Circuit 1 can be applied to communication equipment and information technology systems, providing stable power to wireless communication base stations, data centers, network switches, etc. Integrated Circuit 1 can be applied to industrial automation and control systems, providing stable low-voltage DC power to industrial automation equipment. Integrated Circuit 1 can be applied to medical equipment and systems, providing high-precision, low-noise, and low-leakage-current power. Integrated Circuit 1 can be applied to industrial robots and automation equipment, providing high-power, high-efficiency power. Integrated Circuit 1 can be applied to consumer electronics devices, playing a core role in portable electronic devices such as smartphones and laptops, providing stable power for extended periods and under different operating modes. Integrated Circuit 1 can also be applied to automotive electronics devices, providing high-performance, high-reliability power.

[0063] Please see Figure 4 , Figure 4 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the third embodiment of this application. The integrated circuit 1 mentioned above includes an electronic device (not shown) and a semiconductor device 100. The semiconductor device 100 is electrically connected to the electronic device to transmit electrical signals. The electronic device includes resistors, capacitors, and controllers, etc., which are not specifically limited in this application.

[0064] Based on this, this application provides a semiconductor device 100, which can be a power converter, such as an AC-DC converter, a DC-DC converter, etc. This application does not impose any special restrictions on the specific type of the semiconductor device.

[0065] like Figure 4 As shown, the semiconductor device 100 includes a first III-V transistor 10, a second III-V transistor 20, a substrate 30, and a dielectric layer 40. The first III-V transistor 10 and the second III-V transistor 20 are spaced apart and disposed on one surface of the substrate 30. The dielectric layer 40 covers the first III-V transistor 10, the second III-V transistor 20, and the substrate 30. That is, the first III-V transistor 10 and the second III-V transistor 20 are spaced apart on one surface of the substrate 30, and the dielectric layer 40 covers the first III-V transistor 10, the second III-V transistor 20, and the substrate 30. The dielectric layer 40 is used to prevent external moisture, oxygen, dust, and other impurities from penetrating the first III-V transistor 10, the second III-V transistor 20, and the substrate 30, thereby protecting them.

[0066] Please see Figure 5 , Figure 5 This is a schematic diagram of the circuit structure of the semiconductor device disclosed in this application. The first III-V transistor 10 includes a first gate 14, a first source 15, and a first drain 16. The second III-V transistor 20 includes a second gate 24, a second source 25, and a second drain 26. The first gate 14 is electrically connected to the first signal terminal V1, the first drain 16 is electrically connected to the power supply Vin, and the first source 15 is electrically connected to the output terminal Vout. The second gate 24 is electrically connected to the second signal terminal V2, the second source 25 is electrically connected to the ground terminal GND, and the second drain 26 is electrically connected to the output terminal Vout, i.e., the second drain 26 is electrically connected to the first source 15.

[0067] In this configuration, the first gate 14 receives a first control signal output from the first signal terminal V1, and the first III-V transistor 10 is turned on or off according to the first control signal. The second gate 24 receives a second control signal output from the second signal terminal V2, and the second III-V transistor 20 is turned on or off according to the second control signal. The first III-V transistor 10 and the second III-V transistor 20 are not turned on simultaneously.

[0068] For example, when the first III-V transistor 10 is turned on, the first source 15 and the first drain 16 of the first III-V transistor 10 are connected. At this time, the second III-V transistor 20 is turned off, and the second source 25 and the second drain 26 of the second III-V transistor 20 are cut off. Then, the potential of the output terminal Vout is the potential of the power supply Vin, and the output terminal Vout outputs a high-level signal. When the second III-V transistor 20 is turned on, the second source 25 and the second drain 26 of the second III-V transistor 20 are connected. At this time, the first III-V transistor 10 is turned off, and the first source 15 and the first drain 16 of the first III-V transistor 10 are cut off. Then, the potential of the output terminal Vout is the potential of the ground terminal GND, and the output terminal Vout outputs a low-level signal.

[0069] Since the first III-V transistor 10 is electrically connected to the power supply Vin, it can be referred to as a high-side transistor. Since the second III-V transistor 20 is electrically connected to the ground terminal GND, it can be referred to as a low-side transistor. In other embodiments, the first III-V transistor 10 may not be electrically connected to the power supply Vin, and the second III-V transistor 20 may not be electrically connected to the ground terminal GND, as long as the potential of the first drain 16 is greater than the potential of the second drain 26.

[0070] For ease of description, define Figure 4 The length direction of the semiconductor device 100 shown is the X-axis direction, the width direction is the Y-axis direction, and the thickness direction is the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are mutually perpendicular. The directional terms such as "upper" and "lower" mentioned in the description of the embodiments in this application are based on the appendix to the specification. Figure 4 The description of the orientation shown uses "up" or "top" for the positive direction of the Z-axis and "down" or "bottom" for the negative direction of the Z-axis. This does not constitute a limitation on the actual application scenario of the semiconductor device 100.

[0071] In the embodiments of this application, please refer to Figure 4 The first III-V transistor 10 also includes a first semiconductor layer 11, which is disposed on one surface of the substrate 30. The first gate 14, the first source 15 and the first drain 16 are all disposed on the surface of the first semiconductor layer 11 facing away from the substrate 30.

[0072] Specifically, the first semiconductor layer 11 includes a first buffer layer 111, a first channel layer 112, and a first barrier layer 113. The first buffer layer 111, the first channel layer 112, and the first barrier layer 113 are sequentially stacked on the substrate 30, that is, the first buffer layer 111 is disposed on one surface of the substrate 30, the first channel layer 112 is disposed on the surface of the first buffer layer 111 facing away from the surface of the substrate 30, and the first barrier layer 113 is disposed on the surface of the first channel layer 112 facing away from the first buffer layer 111. The first gate 14 is disposed on the surface of the first barrier layer 113 facing away from the first channel layer 112.

[0073] The first barrier layer 113 has a first via 113a and a second via 113b, both of which penetrate the first barrier layer 113 along the Z-axis. The second via 113b surrounds the first via 113a and is spaced apart from it. The first via 113a exposes the surface of the first channel layer 112 facing away from the first buffer layer 111, and the second via 113b also exposes the surface of the first channel layer 112 facing away from the first buffer layer 111. A first drain 16 is disposed in the first via 113a and connected to the first channel layer 112, and is electrically connected to the first channel layer 112. A first source 15 is disposed in the second via 113b and connected to the first channel layer 112, and is electrically connected to the first channel layer 112.

[0074] The first source electrode 15 and the first drain electrode 16 can also extend into the first channel layer 112 and be disposed within the first channel layer 112.

[0075] In an exemplary embodiment, the first via 113a is a cylindrical via, and the second via 113b is an annular via, meaning the cross-section of the second via 113b along the Y-axis is annular. For example, the cross-section of the first via 113a along the Y-axis may be circular, rectangular, or other shapes, and the cross-section of the second via 113b along the Y-axis may be annular or other shapes. The first drain 16 is cylindrical, the first gate 14 is annular, and the first source 15 is annular, meaning the cross-sections of the first gate 14 and the first source 15 along the Y-axis are both annular. The first gate 14 surrounds the first drain 16, and the first gate 14 and the first drain 16 are spaced apart. The first source 15 surrounds the first gate 14, and the first source 15 is spaced apart from the first gate 14.

[0076] The first buffer layer 111 is made of carbon-doped gallium nitride (GaN), the first channel layer 112 is made of gallium nitride, and the first barrier layer 113 is made of aluminum gallium nitride (AlGaN). The first buffer layer 111 is used to prevent lattice mismatch between the first channel layer 112 and the substrate 30. The band gap of the first barrier layer 113 is larger than that of the first channel layer 112, thus forming a heterojunction between the first barrier layer 113 and the first channel layer 112. A large potential well exists at the interface of this heterojunction, and electrons are confined in the potential well to form a high-density two-dimensional electron gas (2DEG), which is an electron layer that can move freely in a two-dimensional plane. The first gate 14 is used to control the conduction or disconnection of the two-dimensional electron gas in the first channel layer 112. In this configuration, the two-dimensional electron gas within the first channel layer 112 is conductive, the first source 15 and the first drain 16 are electrically connected, the two-dimensional electron gas within the first channel layer 112 is disconnected, and the first source 15 and the first drain 16 are disconnected.

[0077] In this embodiment, the second III-V transistor 20 further includes a second semiconductor layer 21. The second semiconductor layer 21 and the first semiconductor layer 11 are disposed on the same surface of the substrate 30, and the second semiconductor layer 21 is spaced apart from the first semiconductor layer 11, thereby achieving physical isolation between the first III-V transistor 10 and the second III-V transistor 20. The second gate 24, the second source 25, and the second drain 26 are all disposed on the surface of the second semiconductor layer 21 facing away from the substrate 30.

[0078] Specifically, the second semiconductor layer 21 includes a second buffer layer 211, a second channel layer 212, and a second barrier layer 213. The second buffer layer 211, the second channel layer 212, and the second barrier layer 213 are sequentially stacked on the substrate 30, i.e., the second buffer layer 211 is disposed on one surface of the substrate 30, the second channel layer 212 is disposed on the surface of the second buffer layer 211 opposite to the substrate 30, and the second barrier layer 213 is disposed on the surface of the second channel layer 212 opposite to the second buffer layer 211. The second gate 24 is disposed on the surface of the second barrier layer 213 opposite to the second channel layer 212.

[0079] The second barrier layer 213 has a third via 213a and a fourth via 213b, both of which penetrate the second barrier layer 213 along the Z-axis. The fourth via 213b surrounds the third via 213a and is spaced apart from the third via 213a. The third via 213a exposes the surface of the second channel layer 212 facing away from the second buffer layer 211, and the fourth via 213b also exposes the surface of the second channel layer 212 facing away from the second buffer layer 211. The second drain 26 is disposed within the third via 213a and connected to the second channel layer 212, and is electrically connected to the second channel layer 212. The second drain 26 is disposed within the fourth via 213b and connected to the second channel layer 212, and the second source 25 is electrically connected to the second channel layer 212.

[0080] The second source 25 and the second drain 26 can also extend into the second channel layer 212 and be embedded in the second channel layer 212.

[0081] In an exemplary embodiment, the third via 213a is a cylindrical via, and the fourth via 213b is an annular via, meaning the cross-section of the fourth via 213b along the Y-axis is annular. For example, the cross-section of the third via 213a along the Y-axis may be circular, rectangular, or other shapes, and the cross-section of the fourth via 213b along the Y-axis may be annular or other shapes. The second drain 26 is cylindrical, the second gate 24 is annular, and the second source 25 is annular, meaning the cross-sections of the second gate 24 and the second source 25 along the Y-axis are both annular. The second gate 24 surrounds the second drain 26, and the second gate 24 and the second drain 26 are spaced apart. The second source 25 surrounds the second gate 24, and the second source 25 is spaced apart from the second gate 24.

[0082] The second buffer layer 211 is made of carbon-doped gallium nitride (GaN), the second channel layer 212 is made of gallium nitride, and the second barrier layer 213 is made of aluminum gallium nitride (AlGaN). The second buffer layer 211 is used to prevent lattice mismatch between the second channel layer 212 and the substrate 30. The band gap of the second barrier layer 213 is larger than that of the second channel layer 212, thus forming a heterojunction between the second barrier layer 213 and the second channel layer 212. The second gate 24 is used to control the conduction or disconnection of the two-dimensional electron gas in the second channel layer 212. When the two-dimensional electron gas in the second channel layer 212 is on, the second source 25 and the second drain 26 are electrically connected; when the two-dimensional electron gas in the second channel layer 212 is off, the second source 25 and the second drain 26 are disconnected.

[0083] In an exemplary embodiment, a dielectric layer 40 is disposed on the peripheral side surface of the first buffer layer 111, the peripheral side surface of the first channel layer 112, the peripheral side surface of the first barrier layer 113, the surface of the first barrier layer 113 facing away from the first channel layer 112, the peripheral side surface of the second buffer layer 211, the peripheral side surface of the second channel layer 212, the peripheral side surface of the second barrier layer 213, and the surface of the second barrier layer 213 facing away from the second channel layer 212, and covers the substrate 30.

[0084] In the embodiments of this application, please refer to Figure 4 The substrate 30 includes a first doped layer 31, a second doped layer 32, and a base 33. The first doped layer 31 and the second doped layer 32 are disposed on the base 33. The second doped layer 32 is connected to the peripheral surface of the first doped layer 31 and also to the bottom surface of the first doped layer 31. The depth of the second doped layer 32 is greater than the depth of the first doped layer 31, and the depth direction is the Z-axis direction. The boundary region between the first doped layer 31 and the second doped layer 32 in the transverse direction (X-axis direction) is a transition region 30a. That is, the transition region 30a is a part where the first doped layer 31 and the second doped layer 32 are close to each other in the transverse direction. The transition region 30a contains a part of the first doped layer 31 and a part of the second doped layer 32. Figure 4 The position of the transition region 30a is illustrated by a dashed line.

[0085] In an exemplary embodiment, the semiconductor device 100 has a trench 100a, which is located above the transition region 30a at the junction of the first doped layer 31 and the second doped layer 32. The first III-V transistor 10 and the second III-V transistor 20 are isolated by the trench 100a.

[0086] In an exemplary embodiment, the first doped layer 31 includes a first surface 31a, which is the top surface of the first doped layer 31. The first surface 31a is disposed opposite to the bottom surface of the first doped layer 31, and the peripheral side surfaces of the first doped layer 31 are connected to the bottom surface and the first surface 31a, respectively. The first surface 31a faces away from the substrate 33.

[0087] The second doped layer 32 includes a second surface 32a, all of which face away from the substrate 33. A first surface 31a is connected to the second surface 32a and is aligned with the second surface 32a.

[0088] A first semiconductor layer 11 is disposed on a first surface 31a. Specifically, a first buffer layer 111 is disposed on the first surface 31a of the first doped layer 31, and a first channel layer 112 is disposed on the surface of the first buffer layer 111 opposite to the first doped layer 31. A second buffer layer 211 is disposed on a surface of the second doped layer 32, and a second channel layer 212 is disposed on the surface of the second buffer layer 211 opposite to the second doped layer 32.

[0089] The periphery of the first surface 31a exposes the first III-V transistor 10, meaning that the periphery of the first doped layer 31 is not connected to the first semiconductor layer 11, while the portion of the first doped layer 31 other than the periphery is connected to the first semiconductor layer 11. In other words, the orthographic projection of the periphery of the first surface 31a onto the substrate 33 surrounds the orthographic projection of the first III-V transistor 10 onto the substrate 33.

[0090] In an exemplary embodiment, the dielectric layer 40 is disposed on the periphery of the first surface 31a and the second surface 32a, that is, the dielectric layer 40 is disposed above the transition region 30a.

[0091] In this design, the first doped layer 31 is of the first doping type, the second doped layer 32 is of the second doping type, and the substrate 33 is of the second doping type. The first doping type is N-type doping, and the second doping type is P-type doping. A PN junction is formed at the interface between the first doped layer 31 and the second doped layer 32. Figure 4 The location of the PN junction is illustrated by dashed lines, and the PN junction has a depletion region. In the lateral direction, a portion of the PN junction is located within the transition region 30a. The first doped layer 31 is the well region, and the second doped layer 32 is the epitaxial layer.

[0092] Understandably, the PN junction is located at the interface between the first doped layer 31 and the second doped layer 32. If the potential of the second doped layer 32 is greater than the potential of the first doped layer 31, the PN junction is forward biased, conducts, and current flows between the second doped layer 32 and the first doped layer 31. If the potential of the first doped layer 31 is greater than the potential of the second doped layer 32, the PN junction is reverse biased, cut off, and no current flows between the second doped layer 32 and the first doped layer 31. Furthermore, the periphery of the first surface 31a exposes the first III-V group transistor 10, preventing leakage current between the first semiconductor layer 11 and the second doped layer 32 caused by direct connection between the first semiconductor layer 11 and the second doped layer 32. This application forms only one PN junction within the substrate 30, thus avoiding latch-up effects on the substrate 30.

[0093] In an exemplary embodiment, the substrate 33 can be a heavily doped or lightly doped silicon layer, and the dopant ion of the substrate 33 is boron. The second doped layer 32 can also be a heavily doped or lightly doped silicon layer, and the dopant ion of the second doped layer 32 is boron. The doping concentration of the substrate 33 is greater than the doping concentration of the second doped layer 32, and the doping concentration of the second doped layer 32 is typically adjustable.

[0094] In an exemplary embodiment, a second doped layer 32 is formed on a substrate 33 by an epitaxial growth process, and ions are implanted into the second doped layer to form a first doped layer 31.

[0095] like Figure 4 As shown, the semiconductor device 100 also includes a first conductor 50, which is disposed inside the first III-V transistor 10. The first conductor 50 is connected to the first source 15 and the first doped layer 31, respectively, so that the first source 15 is electrically connected to the first doped layer 31 through the first conductor 50.

[0096] Specifically, the first channel layer 112 has a first through-hole 112a, which penetrates the first channel layer 112 along the Z-axis. The orthographic projection of the first through-hole 112a in the Z-axis direction lies within the orthographic projection of the second via 113b in the Z-axis direction, and the first through-hole 112a and the second via 113b are connected. Here, "connected" means that they are linked and communicate with each other. The first buffer layer 111 has a second through-hole 111a, which penetrates the first buffer layer 111 along the Z-axis direction. The orthographic projection of the second through-hole 111a in the Z-axis direction coincides with the orthographic projection of the first through-hole 112a in the Z-axis direction, and the second through-hole 111a and the first through-hole 112a are connected. A first conductor 50 is disposed within the first through-hole 112a and the second through-hole 111a.

[0097] In an exemplary embodiment, the first conductor 50 is disposed within the first through-hole 112a and the second through-hole 111a, and one end of the first conductor 50 is disposed within the first doped layer 31 to ensure the stability of the electrical connection between the first conductor 50 and the first doped layer 31. In other embodiments, the first conductor 50 may not be disposed within the first doped layer 31.

[0098] In an exemplary embodiment, both the first through hole 112a and the second through hole 111a are annular holes. Correspondingly, the cross-section of the first conductor 50 along the Y direction is also annular.

[0099] In this configuration, the first drain 16 is electrically connected to the power supply Vin. When the first III-V transistor 10 is turned on, the first drain 16 is electrically connected to the first source 15. The first source 15 is electrically connected to the first doped layer 31 through the first conductor 50. The second doped layer 32 is electrically connected to the ground terminal GND. The power supply Vin causes the potential of the first doped layer 31 to be greater than the potential of the second doped layer 32, thus reverse-biasing the PN junction at the junction of the first doped layer 31 and the second doped layer 32.

[0100] In this embodiment of the application, the semiconductor device 100 further includes a second conductor 60, which is disposed inside the second III-V transistor 20. The second conductor 60 is connected to the second source 25 and the second doped layer 32, respectively, so that the second source 25 is electrically connected to the second doped layer 32 through the second conductor 60.

[0101] Specifically, the second channel layer 212 has a third through-hole 212a, which penetrates the second channel layer 212 along the Z-axis. The orthographic projection of the third through-hole 212a in the Z-axis direction lies within the orthographic projection of the fourth through-hole 213b in the Z-axis direction, and the third through-hole 212a and the fourth through-hole 213b are connected. Here, "connected" means that they are linked and communicate with each other. The second buffer layer 211 has a fourth through-hole 211a, which penetrates the second buffer layer 211 along the Z-axis direction. The orthographic projection of the fourth through-hole 211a in the Z-axis direction coincides with the orthographic projection of the third through-hole 212a in the Z-axis direction, and the fourth through-hole 211a and the third through-hole 212a are connected. The second conductor 60 is disposed within the third through-hole 212a and the fourth through-hole 211a.

[0102] In an exemplary embodiment, the second conductor 60 is disposed within the third through-hole 212a and the fourth through-hole 211a, and one end of the second conductor 60 is disposed within the second doped layer 32 to ensure the stability of the electrical connection between the second conductor 60 and the second doped layer 32. In other embodiments, the second conductor 60 may not be disposed within the second doped layer 32.

[0103] In an exemplary embodiment, both the third through-hole 212a and the fourth through-hole 211a are annular holes. Correspondingly, the cross-section of the second conductor 60 along the Y direction is annular. The second source electrode 25 is electrically connected to the ground terminal GND, and the second source electrode 25 is electrically connected to the second doped layer 32 through the second conductor 60. The second doped layer 32 is electrically connected to the ground terminal GND through the second conductor 60 and the second source electrode 25.

[0104] Understandably, the second doped layer 32 is electrically connected to the ground terminal GND through the second conductor 60 and the second source 25. This eliminates the need for additional conductive components to ground the second doped layer 32, saving material, increasing the integration density of the semiconductor device 100, and reducing the design complexity of the peripheral circuitry. Furthermore, grounding the second doped layer 32 reduces parasitic effects and improves circuit stability and reliability. Moreover, by changing the potential of the second source 25, the potential of the second doped layer 32 can be changed, enabling controllable potential of the substrate 30.

[0105] Please see Figure 6 , Figure 6 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 6 The semiconductor device 100 shown and Figure 4 The difference in the semiconductor device 100 shown is that the substrate 30 also includes a first variable doping region 34. Figure 6 The semiconductor device 100 shown and Figure 4 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 4 The relevant descriptions will not be elaborated here.

[0106] Specifically, the first variable doping region 34 is disposed around the periphery of the first doped layer 31. In the direction from the first doped layer 31 to the second doped layer 32 (the direction from the center of the first doped layer 31 to the periphery of the first doped layer 31), the doping concentration of the first variable doping region 34 gradually decreases. The first variable doping region 34 is a lateral doping (VLD) region and is the first doping type.

[0107] It should be noted that the overall doping concentration of the first variable doped region 34 decreases in the direction from the first doped layer 31 to the second doped layer 32. Since the first variable doped region 34 is formed by implanting ions in multiple spaced implantation regions, the doping concentration between two adjacent implantation regions is greater than the concentration of those two implantation regions. That is, the doping concentration of the first variable doped region 34 fluctuates to a certain extent between two adjacent implantation regions and between those two implantation regions.

[0108] Understandably, the above description of forming a PN junction at the interface between the first doped layer 31 and the second doped layer 32 avoids leakage current between the first doped layer 31 and the second doped layer 32 caused by the potential of the first doped layer 31 being greater than that of the second doped layer 32. However, if the potential difference between the first doped layer 31 and the second doped layer 32 is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse broken down. Therefore, by forming a first variable doping region 34 around the periphery of the first doped layer 31, the first variable doping region 34 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0109] In an exemplary embodiment, the surface of the first variable-doped region 34 facing away from the first doped layer 31 is connected to the second doped layer 32. The top surface of the first variable-doped region 34 is connected to both the first surface 31a and the second surface 32a, and the top surface of the first variable-doped region 34 is aligned with both the first surface 31a and the second surface 32a. The top surface of the first variable-doped region 34 is also connected to the dielectric layer 40.

[0110] In an exemplary embodiment, the maximum depth of the first variable doped region 34 may be equal to the depth of the first doped layer 31.

[0111] In an exemplary embodiment, the first variable-doped region 34 is formed by an ion implantation process. The first variable-doped region 34 and the first doped layer 31 can be formed together in a single ion implantation process.

[0112] Please see Figure 7 , Figure 7 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 7 The semiconductor device 100 shown and Figure 4 The difference in the semiconductor device 100 shown is that the substrate 30 also includes at least one first guard ring 35. Figure 7 The semiconductor device 100 shown and Figure 4 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 4 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0113] Please refer to the following: Figure 7 and Figure 8 , Figure 8 for Figure 7 The diagram shows a top view of the first III-V group transistor of the semiconductor device. At least one first guard ring 35 is disposed within the second doped layer 32, and at least one first guard ring 35 is disposed around the periphery of the first doped layer 31, with each first guard ring 35 spaced apart from the first doped layer 31. The first guard ring 35 is of the first doping type.

[0114] At least one first protective ring 35 is disposed within the second doped layer 32. The second doped layer 32 connects the inner side, outer side, and bottom surface of the first protective ring 35. The top surface of the first protective ring 35 exposes the surface of the second doped layer 32 that faces away from the substrate 33. The bottom and top surfaces of the first protective ring 35 are positioned opposite each other.

[0115] For example, there may be one first guard ring 35, which is disposed around the periphery of the first doped layer 31 and spaced apart from it. Alternatively, there may be multiple first guard rings 35, stacked and arranged around the periphery of the first doped layer 31, i.e., in a direction from the center of the first doped layer 31 to its periphery, with the multiple first guard rings 35 arranged sequentially. The multiple first guard rings 35 are spaced apart from each other and from the first doped layer 31. A second doped layer 32 is disposed between the first guard ring 35 closest to the first doped layer 31 and the first doped layer 31, and a second doped layer 32 is disposed between two adjacent first guard rings 35.

[0116] Understandably, as described above, the first doped layer 31 and the second doped layer 32 form a PN junction, preventing leakage current between the first doped layer 31 and the second doped layer 32 due to the potential of the first doped layer 31 being greater than that of the second doped layer 32. However, if the potential difference between the first doped layer 31 and the second doped layer 32 is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken. Therefore, by forming at least one first guard ring 35 on the periphery of the first doped layer 31, the first guard ring 35 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0117] This application does not impose specific restrictions on the doping concentration of the first guard ring 35, the spacing between the first guard ring 35 and the first doped layer 31, or the spacing between adjacent first guard rings 35, as long as the first guard ring 35 can increase the reverse breakdown voltage between the second doped layer 32 and the first doped layer 31.

[0118] In an exemplary embodiment, the first guard ring 35 is formed by an ion implantation process. The first guard ring 35 and the first doped layer 31 can be formed together in a single ion implantation process.

[0119] It should be noted that both the first guard ring 35 and the first variable-doped region 34 are formed through ion implantation, but the difference lies in the spacing between the ion implantations. When forming the first variable-doped region 34, the ion implantation spacing is relatively close, allowing ions to diffuse within the second doped layer 32. After annealing, the first variable-doped region 34 is a single entity, with the doping concentration gradually decreasing outwards. When forming multiple first guard rings 35, the ion implantation spacing is relatively far, limiting ion diffusion; therefore, the multiple first guard rings 35 are spaced apart.

[0120] In an exemplary embodiment, the depth of the first guard ring 35 is equal to the depth of the first doped layer 31. The first guard ring 35 includes a third surface 35a, which is the top surface of the first guard ring 35. The orientation of the third surface 35a is the same as that of the second surface 32a. The third surface 35a exposes the second surface 32a and is flush with the first surface 31a. The surface of the first guard ring 35 that is opposite to the third surface 35a is flush with the surface of the first doped layer 31 that is opposite to the first surface 31a.

[0121] The depth of the first doped layer 31 is less than the depth of the second doped layer 32, and the depth of the first guard ring 35 is less than the depth of the second doped layer 32. The second doped layer 32 connects the inner surface of the first guard ring 35, the outer surface of the first guard ring 35, and the surface of the first guard ring 35 that is opposite to the third surface 35a.

[0122] Please see Figure 9 , Figure 9 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 9 The semiconductor device 100 shown and Figure 4 The difference in the semiconductor device 100 shown is that the semiconductor device 100 also includes a field plate 80. Figure 9 The semiconductor device 100 shown and Figure 4 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 4 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0123] Specifically, the field plate 80 is disposed on the surface of the dielectric layer 40 opposite to the first surface 31a, the surface of the dielectric layer 40 opposite to the second surface 32a, the surface of the dielectric layer 40 opposite to the peripheral side of the first semiconductor layer 11, and the surface of the first semiconductor layer 11 opposite to the first doped layer 31, and extends to the first source 15. The field plate is located above the dielectric layer 40, and the field plate 80 is located in the trench 100a. Figure 8 The field plate 80 and the first source 15 are distinguished by dashed lines. The dielectric layer 40 is used to insulate the field plate 80 from the second doped layer 32.

[0124] In an exemplary embodiment, the periphery of the field plate 80 protrudes from the periphery of the first surface 31a. That is, in the Z-axis direction, the first doped layer 31 is not disposed below the periphery of the field plate 80, but the first doped layer 31 is disposed below the portion of the field plate 80 other than the periphery. The field plate 80 is spaced apart from the second III-V group transistor 20, that is, the orthographic projection of the field plate 80 in the Z-axis direction is spaced apart from the orthographic projection of the second semiconductor layer 21 in the Z-axis direction. The field plate 80 is connected to and electrically connected to the first source 15, and the field plate 80 is electrically connected to the first doped layer 31 through the first source 15 and the first conductor 50. The potential of the field plate 80 is the same as the potential of the first doped layer 31.

[0125] Understandably, the potential of the field plate 80 is the same as that of the first doped layer 31, and the PN junction will extend to the bottom of the field plate 80. That is, the field plate 80 increases the width of the PN junction, which increases the reverse breakdown voltage of the PN junction and improves the withstand voltage of the semiconductor device 100.

[0126] In an exemplary embodiment, the first source electrode 15 is integrally formed with the field plate 80.

[0127] In other embodiments, the field plate 80 may not be connected to the first source 15. Applying a negative bias to the field plate 80 can also increase the width of the PN junction.

[0128] Please see Figure 10 , Figure 10 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 10 The semiconductor device 100 shown and Figure 9 The difference in the semiconductor device 100 shown is that the substrate 30 further includes a first variable doping region 34, i.e. Figure 10 The semiconductor device 100 shown includes a field plate 80 and a first variable doping region 34. Figure 10 The semiconductor device 100 shown and Figure 9 , Figure 6 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 9 , Figure 6 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0129] Specifically, the orthographic projection of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable-doped region 34. The orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable-doped region 34 onto the substrate 33. Alternatively, the periphery of the field plate 80 protrudes beyond the periphery of the first variable-doped region 34.

[0130] Understandably, the field plate 80 causes the PN junction to extend beneath it. The orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable-doped region 34 onto the substrate 33. Alternatively, the periphery of the field plate 80 protrudes beyond the periphery of the first variable-doped region 34, further expanding the width of the PN junction around the first variable-doped region 34. Through the combination of the field plate 80 and the first variable-doped region 34, the reverse breakdown voltage of the PN junction is significantly increased, greatly improving the breakdown voltage of the semiconductor device 100.

[0131] Please see Figure 11 , Figure 11 This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 11 The semiconductor device 100 shown and Figure 9 The difference in the semiconductor device 100 shown is that the substrate 30 further includes at least one first guard ring 35, i.e. Figure 11 The semiconductor device 100 shown includes a field plate 80 and at least one first guard ring 35. Figure 11 The semiconductor device 100 shown and Figure 9 , Figure 7 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 9 , Figure 7 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0132] Specifically, the field plate 80 is located above each of the first guard rings 35. The periphery of the field plate 80 protrudes outward from the outer side of the first guard ring 35 furthest from the first doped layer 31; that is, at least one first guard ring 35 is spaced apart on the periphery of the first doped layer 31, and the periphery of the field plate 80 protrudes outward from the periphery of the outermost first guard ring 35. In other words, in the Z-axis direction, there is no first guard ring 35 below the periphery of the field plate 80; the first guard ring 35 and the first doped layer 31 are located below the portion of the field plate 80 excluding the periphery.

[0133] Understandably, the field plate 80 causes the PN junction to extend beneath it, and the first guard ring 35 expands the width of the PN junction at the lateral contact between the first doped layer 31 and the second doped layer 32. The periphery of the field plate 80 protrudes outward from the outer side of the first guard ring 35, which is furthest from the first doped layer 31, further expanding the width of the PN junction around the first guard ring 35. Through the combination of the field plate 80 and the first guard ring 35, the reverse breakdown voltage of the PN junction is significantly increased, greatly improving the breakdown voltage of the semiconductor device 100.

[0134] Please see Figure 12 , Figure 12 This is a schematic diagram of the seventh layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 12The semiconductor device 100 shown and Figure 11 The difference in the semiconductor device 100 shown is that the depth of the first doped layer 31 is greater than the depth of the second doped layer 32, and the depth of the first guard ring 35 is greater than the depth of the second doped layer 32. Figure 12 The semiconductor device 100 shown and Figure 11 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 11 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0135] Specifically, the surface of the first doped layer 31 facing away from the first semiconductor layer 11 protrudes from the surface of the second doped layer 32 facing away from the second semiconductor layer 21 and is disposed inside the substrate 33. Similarly, the surface of the first protective ring 35 facing away from the dielectric layer 40 protrudes from the surface of the second doped layer 32 facing away from the second semiconductor layer 21 and is disposed inside the substrate 33. That is, the first doped layer 31 passes through the second doped layer 32 and is disposed within the substrate 33, and the first protective ring 35 passes through the second doped layer 32 and is disposed within the substrate 33. The second doped layer 32 and the substrate 33 together connect the peripheral side surface of the first doped layer 31 and the inner and outer sides of the first protective ring 35. The substrate 33 connects the surface of the first doped layer 31 facing away from the semiconductor layer 11 and the surface of the first protective ring 35 facing away from the dielectric layer 40.

[0136] Please see Figure 13 , Figure 13 This is a schematic diagram of the eighth layer structure of the semiconductor device disclosed in the third embodiment of this application. Figure 13 The semiconductor device 100 shown and Figure 10 The difference in the semiconductor device 100 shown is that the depth of the first doped layer 31 is greater than the depth of the second doped layer 32, and the depth of the first variable doped region 34 is greater than the depth of the second doped layer 32. Figure 13 The semiconductor device 100 shown and Figure 10 For a description of the structural similarities between the semiconductor device 100 shown, please refer to [link / reference]. Figure 10 The relevant description of the semiconductor device 100 shown will not be repeated here.

[0137] Specifically, the surface of the first doped layer 31 facing away from the first semiconductor layer 11 protrudes beyond the surface of the second doped layer 32 facing away from the second semiconductor layer 21 and is disposed inside the substrate 33. Similarly, the surface of the first variable doped region 34 facing away from the dielectric layer 40 protrudes beyond the surface of the second doped layer 32 facing away from the second semiconductor layer 21 and is disposed inside the substrate 33. That is, the first doped layer 31 passes through the second doped layer 32 and is disposed within the substrate 33, and the first variable doped region 34 passes through the second doped layer 32 and is disposed within the substrate 33. The second doped layer 32 and the substrate 33 together connect to the periphery of the first variable doped region 34.

[0138] Please see Figure 14 , Figure 14 This is a schematic diagram of the layer structure of one type of first III-V transistor disclosed in an embodiment of this application. The first III-V transistor 10 is an enhancement-mode transistor. When no potential is applied to the gate 14 of the first III-V transistor 10, the two-dimensional electron gas of the first III-V transistor 10 is disconnected. The gate 14 includes an isolation layer 141 and a metal gate 142, which are sequentially stacked on the surface of the first barrier layer 113 facing away from the first channel layer 112. The isolation layer 141 is spaced apart from the first source 15 and the first drain 16, respectively, and the metal gate 142 is spaced apart from the first source 15 and the first drain 16, respectively. The isolation layer 141 injects holes into the heterojunction between the first channel layer 112 and the first barrier layer 113, thereby depleting the two-dimensional electron gas below the isolation layer 141, that is, the two-dimensional electron gas below the isolation layer 141 is disconnected.

[0139] The second III-V transistor 20 can also be an enhancement transistor. For the structure of the second III-V transistor 20, please refer to [link to documentation]. Figure 14 The structure of the first III-V group transistor 10 shown will not be described in detail here.

[0140] Please see Figure 15 , Figure 15 This is a schematic diagram of another type of layer structure of the first III-V transistor disclosed in this application. The first III-V transistor 10 is a depletion-type transistor. When no potential is applied to the gate 14 of the first III-V transistor 10, the two-dimensional electron gas of the first III-V transistor 10 is conductive. The gate 14 includes an insulating layer 143 and a metal gate 142, which are stacked together. A groove is formed on the surface of the first barrier layer 113 opposite to the first channel layer 112. The insulating layer 143 is disposed in the groove, and the metal gate 142 is disposed on the surface of the insulating layer 143 opposite to the bottom wall of the groove, with the metal gate 142 spaced apart from the first barrier layer 113. The insulating layer 143 is used to insulate the metal gate 142 from the first barrier layer 113.

[0141] The second III-V group transistor 20 can also be a depletion-type transistor. For the structure of the second III-V group transistor 20, please refer to [link to documentation]. Figure 15 The structure of the first III-V group transistor 10 shown will not be described in detail here.

[0142] Please see Figure 16 , Figure 16 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 16 The semiconductor device 100 shown and Figure 4The difference between the semiconductor device 100 shown is that the first doped layer 31 is an epitaxial layer and the second doped layer 32 is a well region. Figure 16 The semiconductor device 100 shown and Figure 4 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 4 The relevant descriptions will not be repeated here.

[0143] In an exemplary embodiment, a first doped layer 31 is formed on a substrate 33 by an epitaxial growth process, and ions are implanted into the first doped layer 31 to form a second doped layer 32.

[0144] To prevent the first doped layer 31 from extending below the second semiconductor layer 21, a second doped layer 32 is also formed on a portion of the substrate 33 using an ion implantation process. Specifically, the depth of the second doped layer 32 is greater than the depth of the first doped layer 31. The second doped layer 32 is connected to the peripheral side surface of the first doped layer 31, and the surface of the second doped layer 32 facing away from the second semiconductor layer 21 protrudes beyond the surface of the first doped layer 31 facing away from the first semiconductor layer 11. The substrate 33 is connected to the surface of the first doped layer 31 facing away from the first semiconductor layer 11.

[0145] Please see Figure 17 , Figure 17 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 17 The semiconductor device 100 shown and Figure 16 The difference in the semiconductor device 100 shown is that the substrate 30 also includes a second variable doping region 36. Figure 17 The semiconductor device 100 shown and Figure 16 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 16 The relevant descriptions will not be elaborated here.

[0146] Specifically, the second variable doping region 36 is disposed around the periphery of the first doped layer 31. In the direction from the first doped layer 31 to the second doped layer 32 (the direction from the center of the first doped layer 31 to the periphery of the first doped layer 31), the doping concentration of the second variable doping region 36 gradually increases. The second variable doping region 36 is a lateral doping (VLD) and is a second doping type.

[0147] It should be noted that the overall doping concentration of the second variable doped region 36 increases in the direction from the first doped layer 31 to the second doped layer 32. Since the second variable doped region 36 is formed by implanting ions in multiple spaced implantation regions, the doping concentration between two adjacent implantation regions is greater than the concentration of the two implantation regions. That is, the doping concentration of the second variable doped region 36 in the region between two adjacent implantation regions and the region between the two adjacent implantation regions fluctuates to a certain extent.

[0148] Understandably, the above description of forming a PN junction at the interface between the first doped layer 31 and the second doped layer 32 avoids leakage current between the first doped layer 31 and the second doped layer 32 caused by the potential of the first doped layer 31 being greater than that of the second doped layer 32. However, if the potential difference between the first doped layer 31 and the second doped layer 32 is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken down. Therefore, by forming a second variable doping region 36 around the periphery of the first doped layer 31, the second variable doping region 36 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0149] In an exemplary embodiment, the surface of the second variable-doped region 36 facing away from the first doped layer 31 is connected to the second doped layer 32. The top surface of the second variable-doped region 36 is connected to both the first surface 31a and the second surface 32a, and is aligned with both the first surface 31a and the second surface 32a. The top surface of the second variable-doped region 36 is also connected to the dielectric layer 40.

[0150] In an exemplary embodiment, the maximum depth of the second variable doped region 36 may be equal to the depth of the second doped layer 32.

[0151] In an exemplary embodiment, the second variable-doped region 36 is formed by an ion implantation process. The second variable-doped region 36 and the second doped layer 32 can be formed together in a single ion implantation process.

[0152] Please see Figure 18 , Figure 18 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 18 The semiconductor device 100 shown and Figure 16 The difference in the semiconductor device 100 shown is that the substrate 30 includes at least one second guard ring 37. Figure 18 The semiconductor device 100 shown and Figure 16 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 16 The relevant descriptions will not be repeated here.

[0153] At least one second guard ring 37 is disposed within the first doped layer 31. The orthographic projection of each second guard ring 37 onto the substrate 33 is spaced apart from the orthographic projection of the first III-V transistor 10 onto the substrate 33, meaning the second guard ring 37 is located only within the periphery of the first doped layer 31. The second guard ring 37 is also spaced apart from the second doped layer 32, and the second guard ring 37 is of the second doping type.

[0154] The first doped layer 31 connects the inner side, outer side, and bottom surface of the second protective ring 37, and the top surface of the second protective ring 37 exposes the first surface 31a. The bottom and top surfaces of the second protective ring 37 are positioned opposite each other.

[0155] For example, there may be one second guard ring 37, which is disposed within the first doped layer 31. Alternatively, there may be multiple second guard rings 37, with multiple first guard rings 35 stacked and disposed within the first doped layer 31, i.e., multiple second guard rings 37 sequentially arranged in a direction from the center of the first doped layer 31 to its periphery. The multiple second guard rings 37 are spaced apart from each other and from the second doped layer 32. A first doped layer 31 is disposed between the second guard ring 37 closest to the second doped layer 32 and the second doped layer 32, and a first doped layer 31 is also disposed between two adjacent second guard rings 37.

[0156] Understandably, as described above, the first doped layer 31 and the second doped layer 32 form a PN junction, preventing leakage current between the first doped layer 31 and the second doped layer 32 due to the potential of the first doped layer 31 being greater than that of the second doped layer 32. However, if the potential difference between the first doped layer 31 and the second doped layer 32 is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken. Therefore, by forming at least one second guard ring 37 inside the first doped layer 31, the second guard ring 37 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0157] This application does not impose specific restrictions on the doping concentration of the second guard ring 37 or the spacing between adjacent second guard rings 37, as long as the second guard ring 37 can increase the reverse breakdown voltage between the second doped layer 32 and the first doped layer 31.

[0158] In an exemplary embodiment, the second guard ring 37 is formed by an ion implantation process. The second guard ring 37 and the second doped layer 32 can be formed together in a single ion implantation process.

[0159] It should be noted that both the second guard ring 37 and the second variable-doped region 36 are formed through ion implantation, but the difference lies in the spacing between the ion implantations. When forming the second variable-doped region 36, the ion implantation spacing is relatively close, allowing ions to diffuse within the first doped layer 31. After annealing, the second variable-doped region 36 is a single entity, with the doping concentration gradually decreasing outwards. When forming multiple second guard rings 37, the ion implantation spacing is relatively far, limiting ion diffusion, and thus the multiple second guard rings 37 are spaced apart.

[0160] In an exemplary embodiment, the depth of the second doped layer 32 is equal to the depth of the second guard ring 37. The top surface of the second guard ring 37 is aligned with the first surface 31a, and the top surface of the second guard ring 37 is connected to the dielectric layer 40. The bottom surface of the second doped layer 32 is aligned with the bottom surface of the second guard ring 37.

[0161] Please see Figure 19 , Figure 19 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 19 The semiconductor device 100 shown and Figure 16 The difference in the semiconductor device 100 shown is that the semiconductor device 100 also includes a field plate 80. Figure 19 The semiconductor device 100 shown and Figure 16 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 16 The relevant descriptions will not be repeated here. For a detailed description of the 80mm plate, please refer to [link / reference needed]. Figure 9 The relevant descriptions will not be repeated here.

[0162] Please see Figure 20 , Figure 20 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 20 The semiconductor device 100 shown and Figure 17 The difference in the semiconductor device 100 shown is that the semiconductor device 100 also includes a field plate 80. Figure 20 The semiconductor device 100 shown and Figure 17 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 17 The relevant descriptions will not be repeated here.

[0163] In an exemplary embodiment, the field plate 80 coincides with the periphery of the first doped layer 31 and with the second variable doped region 36, that is, the orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the second variable doped region 36 onto the substrate 33. The periphery of the field plate 80 may also protrude from the periphery of the second variable doped region 36.

[0164] Understandably, the field plate 80 extends the PN junction beneath it. The periphery of the field plate 80 is located above the second variable doping region 36, or the periphery of the field plate 80 protrudes beyond the periphery of the second variable doping region 36. The field plate 80 further expands the width of the PN junction around the first doped layer 31. Through the combination of the field plate 80 and the second variable doping region, the reverse breakdown voltage of the PN junction is significantly increased, greatly improving the breakdown voltage of the semiconductor device 100.

[0165] Please see Figure 21 , Figure 21 This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the fourth embodiment of this application. Figure 21 The semiconductor device 100 shown and Figure 18 The difference in the semiconductor device 100 shown is that the semiconductor device 100 also includes a field plate 80. Figure 21 The semiconductor device 100 shown and Figure 18 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 18 The relevant descriptions will not be repeated here.

[0166] Specifically, the field plate 80 is located above each of the second guard rings 37. The periphery of the field plate 80 protrudes from the periphery of the first doped layer 31 and is located above the second doped layer 32, that is, the orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the second doped layer 32 onto the substrate 33.

[0167] Understandably, the field plate 80 causes the PN junction to extend beneath it, and the second guard ring 37 expands the width of the PN junction at the lateral contact between the first doped layer 31 and the second doped layer 32. The periphery of the field plate 80 protrudes beyond the periphery of the first doped layer 31 and is located above the second doped layer 32, further increasing the width of the PN junction. The combination of the field plate 80 and the second guard ring 37 significantly increases the reverse breakdown voltage of the PN junction, greatly improving the breakdown voltage of the semiconductor device 100.

[0168] In summary, the electronic device provided in this application includes an integrated circuit 1, which includes a semiconductor device 100. The semiconductor device 100 includes a first III-V transistor 10, a second III-V transistor 20, and a substrate 30. The substrate 30 includes a base 33, a first doped layer 31, and a second doped layer 32. The first doped layer 31 and the second doped layer 32 are disposed on the base 33. The second doped layer 32 is connected to the periphery of the first doped layer 31. The first doped layer 31 includes a first surface 31a facing away from the base 33. The second doped layer 32 includes a second surface 32a facing away from the base 33. The first doped layer 31 is of a first doping type, and the second doped layer 32 is of a second doping type. A first III-V transistor 10 is disposed on a first surface 31a, and a second III-V transistor 20 is disposed on a second surface 32a. The first III-V transistor 10 and the second III-V transistor 20 are isolated by a trench 100a located above the transition region at the junction of the first doped layer 31 and the second doped layer 32. The periphery of the first surface 31a exposes the first III-V transistor 10. Therefore, a PN junction is formed at the junction of the first doped layer 31 and the second doped layer 32. When the semiconductor device is operating, this PN junction is reverse biased, and no current flows between the first doped layer 31 and the second doped layer 32. No leakage current occurs between the first III-V transistor 10 and the second III-V transistor 20, thus enabling the semiconductor device 100 to operate normally. Furthermore, the exposure of the first III-V transistor 10 at the periphery of the first surface 31a prevents leakage current between the first III-V transistor 10 and the second doped layer 32 caused by direct connection between the first III-V transistor 10 and the second doped layer 32.

[0169] Please see Figure 22 , Figure 22 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 22 The semiconductor device 100 shown and Figure 4 The difference between the semiconductor device 100 shown is that the structure of the substrate 30 is different. Figure 22 The semiconductor device 100 shown and Figure 4 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 4 The relevant descriptions will not be repeated here.

[0170] Specifically, the substrate 30 includes a base 33 and a doped layer 38, with the base 33 connecting the peripheral side surface and the bottom surface of the doped layer 38. The doped layer 38 includes a first top surface 38a, which is disposed opposite to the bottom surface of the doped layer 38, and the peripheral side surface of the doped layer 38 is connected to both the first top surface 38a and the bottom surface of the doped layer 38. The base 33 includes a second top surface 33a, with the first top surface 38a and the second top surface 33a facing the same direction, and the first top surface 38a and the second top surface 33a are connected and flush. A first III-V transistor 10 is disposed on the first top surface 38a, and a second III-V transistor 20 is disposed on the second top surface 33a. The first III-V transistor 10 and the second III-V transistor 20 are isolated by a trench 100a, which is located above the transition region 30a between the base 33 and the doped layer 38.

[0171] It should be noted that the boundary region between the substrate 33 and the doped layer 38 in the lateral direction (X-axis direction) is the transition region 30a. That is, the transition region 30a is a part where the substrate 33 and the doped layer 38 are close to each other in the lateral direction. The transition region 30a contains both a part of the substrate 33 and a part of the doped layer 38. Figure 22 The position of the transition region 30a is illustrated by a dashed line.

[0172] The periphery of the first top surface 38a exposes the first III-V transistor 10, meaning that the periphery of the doped layer 38 is not connected to the first semiconductor layer 11, while the portion of the doped layer 38 other than the periphery is connected to the first semiconductor layer 11. In other words, the orthographic projection of the periphery of the first top surface 38a onto the substrate 33 surrounds the orthographic projection of the first III-V transistor 10 onto the substrate 33. A dielectric layer 40 is disposed between the periphery of the first top surface 38a and the second top surface 33a.

[0173] In this design, the doped layer 38 is of the first doping type, and the substrate 33 is of the second doping type. The junction between the doped layer 38 and the substrate 33 forms a PN junction.

[0174] In an exemplary embodiment, the doped layer 38 is formed by implanting ions into the substrate 33.

[0175] It should be noted that in the third embodiment, the doping concentration of the substrate 33 is greater than that of the second doped layer 32. Because the doping concentration of the substrate 33 is greater than that of the second doped layer 32, the reverse breakdown voltage of the PN junction at the junction of the first doped layer 31 and the second doped layer 32 is greater than the reverse breakdown voltage of the PN junction at the junction of the doped layer 38 and the substrate 33. That is... Figure 4 The semiconductor device shown is 100 times Figure 22The semiconductor device 100 shown is more voltage-resistant. Therefore, depending on the size of the power supply Vin to which the semiconductor device 100 is connected, the first doped layer 31 can be formed within the second doped layer 32 or the doped layer 38 can be formed within the substrate 33.

[0176] Please see Figure 23 , Figure 23 This is a schematic diagram of the second layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 23 The semiconductor device 100 shown and Figure 22 The difference in the semiconductor device 100 shown is that the substrate 30 also includes a first variable doping region 34. Figure 23 The semiconductor device 100 shown and Figure 22 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 21 The relevant descriptions will not be elaborated here.

[0177] The first variable doping region 34 is disposed around the periphery of the doped layer 38. In the direction from the doped layer 38 to the substrate 33 (the direction from the center of the doped layer 38 to the periphery of the doped layer 38), the doping concentration of the first variable doping region 34 gradually decreases. The first variable doping region 34 is a variation lateral doping (VLD) and is the first doping type.

[0178] It should be noted that the overall doping concentration of the first variable doped region 34 decreases in the direction from the doped layer 38 to the substrate 33. Since the first variable doped region 34 is formed by implanting ions in multiple spaced implantation regions, the doping concentration between two adjacent implantation regions is greater than the concentration of those two implantation regions. That is, the doping concentration of the first variable doped region 34 fluctuates to a certain extent between two adjacent implantation regions and between those two adjacent implantation regions.

[0179] Understandably, the above description of the PN junction formed at the interface between the doped layer 38 and the substrate 33 avoids leakage current between the doped layer 38 and the substrate 33 caused by the potential of the doped layer 38 being greater than that of the substrate 33. However, if the potential difference between the doped layer 38 and the substrate 33 is greater than the reverse breakdown voltage of the PN junction, the PN junction will be reverse-broken down. Therefore, by forming a first variable doping region 34 around the periphery of the doped layer 38, the first variable doping region 34 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0180] In an exemplary embodiment, the surface of the first variable-doped region 34 facing away from the doped layer 38 is connected to the substrate 33. The top surface of the first variable-doped region 34 is connected to both the first top surface 38a and the second top surface 33a, and the top surface of the first variable-doped region 34 is aligned with both the first top surface 38a and the second top surface 33a.

[0181] In an exemplary embodiment, the first variable-doped region 34 is formed by an ion implantation process. The first variable-doped region 34 and the doped layer 38 can be formed together in a single ion implantation process.

[0182] Please see Figure 24 , Figure 24 This is a schematic diagram of the third layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 24 The semiconductor device 100 shown and Figure 22 The difference in the semiconductor device 100 shown is that the substrate 30 also includes at least one first guard ring 35. Figure 24 The semiconductor device 100 shown and Figure 22 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 22 The relevant descriptions will not be elaborated here.

[0183] Specifically, at least one first guard ring 35 is disposed within the substrate 33, at least one first guard ring 35 is disposed around the periphery of the doped layer 38, and each first guard ring 35 is spaced apart from the doped layer 38, and the first guard ring 35 is of the first doping type.

[0184] The depth of the first guard ring 35 is equal to the depth of the doped layer 38. The substrate 33 connects the inner side, outer side and bottom surface of the first guard ring 35, and the top surface of the first guard ring 35 exposes the second top surface 33a. The top surface of the first guard ring 35 is connected to the dielectric layer 40.

[0185] For example, there may be one first guard ring 35, which is disposed around the periphery of the doped layer 38 and spaced apart from it. Alternatively, there may be multiple first guard rings 35, stacked and arranged around the periphery of the doped layer 38, i.e., in a direction from the center of the doped layer 38 to its periphery, with the multiple first guard rings 35 arranged sequentially. The multiple first guard rings 35 are spaced apart from each other and from the doped layer 38. A substrate 33 is disposed between the first guard ring 35 closest to the doped layer 38 and the doped layer 38, and a substrate 33 is disposed between two adjacent first guard rings 35.

[0186] Understandably, by forming at least one first guard ring 35 on the periphery of the doped layer 38, the first guard ring 35 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0187] In an exemplary embodiment, the first guard ring 35 is formed by an ion implantation process. The first guard ring 35 and the doped layer 38 can be formed together in a single ion implantation process.

[0188] Please see Figure 25 , Figure 25 This is a schematic diagram of the fourth layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 25 The semiconductor device 100 shown and Figure 22 The difference in the semiconductor device 100 shown is that the semiconductor device 100 also includes a field plate 80. Figure 25 The semiconductor device 100 shown and Figure 22 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 22 The relevant descriptions will not be repeated here.

[0189] Specifically, the field plate 80 is disposed on the surface of the dielectric layer 40 opposite to the first top surface 38a, the surface of the dielectric layer 40 opposite to the second top surface 33a, the surface of the dielectric layer 40 opposite to the peripheral side surface of the first semiconductor layer 11, the surface of the first semiconductor layer 11 opposite to the doped layer 38, and extends to the first source 15. Figure 25 The field plate 80 and the first source 15 are distinguished by dashed lines. The dielectric layer 40 is used to insulate the field plate 80 from the substrate 33.

[0190] In an exemplary embodiment, the periphery of the field plate 80 protrudes from the periphery of the first top surface 38a. That is, in the Z-axis direction, no doped layer 38 is disposed below the periphery of the field plate 80, but a doped layer 38 is disposed below the portion of the field plate 80 other than the periphery. The field plate 80 is spaced apart from the second III-V transistor 20, that is, the orthographic projection of the field plate 80 in the Z-axis direction is spaced apart from the orthographic projection of the second semiconductor layer 21 in the Z-axis direction. The field plate 80 is connected to and electrically connected to the first source 15, and the field plate 80 is electrically connected to the doped layer 38 through the first source 15 and the first conductor 50. The potential of the field plate 80 is the same as the potential of the doped layer 38.

[0191] Understandably, since the potential of the field plate 80 is the same as that of the doped layer 38, the PN junction will extend below the field plate 80. That is, the field plate 80 increases the width of the PN junction, thereby increasing the reverse breakdown voltage of the PN junction and improving the withstand voltage of the semiconductor device 100.

[0192] Please see Figure 26 , Figure 26 This is a schematic diagram of the fifth layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 26 The semiconductor device 100 shown and Figure 25The difference in the semiconductor device 100 shown is that the substrate 30 further includes a first variable doping region 34, i.e. Figure 26 The semiconductor device 100 shown includes a field plate 80 and a first variable doping region 34. Figure 26 The semiconductor device 100 shown and Figure 25 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 25 The relevant descriptions will not be repeated here.

[0193] Specifically, the orthographic projection of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable-doped region 34 onto the substrate 33. The orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable-doped region 34 onto the substrate 33. Alternatively, the periphery of the field plate 80 protrudes beyond the periphery of the first variable-doped region 34.

[0194] Understandably, the field plate 80 causes a PN junction to form within the second doped layer 32 beneath it. The orthographic projection of the periphery of the field plate 80 onto the substrate 33 coincides with the orthographic projection of the first variable doped region 34 onto the substrate 33. Alternatively, the periphery of the field plate 80 protrudes beyond the periphery of the first variable doped region 34. The field plate 80 further expands the width of the PN junction around the first variable doped region 34. Through the combination of the field plate 80 and the first variable doped region 34, the reverse breakdown voltage of the PN junction is significantly increased, greatly improving the breakdown voltage of the semiconductor device 100.

[0195] Please see Figure 27 , Figure 27 This is a schematic diagram of the sixth layer structure of the semiconductor device disclosed in the fifth embodiment of this application. Figure 27 The semiconductor device 100 shown and Figure 25 The difference in the semiconductor device 100 shown is that the substrate 30 further includes at least one first guard ring 35. Figure 27 The semiconductor device 100 shown and Figure 25 For a description of the semiconductor device 100 shown where the structure is identical, please refer to [link to description]. Figure 25 The relevant descriptions will not be repeated here.

[0196] Specifically, the field plate 80 is located above each of the first guard rings 35. The periphery of the field plate 80 protrudes beyond the outer side of the first guard ring 35 furthest from the doped layer 38; that is, at least one first guard ring 35 is spaced apart on the periphery of the doped layer 38, and the periphery of the field plate 80 protrudes beyond the outermost first guard ring 35. In other words, in the Z-axis direction, there is no first guard ring 35 below the periphery of the field plate 80; the first guard ring 35 and the doped layer 38 are located below the portion of the field plate 80 excluding the periphery.

[0197] The combination of the field plate 80 and the first protection ring 35 significantly increases the reverse breakdown voltage of the PN junction, thereby greatly improving the withstand voltage of the semiconductor device 100.

[0198] In summary, the electronic device provided in this application includes an integrated circuit 1, which includes a semiconductor device 100. The semiconductor device 100 includes a first III-V transistor 10, a second III-V transistor 20, and a substrate 30. The substrate 30 includes a base 33 and a doped layer 38. The base 33 is connected to the periphery of the doped layer 38. The doped layer 38 includes a first top surface 38a, and the base 33 includes a second top surface 33a. The first top surface 38a and the second top surface 33a have the same orientation. The doped layer 38 is of a first doping type, and the base 33 is of a second doping type. The first III-V transistor 10 is disposed on the first top surface 38a, and the second III-V transistor 20 is disposed on the second top surface 33a. The first III-V transistor 10 and the second III-V transistor 20 are isolated by a trench 100a. The trench 100a is located above the transition region at the junction of the base 33 and the doped layer 38, and the periphery of the first top surface 38a exposes the first III-V transistor 10. The periphery of the doped layer 38 has a first variable doping region 34. The concentration of the first variable doping region 34 decreases from the doped layer 38 towards the first variable doping region 34, which is a first doping type. Therefore, a PN junction is formed at the boundary between the first doped layer 31 and the second doped layer 32. When the semiconductor device is operating, this PN junction is reverse biased, and no current flows between the first doped layer 31 and the second doped layer 32. No leakage current occurs between the first III-V transistor 10 and the second III-V transistor 20, thus enabling the semiconductor device 100 to operate normally. Furthermore, by forming the first variable doping region 34 at the periphery of the doped layer 38, the width of the PN junction is increased, thereby raising the reverse breakdown voltage of the PN junction and improving the breakdown voltage of the semiconductor device 100.

[0199] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A semiconductor device, characterized in that, The device includes a first III-V transistor, a second III-V transistor, and a substrate. The substrate includes a base, a first doped layer, and a second doped layer. The first doped layer and the second doped layer are disposed on the base. The second doped layer is connected to the periphery of the first doped layer. The first doped layer includes a first surface facing away from the base. The second doped layer includes a second surface facing away from the base. The first doped layer is of a first doping type, and the second doped layer is of a second doping type. The first III-V transistor is disposed on the first surface, and the second III-V transistor is disposed on the second surface. A trench is provided between the first III-V transistor and the second III-V transistor. The trench is located above the transition region at the junction of the first doped layer and the second doped layer. The periphery of the first surface surrounds the orthographic projection of the first III-V transistor on the substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The first doped layer is a well region, and the second doped layer is an epitaxial layer; The periphery of the first doped layer has a first variable doping region. The doping concentration of the first variable doping region decreases in the direction from the first doped layer to the second doped layer. The first variable doping region is a first doping type.

3. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes a dielectric layer disposed above the transition region; The semiconductor device further includes a field plate disposed above the dielectric layer. The periphery of the field plate, when projected onto the substrate, coincides with the projected onto the substrate of the first variable doped region, or the periphery of the field plate protrudes beyond the periphery of the first variable doped region.

4. The semiconductor device as claimed in claim 1, characterized in that, The first doped layer is a well region, and the second doped layer is an epitaxial layer; The substrate further includes at least one first guard ring, which is disposed within the second doped layer. The first guard ring is disposed around the periphery of the first doped layer and is spaced apart from the first doped layer. The first guard ring is of a first doping type.

5. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device further includes a dielectric layer disposed above the transition region; The semiconductor device further includes a field plate disposed above the dielectric layer, and the periphery of the field plate protrudes from the periphery of the first protective ring furthest from the first doped layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The first doped layer is an epitaxial layer, and the second doped layer is a well region; The periphery of the first doped layer has a second variable doping region. The doping concentration of the second variable doping region increases in the direction from the first doped layer to the second doped layer. The second variable doping region is a second doping type.

7. The semiconductor device as claimed in claim 6, characterized in that, The semiconductor device further includes a dielectric layer disposed above the transition region; The semiconductor device further includes a field plate disposed above the dielectric layer. The field plate's orthographic projection onto the substrate coincides with the orthographic projection of the second variable doping region onto the substrate, or the periphery of the field plate protrudes beyond the periphery of the second variable doping region.

8. The semiconductor device as claimed in claim 1, characterized in that, The first doped layer is an epitaxial layer, and the second doped layer is a well region; The substrate further includes at least one second guard ring, which is disposed within the first doped layer. The orthogonal projection of each second guard ring onto the substrate is spaced apart from the orthogonal projection of the first III-V transistor onto the substrate. The second guard ring is also spaced apart from the substrate. The second guard ring is of a second doping type.

9. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor device further includes a dielectric layer disposed above the transition region; The semiconductor device further includes a field plate disposed above the dielectric layer, the field plate having a periphery protruding from the periphery of the first doped layer.

10. The semiconductor device according to any one of claims 6-9, characterized in that, The depth of the second doped layer is greater than the depth of the first doped layer.

11. The semiconductor device according to any one of claims 1-9, characterized in that, The first III-V transistor includes a first semiconductor layer, a first gate, a first source, and a first drain. The first gate, the first source, and the first drain are disposed on a surface of the first semiconductor layer, and the surface of the first semiconductor layer opposite to the first gate is connected to the first surface. The semiconductor device further includes a first conductor disposed inside the first semiconductor layer, and the first conductor is connected to the first source electrode and the first doped layer respectively.

12. The semiconductor device as claimed in claim 11, characterized in that, The second III-V transistor includes a second semiconductor layer, a second gate, a second source, and a second drain. The second gate, the second source, and the second drain are disposed on a surface of the second semiconductor layer, and the surface of the second semiconductor layer opposite to the second gate is connected to the second surface. The semiconductor device further includes a second conductor disposed inside the second semiconductor layer, and the second conductor is connected to the second source electrode and the second doped layer, respectively.

13. A semiconductor device, characterized in that, The device includes a first III-V transistor, a second III-V transistor, and a substrate. The substrate includes a base and a doped layer. The base is connected to the periphery of the doped layer. The doped layer includes a first top surface, and the base includes a second top surface. The first top surface and the second top surface have the same orientation. The doped layer is a well region. The doped layer is of a first doping type, and the base is of a second doping type. The first III-V transistor is disposed on the first top surface, and the second III-V transistor is disposed on the second top surface. A trench is provided between the first III-V transistor and the second III-V transistor. The trench is located above the transition region at the junction of the substrate and the doped layer. The periphery of the first top surface surrounds the orthographic projection of the first III-V transistor on the substrate. The periphery of the doped layer has a first variable doping region. The concentration of the first variable doping region decreases in the direction from the doped layer to the substrate. The first variable doping region is a first doping type.

14. The semiconductor device as claimed in claim 13, characterized in that, The semiconductor device further includes a dielectric layer disposed above the transition region; The semiconductor device further includes a field plate disposed above the dielectric layer. The periphery of the field plate, when projected onto the substrate, coincides with the projected onto the substrate of the first variable doped region, or the periphery of the field plate protrudes beyond the periphery of the first variable doped region.

15. An integrated circuit, characterized in that, It includes electronic devices and semiconductor devices as described in any one of claims 1-14, wherein the semiconductor device is electrically connected to the electronic devices.

16. An electronic device, characterized in that, The device includes a circuit board and an integrated circuit as described in claim 15, wherein the integrated circuit is disposed on the circuit board and connected to the circuit board.

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