Radiation resistant gan high electron mobility transistor with high voltage and current continuation capability and method of fabrication

Abstract

This invention discloses a radiation-resistant GaN high electron mobility transistor with freewheeling and high voltage withstand capability, and its fabrication method, mainly addressing the problems of insufficient built-in freewheeling paths, low voltage withstand capability, and weak radiation resistance in existing GaN power devices. It includes a substrate, a buffer layer, a channel layer, a barrier layer, a p-GaN gate, a passivation layer, a Schottky layer, and source, drain, and gate electrodes. Multiple vertically spaced p-GaN regions are arranged on the right side of the Schottky layer, forming a diode with the underlying barrier layer and channel layer, and forming a lateral superjunction structure with the two-dimensional electron gas in the channel layer. An ohmic contact metal layer is provided on this region to achieve electrical connection of the p-GaN regions. A source field plate is provided on the source electrode, Schottky metal layer, and ohmic contact metal layer, and the three are electrically connected in parallel. This invention can synergistically achieve built-in dual-diode freewheeling, superjunction voltage withstand, and distributed hole collection and extraction, improving device efficiency, breakdown voltage, and single-particle burn-out threshold, and can be used in radiation environments with high voltage withstand and reverse freewheeling.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and in particular to a radiation-resistant GaN high electron mobility transistor with freewheeling and high voltage withstand capability, which can be used in radiation environments with high voltage withstand and reverse freewheeling. Background Technology

[0002] GaN high electron mobility transistors (HEP transistors) have been widely used in many high-frequency, high-power applications due to their excellent material properties. However, their application in more demanding fields such as aerospace, high-reliability industrial drives, and automotive electric drives still faces fundamental technical bottlenecks. Because the devices themselves lack a body diode similar to silicon-based MOSFETs, the dead time in topologies such as bridge circuits must rely on external discrete diodes or complex driving timings to construct a freewheeling path. This increases system size, cost, and conduction losses, limiting further improvements in efficiency and power density. Simultaneously, the electric field concentration at the gate edge of traditional planar gate structures under high voltages easily leads to local breakdown and hot carrier effects, which not only restricts the operating voltage but also introduces reliability issues such as dynamic resistance degradation. Furthermore, in radiated environments, the accumulation of holes induced by high-energy particles can trigger parasitic bipolar transistor effects or gate dielectric damage, leading to single-particle burnout or parameter drift, seriously threatening the long-term reliable operation of the system.

[0003] Patent application number 202211104081.0 discloses a P-GaN-enhanced gallium nitride high electron mobility transistor with resistance to single-particle burn-out. It achieves this by introducing a separate Schottky metal layer above the barrier layer between the gate and drain fields, and placing an N-type transistor below it. + In the doped region, the primary function of the Schottky metal layer is as a hole collector to absorb holes generated by radiation, thereby increasing the single-particle burn-off threshold voltage of the device. However, its single function cannot meet the system-level requirement for built-in freewheeling, necessitating external freewheeling devices in applications, which limits system efficiency, power density, and reliability. Furthermore, this approach, by introducing an independent metal structure, can only generate minor perturbations to the local electric field, failing to address the fundamental physical issue of lateral electric field concentration inherent in traditional planar structures. Its breakdown voltage capability still relies on conventional field plate technology, lacking advanced mechanisms such as charge compensation, resulting in a very limited improvement in breakdown voltage and failing to overcome the bottleneck of high-voltage applications. Moreover, its radiation resistance mechanism relies on an isolated, limited-area Schottky metal block to collect holes, leading to low collection efficiency. Additionally, the low-impedance connection path between this metal block and the source is unclear, resulting in slow and limited hole extraction. Summary of the Invention

[0004] The purpose of this invention is to address the problems of the prior art by proposing a radiation-resistant GaN high electron mobility transistor with freewheeling and high voltage withstand capability, and a method for its fabrication, so as to simultaneously realize built-in freewheeling, high voltage withstand and radiation resistance functions on a single device, thereby greatly improving the efficiency, density and reliability of power systems.

[0005] The technical approach to achieve the objective of this invention is as follows: multiple longitudinally spaced p-GaN regions and Schottky metal regions are constructed in the drift region between the gate electrode and the drain electrode of the device to form pin diodes and Schottky diodes, respectively, and connected in parallel to the source electrode through the source field plate to achieve dynamic freewheeling during reverse conduction; at the same time, by forming a lateral superjunction between the two-dimensional electron gas of the p-GaN region and the channel layer, the electric field is homogenized to compensate for the charge, which significantly improves the breakdown voltage; in addition, radiation-induced holes are collected by the distributed p-GaN regions and the Schottky metal regions and rapidly discharged through the low-resistivity path of the field plate to effectively suppress single-particle burn-out.

[0006] Based on the above ideas, the technical solution of the present invention includes the following:

[0007] 1. A radiation-resistant GaN high electron mobility transistor with freewheeling capability and high voltage withstand capability, comprising a substrate, a buffer layer, a channel layer, a barrier layer, a p-GaN gate, a passivation layer, a Schottky metal layer, a source electrode, a drain electrode, and a gate electrode, characterized in that:

[0008] The Schottky metal layer has multiple vertically spaced p-GaN regions on its right side. The p-GaN regions, together with the barrier layer and the channel layer below, form a pin diode. The p-GaN regions also form a lateral superjunction structure with the two-dimensional electron gas in the channel layer.

[0009] An ohmic contact metal layer is provided on the left side of the upper surface of the p-GaN region to realize the electrical connection of the p-GaN region;

[0010] A source field plate is provided above the Schottky metal layer, the ohmic contact metal layer and the source electrode to electrically connect the Schottky metal layer and the ohmic contact metal layer to the source electrode, so as to synergistically realize the device's freewheeling, withstand voltage and radiation resistance functions.

[0011] Furthermore, the Mg doping concentration in the p-GaN region is 1×10⁻⁶. 19 cm -3 ~5×10 19 cm -3 With a thickness of 50nm~200nm, it is used to form the p-region of the pin diode to achieve reverse freewheeling, while achieving charge balance with the two-dimensional electron gas in the channel layer to adjust the electric field, and serving as an efficient trap to collect radiation-induced holes.

[0012] Furthermore, the ohmic contact metal layer is a Ni / Au or Pt / Au metal stack structure, used to form a low-resistance ohmic contact on the surface of the p-GaN region.

[0013] Furthermore, the Schottky metal layer and the barrier layer form a Schottky diode;

[0014] Furthermore, the source field plate is a metal stack formed of one or more of Ti, Au, Al, Ni, and Pt, which is used to connect the Schottky diode and the pin diode in parallel to provide a bidirectional freewheeling path; and clamp the potential of the p-GaN region to the same potential as the source electrode to stabilize the electric field distribution of the lateral superjunction; at the same time, it provides a low-resistance collection path to the source electrode for radiation-induced holes to enhance the radiation resistance of the device.

[0015] 2. A method for fabricating a radiation-resistant GaN high electron mobility transistor with freewheeling capability and high voltage withstand capability, characterized in that it comprises:

[0016] S1) Select a substrate and clean it to obtain a clean epitaxial growth surface;

[0017] S2) On the cleaned substrate surface, a buffer layer, a channel layer, a barrier layer and a p-GaN cap layer are grown sequentially by metal-organic chemical vapor deposition (MOCVD).

[0018] S3) Using photolithography and inductively coupled plasma (ICP) technology, the p-GaN cap layer is selectively etched to simultaneously form a long strip-shaped p-GaN gate located on the left edge of the device and multiple vertically spaced p-GaN regions located in the right region of the p-GaN gate.

[0019] S4) Using an electron beam evaporation deposition apparatus, Ti / Al / Ni / Au metal stacks are deposited on the left and right sides of the upper surface of the barrier layer, and then rapidly thermally annealed to form the source and drain electrodes.

[0020] S5) Using an electron beam evaporation deposition apparatus, Ni / Au or Pt / Au metal stacks are deposited sequentially on the left side of the upper surface of the p-GaN region, the upper surface of the p-GaN gate, and the upper surface of the barrier layer on the right side of the p-GaN gate to form an ohmic contact metal layer, a gate electrode, and a Schottky metal layer, respectively.

[0021] S6) A SiO2 or Si3N4 dielectric layer is grown on the entire sample surface as a passivation layer using plasma-enhanced chemical vapor deposition (PECVD).

[0022] S7) Using inductively coupled plasma etching (ICP) technology, the passivation layer on the source electrode, drain electrode, Schottky metal layer and ohmic contact metal layer is etched away.

[0023] S8) Using an electron beam evaporation deposition apparatus, metal is deposited on the left side of the passivation layer as a source field plate to connect the source electrode, the Schottky metal layer and the ohmic contact metal layer, thus completing the device fabrication.

[0024] Compared with existing methods, the present invention has the following advantages:

[0025] Firstly, compared to existing technologies that only make local improvements to a single performance characteristic, this invention adopts a structure that integrates a Schottky metal region and a vertically arranged p-GaN region within the gate-drain drift region, and connects them in parallel through a source field plate. On the one hand, the parallel Schottky diode and pin diode allow current to preferentially flow through the low-current Schottky diode under low current conditions, while the pin diode conducts to share the current under high current or surge conditions, achieving efficient and reliable built-in freewheeling and eliminating dependence on external discrete devices. On the other hand, the lateral superjunction formed by the p-GaN region and the two-dimensional electron gas in the channel uniformizes the lateral electric field through charge compensation, which can improve the breakdown voltage. At the same time, the distributed p-GaN region and the Schottky metal region together form an efficient hole collection network. Combined with the low-impedance field plate discharge path, it can significantly enhance the device's resistance to single-event burn-out, thereby achieving built-in freewheeling, high withstand voltage, and radiation resistance in a single device, greatly improving the efficiency, density, and reliability of the power system.

[0026] Secondly, this invention achieves high integration through a multifunctional design within the same physical structure. The p-GaN region simultaneously serves as the anode of the pin diode, the p-type pillar of the lateral superjunction, and the hole collector; the source field plate simultaneously achieves the parallel connection of the Schottky diode and the pin diode, the clamping effect to stabilize the superjunction potential, and the efficient outflow of holes. This reusable design structure allows the device to improve overall performance while maintaining good compatibility with existing GaN high electron mobility transistor manufacturing processes, providing a highly competitive solution for the monolithic, miniaturized, and low-cost production of high-performance, high-reliability power systems. Attached Figure Description

[0027] Figure 1 This is a 3D structural schematic diagram of the device of the present invention;

[0028] Figure 2 yes Figure 1 Top view;

[0029] Figure 3 yes Figure 1 The main view;

[0030] Figure 4 yes Figure 2 AA' section diagram;

[0031] Figure 5yes Figure 2 BB' cross-sectional view;

[0032] Figure 6 This is a schematic diagram illustrating the fabrication process of the device of the present invention. Detailed Implementation

[0033] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Reference Figure 1 , Figure 2 , Figure 3 This invention relates to a radiation-resistant GaN high electron mobility transistor with freewheeling and high voltage withstand capability, comprising a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a p-GaN gate 5, a passivation layer 6, a Schottky metal layer 7, a source electrode 8, a drain electrode 9, a gate electrode 10, a p-GaN region 11, an ohmic contact metal layer 12, and a source field plate 13, wherein:

[0035] The substrate 1 is any one of silicon, silicon carbide or sapphire substrate, and its thickness is 200μm~1000μm;

[0036] The buffer layer 2, located on the substrate 1, is made of at least one of AlN, AlGaN or GaN materials, and has a thickness of 0.5μm to 6μm. It can be used to alleviate lattice mismatch and thermal mismatch between the substrate and the nitride epitaxial layer.

[0037] The channel layer 3, located above the buffer layer 2, is made of unintentionally doped GaN material with a thickness of 100nm~300nm, and is used to provide a high-mobility two-dimensional electron gas conductive channel.

[0038] The barrier layer 4, located above the channel layer 3, is made of AlGaN material with a thickness of 8nm~30nm and an aluminum composition of 18%~30%. It is used to induce a high concentration of two-dimensional electron gas at the interface of the channel layer 3 through the polarization effect.

[0039] The p-GaN gate 5 is located on the left side of the upper surface of the barrier layer 4, with a thickness of 50 nm to 200 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 ;

[0040] The passivation layer 6 covers the upper surface of the barrier layer 4, excluding the areas of the source electrode 8, the source field plate 13, and the drain electrode 9, and is made of SiO2 or Si3N4 material.

[0041] The Schottky metal layer 7 is located to the right of the p-GaN gate 5, and its thickness is 50nm~200nm. It adopts a Ni / Au or Pt / Au metal stack, and forms a Schottky diode with the barrier layer 4.

[0042] The source electrode 8 is located on the left side of the upper surface of the barrier layer 4, and it is made of Ti / Al / Ni / Au metal stack.

[0043] The drain electrode 9 is located on the right side of the upper surface of the barrier layer 4, and it is made of Ti / Al / Ni / Au metal stack.

[0044] The gate electrode 10 is located on the upper surface of the p-GaN gate 5 and is made of Ni / Au or Pt / Au metal stack;

[0045] The p-GaN region 11 is located to the right of the Schottky metal layer 7, arranged longitudinally at intervals, with a duty cycle of 10% to 50%, and its length along the gate-drain direction accounts for 10% to 70% of the distance between the Schottky metal layer 7 and the drain electrode 9. The p-GaN region 11, together with the underlying barrier layer 4 and the channel layer 3, can form a pin diode. It can also form a lateral superjunction structure with the two-dimensional electron gas in the channel layer 3, and can serve as a hole collector. The relative positional relationship between the p-GaN region and the Schottky metal layer along the gate-drain direction is as follows: Figure 2 As shown, Figure 4 The longitudinal cross-sectional structure containing the p-GaN region is further shown, clearly demonstrating the composition of the pin diode and its spacing relationship with the Schottky diode region on the left. Figure 5 The structure of adjacent regions without p-GaN regions is shown. Figure 4 and Figure 5 These elements corroborate each other, fully characterizing the features of the longitudinally spaced arrangement. This layout, through structural reuse, collaboratively achieves reverse current flow, enhances withstand voltage, and improves hole collection and extraction capabilities within a single area.

[0046] The ohmic contact metal layer 12 is located on the left side of the upper surface of the p-GaN region 11. It is a Ni / Au or Pt / Au metal stack structure and is used to form a low-resistance ohmic contact on the surface of the p-GaN region.

[0047] The source field plate 13 is located above the Schottky metal layer 7, the ohmic contact metal layer 12 and the source electrode 8. It is a metal stack formed by one or more of Ti, Au, Al, Ni and Pt. The field plate electrically connects the Schottky metal layer and the ohmic contact metal layer on each p-GaN region to the source electrode (8), thereby connecting the Schottky diode and the pin diode in parallel to provide a bidirectional freewheeling path. At the same time, it clamps the potential of each p-GaN region to the same potential as the source electrode to stabilize the electric field distribution of the lateral superjunction and provides a low-resistance guiding path for radiation-induced holes to improve the radiation resistance of the device.

[0048] refer to Figure 6 This invention provides the following three embodiments for fabricating radiation-resistant GaN high electron mobility transistors with freewheeling capability and high voltage withstand capability:

[0049] Example 1: A 0.5 μm thick AlN buffer layer was fabricated on a 200 μm thick silicon substrate; the channel layer was 100 nm of unintentionally doped GaN; the barrier layer was 8 nm thick AlGaN with an Al composition of 18%; the p-GaN gate thickness was 50 nm, and the Mg doping concentration was 1 × 10⁻⁶. 19 cm -3 The Schottky metal layer is a 50 nm thick Ni / Au metal stack; the p-GaN region is 50 nm thick, and the Mg doping concentration is 1 × 10⁻⁶. 19 cm -3 A radiation-resistant GaN high electron mobility transistor with a longitudinal duty cycle of 10% and a length along the gate-drain direction that accounts for 10% of the drift region length.

[0050] Step 1: Select and clean the substrate.

[0051] A silicon substrate 1 with a thickness of 200 μm was selected and ultrasonically cleaned for 10 minutes each with acetone, ethanol and deionized water to remove organic and particulate contaminants. It was then dried with nitrogen to obtain a clean epitaxial growth surface.

[0052] Step 2: Epitaxially grow a buffer layer, a channel layer, a barrier layer, and a p-GaN layer.

[0053] 2.1) Under the conditions of a temperature of 1050℃, a reaction chamber pressure of 100 Torr, an ammonia flow rate of 4000 sccm, a trimethylaluminum flow rate of 120 sccm, and a hydrogen flow rate of 5000 sccm, an AlN buffer layer 2 with a thickness of 0.5 μm was epitaxially grown on a cleaned silicon substrate 1 by MOCVD process.

[0054] 2.2) Under the conditions of a temperature of 1020℃, a reaction chamber pressure of 150 Torr, a trimethylgallium flow rate of 150 sccm, an ammonia flow rate of 6000 sccm, and a hydrogen flow rate of 4000 sccm, a GaN channel layer 3 with a thickness of 100 nm was epitaxially grown on the AlN buffer layer 2 by MOCVD process.

[0055] 2.3) Under the conditions of a temperature of 1000℃, a reaction chamber pressure of 100 Torr, a trimethylgallium flow rate of 80 sccm, a trimethylaluminum flow rate of 12 sccm, an ammonia flow rate of 5000 sccm, and a hydrogen flow rate of 3000 sccm, an AlGaN barrier layer 4 with a thickness of 8 nm and an Al composition of 18% was epitaxially grown on the GaN channel layer 3 by MOCVD process.

[0056] 2.4) Under the conditions of a temperature of 950℃, a reaction chamber pressure of 200 Torr, a trimethylgallium flow rate of 100 sccm, a dicyclopentadienylmagnesium flow rate of 150 sccm, an ammonia flow rate of 8000 sccm, a nitrogen flow rate of 5000 sccm, and a hydrogen flow rate of 500 sccm, a 50 nm thick Mg doping concentration of 1×10⁻⁶ was epitaxially grown on AlGaN barrier layer 4 using MOCVD process. 19 cm -3 The p-GaN cap layer.

[0057] Step 3: Form the p-GaN gate and p-GaN region.

[0058] Under the conditions of a reaction chamber pressure of 1.5 Pa, an ICP power of 400 W, an RF bias power of 80 W, a chlorine flow rate of 45 sccm, a boron trichloride flow rate of 25 sccm, and an argon flow rate of 10 sccm, the p-GaN cap layer is selectively etched using inductively coupled plasma etching technology. Simultaneously, a long strip-shaped p-GaN gate 5 located on the left edge of the device and multiple longitudinally spaced p-GaN regions 11 located in the region on the right side of the p-GaN gate are formed. The longitudinal duty cycle of the p-GaN region is 10%, and its length along the gate-drain direction accounts for 10% of the drift region length.

[0059] Step 4: Prepare source and drain electrodes.

[0060] 4.1) Under the conditions of a current intensity of 150mA and a deposition rate of 0.5nm / s, an electron beam evaporation apparatus was used to deposit Ti / Al / Ni / Au metal stacks on the left and right sides of the upper surface of the barrier layer as source electrode 8 and drain electrode 9, respectively.

[0061] 4.2) After deposition, rapid thermal annealing is performed at 830°C for 30 seconds in a nitrogen atmosphere to form good ohmic contact.

[0062] Step 5: Prepare the gate electrode, Schottky metal layer, and p-GaN ohmic contact.

[0063] 5.1) Under the conditions of a current intensity of 100mA and a deposition rate of 0.3nm / s, an electron beam evaporation device is used to deposit a Ni / Au metal stack on the left side of the upper surface of the p-GaN region 11 to form an ohmic contact metal layer 12.

[0064] 5.2) Under the conditions of a current intensity of 100mA and a deposition rate of 0.3nm / s, an electron beam evaporation apparatus is used to deposit a Ni / Au metal stack on the upper surface of the p-GaN gate 5 to form the gate electrode 10;

[0065] 5.3) Under the conditions of a current intensity of 80mA and a deposition rate of 0.2nm / s, an electron beam evaporation device was used to deposit a Ni / Au metal stack on the upper surface of the barrier layer 4 on the right side of the p-GaN gate to form a Schottky metal layer 7.

[0066] 5.4) After deposition, rapid thermal annealing is performed at 650°C for 60 seconds in a nitrogen atmosphere.

[0067] Step 6: Deposit a passivation layer.

[0068] Under conditions of 280℃, 150Pa reaction chamber pressure, 30sccm silane flow rate, and 400sccm nitrous oxide flow rate, a SiO2 layer was grown as a passivation layer 6 on the entire sample surface using plasma-enhanced chemical vapor deposition.

[0069] Step 7: Open a hole in the passivation layer.

[0070] Under the conditions of a reaction chamber pressure of 1.5 Pa, a radio frequency power of 100 W, a carbon tetrafluoride flow rate of 40 sccm, and an oxygen flow rate of 5 sccm, the passivation layer covering the source electrode 8, drain electrode 9, Schottky metal layer 7, and ohmic contact metal layer 12 is removed using inductively coupled plasma etching technology.

[0071] Step 8: Prepare the source field plate.

[0072] Under conditions of a current intensity of 200mA and a deposition rate of 1.0nm / s, an electron beam evaporation apparatus was used to deposit a Ti / Au metal stack as a source field plate 13 on the left side of the upper surface of the passivation layer 6, the upper surface of the source electrode 8, the upper surface of the Schottky metal layer 7, and the upper surface of the ohmic contact metal layer 12, thus completing the device fabrication.

[0073] Example 2: A 3 μm thick AlGaN buffer layer was fabricated on a 650 μm thick sapphire substrate; the channel layer was 200 nm of unintentionally doped GaN; the barrier layer was 15 nm thick AlGaN with an Al composition of 22%; the p-GaN gate thickness was 100 nm, and the Mg doping concentration was 2 × 10⁻⁶. 19 cm -3 The Schottky metal layer is a 100 nm thick Ni / Au metal stack; the p-GaN region is 100 nm thick, and the Mg doping concentration is 2 × 10⁻⁶. 19 cm -3 This is a radiation-resistant GaN high electron mobility transistor with a longitudinal duty cycle of 30% and a length along the gate-drain direction that accounts for 50% of the drift region length.

[0074] Step A: Select and clean the substrate.

[0075] A sapphire substrate 1 with a thickness of 650 μm was selected and ultrasonically cleaned for 10 minutes each with acetone, ethanol and deionized water to remove organic and particulate contaminants. It was then dried with nitrogen to obtain a clean epitaxial growth surface.

[0076] Step B involves epitaxially growing a buffer layer, a channel layer, a barrier layer, and a p-GaN layer.

[0077] B1) An AlGaN buffer layer 2 with a thickness of 3 μm and an Al composition of 5% was epitaxially grown on a cleaned sapphire substrate 1 using MOCVD process. The process conditions were: temperature 1060℃, reaction chamber pressure 200 Torr, ammonia flow rate 5000 sccm, trimethylgallium flow rate 100 sccm, trimethylaluminum flow rate 10 sccm, and hydrogen flow rate 5000 sccm.

[0078] B2) A GaN channel layer 3 with a thickness of 200 nm was epitaxially grown on the AlGaN buffer layer 2 by MOCVD process. The process conditions were: temperature 1040℃, reaction chamber pressure 180 Torr, trimethylgallium flow rate 160 sccm, ammonia flow rate 6000 sccm, and hydrogen flow rate 4500 sccm.

[0079] B3) An AlGaN barrier layer 4 with a thickness of 15 nm and an Al composition of 22% was epitaxially grown on the GaN channel layer 3 by MOCVD process. The process conditions were: temperature 1010℃, reaction chamber pressure 120 Torr, trimethylgallium flow rate 100 sccm, trimethylaluminum flow rate 20 sccm, ammonia flow rate 5500 sccm, and hydrogen flow rate 3500 sccm.

[0080] B4) Using MOCVD, Mg-doped material with a concentration of 2×10⁻⁶ was epitaxially grown on AlGaN barrier layer 4. 19 cm-3 The p-GaN cap layer with a thickness of 100 nm was fabricated under the following conditions: temperature 970℃, reaction chamber pressure 220 Torr, trimethylgallium flow rate 120 sccm, dicyclopentadienylmagnesium flow rate 180 sccm, ammonia flow rate 9000 sccm, nitrogen flow rate 5000 sccm, and hydrogen flow rate 500 sccm.

[0081] Step C: Forming the p-GaN gate and p-GaN region.

[0082] Using inductively coupled plasma etching (ICP-C) technology, the p-GaN cap layer is selectively etched to simultaneously form an elongated p-GaN gate 5 located on the left edge of the device and multiple longitudinally spaced p-GaN regions 11 located on the right side of the p-GaN gate. The p-GaN region has a longitudinal duty cycle of 30% and its length along the gate-drain direction accounts for 50% of the drift region length. The process conditions are: reaction chamber pressure 1.8 Pa, ICP power 500 W, RF bias power 100 W, chlorine flow rate 60 sccm, boron trichloride flow rate 30 sccm, and argon flow rate 15 sccm.

[0083] Step D: Prepare the source and drain electrodes.

[0084] D1) Using an electron beam evaporation apparatus, Ti / Al / Ni / Au metal stacks were deposited on the left and right sides of the upper surface of the barrier layer as source electrode 8 and drain electrode 9, respectively. The process conditions were: current intensity 160mA, deposition rate 0.5nm / s.

[0085] D2) After deposition, rapid thermal annealing is performed at 850°C for 60 seconds in a nitrogen atmosphere to form good ohmic contact.

[0086] Step E: Prepare the gate electrode, Schottky metal layer, and p-GaN ohmic contact.

[0087] E1) Using an electron beam evaporation apparatus, a Ni / Au metal stack is deposited on the left side of the upper surface of the p-GaN region 11 to form an ohmic contact metal layer 12. The process conditions are: current intensity 110mA, deposition rate 0.35nm / s.

[0088] E2) Using an electron beam evaporation apparatus, a Ni / Au metal stack is deposited on the upper surface of the p-GaN gate 5 to form the gate electrode 10. The process conditions are: current intensity 110mA, deposition rate 0.35nm / s.

[0089] E3) Using an electron beam evaporation apparatus, a Ni / Au metal stack is deposited on the upper surface of the barrier layer 4 on the right side of the p-GaN gate to form a Schottky metal layer 7. The process conditions are: current intensity 90mA, deposition rate 0.25nm / s.

[0090] After E4 deposition, rapid thermal annealing was performed at 660°C for 60 seconds in a nitrogen atmosphere.

[0091] Step F: Deposit a passivation layer.

[0092] A SiO2 passivation layer 6 was grown on the entire sample surface using plasma-enhanced chemical vapor deposition. The process conditions were: temperature 290℃, reaction chamber pressure 160Pa, silane flow rate 35sccm, and nitrous oxide flow rate 450sccm.

[0093] Step G: Opening a hole in the passivation layer.

[0094] The passivation layer covering the source electrode 8, drain electrode 9, Schottky metal layer 7 and ohmic contact metal layer 12 was removed using inductively coupled plasma etching technology. The process conditions were: reaction chamber pressure 1.8 Pa, radio frequency power 110 W, carbon tetrafluoride flow rate 45 sccm, and oxygen flow rate 6 sccm.

[0095] Step H: Fabricate the source field plate.

[0096] Using an electron beam evaporation apparatus, a Ti / Au metal stack was deposited as the source field plate 13 on the left side of the passivation layer 6, the source electrode 8, the Schottky metal layer 7, and the ohmic contact metal layer 12. The process conditions were: current intensity 220mA, deposition rate 1.1nm / s, and the device fabrication was completed.

[0097] Example 3: A 6 μm thick GaN buffer layer was fabricated on a 1000 μm thick silicon carbide substrate; the channel layer was 300 nm of unintentionally doped GaN; the barrier layer was 30 nm thick AlGaN with an Al composition of 30%; the p-GaN gate thickness was 200 nm, and the Mg doping concentration was 5 × 10⁻⁶. 19 cm -3 The Schottky metal layer is a 200 nm thick Ni / Au metal stack; the p-GaN region is 200 nm thick, and the Mg doping concentration is 5 × 10⁻⁶. 19 cm -3 This is a radiation-resistant GaN high electron mobility transistor with a longitudinal duty cycle of 50% and a length along the gate-drain direction that accounts for 70% of the drift region length.

[0098] Step 1: Select and clean the substrate.

[0099] A silicon carbide substrate 1 with a thickness of 1000 μm was selected and ultrasonically cleaned for 10 minutes each with acetone, ethanol and deionized water to remove organic and particulate contaminants. It was then dried with nitrogen to obtain a clean epitaxial growth surface.

[0100] Step 2: Epitaxial growth of buffer layer, channel layer, barrier layer and p-GaN layer.

[0101] 2-1) Under the conditions of setting the temperature to 1080℃, the reaction chamber pressure to 300 Torr, the ammonia flow rate to 6000 sccm, the trimethylgallium flow rate to 200 sccm, and the hydrogen flow rate to 6000 sccm, a GaN buffer layer 2 with a thickness of 6 μm is epitaxially grown on the cleaned silicon carbide substrate 1 using the MOCVD process.

[0102] 2-2) Under the conditions of setting the temperature to 1050℃, the reaction chamber pressure to 200Torr, the trimethylgallium flow rate to 180sccm, the ammonia flow rate to 7000sccm, and the hydrogen flow rate to 5000sccm, a GaN channel layer 3 with a thickness of 300nm was epitaxially grown on the GaN buffer layer 2 using the MOCVD process.

[0103] 2-3) Under the conditions of setting the temperature to 1020℃, the reaction chamber pressure to 150 Torr, the trimethylgallium flow rate to 100 sccm, the trimethylaluminum flow rate to 30 sccm, the ammonia flow rate to 6000 sccm, and the hydrogen flow rate to 4000 sccm, an AlGaN barrier layer 4 with a thickness of 30 nm and an Al composition of 30% is epitaxially grown on the GaN channel layer 3 using the MOCVD process.

[0104] 2-4) Under the following conditions: temperature 980℃, reaction chamber pressure 250 Torr, trimethylgallium flow rate 150 sccm, dicyclopentadienylmagnesium flow rate 300 sccm, ammonia flow rate 10000 sccm, nitrogen flow rate 6000 sccm, and hydrogen flow rate 500 sccm, Mg doping concentration of 5×10⁻⁶ is epitaxially grown on AlGaN barrier layer 4 using MOCVD process. 19 cm -3 A p-GaN cap layer with a thickness of 200 nm.

[0105] Step 3: Form the p-GaN gate and p-GaN region.

[0106] Under the conditions of a reaction chamber pressure of 2.5 Pa, ICP power of 600 W, RF bias power of 150 W, chlorine flow rate of 80 sccm, boron trichloride flow rate of 40 sccm, and argon flow rate of 20 sccm, inductively coupled plasma etching technology is used to selectively etch the p-GaN cap layer, simultaneously forming a long strip-shaped p-GaN gate 5 located on the left edge of the device and multiple longitudinally spaced p-GaN regions 11 located in the region to the right of the p-GaN gate. The p-GaN region has a longitudinal duty cycle of 50%, and its length along the gate-drain direction accounts for 70% of the drift region length.

[0107] Step 4: Prepare source and drain electrodes.

[0108] 4-1) Under the conditions of a current intensity of 180mA and a deposition rate of 0.6nm / s, an electron beam evaporation device is used to deposit Ti / Al / Ni / Au metal stacks on the left and right sides of the upper surface of the barrier layer as the source electrode 8 and the drain electrode 9, respectively.

[0109] 4-2) After deposition, set the temperature to 870℃ and the time to 60 seconds, and perform rapid thermal annealing in a nitrogen atmosphere to form good ohmic contact.

[0110] Step 5: Fabricate the gate electrode, Schottky metal layer, and p-GaN ohmic contact.

[0111] 5-1) Under the conditions of a current intensity of 120mA and a deposition rate of 0.4nm / s, an electron beam evaporation device is used to deposit a Ni / Au metal stack on the left side of the upper surface of the p-GaN region 11 to form an ohmic contact metal layer 12.

[0112] 5-2) Under the conditions of a current intensity of 120mA and a deposition rate of 0.4nm / s, an electron beam evaporation device is used to deposit a Ni / Au metal stack on the upper surface of the p-GaN gate 5 to form the gate electrode 10.

[0113] 5-3) Under the conditions of a current intensity of 100mA and a deposition rate of 0.3nm / s, an electron beam evaporation device is used to deposit a Ni / Au metal stack on the upper surface of the barrier layer 4 on the right side of the p-GaN gate to form a Schottky metal layer 7.

[0114] 5-4) After deposition, set the temperature to 680℃ and the time to 60 seconds for rapid thermal annealing in a nitrogen atmosphere.

[0115] Step 6: Deposit a passivation layer.

[0116] Under the conditions of a temperature of 300℃, a reaction chamber pressure of 180Pa, a silane flow rate of 40sccm, and a nitrous oxide flow rate of 500sccm, a SiO2 layer was grown as a passivation layer 6 on the entire sample surface using plasma-enhanced chemical vapor deposition.

[0117] Step 7: Open holes in the passivation layer.

[0118] Under the conditions of a reaction chamber pressure of 2.0 Pa, RF power of 120 W, carbon tetrafluoride flow rate of 50 sccm, and oxygen flow rate of 8 sccm, inductively coupled plasma etching technology was used to remove the passivation layer covering the source electrode 8, drain electrode 9, Schottky metal layer 7, and ohmic contact metal layer 12.

[0119] Step 8: Prepare the source field plate.

[0120] Under conditions of a current intensity of 250mA and a deposition rate of 1.2nm / s, an electron beam evaporation apparatus was used to deposit a Ti / Au metal stack as the source field plate 13 on the left side of the upper surface of the passivation layer 6, the upper surface of the source electrode 8, the upper surface of the Schottky metal layer 7, and the upper surface of the ohmic contact metal layer 12, thus completing the device fabrication.

[0121] The above descriptions are merely a few specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. For example, the p-GaN region may use other p-type semiconductors such as p-type AlGaN or p-type InGaN, in addition to p-type GaN; the p-GaN region may use trapezoidal or transversely discontinuous stripes in addition to longitudinally spaced long stripes; the drain electrode and source electrode may use Ti / Al / Ni / Au, Ti / Al / Ti / Au, or Ti / Al / Ti / TiN in addition to Ti / Al / Ni / Au; the gate electrode, Schottky metal layer, and ohmic contact metal layer may use Mo / Au or W / Au in addition to Pt / Au and Ni / Au. However, these modifications and changes based on the present idea are still within the scope of the claims and protection of the present invention.

Claims

1. A radiation-resistant GaN high electron mobility transistor with freewheeling and high voltage withstand capability, comprising a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), a p-GaN gate (5), a passivation layer (6), a Schottky metal layer (7), a source electrode (8), a drain electrode (9), and a gate electrode (10), characterized in that: The Schottky metal layer (7) has multiple vertically spaced p-GaN regions (11) on its right side. The p-GaN regions together with the barrier layer (4) and the channel layer (3) below them form a pin diode. The p-GaN regions also form a lateral superjunction structure with the two-dimensional electron gas in the channel layer (3). An ohmic contact metal layer (12) is provided on the left side of the upper surface of the p-GaN region (11) to realize the electrical connection of the p-GaN region; A source field plate (13) is provided above the Schottky metal layer (7), the ohmic contact metal layer (12) and the source electrode (8) to electrically connect the Schottky metal layer and the ohmic contact metal layer to the source electrode in order to jointly realize the device's freewheeling, withstand voltage and radiation resistance functions.

2. The device according to claim 1, characterized in that: The p-GaN region (11) has a thickness of 50 nm to 200 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 , used to form the p region of the pin diode to achieve reverse freewheeling, while achieving charge balance with the two-dimensional electron gas in the channel layer (3) to adjust the electric field, and serving as an efficient trap to collect radiation-induced holes; The ohmic contact metal layer (12) is a Ni / Au or Pt / Au metal stack structure, used to form a low-resistance ohmic contact on the surface of the p-GaN region.

3. The device according to claim 1, characterized in that: The Schottky metal layer (7) and the barrier layer (4) form a Schottky diode; The source field plate (13) is a metal stack formed by one or more of Ti, Au, Al, Ni and Pt. It is used to connect the Schottky diode and the pin diode in parallel to provide a bidirectional freewheeling path. It also clamps the potential of the p-GaN region (11) to the same potential as the source electrode (8) to stabilize the electric field distribution of the lateral superjunction. At the same time, it provides a low-resistance collection path to the source electrode (8) for radiation-induced holes to enhance the radiation resistance of the device.

4. The device according to claim 1, characterized in that: The substrate (1) is any one of silicon, silicon carbide or sapphire substrate, and its thickness is 200μm~1000μm; The buffer layer (2) is located on the substrate (1) and is made of at least one of AlN, AlGaN or GaN materials. The thickness is 0.5μm~6μm. It can be used to alleviate the lattice mismatch and thermal mismatch between the substrate and the nitride epitaxial layer. The channel layer (3) is located above the buffer layer (2) and is made of GaN material with unintentional doping. The thickness is 100nm~300nm. It is used to provide a two-dimensional electron gas conductive channel with high mobility. The barrier layer (4), located above the channel layer (3), is made of AlGaN material with a thickness of 8nm~30nm and an aluminum composition of 18%~30%, and is used to induce a high concentration of two-dimensional electron gas at the interface of the channel layer (3) through polarization effect.

5. The device according to claim 1, characterized in that: The p-GaN gate (5) is located on the left side of the upper surface of the barrier layer (4), with a thickness of 50 nm to 200 nm and a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 ; The gate electrode (10) is located on the upper surface of the p-GaN gate (5) and is made of Ni / Au or Pt / Au metal stack; The Schottky metal layer (7) is located to the right of the p-GaN gate (5), and its thickness is 50nm~200nm. It is a Ni / Au or Pt / Au metal stack. The p-GaN region (11) is arranged longitudinally on the right side of the Schottky metal layer (7), with a duty cycle of 10% to 50%, and its length along the gate-drain direction accounts for 10% to 70% of the distance between the Schottky metal layer and the drain electrode.

6. The device according to claim 1, characterized in that: The source electrode (8) is located on the left side of the upper surface of the barrier layer (4), and it adopts a Ti / Al / Ni / Au metal stack. The drain electrode (9) is located on the right side of the upper surface of the barrier layer (4) and is made of Ti / Al / Ni / Au metal stack. The passivation layer (6) covers the upper surface of the barrier layer (4) except for the regions of the source electrode (8), the source field plate (13) and the drain electrode (9), and is made of SiO2 or Si3N4 material.

7. A method for fabricating a radiation-resistant GaN high electron mobility transistor with freewheeling capability and high voltage withstand capability, characterized in that, include: S1) Select a substrate (1) and clean it to obtain a clean epitaxial growth surface; S2) On the cleaned substrate surface, a buffer layer (2), a channel layer (3), a barrier layer (4) and a p-GaN cap layer are grown sequentially by metal-organic chemical vapor deposition (MOCVD). S3) Using photolithography and inductively coupled plasma (ICP) technology, the p-GaN cap layer is selectively etched to simultaneously form a long strip p-GaN gate (5) located on the left edge of the device and multiple longitudinally spaced p-GaN regions (11) located in the right region of the p-GaN gate. S4) Using an electron beam evaporation deposition apparatus, Ti / Al / Ni / Au metal stacks are deposited on the left and right regions of the upper surface of the barrier layer (4) and rapidly thermally annealed to form the source electrode (8) and drain electrode (9). S5) Using an electron beam evaporation deposition apparatus, Ni / Au or Pt / Au metal stacks are deposited sequentially on the left side of the upper surface of the p-GaN region (11), the upper surface of the p-GaN gate (5), and the upper surface of the barrier layer (4) on the right side of the p-GaN gate to form an ohmic contact metal layer (12), a gate electrode (10), and a Schottky metal layer (7), respectively. S6) A SiO2 or Si3N4 dielectric layer is grown on the entire sample surface as a passivation layer using plasma-enhanced chemical vapor deposition (PECVD) process (6). S7) Using inductively coupled plasma etching (ICP) technology, the passivation layer on the source electrode (8), drain electrode (9), Schottky metal layer (7) and ohmic contact metal layer (12) is etched away; S8) Using an electron beam evaporation deposition apparatus, metal is deposited on the left side of the passivation layer as a source field plate (13) to connect the source electrode (8), the Schottky metal layer (7) and the ohmic contact metal layer (12), thus completing the device fabrication.

8. The method according to claim 7, characterized in that, The metal-organic chemical vapor deposition (MOCVD) process used in S2) has the following process conditions: Temperature: 850℃~1150℃ Reaction chamber pressure: 50 Torr~500 Torr The flow rates of trimethylgallium, trimethylaluminum, and dicyclopentadienylmagnesium are all 0 sccm to 500 sccm. The flow rates of ammonia, hydrogen, and nitrogen are all 500 sccm to 10000 sccm.

9. The method according to claim 7, characterized in that, The inductively coupled plasma etching (ICP) technology used in S3) and S7) has the following process conditions: The pressure in the reaction chamber is 0.1 Pa to 40 Pa. ICP source power: 100W~2000W RF bias power: 20W~400W The flow rates of chlorine, boron trichloride, and argon were all between 10 sccm and 450 sccm.

10. The method according to claim 7, characterized in that: The electron beam evaporation deposition equipment used in S4), S5), and S8) has the following process conditions: Current intensity: 50mA~400mA Deposition rate: 0.1 nm / s ~ 2.0 nm / s; The plasma-enhanced chemical vapor deposition (PECVD) process used in S6) has the following process conditions: Temperature: 250~350℃ Reaction chamber pressure: 50Pa~200Pa The flow rates of silane, nitrous oxide, and ammonia are all between 0 sccm and 500 sccm. The flow rates of nitrogen and argon are both 0 sccm to 1000 sccm.

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