Method of forming a gate stack including a dielectric layer

Abstract

A method for forming a gate stack includes providing a substrate, optionally forming an interface layer, forming a dielectric layer, and optionally forming a dipole layer, wherein the dielectric layer includes hafnium, zirconium, and oxygen and at least one of silicon or aluminum.

Description

Technical Field

[0001] This disclosure generally relates to methods for forming electronic devices. More specifically, it describes methods for forming gate stacks suitable for use with transistors, as well as structures including gate stacks and examples of substrate processing apparatus for forming gate stacks including dielectric layers. Background Technology

[0002] Scaling of semiconductor devices has led to significant improvements in the speed and density of integrated circuits. However, scaling of semiconductor devices has also presented challenges. For example, during the formation of field-effect transistors such as metal-oxide-semiconductor field-effect transistors, forming gate stacks with dielectric layers (high-k materials) that maintain relatively high dielectric constants while maintaining relatively low equivalent oxide thickness (EOT) or capacitance equivalent thickness (CET) and leakage current has been challenging.

[0003] High-k materials can exhibit the desired electrical properties for the functionality of gate stacks. However, current high-k materials may not be able to exhibit the desired dielectric constant while maintaining other desired electrical properties (e.g., high bandgap) to allow for relatively low EOT or CET in the gate stack. Therefore, there is a need for improved dielectric layers and improved methods for forming dielectric layers and gate stacks that retain the desired properties and can be formed accurately and precisely.

[0004] Any discussion set forth in this section (including discussions of problems and solutions) is included in this disclosure and is for the purpose of providing background to this disclosure only. Such discussion should not be construed as an admission that any or all information was known at the time of making this invention or otherwise constitutes prior art. Summary of the Invention

[0005] This synopsis is provided to introduce some concepts in a simplified form. These concepts are further described in detail in the following detailed description of exemplary embodiments of this disclosure. This synopsis is not intended to necessarily identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] The various examples described herein provide a method for forming a gate stack and for forming a dielectric layer in the gate stack. The methods disclosed herein provide a gate stack with a dielectric layer having desired properties, such as a high dielectric constant (e.g., greater than 12) and a high bandgap (e.g., greater than about 5 eV or about 6 eV or greater than 8 eV), for use with a gate stack having a relatively low CET (e.g., less than 16 angstroms or less than 14 angstroms).

[0007] According to one or more embodiments, a method for forming a gate stack is provided, comprising forming a dielectric layer. An exemplary method includes providing a substrate in a reaction chamber. The exemplary method continues to form the dielectric layer by a cyclic deposition process. In some embodiments, the cyclic deposition method is an atomic layer deposition (ALD) method. In the exemplary method, forming the dielectric layer includes pulsed hafnium precursor multiple times, pulsed zirconium precursor at least once, pulsed additive precursor at least once, and pulsed oxygen reactant. In some embodiments, the additive precursor comprises a silicon precursor. In some embodiments, the additive precursor comprises an aluminum precursor.

[0008] In some embodiments, an interface layer is formed on the surface of a substrate. The interface layer may be formed, for example, by a cyclic deposition process or by oxidation of the substrate surface. In some embodiments, the interface layer comprises a semiconductor oxide, such as silicon oxide. In some embodiments, the interface layer comprises SiO2 or crystalline SiO2. In some embodiments, the thickness of the interface layer is about 2 to 10 angstroms, or about 2 to 7 angstroms.

[0009] In some embodiments, the dielectric layer is formed (e.g., directly) on the interface layer. In some embodiments, the dielectric layer is formed (e.g., directly) on the dipole layer. The dielectric layer may include hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer may also include aluminum. In some embodiments, the dielectric layer may include hafnium, zirconium, aluminum, and oxygen. In some embodiments, the dielectric layer includes zirconium-doped hafnium silicon oxide, zirconium-doped hafnium aluminum oxide, or zirconium-doped hafnium silicate. In some embodiments, the dielectric layer may include multiple sublayers. The dielectric layer may include sublayers of hafnium oxide, silicon oxide, aluminum oxide, and / or zirconium oxide. In some embodiments, the sublayer containing silicon oxide and / or aluminum oxide and the sublayer containing zirconium oxide are separated by at least one sublayer containing hafnium oxide. In some embodiments, the dielectric layer includes a first hafnium oxide sublayer, a silicon oxide sublayer or an aluminum oxide sublayer, a second hafnium oxide sublayer, and a zirconium oxide sublayer, wherein the silicon oxide sublayer or aluminum oxide sublayer and the zirconium oxide sublayer are not in direct contact with each other. The dielectric layer may include a hafnium oxide sublayer between each zirconium oxide sublayer and a silicon oxide sublayer or an aluminum oxide sublayer.

[0010] In some embodiments, the dielectric layer is or comprises a bilayer, and includes a first sublayer and a second sublayer. In some embodiments, the first sublayer comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the first sublayer is disposed (e.g., directly) on the interface layer. In some embodiments, the first sublayer is disposed (e.g., directly) on the dipole layer. In some embodiments, the second sublayer comprises zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, or zirconium silicate. In some embodiments, the second sublayer is disposed (e.g., directly) on the first sublayer.

[0011] In some embodiments, during dielectric layer formation, the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the additive precursor. In some embodiments, dielectric layer formation includes performing one or more first cycles. In some embodiments, the first cycle sequentially includes pulsed hafnium precursor to a first time period, pulsed additive precursor, pulsed hafnium precursor to a second time period, and pulsed zirconium precursor. In some embodiments, the zirconium precursor is not pulsed before the second time period in each first cycle. In some embodiments, the additive precursor is not pulsed before the first time period or after the second time period in each first cycle.

[0012] In some embodiments, during the formation of the dielectric layer, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1, or about 2.7:1 to about 3.5:1, or about 2.9:1 to about 3.2:1. The ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor in the first cycle may be in the range of about 1.5:1 to about 2.5:1, or about 1.7:1 to about 2.3:1, or about 1.9:1 to about 2.1:1. The ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle may be in the range of about 1.25:1 to 1.75:1, or about 1.4:1 to about 1.6:1.

[0013] In some embodiments, during the formation of the dielectric layer, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor is about 30:1 to about 7:1 or about 20:1 to about 10:1.

[0014] The precursors and reactants can be any suitable precursors or reactants. In some embodiments, the hafnium precursor comprises a hafnium halide or an organometallic hafnium precursor. In some embodiments, the zirconium precursor comprises a zirconium halide or an organometallic zirconium precursor. In some embodiments, the silicon precursor comprises a silane, a chlorosilane, an organosilane, a heterosilane, or a silicon halide. In some embodiments, the aluminum precursor comprises triethylaluminum (TEA), trimethylaluminum (TMA), dimethylaluminum hydride (DMAH), and aluminum chloride. In some embodiments, the oxygen reactant comprises one or more of any combination of H₂O, O₂, O₃, H₂O₂, NO, NO₂, or N₂O.

[0015] In some embodiments, the dielectric layer has a thickness between about 15 angstroms and about 25 angstroms, or between about 16 angstroms and about 20 angstroms, or between about 12 angstroms and about 16 angstroms. In some embodiments, the dielectric layer has a dielectric constant greater than about 12, or between about 12 and 30, or between about 12 and 24, or between about 12 and 15, or between about 18 and 22.

[0016] In some embodiments, the method includes forming a dipole layer. In some embodiments, the dipole layer comprises a metal oxide, a metal nitride, or a metal oxide nitride. In some embodiments, the dipole layer comprises lanthanum, aluminum, yttrium, scandium, and / or gallium. In some embodiments, the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide. In some embodiments, the dipole layer may be formed (e.g., directly) on a dielectric layer. In some embodiments, the dipole layer is directly disposed on a second sublayer of the dielectric layer. In some embodiments, the dielectric layer may be formed (e.g., directly) on the dipole layer, and the dipole layer may be formed (e.g., directly) on an interface layer. In some embodiments, the dipole layer may be formed between sublayers of the dielectric layer.

[0017] According to further examples of this disclosure, devices and / or devices comprising the structures described herein are formed using the methods described herein.

[0018] According to yet another exemplary embodiment of this disclosure, a system is provided for performing the methods described herein and / or for forming structures as described herein.

[0019] According to various other embodiments of the present disclosure, a method for forming a gate stack is provided, the method comprising: providing a substrate including a surface in a reaction chamber, the surface including an interface layer; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein forming the dielectric layer comprises: pulsed hafnium precursor multiple times, pulsed zirconium precursor at least once, pulsed additive precursor at least once, and pulsed oxygen reactant, wherein the additive precursor includes a silicon precursor or an aluminum precursor, and wherein the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the additive precursor.

[0020] In some embodiments, the dielectric layer includes a plurality of sublayers, including a first sublayer containing hafnium oxide, a second sublayer containing silicon oxide or aluminum oxide, a third sublayer containing hafnium oxide and a fourth sublayer containing zirconium oxide, wherein the second sublayer and the fourth sublayer are not in direct contact with each other.

[0021] In some embodiments, forming a dielectric layer includes performing a plurality of first cycles, wherein the first cycle sequentially includes: a pulsed hafnium precursor for a first time period, a pulsed additive precursor, a pulsed hafnium precursor for a second time period, and a pulsed zirconium precursor.

[0022] In some embodiments, the zirconium precursor is not pulsed before the second time period, and the additive precursor is not pulsed before the first time period or after the second time period in the first cycle.

[0023] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1.

[0024] In some embodiments, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 1.5:1 to about 2.5:1.

[0025] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle is in the range of about 1.25:1 to 1.75:1.

[0026] In some embodiments, the method further includes forming a dipole layer directly on the dielectric layer.

[0027] In some embodiments, the dipole layer includes lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0028] In some embodiments, the method further includes forming a dipole layer directly on the interface layer.

[0029] In some embodiments, the ratio of oxygen atoms to the sum of hafnium, zirconium, aluminum and silicon atoms is in the range of about 1.6:1 to about 2.5:1.

[0030] In some embodiments, the additive precursor includes a silicon precursor.

[0031] According to various other embodiments of the present disclosure, a method for forming a gate stack is provided, the method comprising: providing a substrate including a surface in a reaction chamber, the surface including an interface layer; and forming a dielectric layer on the interface layer by an atomic layer deposition process, wherein the dielectric layer includes a first sublayer directly disposed on the interface layer and a second sublayer directly disposed on the first sublayer, the first sublayer including hafnium silicate, hafnium silicon oxide or hafnium aluminum oxide, and the second sublayer including zirconium oxide, zirconium silicon oxide or zirconium silicate.

[0032] In some embodiments, the method further includes forming a dipole layer directly on the second sublayer, wherein the dipole layer comprises lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0033] In some embodiments, the dielectric layer has a thickness between about 15 angstroms and about 25 angstroms.

[0034] In some embodiments, the interface layer comprises silicon oxide.

[0035] In some embodiments, the dielectric layer has a dielectric constant in the range of about 12 to about 30.

[0036] These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying drawings; the invention is not limited to any particular embodiment disclosed. Attached Figure Description

[0037] Figure 1A method for forming a gate stack according to one or more embodiments of the present disclosure is shown;

[0038] Figure 2 A method for forming a dielectric layer according to one or more embodiments of the present disclosure is illustrated;

[0039] Figure 3 Another method for forming a dielectric layer according to one or more embodiments of the present disclosure is shown;

[0040] Figure 4 Another method for forming a dielectric layer according to one or more embodiments of the present disclosure is shown;

[0041] Figure 5 An example of a substrate processing apparatus according to one or more examples of this disclosure is shown;

[0042] Figure 6 Examples of structures that can form part of a device according to one or more examples of this disclosure are shown;

[0043] Figure 7 Another example of a structure that can form part of a device according to one or more examples of this disclosure is shown;

[0044] Figure 8 Another example of a structure that can form part of a device according to one or more examples of this disclosure is shown;

[0045] Figure 9 Another example of a structure that can form part of a device according to one or more examples of this disclosure is shown;

[0046] Figure 10 Another example of a structure that can form part of a device according to one or more examples of this disclosure is shown;

[0047] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements to aid in understanding the embodiments shown in this disclosure. Detailed Implementation

[0048] The following description of exemplary embodiments of the methods, structures, apparatuses, and systems is merely illustrative and for purposes of explanation only; the following description is not intended to limit the scope of this disclosure or the claims. Furthermore, the description of multiple embodiments having the described features is not intended to exclude other embodiments having additional features or other embodiments including different combinations of the described features. For example, various embodiments are set forth as exemplary embodiments and may be recited in the dependent claims. Unless otherwise stated, exemplary embodiments or components thereof may be combined or may be applied separately from each other.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Unless otherwise stated, expressions such as “at least one of…” modify the entire column of elements when following an element in the column, and not necessarily any individual element in that column.

[0050] As used in this article, the singular forms “a,” “one,” and “the” are intended to include both singular and plural forms, unless the context otherwise requires.

[0051] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films are formed. A substrate may comprise a bulk material, such as silicon (e.g., single-crystal silicon), other group IV materials (e.g., germanium), or compound semiconductor materials (e.g., group III-V or group II-VI semiconductors), and may comprise one or more layers overlaid or under the bulk material. For example, a substrate may comprise silicon or silicon-germanium.

[0052] In some embodiments, "film" refers to a layer extending in a direction perpendicular to the thickness direction. In some embodiments, "layer" refers to a material of a certain thickness formed on a surface, and can be synonymous with a film or non-film structure. A film or layer may consist of discrete single films or layers or multiple films or layers having certain properties, and the boundaries between adjacent films or layers may or may not be clear, and may or may not be based on the physical, chemical and / or any other properties, formation process or sequence and / or function or purpose of adjacent films or layers. A layer or film may be continuous or discontinuous. Furthermore, a single film or layer may be formed using one or more deposition cycles.

[0053] As used herein, the term "structure" can refer to a device structure that is partially or fully fabricated. For example, a structure can be a substrate or a substrate having one or more layers and / or features formed thereon.

[0054] As used in this article, terms including an element followed by "precursor" can refer to compounds containing that element.

[0055] As used in this article, the term "coverage" can refer to two membranes that are in contact with each other.

[0056] As used herein, the term "cyclic deposition process" or "cyclic deposition process" can refer to a vapor phase deposition process in which deposition cycles (typically multiple consecutive deposition cycles) are performed in a processing chamber. Cyclic deposition processes can include, for example, cyclic chemical vapor deposition (CCVD) and / or atomic layer deposition (ALD) processes.

[0057] In this disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. Furthermore, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and include equivalents, and may refer to an average, median, representative value, multi-value, etc. For example, the value of a variable may include + / -20%, or + / -10%, or + / -5%, or + / -1%, or + / -0% of the value of the listed variable. Additionally, in this disclosure, the terms “comprising,” “including,” “consisting of,” and “having” may independently mean “generally or broadly comprising,” “including,” “substantially constitutes,” or “consisting of” in some embodiments. The meaning of any definition in this disclosure does not necessarily exclude the common and customary meaning in some embodiments.

[0058] In some embodiments, the term "dielectric" or "dielectric material" may refer to a material with a dielectric constant greater than 1, or greater than 2, or greater than 3.9, or greater than 10.

[0059] Figure 1 A method 100 for forming a gate stack according to an exemplary embodiment of the present disclosure is shown. The method 100 includes the steps of: providing a substrate in a reaction chamber (step 110), optionally forming an interface layer (step 120), forming a dielectric layer (step 130), optionally forming a dipole layer (step 140), and forming a gate electrode (step 150).

[0060] During step 110, a substrate is provided into the reaction space within the reaction chamber. According to examples of this disclosure, the reaction chamber may form part of a chemical vapor deposition reactor, such as a chemical vapor deposition (CVD) reactor, an atomic layer deposition (ALD) reactor, etc. Various steps of the methods described herein may be performed in a single reaction chamber or in multiple reaction chambers (e.g., reaction chambers of clustered tools).

[0061] During step 110, the substrate may be brought to a desired temperature and / or the reaction space may be brought to a desired pressure, such as a temperature and / or pressure suitable for subsequent steps. For example, the temperature within the reaction space (e.g., the temperature of the substrate, substrate support, or ambient temperature) may be between about 0°C and about 500°C, or between about 250°C and about 425°C. For example, the pressure within the reaction space may be less than 760 Torr, or between about 1 Torr and 500 Torr, or between about 1 Torr and about 100 Torr.

[0062] In some embodiments, the surface of the substrate includes an interface layer. In some embodiments, the interface layer is disposed directly on a semiconductor material, such as silicon, single-crystal silicon, other group IV materials (e.g., germanium), or compound semiconductor materials (e.g., silicon-germanium, group III-V, or group II-VI semiconductors).

[0063] If the surface of the substrate does not include an interface layer, method 100 includes step 120 of forming an interface layer on the substrate. The interface layer can be formed by any suitable method. In some embodiments, the interface layer is formed by a (e.g., cyclic) deposition process or oxidation of a semiconductor material. In some embodiments, the interface layer comprises silicon oxide. In some embodiments, the interface layer comprises SiO2. In some embodiments, the interface layer comprises crystalline SiO2. In some embodiments, the thickness of the interface layer is about 2 to 10 angstroms, or about 2 to 7 angstroms.

[0064] Method 100 continues to form a dielectric layer (step 130). During step 130, the substrate can be brought to a desired temperature and / or the reaction space can be brought to a desired pressure. For example, the temperature within the reaction space (e.g., the temperature of the substrate or substrate support) can be between about 200°C and about 500°C, or between about 250°C and about 425°C. The pressure within the reaction chamber can also be controlled. For example, the pressure within the reaction space can be less than 760 Torr, or between about 1 Torr and 100 Torr. In some embodiments, the dielectric layer is formed directly on the interface layer. In some embodiments, forming the dielectric material includes a cyclic deposition process, such as an atomic layer deposition (ALD) process or a cyclic CVD process.

[0065] In some embodiments, the dielectric layer has a thickness between about 15 angstroms and about 25 angstroms, or between about 16 angstroms and about 20 angstroms. In some embodiments, the dielectric layer has a dielectric constant greater than about 12, or between about 12 and 30, or between about 12 and 24, or between about 12 and 15, or between about 18 and 22.

[0066] In some embodiments, the dielectric layer comprises hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer comprises Hf x Zr y Az O2, wherein x, y, and z are in the range of 0 to about 1, and the sum of x, y, and z is in the range of about 0.8 to 1.2, or between about 0.9 and 1.1, and wherein A is aluminum, silicon, or a combination of aluminum and silicon. In some embodiments, the dielectric layer comprises a tetragonal crystal structure.

[0067] In some embodiments, the dielectric layer comprises zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. In some embodiments, the dielectric material comprises hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide, wherein zirconium replaces a plurality of hafnium atoms in its crystal structure. In some embodiments, the dielectric layer may comprise a plurality of sublayers. In some embodiments, the dielectric layer may comprise one or more sublayers of hafnium oxide, silicon oxide, aluminum oxide, and / or zirconium oxide. In some embodiments, a sublayer comprising silicon oxide or aluminum oxide and a sublayer comprising zirconium oxide are separated by at least one sublayer comprising hafnium oxide. In some embodiments, the dielectric layer comprises a first hafnium oxide sublayer, a silicon oxide sublayer or an aluminum oxide sublayer, a second hafnium oxide sublayer, and a zirconium oxide sublayer, wherein the silicon oxide or aluminum oxide sublayer and the zirconium oxide sublayer are not in direct contact with each other. The dielectric layer may include a hafnium oxide sublayer between each zirconium oxide sublayer and each silicon oxide or aluminum oxide sublayer.

[0068] In some embodiments, the dielectric layer includes a first sublayer and a second sublayer. In some embodiments, the first sublayer includes hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the first sublayer is directly disposed on the interface layer. In some embodiments, the second sublayer includes zirconium oxide, zirconium silicon oxide, or zirconium silicate. In some embodiments, the second sublayer is directly disposed on the first sublayer. In some embodiments, the dielectric layer consists of a first sublayer and a second sublayer.

[0069] Figure 2 It shows the applicable Figure 1Method 200 is the method of step 130 in the above. Method 200 can produce a dielectric layer comprising zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. Method 200 can produce a dielectric layer comprising hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide, wherein about 5-10 atomic percent of the hafnium in the hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide is replaced by zirconium. Method 200 includes pulsed hafnium precursor or zirconium precursor (sub-step 210), pulsed oxygen reactant (sub-step 220), pulsed additive precursor containing aluminum precursor or silicon precursor (sub-step 230), optionally performing one or more purgings 240, and optionally repeating these steps one or more times (loop 250). Sub-steps 210-240 of method 200 can be performed in any order. Each sub-step 210-240 of method 200 can be performed one or more times. In some embodiments, purging 240 is performed after any or all of substeps 210-230, including the pulsed hafnium or zirconium precursor (substep 210), the pulsed oxygen reactant (substep 220), and the pulsed additive precursor (substep 230). In some embodiments, the pulse of the oxygen reactant (substep 220) is performed after the pulse of the hafnium or zirconium precursor (substep 210) or the additive precursor (substep 230). In some embodiments, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor during dielectric layer formation is about 30:1 to about 7:1, or about 20:1 to about 10:1. In some embodiments, the ratio of the number of hafnium atoms to the number of zirconium atoms in the dielectric layer is between about 20:1 and about 10:1, or between about 30:1 and about 7:1, or between about 20:1 and about 10:1. In some embodiments, substeps 210-240 constitute a first process cycle. In some embodiments, the first process cycle is repeated multiple times. In some embodiments that perform multiple first process cycles, the ratio of the number of first process cycles including the pulsed zirconium precursor to the number of first process cycles including the pulsed hafnium precursor is about 1:10 to about 1:20. In some embodiments, the dielectric layer formed by method 200 has the formula Hf x Zr y A z O2, wherein x, y, and z are between 0 and about 1, the sum of x, y, and z is in the range of about 0.8 to 1.2, and x is about 10 to 20 times more than y, and wherein A is aluminum, silicon, or a combination of aluminum and silicon. In some embodiments, z is in the range of about 0.05 to about 0.2, or about 0.06 to about 0.14.

[0070] Unbound by theory, it is believed that replacing about 5-10% of hafnium with zirconium while forming hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide can increase the dielectric constant to above 12, while maintaining a high band gap (e.g., above 5 eV or above 6 eV) and keeping the CET of the gate stack below about 16 angstroms or below about 14 angstroms.

[0071] Figure 3 It shows the applicable Figure 1 Another method 300 of step 130. Method 300 may produce a dielectric layer comprising zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide, wherein the zirconium is separated from the silicon or aluminum, for example, by the hafnium. Method 300 includes pulsing a hafnium precursor up to a first time period 310, pulsing an additive precursor 320 comprising a silicon precursor or an aluminum precursor, pulsing a hafnium precursor up to a second time period 330, pulsing a zirconium precursor 340, pulsing an oxygen reactant 350, optionally performing a purging, and optionally repeating sub-steps 310-360 once or more (loop 370). In some embodiments, method 300 includes performing sub-steps 310-340 once or more in any order, wherein at least one pulse of the hafnium precursor occurs between pulses of the zirconium precursor and pulses of the additive precursor. In some embodiments, the pulsed oxygen reactant is performed after one or more of sub-steps 310-340. In some embodiments, a pulsed oxygen reactant is performed after one or more of substeps 310-340 and before another of substeps 310-340. In some embodiments, purging 360 is performed after any or all of substeps 310-350. In some embodiments, substeps 310-360 constitute a deposition cycle. In some embodiments, the deposition cycle is repeated once or more (loop 370).

[0072] In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 2.5:1 to about 4:1, or about 2.7:1 to about 3.5:1, or about 2.9:1 to about 3.2:1. In some embodiments, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor in the first cycle is in the range of about 1.5:1 to about 2.5:1, or about 1.7:1 to about 2.3:1, or about 1.9:1 to about 2.1:1. In some embodiments, the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor in the first cycle is in the range of about 1.25:1 to 1.75:1, or about 1.4:1 to about 1.6:1.

[0073] In some embodiments, forming the dielectric layer includes performing one or more first cycles. In some embodiments, the first cycle sequentially includes pulsing a hafnium precursor for a first time period, pulsing an additive precursor, pulsing a hafnium precursor for a second time period, and pulsing a zirconium precursor. In some embodiments, no pulsed zirconium precursor is applied before the second time period in each first cycle. In some embodiments, no pulsed additive precursor is applied before the first time period or after the second time period in each first cycle. In some embodiments, the first cycle includes pulsing a hafnium precursor for the first time period exactly once, pulsing an additive precursor exactly three times, pulsing a hafnium precursor for the second time period exactly once, and pulsing a zirconium precursor exactly once.

[0074] Unbound by theory, it is believed that the presence of a zirconium-silicon or aluminum interface, or the presence of a zirconium silicate, zirconium oxide silicon, or zirconium oxide aluminum sublayer, can reduce the dielectric constant of the dielectric layer. To prevent the formation of a zirconium-silicon interface or a zirconium silicate, zirconium oxide silicon, or zirconium oxide aluminum sublayer, the pulses of the zirconium precursor can be separated from those of the additive precursor by pulses of the hafnium precursor. In this case, hafnium or hafnium oxide prevents the formation of the zirconium silicate, zirconium oxide silicon, or zirconium oxide aluminum sublayer. In embodiments where the hafnium precursor is pulsed at least once between each pulse of the zirconium precursor and each pulse of the additive precursor, a gate structure with a dielectric layer having a dielectric constant greater than 12 and a gate stack of less than about 16 angstroms or less than about 14 angstroms is obtained for a CET (Central Electron) layer.

[0075] Figure 4 It shows the applicable Figure 1 Another method 400 of step 130. Method 400 can be used to form a dielectric layer including a first sublayer and a second sublayer. In some embodiments, the first sublayer includes hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. In some embodiments, the second sublayer includes zirconium oxide, zirconium silicon oxide, or zirconium silicate. Method 400 includes pulsed hafnium precursor (sub-step 410), pulsed additive precursor containing silicon or hafnium precursor (sub-step) 420, pulsed oxygen reactant (sub-step 430), optionally purging (sub-step 440), optionally repeating sub-steps 410-440 once or more (loop 450), pulsed zirconium precursor (sub-step 460), pulsed oxygen reactant (sub-step 470), optionally pulsed additive precursor containing silicon or aluminum precursor (sub-step 480), optionally purging (sub-step 490), and optionally repeating sub-steps 460-490 once or more (loop 495).

[0076] In some embodiments, substeps 410-440 may be performed once or multiple times and in any order. In some embodiments, a pulsed oxygen reactant is performed after one or more of substeps 410 and 420 (substep 430). In some embodiments, a pulsed oxygen reactant is performed after one or more of substeps 410 and 420 and before performing another of substeps 410 and 420 (substep 430). In some embodiments, a purging process (substep 440) is performed after any or all of substeps 410-430. In some embodiments, substeps 410-450 form a first sublayer. In some embodiments, substeps 410-440 constitute a first sublayer deposition cycle. In some embodiments, the first sublayer deposition cycle is repeated once or multiple times (cycle 450).

[0077] In some embodiments, substeps 460-490 may be performed once or multiple times and in any order. In some embodiments, a pulsed oxygen reactant is performed after one or more of substeps 460 and 480 (substep 470). In some embodiments, a pulsed oxygen reactant is performed after one or more of substeps 460 and 480 and before performing another of substeps 460 and 480 (substep 470). In some embodiments, a purging process (substep 490) is performed after any or all of substeps 460-480. In some embodiments, substeps 460-495 form a second sublayer. In some embodiments, substeps 460-490 constitute a second sublayer deposition cycle. In some embodiments, the second sublayer deposition cycle is repeated once or multiple times (loop 495).

[0078] In some embodiments, a first sublayer is disposed directly on the interface layer. In some embodiments, a first sublayer is disposed directly on the dipole layer. In some embodiments, a second sublayer is disposed directly on the first sublayer. In some embodiments, a dielectric layer comprises a first sublayer and a second sublayer. In some embodiments, the first sublayer has a thickness of about 10 angstroms to 22 angstroms, or about 15 angstroms to about 22 angstroms. In some embodiments, the second sublayer has a thickness of about 3 angstroms to about 10 angstroms, or about 3 angstroms to 7 angstroms.

[0079] Unbound by theory, method 400 is thought to form a dielectric layer that maintains a high band gap of hafnium silicon oxide, hafnium silicate, or hafnium aluminum oxide at the interface layer, while increasing the dielectric constant of the dielectric layer with zirconium silicon oxide, zirconium silicate, or zirconium oxide. Method 400 can form a dielectric layer with a dielectric constant higher than 12 (e.g., between 12 and 30, or between 12 and 24, or between 12 and 15, or between 18 and 22).

[0080] In some embodiments of step 130 (including embodiments of methods 200, 300, and 400), the hafnium precursor comprises a hafnium halide or an organometallic hafnium precursor. In some embodiments of step 130, including embodiments of methods 200, 300, and 400, the zirconium precursor comprises a zirconium halide or an organometallic zirconium precursor. For example, the hafnium precursor may be or include hafnium chloride or tetrakis(dimethylamino)hafnium, and the zirconium precursor may be or include zirconium chloride. In some embodiments of step 130, including embodiments of methods 200, 300, and 400, the silicon precursor comprises a silane, a chlorosilane, an organosilane, a heterosilane, or silicon tetrachloride. In some embodiments, the aluminum precursor comprises triethylaluminum (TEA), trimethylaluminum (TMA), dimethylaluminum hydride (DMAH), or aluminum chloride. In some embodiments of step 130, including some embodiments of methods 200, 300, and 400, the oxygen reactants include any combination of H2O, O2, O3, H2O2, NO, NO2, or N2O.

[0081] Back Figure 1 Method 100 continues to form a dipole layer (step 140). In some embodiments, forming the dipole layer (step 140) occurs before forming the dielectric layer (step 130). In some embodiments, forming the dipole layer (step 140) occurs after forming the dielectric layer (step 130). In some embodiments, forming the dipole layer occurs during forming the dielectric layer (step 130) (e.g., between various sub-steps of methods 200, 300, or 400). In some embodiments, the dipole layer is formed directly on the dielectric layer. In embodiments where the dielectric layer includes a second sub-layer (which includes zirconium oxide, zirconium silicon oxide, or zirconium silicate), the dipole layer is disposed directly on the second sub-layer. In some embodiments, the dipole layer is formed directly on the interface layer. In some embodiments, the dipole layer is formed between sub-layers of the dielectric layer. The dipole layer can be formed by any suitable method, including a cyclic deposition process. In some embodiments, the dipole layer includes a metal oxide, a metal nitride, or a metal oxynitride. In some embodiments, the dipole layer includes lanthanum, aluminum, yttrium, scandium, or gallium. In some embodiments, the dipole layer includes lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

[0082] Method 100 continues to form a gate electrode (step 150). As used herein, forming a gate electrode may include forming an additional layer in the gate stack. Step 150 may include any deposition, etching, annealing, etc., to complete the gate stack. In some embodiments, the gate electrode comprises a metal nitride, such as TiN or TaN. In some embodiments, the gate electrode comprises a conductive layer. In some embodiments, forming a gate electrode (step 150) comprises forming a layer comprising a metal or metal nitride layer (such as TiN) directly on the dipole layer. In some embodiments, forming a gate electrode (step 150) comprises forming a TiN-containing layer directly on the dielectric layer.

[0083] The various steps of the methods described herein may be performed in a single reaction chamber or in multiple reaction chambers (e.g., the reaction chamber for clustering tools). In some embodiments, method 100 may be performed in a single reaction space. In some embodiments, one or more sub-steps of method 100 may be performed in different reaction spaces or different reaction chambers.

[0084] Additionally, the carrier gas and / or inert gas may co-flow throughout methods 100, 200, 300, and 400 or during any sub-step of methods 100, 200, 300, or 400. For example, the carrier gas and / or inert gas may be one or more of helium, argon, or nitrogen.

[0085] Figure 5An example of a substrate processing apparatus 500 according to one or more examples of this disclosure is shown. Apparatus 500 can be used to perform the methods described herein and / or form structural or device portions as described herein.

[0086] In the example shown, device 500 includes one or more reaction chambers 502, hafnium precursor gas source 504, zirconium precursor gas source 506, additive precursor gas source 508, oxygen reactant gas source 510, exhaust source 522, and controller 512.

[0087] Reaction chamber 502 may include any suitable reaction chamber, such as an atomic layer deposition (ALD) or chemical vapor deposition (CVD) reaction chamber.

[0088] Hafnium precursor gas source 504 may include a container and one or more hafnium precursors as described herein—alone or mixed with one or more carrier gases (e.g., inert gases). Zirconium precursor gas source 506 may include a container and one or more zirconium precursors as described herein—alone or mixed with one or more carrier gases (e.g., inert gases). Additive precursor gas source 508 may include a container and one or more silicon or aluminum precursors as described herein—alone or mixed with one or more carrier gases. Oxygen reactant gas source 510 may include one or more oxygen reactant gases as described herein. Although four gas sources 504-510 are shown, apparatus 500 may include any suitable number of gas sources. Gas sources 504-510 may be coupled to reaction chamber 502 via lines 514-520, each of which may include a flow controller, valve, heater, etc.

[0089] The exhaust source 522 may include one or more vacuum pumps.

[0090] Controller 512 includes electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in apparatus 500. Such circuitry and components operate to introduce precursors, reactants, and gases from respective sources 504-510. Controller 512 can control the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to provide appropriate operation of apparatus 500. Controller 512 may include control software to electrically or pneumatically control valves to control the inflow and outflow of precursors, reactants, and purge gases from reaction chamber 502. Controller 512 may include modules, such as software or hardware components like FPGAs or ASICs, to perform certain tasks. Modules may advantageously be configured to reside on addressable storage media of the control system and configured to perform one or more processes or methods as described herein.

[0091] Other configurations of the apparatus 500 are possible, including different numbers and types of precursor and reactant sources, as well as purge gas sources. Furthermore, it should be understood that numerous arrangements of valves, conduits, precursor sources, and purge gas sources exist to achieve the objective of selectively supplying gases to the reaction chamber 502. Additionally, for the sake of illustrative purposes and for simplicity, many components have been omitted, and these components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0092] During operation of the apparatus 500, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate processing system to a reaction chamber 502. Once the substrate is transferred to the reaction chamber 502, one or more gases (e.g., precursors, reactants, carrier gases, and / or purge gases) from gas sources 504-510 are introduced into the reaction chamber 502.

[0093] Figure 6The structure / partial view of a device 600 according to an additional example of this disclosure is shown. The device or structure 600 includes a substrate 610, an interface layer 620, a dielectric layer 630, a dipole layer 640, and one or more additional layers 650. In some embodiments, the device or structure 600 is a gate stack or at least a portion thereof. The interface layer 620 can be formed by the methods described in this disclosure. In some embodiments, the interface layer 620 includes silicon oxide. The interface layer 620 may have a thickness between about 2 and 10 angstroms or about 2 and 7 angstroms. The dielectric layer 630 can be formed by the methods described in this invention. In some embodiments, the dielectric layer 630 includes hafnium, zirconium, silicon, and oxygen. In some embodiments, the dielectric layer 630 includes hafnium, zirconium, aluminum, and oxygen. In some embodiments, the dielectric layer 630 includes hafnium, zirconium, silicon, aluminum, and oxygen. In some embodiments, the dielectric layer 630 is zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide. In some embodiments, dielectric layer 630 may include sublayers of hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide. In some embodiments, the sublayer containing silicon oxide or aluminum oxide and the sublayer containing zirconium oxide are separated by at least one hafnium oxide sublayer. In some embodiments, dielectric layer 630 has a thickness between about 15 angstroms and about 25 angstroms, or between about 16 angstroms and about 20 angstroms. In some embodiments, dielectric layer 630 has a dielectric constant greater than about 12, or between about 12 and 30, or between about 12 and 24, or between about 12 and 15, or between about 18 and 22. In some embodiments, dielectric layer 630 is disposed directly on interface layer 620. Dipole layer 640 may be formed by the methods described in this disclosure. In some embodiments, dipole layer 640 includes a metal nitride, a metal oxynitride, or a metal oxide, such as lanthanum oxide, yttrium oxide, aluminum oxide, scandium oxide, or gallium oxide. Dipole layer 640 may have a thickness less than 50 angstroms, or between about 5 angstroms and 30 angstroms. In some embodiments, the dipole layer 640 is disposed directly on the dielectric layer 630. The additional layer 650 may include a gate electrode, a barrier layer, or a pad layer, as well as any other layers formed in the gate stack. In some embodiments, the additional layer 650 may include TiN.

[0094] Figure 7The structure / partial view of device 700 according to an additional example of this disclosure is shown. Device 700 is substantially the same as device 600 except that dielectric layer 730 includes a first sublayer 730a and a second sublayer 730b. The first sublayer 730a is disposed directly on interface layer 720. The second sublayer 730b is disposed directly on the first sublayer 730a. Dipole layer 740 is disposed directly on the second sublayer 730b. The first sublayer 730a comprises hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide. The second sublayer 730b comprises zirconium oxide, zirconium silicon oxide, or zirconium silicate. The first sublayer 730a may have a thickness between about 10 angstroms and 22 angstroms or between about 15 angstroms and about 22 angstroms. The second sublayer 730b may have a thickness between about 3 angstroms and about 10 angstroms or between about 3 angstroms and 7 angstroms.

[0095] Figure 8 The structure / part of device 800 according to an additional example of this disclosure is shown. Device 800 is substantially the same as device 600 except that the dipole layer 640 is disposed between the interface layer 620 and the dielectric layer 630.

[0096] Figure 9 The structure / part of a device 900 according to an additional example of this disclosure is shown. Device 900 is substantially the same as device 700, except that a dipole layer 740 is disposed between the interface layer 720 and the first sublayer 730a of the dielectric layer 730.

[0097] Figure 10 The structure / part of device 1000 according to an additional example of this disclosure is shown. Device 1000 is substantially the same as device 600, except that the dipole layer 640 is configured as a layer between sublayers 1030a and 1030b of the dielectric layer. Sublayers 1030a and 1030b can be any sublayer of the dielectric layer as described herein.

[0098] The exemplary embodiments described above do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the invention, the scope of which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to fall within the scope of the invention. In fact, various modifications to this disclosure, such as alternative useful combinations of the described elements, in addition to those shown and described herein, will become apparent to those skilled in the art from the description. These modifications and embodiments are also intended to fall within the scope of the appended claims.

Claims

1. A method for forming a gate stack, the method comprising: A substrate including a surface is provided in the reaction chamber, the surface including an interface layer; and A dielectric layer is formed on the interface layer through an atomic layer deposition process, wherein the formation of the dielectric layer includes multiple pulses of hafnium precursor, at least one pulse of zirconium precursor, at least one pulse of additive precursor, and pulse of oxygen reactant. The additive precursor includes a silicon precursor or an aluminum precursor, and The hafnium precursor pulses at least once between each pulse of the zirconium precursor and each pulse of the additive precursor.

2. The method of claim 1, wherein, The dielectric layer comprises multiple sublayers, including a first sublayer containing hafnium oxide, a second sublayer containing silicon oxide or aluminum oxide, a third sublayer containing hafnium oxide, and a fourth sublayer containing zirconium oxide. The second and fourth sub-layers do not directly contact each other.

3. The method according to claim 1, wherein, Forming the dielectric layer includes performing a plurality of first cycles, wherein the first cycles sequentially include: The pulsed hafnium precursor reaches the first time period. The pulsed additive precursor. The pulsed hafnium precursor reaches the second time period, and The zirconium precursor described in the pulse.

4. The method according to claim 3, wherein, The zirconium precursor is not pulsed before the second time period, and the additive precursor is not pulsed before the first time period or after the second time period in the first cycle.

5. The method according to claim 3, wherein, In the first cycle, the ratio of the number of pulses of the additive precursor to the number of pulses of the zirconium precursor is in the range of about 2.5:1 to about 4:

1.

6. The method according to claim 3, wherein, In the first cycle, the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor is in the range of about 1.5:1 to about 2.5:

1.

7. The method according to claim 3, wherein, In the first cycle, the ratio of the number of pulses of the additive precursor to the number of pulses of the hafnium precursor is in the range of about 1.25:1 to 1.75:

1.

8. The method according to claim 1, further comprising forming a dipole layer directly on the dielectric layer.

9. The method according to claim 8, wherein, The dipole layer includes lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

10. The method of claim 1, further comprising forming a dipole layer directly on the interface layer.

11. The method according to claim 1, wherein, The ratio of oxygen atoms to the total number of hafnium, zirconium, aluminum and silicon atoms is in the range of about 1.6:1 to about 2.5:

1.

12. The method according to claim 1, wherein, The additive precursors include silicon precursors.

13. A method for forming a gate stack, the method comprising: A substrate including a surface is provided in the reaction chamber, the surface including an interface layer; and A dielectric layer is formed on the interface layer by an atomic layer deposition process. The dielectric layer includes a first sublayer directly disposed on the interface layer and a second sublayer directly disposed on the first sublayer. The first sublayer includes hafnium silicate, hafnium silicon oxide, or hafnium aluminum oxide, and the second sublayer includes zirconium oxide, zirconium silicon oxide, or zirconium silicate.

14. The method of claim 13, further comprising forming a dipole layer directly on the second sublayer, wherein, The dipole layer includes lanthanum oxide, aluminum oxide, yttrium oxide, scandium oxide, or gallium oxide.

15. The method according to claim 13, wherein, The dielectric layer has a thickness between approximately 15 angstroms and approximately 25 angstroms.

16. The method according to claim 13, wherein, The interface layer comprises silicon oxide.

17. The method according to claim 13, wherein, The dielectric layer has a dielectric constant in the range of about 12 to about 30.

18. A method for forming a gate stack, the method comprising: A substrate including a surface is provided in the reaction chamber, the surface including an interface layer; and A dielectric layer is formed on the interface layer through an atomic layer deposition process, wherein the formation of the dielectric layer includes multiple pulses of hafnium precursor, at least one pulse of zirconium precursor, at least one pulse of additive precursor, and pulse of oxygen reactant. The additive precursor includes a silicon precursor or an aluminum precursor, and The dielectric layer includes zirconium-doped hafnium silicon oxide, zirconium-doped hafnium silicate, or zirconium-doped hafnium aluminum oxide, wherein the ratio of the number of pulses of the hafnium precursor to the number of pulses of the zirconium precursor is about 30:1 to about 7:1 during the formation of the dielectric layer.

19. The method according to claim 18, wherein, The additive precursors include silicon precursors.

20. The method of claim 18, further comprising forming a dipole layer directly on the dielectric layer.

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