Electronic device

Abstract

The present application provides an electronic device, comprising a substrate, a driving circuit on the substrate, a first shielding pattern, a second shielding pattern, a first organic layer and a conductive layer. In some embodiments, the first shielding pattern is on the driving circuit and comprises a first opening, the first organic layer is on the first shielding pattern and comprises a second opening overlapping the first opening, the conductive layer is electrically connected with the driving circuit through the first opening and the second opening, and the second shielding pattern is in the first opening and the second opening. In some embodiments, the first organic layer is on the driving circuit and comprises a first opening and a second opening, the conductive layer is electrically connected with the driving circuit through the second opening, the first shielding pattern and the second shielding pattern are in the first opening and the second opening respectively, and a depth of the first opening is different from a depth of the second opening.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to an electronic device comprising a masking pattern disposed on a driving circuit. Background Technology

[0002] With technological advancements, electronic devices have become indispensable in modern life. Among electronic devices such as virtual reality (VR) devices, augmented reality (AR) devices, and liquid crystal displays, products with small pixel sizes place higher demands on the alignment accuracy and pattern design of light-filtering layers and light-blocking patterns. Therefore, the architectural design of light-filtering layers and light-blocking patterns in electronic devices remains one of the important research topics today. Summary of the Invention

[0003] The purpose of this invention is to provide an electronic device in which a masking pattern is provided on the driving circuit and the position design of the masking pattern can reduce the negative impact on the aperture ratio and / or reduce light leakage, thereby improving the display quality of the electronic device.

[0004] This invention provides an electronic device, including a substrate, a driving circuit, a first masking pattern, a first organic layer, a conductive layer, and a second masking pattern. The driving circuit is located on the substrate, the first masking pattern is located on the driving circuit and includes a first opening, and the first organic layer is located on the first masking pattern and includes a second opening overlapping the first opening. The conductive layer is electrically connected to the driving circuit through the first opening and the second opening, and the second masking pattern is located within the first opening and the second opening.

[0005] The present invention also provides an electronic device, comprising a substrate, a driving circuit, a first organic layer, a conductive layer, a first masking pattern, and a second masking pattern. The driving circuit is located on the substrate, and the first organic layer is located on the driving circuit and includes a first opening and a second opening. The conductive layer is electrically connected to the driving circuit through the second opening. The first masking pattern and the second masking pattern are respectively located in the first opening and the second opening, and the depth of the first opening is different from the depth of the second opening. Attached Figure Description

[0006] Figure 1 This is a partial top view of an electronic device according to an embodiment of the present invention.

[0007] Figure 2 This is another partial top view of an electronic device according to an embodiment of the present invention.

[0008] Figure 3 This is a partial cross-sectional schematic diagram of the electronic device according to the first embodiment of the present invention.

[0009] Figure 4 This is a partial cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention.

[0010] Figure 5 This is a partial cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention.

[0011] Figure 6 This is a partial cross-sectional schematic diagram of the electronic device according to the fourth embodiment of the present invention.

[0012] Figure 7 This is a partial cross-sectional schematic diagram of the electronic device according to the fifth embodiment of the present invention.

[0013] Figure 8 This is a partial cross-sectional schematic diagram of the electronic device according to the sixth embodiment of the present invention.

[0014] Figure 9 This is a partial cross-sectional schematic diagram of the electronic device according to the seventh embodiment of the present invention.

[0015] Figure 10 This is a partial cross-sectional schematic diagram of the electronic device according to the eighth embodiment of the present invention.

[0016] Figure reference numerals: 101, 102, 103, 104, 105, 106, 107, 108 - Electronic devices; AL - Active layer; BF - Buffer layer; BM1, BM2, BM3 - Masking patterns; CC - Circuit layer; CE1, CE2 - Filter elements; CF - Filter layer; CL - Conductive layer; CR - Channel area; CT - Contact element; DE - Drain electrode; DL - Data line; DP1, DP2, DP3 - Depth; DR - Drain area; DU - Drive circuit; EL1, EL2, EL3 - Conductive layers; GE1, GE2 - Gate electrodes; GL1, GL2 - Scan Tracing; IN1, IN2, IN3, IN4, IN5, IN6, IN7 - Insulating layer; LC - Dielectric layer; LS1, LS2 - Masking layer; M1, M2, M3, M4 - Conductive layer; OC - Protective layer; OP1, OP2, OP3, OP4, OP5 - Opening; OSB - Opposing substrate; PL1 - First organic layer; PL2 - Second organic layer; R1 - First region; R2 - Second region; SB - Substrate; SE - Source electrode; SR - Source region; TK1, TK2, TK3 - Thickness; TS1, TS2, TS3 - Top surface; X, XD, Y, Z - Direction. Detailed Implementation

[0017] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the accompanying drawings depict only a portion of the device, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0018] Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This invention is not intended to distinguish between elements that have the same function but different names. In this specification and claims, words such as "comprising," "including," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". When the terms "comprising," "including," and / or "having" are used in this specification, they specify the presence of the stated feature, region, step, operation, and / or element, but do not exclude the presence or addition of one or more other features, regions, steps, operations, elements, and / or combinations thereof.

[0019] It should be understood that when an element or film is referred to as being "on" or "connected" to another element or film, it can be directly on or directly connected to the other element or film, or there may be an inserted element or film between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or film, there may be no inserted element or film between them. When an element or film is referred to as being "electrically connected" to another element or film, it can be interpreted as a direct electrical connection or a non-direct electrical connection. The electrical connection or coupling described in this invention can refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the two circuit components are directly connected or interconnected by a conductor segment, while in the case of an indirect connection, there may be a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the two circuit components, but not limited to these.

[0020] The directional terms used in this invention, such as "up," "down," "front," "back," "left," and "right," are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0021] The ordinal numbers used in the specification and claims of this invention, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing methods. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0022] In this invention, the length and width can be measured using an optical microscope, while the thickness or depth can be measured from a cross-sectional image in an electron microscope, but this is not a limitation.

[0023] Furthermore, there may be a certain degree of error between any two values ​​or directions used for comparison. The terms "approximately," "generally," or "roughly" are generally interpreted as being within ±10% of the given value, or within ±5%, ±3%, ±2%, ±1%, or ±0.5% of the given value.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0025] It should be understood that the technical features of several different embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of the present invention.

[0026] The electronic device described in this invention can be applied to display devices, virtual reality devices, augmented reality devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but is not limited thereto. The electronic device can be bendable or flexible. The electronic device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, other suitable display media, or combinations thereof, but is not limited thereto. The display device can be a non-self-emissive display device or a self-emissive display device. The antenna device can be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device can be a sensing device for capacitance, light, heat, or ultrasound, but is not limited thereto. The electronic device may include, for example, passive and active electronic components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. Light-emitting diodes (LEDs) may include, for example, organic light-emitting diodes (OLEDs), miniLEDs, microLEDs, or quantum dot LEDs, but are not limited thereto. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but are not limited thereto. It should be noted that electronic devices may be any of the aforementioned arrangements and combinations, but are not limited thereto. Electronic devices may have peripheral systems such as driving systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (e.g., augmented reality or virtual reality devices), automotive devices (e.g., automotive windshields), or splicing devices. The following description uses electronic devices including display devices as an example to illustrate the invention, but the invention is not limited thereto. The electronic devices of the present invention may be various combinations of the above-mentioned devices, such as a combination of a display device and other devices, but are not limited thereto.

[0027] Please refer to Figure 1 and Figure 2 . Figure 1 This is a partial top view schematic diagram of an electronic device according to an embodiment of the present invention. Figure 2 This is another partial top view schematic diagram of an electronic device according to an embodiment of the present invention. For the sake of simplicity, in... Figure 1 and Figure 2 The diagram shows only a top view of some components of the electronic device, for example... Figure 1 The scan lines, data lines, and active layer in the driving circuit are shown, but the circuitry in the second area is not shown. Figure 2 Can be regarded as in Figure 1 A top-view diagram showing the addition of a masking pattern under certain conditions. Furthermore, in some embodiments, Figure 3 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line A-A' is an example, but not limited to this. Figure 1 and Figure 2 As shown, the electronic device may include a first region R1 and a second region R2 surrounding the first region R1. In some embodiments, the first region R1 may be considered as a central region and / or a display region, while the second region R2 may be considered as a peripheral region and / or a non-display region, but is not limited thereto. In some embodiments, the electronic device may include a plurality of scan lines GL1, a plurality of scan lines GL2, a plurality of data lines DL, and a plurality of active layers AL disposed in the first region R1. Each scan line GL1 may extend substantially along the direction X, and the scan line GL1 may be formed by at least a portion of the conductive layer M1. Each scan line GL2 may extend substantially along the direction X, and the scan line GL2 may be formed by at least a portion of the conductive layer M2. Each data line DL may extend substantially along the direction Y, and the data line DL may be formed by at least a portion of the conductive layer M3. In some embodiments, a portion of each data line DL may extend along an oblique direction (e.g., direction XD) that is not parallel to the directions X and Y, so direction XD may also be considered as the extension direction of the data line DL, but is not limited thereto. In some embodiments, directions X, Y, and XD can be considered horizontal directions that are substantially orthogonal to a vertical direction (e.g., direction Z), and directions X and Y can also be substantially orthogonal to each other, but are not limited thereto. It is worth noting that the shapes of the scan lines GL1, GL2, data lines DL, and active layer AL in the top view of this invention may include, but are not limited to, those shapes. Figure 1 The situation shown illustrates that the shapes of the scan lines, data lines, and active layer in the top view can be changed as needed for design. In some embodiments, the electronic device may also include multiple masking patterns BM1, multiple masking patterns BM2, and a masking pattern BM3. Masking patterns BM1, BM2, and BM3 may have a high optical density (OD) to provide a light-shielding effect. Each masking pattern BM1 may correspond to a portion of the data line DL, each masking pattern BM2 may correspond to the scan line GL2, and the masking pattern BM3 may be disposed in the second region R2. It is worth noting that the shapes of the masking patterns BM1, BM2, and BM3 in the top view of the present invention may include, but are not limited to, those described above. Figure 2 The situation shown illustrates this, and the shape of each masking pattern in the top view can be changed as needed for the design. Furthermore, Figure 1 and Figure 2 This can also be considered as a partial top view of the electronic device in the following embodiments. The "optical density" of this invention, for example, represents the light-shielding ability of a material or element; a higher optical density indicates better light-shielding ability.

[0028] Please refer to Figures 1 to 3 . Figure 3 This is a partial cross-sectional schematic diagram of the electronic device 101 according to the first embodiment of the present invention. Figures 1 to 3 As shown, the electronic device 101 includes a substrate SB, a driving circuit DU, a first masking pattern (e.g., masking pattern BM1), a first organic layer PL1, a conductive layer EL1, and a second masking pattern (e.g., masking pattern BM2). The driving circuit DU is located on the substrate SB, the masking pattern BM1 is located on the driving circuit DU and includes a first opening (e.g., opening OP1), the first organic layer PL1 is located on the masking pattern BM1 and includes a second opening (e.g., opening OP2) overlapping opening OP1. The conductive layer EL1 is electrically connected to the driving circuit DU through openings OP1 and OP2, and the masking pattern BM2 is located in openings OP1 and OP2. In some embodiments, the electronic device 101 may further include a filter layer CF disposed on the substrate SB. The filter layer CF may include multiple filter elements (e.g., filter element CE1) respectively disposed in different sub-pixel areas, and each filter element may have a specific filter range to provide the desired filter effect (e.g., allowing light of a specific wavelength range or a specific color to pass through). In electronic device 101, the filter layer CF may cover at least a portion of the masking pattern BM1. Therefore, a portion of the filter layer CF may be located between the masking pattern BM1 and the first organic layer PL1. For example, a portion of the filter layer CF may be sandwiched between the masking pattern BM1 and the first organic layer PL1 in the Z direction. Furthermore, the filter layer CF may include a third opening (e.g., opening OP3) overlapping opening OP2, and the masking pattern BM2 may also be located within opening OP3. In some embodiments, opening OP1 of the masking pattern BM1, opening OP3 of the filter layer CF, and opening OP2 of the first organic layer PL1 may at least partially overlap each other in the Z direction. The conductive layer EL1 may be partially disposed within openings OP1, OP3, and OP2 and partially disposed on the upper surface of the first organic layer PL1. The masking pattern BM2 may be disposed on the conductive layer EL1 and located within openings OP1, OP3, and OP2. In some embodiments, the upper surface of the masking pattern BM2 may be substantially coplanar with the upper surface of the conductive layer EL1, but this is not a limitation. In some embodiments, the upper surface of the masking pattern BM2 may be slightly higher than, slightly lower than, or even slightly lower than the upper surface of the conductive layer EL1 in the Z direction. It is worth noting that the opening in the specific element or film layer described in this invention may include a perforation penetrating the element or film layer in the Z direction or an opening that does not penetrate the element or film layer (this condition can also be considered a recess).

[0029] In some embodiments, the electronic device 101 may include a circuit layer CC disposed on the substrate SB. The aforementioned driving circuit DU may be considered as part of the circuit layer CC, and the circuit layer CC may include multiple layers of insulating layers (e.g., insulating layers IN2, IN3, IN4, IN5, and IN6), multiple layers of conductive layers (e.g., conductive layers M1, M2, M3, CL, and M4), and an active layer AL stacked together. The conductive layer M1 may include the gate electrode GE1 in the driving circuit DU. The gate electrode GE1 may be connected to the scan line GL1 or may be considered as part of the scan line GL1. The insulating layer IN2 may cover the conductive layer M1 and be located between the active layer AL and the conductive layer M1. The active layer AL may be disposed on the insulating layer IN2, and the insulating layer IN3 may cover the active layer AL and be located between the active layer AL and the conductive layer M2. The conductive layer M2 may include the gate electrode GE2 in the driving circuit DU and is disposed on the insulating layer IN3. The gate electrode GE2 may be connected to the scan line GL2 or may be considered as part of the scan line GL2, while the insulating layer IN4 may cover the conductive layer M2. The active layer AL may include a channel region CR, a source region SR, and a drain region DR. The channel region CR may be defined as a portion of the active layer AL overlapping the gate electrode GE1 and / or the gate electrode GE2, while the source region SR and the drain region DR may be defined as the portions of the active layer AL located on both sides of the channel region CR, respectively. The active layer AL may include, for example, silicon or metal oxide, such as low-temperature polycrystalline silicon semiconductor or amorphous silicon (a-Si) semiconductor, metal oxide semiconductor (e.g., but not limited to indium gallium zinc oxide (IGZO)) or other suitable semiconductor materials. In this embodiment, the active layer AL is exemplified by including a metal oxide semiconductor material. Conductive layer M3 may include a data line DL electrically connected to the source region SR. A portion of the data line DL may be considered as the source electrode SE in the drive circuit DU, and the source electrode SE may penetrate insulating layers IN4 and IN3 to connect to the source region SR, but is not limited thereto. Insulating layer IN5 may cover insulating layer IN4 and conductive layer M3. Conductive layer CL may include a drain electrode DE electrically connected to the drain region DR, and the drain electrode DE may penetrate insulating layers IN5, IN4, and IN3 to connect to the drain region DR, but is not limited thereto. Insulating layer IN6 may cover insulating layer IN5 and conductive layer CL. Conductive layer M4 may include a contact CT penetrating insulating layer IN6 to be electrically connected to the drain electrode DE. In embodiments of the present invention, conductive layer M1 may not transmit scanning signals but may serve as a light-shielding layer to improve the degradation of the channel region CR due to external ambient light irradiation.

[0030] The circuit layer CC may be partially disposed in the first region R1 and partially disposed in the second region R2. The driving circuit DU may be at least partially disposed in the first region R1 and includes the gate electrode GE1, insulating layer IN2, active layer AL, insulating layer IN3, gate electrode GE2, insulating layer IN4, source electrode SE (and / or data line DL), insulating layer IN5, drain electrode DE, insulating layer IN6, and contact CT. Insulating layers IN2, IN3, IN4, IN5, and IN6 may be partially disposed in the first region R1 and partially disposed in the second region R2, respectively. Furthermore, the masking patterns BM1 and BM2, the filter layer CF, and the first organic layer PL1 may be disposed on the circuit layer CC. The masking patterns BM1 and BM2 and the filter layer CF are at least partially disposed in the first region R1, while the first organic layer PL1 may be partially disposed in the first region R1 and partially disposed in the second region R2. In some embodiments, the electronic device 101 may further include a buffer layer BF disposed between the substrate SB and the circuit layer CC, and an insulating layer IN1 disposed between the buffer layer BF and the conductive layer M1, but is not limited thereto. Furthermore, Figure 3 The structure of the circuit layer CC shown is merely exemplary, and the present invention is not limited thereto. In some embodiments, the opening OP1 of the masking pattern BM1, the opening OP3 of the filter layer CF, and / or the opening OP3 of the first organic layer PL1 may overlap with the contact CT, and the conductive layer EL1 may form an electrical connection with the contact CT through the openings OP2, OP3, and OP1. In other embodiments, the circuit layer CC may not include the conductive layer M4 (nor the contact CT), and the conductive layer EL1 may contact the conductive layer CL to form an electrical connection, but the present invention is not limited thereto.

[0031] In some embodiments, the electronic device 101 may further include a conductive layer EL2, an insulating layer IN7, and a conductive layer EL3. The conductive layer EL2 may be disposed on the first organic layer PL1 and cover the masking pattern BM2 and the conductive layer EL1. The insulating layer IN7 may be disposed on the first organic layer PL1 and cover the conductive layer EL2, and the conductive layer EL3 may be disposed on the insulating layer IN7. The conductive layer EL2 may contact and be electrically connected to the conductive layer EL1. The conductive layer EL2 may serve as a pixel electrode, the conductive layer EL1 may serve as a connection electrode electrically connecting the conductive layer EL2 and the contact CT, and the conductive layer EL3 may serve as a common electrode, but is not limited thereto. In some embodiments, the substrate SB and the components or films disposed on the substrate SB (e.g., circuit layer CC, shielding pattern BM1, shielding pattern BM2, filter layer CF, first organic layer PL1, conductive layer EL1, conductive layer EL2, and conductive layer EL3) can be considered together as an array substrate, and the shielding pattern BM1, shielding pattern BM2, and filter layer CF of the present invention can be considered as a BMon array (BOA) and CF on array (COA) structural design. By disposing the shielding pattern BM1 and shielding pattern BM2 on one side of the array substrate, the negative impacts such as the decrease in aperture ratio caused by the alignment misalignment when the substrate SB and the opposing substrate OSB are aligned can be reduced. Furthermore, by using the shielding pattern BM1 and the shielding pattern BM2 disposed in the opening between the conductive layer EL1 and the driving circuit DU, the distance between the shielding pattern and the material causing reflection (e.g., but not limited to conductive layer M4, conductive layer M3, conductive layer M2, and / or conductive layer M1) can be further shortened, thereby improving the light shielding effect and reducing light leakage. In addition, the masking pattern BM2 can also be regarded as a replacement for the insulating material filled in the opening connecting the conductive layer EL1 and the driving circuit DU, thus simplifying the overall process steps and reducing production costs.

[0032] In some embodiments, the electronic device 101 may further include a dielectric layer LC, a counter substrate OSB, a protective layer OC, and a shielding pattern BM3. The protective layer OC is disposed on the counter substrate OSB and located on the side of the counter substrate OSB facing the substrate SB. The dielectric layer LC is disposed between the counter substrate OSB and the substrate SB and is located between the protective layer OC and the insulating layer IN7 and / or between the protective layer OC and the conductive layer EL3. In some embodiments, the dielectric layer LC may include a display dielectric layer, such as liquid crystal material or other suitable dielectric material, but is not limited thereto. In other words, the electronic device 101 of this embodiment may include a liquid crystal display device. In other embodiments, the electronic device 101 may include other types of display devices, such as light-emitting diode (LED) display devices, and the dielectric layer LC may include LED elements, but is not limited thereto. The shielding pattern BM3 may be located in the second region R2, for example, to provide a light-shielding effect in the peripheral region of the electronic device 101, but is not limited thereto. In some embodiments, the masking pattern BM3 may be disposed on the opposing substrate OSB and located on the side of the opposing substrate OSB facing the substrate SB, and the protective layer OC may cover the masking pattern BM3. Therefore, the protective layer OC may be partially located between the masking pattern BM3 and the dielectric layer LC in the Z direction, but is not limited thereto. The protective layer OC may include any element or film layer that can provide a protective effect.

[0033] The substrate SB and the opposing substrate OSB can be used to support components and films located thereon. The substrate SB and the opposing substrate OSB may comprise rigid or flexible materials. Rigid materials include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or combinations thereof. Flexible materials include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof. It should be noted that in some embodiments, the substrate SB and the opposing substrate OSB may comprise a multilayer structure, and not necessarily... Figure 3 The structure shown is for illustrative purposes only. Insulating layers IN1, IN2, IN3, IN4, IN5, IN6, and IN7 may each comprise any suitable insulating material, such as organic or inorganic insulating materials. For example, each of the above insulating layers may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiN) x O yThe materials used may be polyimide (PI), polyester, other suitable materials, or combinations thereof. The first organic layer PL1 may include any suitable organic insulating material, such as a low-dielectric-constant organic insulating material or other suitable organic insulating material. Conductive layers M1, M2, M3, and M4 may include any suitable conductive material, such as a metallic conductive material, while conductive layers CL, EL1, EL2, and EL3 may include any suitable conductive material, such as a transparent metal oxide conductive material (e.g., but not limited to, indium tin oxide), but not limited thereto. Masking patterns BM1, BM2, and BM3 may include any suitable light-shielding material, such as black photoresist, black printing ink, black resin, organic resin, or glass paste. In some embodiments, the materials used to form the masking patterns BM1, BM2, the filter layer CF, and the first organic layer PL1 may each have photopatternable properties. Therefore, the masking patterns BM1, BM2, CF, PL1, and the aforementioned openings (e.g., openings OP1, OP2, and OP3) can be formed separately using an exposure and development process, thereby simplifying the relevant process steps, but this is not a limitation. Furthermore, depending on the formation location and / or different process methods, the material compositions of the masking patterns BM1, BM2, and BM3 may be the same or different from each other as the design requires.

[0034] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0035] Please refer to Figure 4 . Figure 4 This is a partial cross-sectional schematic diagram of the electronic device 102 according to a second embodiment of the present invention. Furthermore, in some embodiments, Figure 4 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line A-A' is an example, but not limited to this. Figure 4As shown, in the electronic device 102, the masking pattern BM1 can be disposed on the filter layer CF, so the masking pattern BM1 can be located between the filter layer CF and the first organic layer PL1. In this case, the masking pattern BM1 can be formed after the filter layer CF, thus avoiding the masking pattern BM1 from having a negative impact on the process of forming the filter layer CF.

[0036] Please refer to Figure 5 . Figure 5 This is a partial cross-sectional schematic diagram of the electronic device 103 according to a third embodiment of the present invention. Furthermore, in some embodiments, Figure 5 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line A-A' is an example, but not limited to this. Figure 5 As shown, the electronic device 103 may further include a second organic layer PL2 disposed on the masking pattern BM2 and located in the opening OP2. The masking pattern BM2 may be located between the second organic layer PL2 and the conductive layer EL1, and the upper surface of the second organic layer PL2 may be substantially coplanar with the upper surface of the conductive layer EL1, but is not limited thereto. In some embodiments, the upper surface of the second organic layer PL2 may be slightly higher than, slightly lower than, or even slightly lower than the upper surface of the first organic layer PL1 in the Z direction. The second organic layer PL2 may include any suitable organic insulating material, and the material composition of the second organic layer PL2 may be the same as or different from the material composition of the first organic layer PL1 as required by the design. The second organic layer PL2 may be located between the conductive layer EL2 and the masking pattern BM2, thereby avoiding direct contact between the conductive layer EL2 and the masking pattern BM2, thus reducing the influence of the masking pattern BM2 on the material properties of the conductive layer EL2, but is not limited thereto.

[0037] Please refer to Figure 6 . Figure 6 This is a partial cross-sectional schematic diagram of the electronic device 104 according to the fourth embodiment of the present invention. Furthermore, in some embodiments, Figure 6 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line A-A' is an example, but not limited to this. Figure 6As shown, the electronic device 104 may further include a second organic layer PL2 disposed on the masking pattern BM2 and located in the opening OP2. Furthermore, the masking pattern BM1 may be disposed on the filter layer CF, thus the masking pattern BM1 may be located between the filter layer CF and the first organic layer PL1. In some embodiments, the bottom of the second organic layer PL2 may be higher than the upper surface of the masking pattern BM1 in the Z direction or substantially coplanar with the upper surface of the masking pattern BM1, but is not limited thereto. In other embodiments, the bottom of the second organic layer PL2 may be lower than the upper surface of the masking pattern BM1 in the Z direction, thus the second organic layer PL2 may also be partially disposed in the opening OP1 of the masking pattern BM1.

[0038] Please refer to Figure 7 . Figure 7 This is a partial cross-sectional schematic diagram of the electronic device 105 according to the fifth embodiment of the present invention. Furthermore, in some embodiments, Figure 7 A portion can be considered as along Figure 1 and / or Figure 2The cross-sectional view shown by section line A-A' is not limited thereto. In electronic device 105, a first organic layer PL1 is located on a driving circuit DU and includes a first opening (e.g., opening OP4) and a second opening (e.g., opening OP2). A conductive layer EL1 is electrically connected to the driving circuit DU through opening OP2. Masking patterns BM3 and BM2 are located in openings OP4 and OP2, respectively, and the depth of opening OP4 (e.g., depth DP1) is different from the depth of opening OP2 (e.g., depth DP2). Masking pattern BM3 and opening OP4 are located in a second region R2. Masking pattern BM3 is disposed in opening OP4 of the first organic layer PL1, and opening OP2 of the first organic layer PL1 is located in the first region R1, and the depth DP2 of opening OP2 is greater than the depth DP1 of opening OP4. In this invention, the depth of the opening can also be considered as the length of the opening in the Z direction, and opening OP4, which does not penetrate the first organic layer PL1, can also be considered as a recess located in the first organic layer PL1. In some embodiments, the material used to form the first organic layer PL1 may have photo-patternable properties. Using photomasks with different light transmittance regions (e.g., but not limited to gray-tone and half-tone photomasks) for exposure and development processes can form openings of different depths in the first organic layer PL1, thereby simplifying the process and / or reducing production costs, but this is not a limitation. In this embodiment, the masking pattern BM3 is disposed in the opening OP4 of the first organic layer PL1. The masking pattern BM3 may be located between the insulating layer IN7 and the first organic layer PL1 in the Z direction; therefore, the masking pattern BM3 can be considered a structural design of the BOA. Furthermore, due to the formation location and / or different process methods, the material composition of the masking pattern BM3 disposed in the opening OP4 may differ from the material composition of the masking pattern BM3 disposed on the opposing substrate OSB in the above embodiments. For example, the light density of the masking pattern BM3 disposed in the opening OP4 may be lower than that of the masking pattern BM3 disposed on the opposing substrate OSB, but this is not a limitation. Therefore, in some embodiments, the electronic device 105 may include a shielding layer LS1 disposed on the insulating layer IN6 and located in the second region R2. The shielding layer LS1 may overlap with the shielding pattern BM3 in the Z direction, thereby enhancing the light-shielding effect in the second region R2. In some embodiments, the shielding layer LS1 may be part of the conductive layer M4, so the shielding layer LS1 and the contact CT may have the same material composition, but are not limited thereto.

[0039] Please refer to Figure 1 , Figure 2 and Figure 8 . Figure 8 This is a partial cross-sectional schematic diagram of the electronic device 106 according to the sixth embodiment of the present invention. Furthermore, in some embodiments, Figure 8 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line B-B' is not limited to this. Figure 1 , Figure 2 and Figure 8 As shown, in the electronic device 106, the first organic layer PL1 may further include an opening OP5, and a masking pattern BM1 may be disposed in the opening OP5. In some embodiments, the depth of the opening OP5 (e.g., depth DP3) may be different from the depth DP2 of the opening OP2; for example, the depth DP3 of the opening OP5 may be less than the depth DP2 of the opening OP2. In some embodiments, the openings OP2, OP4, and OP5 in the first organic layer PL1 may have different or the same depth; for example, the depth DP3 of the opening OP5 may be greater than the depth DP1 of the opening OP4, but this is not a limitation. In other embodiments, the depth DP3 of the opening OP5 may be less than the depth DP1 of the opening OP4. The masking pattern BM1 and the opening OP5 are located in the first region R1 and overlap the data line DL, and the masking pattern BM1 and the opening OP5 may be along the extension direction of the data line DL (e.g., along the extension direction of the data line DL). Figure 1 and Figure 2 The direction shown is XD). The opening OP5, which does not penetrate the first organic layer PL1, can also be considered as a recess located in the first organic layer PL1, which may be partially located in the Z direction between the shielding pattern BM1 and the filter layer CF. The opening OP5 may be formed on the surface of the first organic layer PL1 that is farther away from the filter element CE1. In some embodiments, the electronic device 106 may also include a shielding layer LS2 disposed on the insulating layer IN6 and located in the first region R1. The shielding layer LS2 may overlap with the shielding pattern BM1 in the Z direction to compensate for the negative impact caused by the relatively large distance between the shielding pattern BM1 and the data line DL due to its location in the opening OP5. For example, the shielding layer LS2 may be used to improve the light shielding effect, but is not limited thereto. In some embodiments, the shielding layer LS2 may be part of the conductive layer M4, so the shielding layer LS2 and the contact CT may have the same material composition, and the filter layer CF may cover the shielding layer LS2 and be partially located between the first organic layer PL1 and the shielding layer LS2, but is not limited thereto. In some embodiments, when the masking pattern BM1 and the masking pattern BM2 are disposed in the opening of the first organic layer PL1, the masking pattern BM3 located in the second region R2 may also be disposed on the opposing substrate OSB for matching.

[0040] Please refer to Figure 9 . Figure 9 This is a partial cross-sectional schematic diagram of the electronic device 107 according to the seventh embodiment of the present invention. Furthermore, in some embodiments, Figure 9 A portion can be considered as along Figure 1 and / or Figure 2The sectional view shown by section line B-B' is not limited to this. Figure 9 As shown, in the electronic device 107, the filter layer CF may also be partially disposed in the second region R2, and the first organic layer PL1 may be partially located in the Z direction between the masking pattern (e.g., masking pattern BM1, masking pattern BM3) and the filter layer CF. In some embodiments, the filter layer CF may include a filter element CE2 disposed in the second region R2, and the first organic layer PL1 may be partially located in the Z direction between the masking pattern BM3 and the filter element CE2. Furthermore, the filter element CE1 located in the first region R1 may include a red, green, blue, or other suitable color filter element, and the filter element CE2 located in the second region R2 may also include a red, green, blue, or other suitable color filter element. The filter layer CF disposed in the second region R2 may overlap with the masking pattern BM3 in the Z direction, thereby improving the light-blocking effect in the second region R2.

[0041] Please refer to Figure 10 . Figure 10 This is a partial cross-sectional schematic diagram of the electronic device 108 according to the eighth embodiment of the present invention. Furthermore, in some embodiments, Figure 10 A portion can be considered as along Figure 1 and / or Figure 2 The sectional view shown by section line B-B' is not limited to this. Figure 10As shown, in electronic device 108, masking patterns BM1 and BM2 can be disposed on insulating layer IN7, and masking patterns BM1 and BM2 can act as spacers, used in some embodiments to control the distance between opposing substrate OSB and substrate SB and / or control the space for accommodating dielectric layer LC. Therefore, masking patterns BM1 and BM2 can directly contact dielectric layer LC, but are not limited thereto. In some embodiments, masking patterns BM1 and BM2 can be disposed on conductive layer EL3, and a portion of conductive layer EL3 can be located in direction Z between masking pattern BM1 and insulating layer IN7 or between masking pattern BM2 and insulating layer IN7. Furthermore, the upper surface TS1 of masking pattern BM1 and the upper surface TS2 of masking pattern BM2 can be at the same or different heights in direction Z as required by design, and the thickness TK1 of masking pattern BM1 in direction Z can be substantially equal to or different from the thickness TK2 of masking pattern BM2 in direction Z as required by design. For example, when the masking pattern BM1 is used as the main spacer, the upper surface TS1 of the masking pattern BM1 may be higher than the upper surface TS2 of the masking pattern BM2 in the Z direction, and the thickness TK1 of the masking pattern BM1 may be greater than the thickness TK2 of the masking pattern BM2, but this is not a limitation. In some embodiments, the materials used to form the masking patterns BM1 and BM2 may have photo-patternable properties, and the masking patterns BM1 and BM2 may be formed simultaneously using photomasks with different light transmittance regions through an exposure and development process, and the height and / or thickness of the masking patterns BM1 and BM2 may be controlled, but this is not a limitation.

[0042] Furthermore, in some embodiments, the masking pattern BM3 may also be disposed on the insulating layer IN7, and the masking pattern BM3 may be located between the dielectric layer LC and the insulating layer IN7 in the Z direction. The upper surface TS3 of the masking pattern BM3 may be lower than the upper surface TS1 of the masking pattern BM1 and the upper surface TS2 of the masking pattern BM2 in the Z direction, and the thickness TK3 of the masking pattern BM3 in the Z direction may be less than the thickness TK1 of the masking pattern BM1 and the thickness TK2 of the masking pattern BM2, but is not limited thereto. In other embodiments, the upper surface TS3 of the masking pattern BM3 may be higher than the upper surface TS1 of the masking pattern BM1 and the upper surface TS2 of the masking pattern BM2 in the Z direction, and the thickness TK3 of the masking pattern BM3 in the Z direction may be greater than the thickness TK1 of the masking pattern BM1 and the thickness TK2 of the masking pattern BM2. In some embodiments, the material composition of the masking pattern BM3 may be the same as that of the masking patterns BM1 and BM2, and the masking patterns BM3, BM2, and BM1 can be formed together through the same process (e.g., but not limited to exposure and development processes) to simplify the relevant processes and control the height and / or thickness of the masking patterns BM1, BM2, and BM3, but this is not a limitation. In some embodiments, when the masking patterns BM1 and BM2 are disposed on the insulating layer IN7 as spacers, the masking pattern BM3 located in the second region R2 may also be disposed on the opposing substrate OSB for matching. Furthermore, when the masking patterns BM1, BM2, and BM3 are disposed on the insulating layer IN7, the above-mentioned... Figure 8 The design of the shielding layers LS1 and LS2 in the middle does not include a filter layer in the second area R2 to achieve the required light-blocking effect.

[0043] In summary, in the electronic device of the present invention, by setting the masking pattern on one side of the array substrate, the negative impacts such as the decrease in aperture ratio caused by the alignment misalignment during the assembly of the substrate and the opposing substrate can be reduced. Furthermore, by setting the masking pattern in the opening connecting the conductive layer and the driving circuit, the distance between the masking pattern and the material causing reflection can be further shortened, thereby improving the light-shielding effect and / or simplifying the relevant process steps, thereby improving the display quality of the electronic device and / or reducing the production cost.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electronic device, characterized in that, include: One substrate; A driving circuit is located on the substrate; A first masking pattern is located on the driving circuit and includes a first opening; A first organic layer is located on the first masking pattern and includes a second opening that overlaps the first opening; A conductive layer is electrically connected to the driving circuit through the first opening and the second opening; and A second masking pattern is located in the first opening and the second opening.

2. The electronic device as claimed in claim 1, characterized in that, Also includes: A filter layer is located between the first masking pattern and the first organic layer.

3. The electronic device as claimed in claim 1, characterized in that, Also includes: A filter layer, wherein the first masking pattern is located between the filter layer and the first organic layer.

4. The electronic device as claimed in claim 1, characterized in that, Also includes: A second organic layer is disposed on the second masking pattern and located in the second opening.

5. The electronic device as claimed in claim 1, characterized in that, Also includes: A filter layer, the filter layer including a third opening overlapping the second opening, and the second masking pattern located in the third opening.

6. An electronic device, characterized in that, include: One substrate; A driving circuit is located on the substrate; A first organic layer is located on the driving circuit and includes a first opening and a second opening; A conductive layer is electrically connected to the driving circuit through the second opening; and A first masking pattern and a second masking pattern are respectively located in the first opening and the second opening, wherein the depth of the first opening is different from the depth of the second opening.

7. The electronic device as claimed in claim 6, characterized in that, The driving circuit includes a data line, the first opening overlaps the data line, and the first opening extends along the extension direction of the data line.

8. The electronic device as claimed in claim 6, characterized in that, The first opening is located in the surrounding area.

9. The electronic device as claimed in claim 8, characterized in that, Also includes: A filter layer, wherein the first organic layer is located between the first masking pattern and the filter layer.

10. The electronic device as claimed in claim 6, characterized in that, Also includes: A filter layer, the filter layer including a third opening overlapping the second opening, and the second masking pattern located in the third opening.

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