Transistor and display device using the same

Abstract

Disclosed are a transistor and a display device including the same. The transistor includes an active layer over a substrate; a first metal pattern and a second metal pattern disposed under the active layer while overlapping the active layer, the first metal pattern and the second metal pattern spaced apart from each other by a first distance in a first direction; a gate electrode disposed on the active layer while overlapping the active layer, the gate electrode having a width greater than the first distance in the first direction; a gate insulating layer between the active layer and the gate electrode; a first source / drain electrode connected to the first metal pattern; and a second source / drain electrode connected to the second metal pattern and spaced apart from the first source / drain electrode.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0015341, filed on February 6, 2025, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to transistors, and more specifically, to a transistor configured to prevent changes in effective channel length and to achieve enhanced reliability, and a display device including the transistor. Background Technology

[0003] Various types and forms of display devices are used to display images in TVs, monitors, smartphones, tablets, laptops, and other similar devices.

[0004] This display device includes multiple pixels to render images and is equipped with transistors to control the operation of the pixels on a pixel-by-pixel basis.

[0005] This type of display device, which includes multiple pixels, has multiple driving and switching elements to drive and control the pixels. The driving and switching elements can be composed of transistors. Such transistors are widely used not only in pixels but also in integrated circuits.

[0006] Recently, various research and development efforts have been undertaken to improve the performance and reliability of transistors. Summary of the Invention

[0007] Therefore, this disclosure relates to transistors and display devices using the transistors, which substantially eliminate one or more problems caused by the limitations and disadvantages of related technologies.

[0008] According to embodiments of this disclosure, the object of this disclosure is to realize a transistor that can prevent and / or reduce changes in the effective channel length by adding a conductive metal.

[0009] According to embodiments of this disclosure, transistors can be constructed by providing a conductive metal, thereby omitting separate ion doping and metallization processes after forming a gate electrode configured to define a metallized region.

[0010] According to embodiments of the present disclosure, a transistor can be configured to include a gate electrode independent of the channel, such that the gate electrode, although overlapping with the active layer, still has design freedom, thereby facilitating integrated design.

[0011] According to embodiments of the present disclosure, the transistor and the display device including the transistor are configured such that a gate electrode larger than the channel region of the active layer is provided above the active layer, thereby preventing the influence of residual hydrogen in the layer above the gate electrode.

[0012] According to embodiments of this disclosure, the transistor further includes a mobility control layer configured to overlap with the channel region, thereby enabling high-speed driving.

[0013] According to embodiments of the present disclosure, another object of the present disclosure is to provide a display device that can reduce the defect rate of its transistors to reduce the amount of materials such as gases and etchants used in the entire manufacturing process of the display device, thereby reducing greenhouse gas emissions caused by the manufacturing process.

[0014] The purpose of this disclosure is not limited to the foregoing, and other purposes of this disclosure, which have not yet been described, will be more clearly understood by those skilled in the art from the following description.

[0015] In one aspect of this disclosure, a transistor includes: an active layer on a substrate; a first metal pattern and a second metal pattern disposed below the active layer while overlapping with the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; a gate electrode disposed on the active layer while overlapping with the active layer, the gate electrode having a width greater than the first distance in the first direction; a gate insulating layer between the active layer and the gate electrode; a first source / drain electrode connected to the first metal pattern; and a second source / drain electrode connected to the second metal pattern and spaced apart from the first source / drain electrode.

[0016] In another aspect of this disclosure, a display device includes: a plurality of sub-pixels, wherein the transistor is disposed in at least one of the plurality of sub-pixels; a planarization layer covering the transistor; and a light-emitting element disposed on the planarization layer.

[0017] In another aspect of this disclosure, a display device includes: a substrate including an effective region and an ineffective region surrounding the effective region, the effective region including a plurality of sub-pixels; a plurality of gate lines and a plurality of data lines intersecting each other at the plurality of sub-pixels; a light-emitting element at each of the plurality of sub-pixels; a pixel transistor in at least one of the plurality of sub-pixels; a driver connected to the plurality of gate lines and disposed in the ineffective region; and a driver transistor in the driver. At least one of the pixel transistor and the driver transistor may include: an active layer on the substrate; a first metal pattern and a second metal pattern disposed below the active layer while overlapping with the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; a gate electrode disposed on the active layer while overlapping with the active layer, the gate electrode having a width greater than the first distance in the first direction; a gate insulating layer between the active layer and the gate electrode; and source and drain electrodes respectively connected to the first metal pattern and the second metal pattern. Attached Figure Description

[0018] The accompanying drawings, which provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0019] Figure 1 This is a plan view showing a display device according to an embodiment of the present disclosure;

[0020] Figure 2 It is shown Figure 1 The diagram shows a cross-sectional view of the display panel in a bent state.

[0021] Figure 3 This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present disclosure;

[0022] Figure 4 This is a circuit diagram illustrating the construction of an in-panel gate according to an embodiment of the present disclosure;

[0023] Figure 5 This is a plan view showing a transistor according to a first embodiment of the present disclosure;

[0024] Figure 6 It is along Figure 5 A cross-sectional view taken from line I-I' in the diagram;

[0025] Figure 7 It is along Figure 5 A cross-sectional view taken from line II-II' in the diagram;

[0026] Figure 8 This is a plan view showing a transistor according to a second embodiment of the present disclosure;

[0027] Figure 9 It is along Figure 8 A cross-sectional view taken from line III-III' in the diagram;

[0028] Figure 10 This is a plan view showing a transistor according to a third embodiment of the present disclosure;

[0029] Figure 11 It is along Figure 10 A cross-sectional view taken from line IV-IV' in the diagram;

[0030] Figure 12 This is a plan view showing a transistor according to a fourth embodiment of the present disclosure;

[0031] Figure 13 It is along Figure 12 A cross-sectional view taken from line V-V' in the diagram;

[0032] Figures 14 to 16 These are cross-sectional views showing various embodiments of the display device according to the present disclosure. Detailed Implementation

[0033] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the class of the claims.

[0034] The same reference numerals denote the same constituent elements. For the purpose of effectively describing the technical content, the thickness, proportions, and dimensions of the constituent elements may be exaggerated in the drawings. Furthermore, for ease of description, the dimensions and proportions of the constituent elements shown in the drawings differ from the actual dimensions and proportions; therefore, the dimensional proportions of the constituent elements are not limited to those shown in the drawings.

[0035] It should be understood that when a component (or region, layer, part, etc.) is referred to as being "set on another component", "connected to", or "coupled to" another component, a component may be directly connected / coupled to another component, or a third component may be set between two components.

[0036] The term "and / or" is used to include one or more combinations of associated constructs.

[0037] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element referred to in the following description may mean a second element. Similarly, a second element may mean a first element. Unless expressly used otherwise, singular expressions include plural meanings.

[0038] Terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are interpreted based on the orientations indicated in the drawings. For example, one or more other components may be positioned between two parts unless “directly” or “immediately” is used. Spatially relative terms such as “below,” “below,” “lower,” “above,” and “upper” can be used to readily describe the relationship between one device or component as shown in the drawings and other devices or components. In addition to the orientations shown in the drawings, these spatially relative terms should be understood to cover different orientations of the device when in use or during operation. For example, if the device in one of the drawings is flipped, an component described as “below” or “below” other elements would be oriented “above” other elements. Thus, the exemplary term “below” can include both downward and upward directions.

[0039] In this specification, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the features, quantities, steps, operations, elements, components, or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0040] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate differently with each other and be technically driven. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0041] In the following, a detailed description of transistors and display devices according to embodiments of the present disclosure will be given with reference to the accompanying drawings.

[0042] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 The diagram shows a cross-sectional view of the display panel in a bent state. Figure 3 This is a circuit diagram illustrating a sub-pixel according to an embodiment of the present disclosure. Figure 4 This is a circuit diagram illustrating the structure of the gate inside the panel according to an embodiment of the present invention.

[0043] Reference Figure 1The display device according to the embodiment, indicated by reference numeral 1000, may include a display panel 110. The display panel 110 may include an effective area AA having a plurality of sub-pixels SP and an ineffective area NA surrounding the effective area AA. The planar shape of the effective area AA may be rectangular. However, the planar shape of the effective area AA is not limited to a rectangle; it may also be a square, circle, ellipse, or other polygon. For example, the effective area AA may be a rectangle with rounded corners, but is not limited thereto; it may also be a rectangle with sharp corners.

[0044] In the implementation, the first direction X and the second direction Y are different directions that intersect each other; for example, they are represented as perpendicularly intersecting directions in a plan view. Figure 1 In the embodiments, the first direction X roughly corresponds to the extension direction of the short side of the display panel 110, and the second direction Y roughly corresponds to the extension direction of the long side of the display panel 110. However, the directions described in the embodiments should be understood as relative directions, and the embodiments are not limited to these explicitly described directions.

[0045] The effective area AA may include a short side extending in the first direction X and a long side extending in the second direction Y. The ineffective area NA may surround the effective area AA. The ineffective area NA may be located on one side of the effective area AA in the first direction X, on the opposite side of the effective area AA in the first direction X, on one side of the effective area AA in the second direction Y, and on the opposite side of the effective area AA in the second direction Y.

[0046] The display panel 110 may also include sensor holes SH1 and SH2, which are configured to overlap with the effective area AA and allow a sensor S to be disposed therein. The sensor S is disposed below the display panel 110 and may have a shape larger than the sensor holes. Although the sensor holes are as... Figure 1 The diagram may include two sensor holes SH1 and SH2, but embodiments of this disclosure are not limited to this. For example, only one sensor hole may be provided. The two sensor holes SH1 and SH2 may include a sensor hole in which an infrared sensor is disposed and a sensor hole in which a camera sensor is disposed, but embodiments of this disclosure are not limited to these configurations. A sensor inactive area may be included between the sensor holes SH1 and SH2 and the active area AA. The sensor inactive area may completely surround the sensor holes SH1 and SH2. Subpixels SP may not be provided in the sensor inactive area.

[0047] In some cases, sensor holes SH1 and SH2 may not be located on the display panel 110, and sensor S may be configured to overlap with the display panel 110. In this case, sensor S and sub-pixel SP may partially overlap each other. The area where sensor S overlaps with display panel 110 will be referred to as the sensor area.

[0048] The in-panel gates (GIPs) can be respectively disposed in the inactive regions NA on both sides of the active region AA in the first direction X. Each in-panel gate GIP is a gate driver configured to supply gate voltage to the gate line GL. A low-level voltage line VSSL can be disposed on the outside of the inactive region NA, on the inactive region NA. For example, as shown... Figure 1 As shown, the low-level voltage line VSSL can extend from the flexible printed circuit board FPCB, pass through the sub-region SR and the bent region BR, and be positioned on the outside of the in-panel gate GIP on the non-active region NA, while surrounding the active region AA.

[0049] The ineffective area NA, located on the opposite side of the effective area AA in the second direction Y, may extend further from the center of the effective area AA toward the opposite side of the second direction Y. The width of the ineffective area NA extending further from the center of the effective area AA toward the opposite side of the second direction Y may be less than the width of the adjacent ineffective area NA in the first direction X.

[0050] The display device 1000 may include a main region MR, a sub-region SR, and a curved region BR between the main region MR and the sub-region SR. An active region AA and inactive regions NA surrounding the active region AA on its four sides constitute the main region MR. A portion of the inactive region NA extending further from the center of the active region AA toward the opposite side of the active region AA in the second direction Y may constitute the curved region BR and the sub-region SR. The curved region BR may be disposed between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 disposed at the ends of the sub-region SR on the opposite side of the second direction Y. The display device 1000 may also include a data driver DIC and a flexible printed circuit board FPCB. The data driver DIC may be disposed in the first pad region PA1, and the flexible printed circuit board FPCB may be attached to the second pad region PA2. Multiple pads connected to the data driver DIC and the flexible printed circuit board FPCB may be disposed in the first pad region PA1 and the second pad region PA2. The data driver DIC may be in the form of a driver chip IC, but is not limited thereto. Although in one embodiment the data driver DIC has been shown as being directly mounted to the display panel 110 in a chip-on-plastic (COP) manner, this disclosure is not limited thereto. The data driver DIC may be disposed in a chip-on-glass (COG) manner or a chip-on-film (COF) manner.

[0051] In one embodiment, the display panel 110 may further include a crack sensing pattern CSP configured to surround a low-level voltage line VSSL. For example... Figure 1 As shown, the crack sensing pattern CSP can be configured to completely surround the active region AA. For example, the crack sensing pattern CSP can be positioned outside the low-level voltage line VSSL. However, embodiments of this disclosure are not limited to the above configuration. The crack sensing pattern CSP may not be positioned in the non-active region NA on the opposite side of the active region AA in the second direction Y.

[0052] Reference Figure 2 In one embodiment, the curved region BR of the display panel 110 in the display device 1000 can be bent in the thickness direction (or the third direction Z). This allows the main region MR and the sub-region SR to overlap each other in the thickness direction. The display panel 110 can be bent such that the lower surface of the main region MR and the upper surface of the sub-region SR face each other. A flexible printed circuit board (FPCB) can be attached to the end of the sub-region SR.

[0053] The effective area AA is the area configured to display an image. Multiple subpixels SP are provided in the effective area AA of the display panel 110, therefore, multiple subpixels SP can be used to display an image. The area outside the effective area AA can constitute the ineffective area NA.

[0054] The inactive area NA can be located in the edge region surrounding the active area AA of the displayed image. In the inactive area NA, at least one driver can be provided to drive multiple sub-pixels SP. The driver may include an in-panel gate GIP. The in-panel gate GIP can be connected to multiple gate lines GL in the active area AA and can sequentially provide gate voltage signals to the multiple gate lines GL.

[0055] In the non-active area NA, various additional elements required to drive the sub-pixels SP in the active area AA can be further configured.

[0056] like Figure 3 As shown, at least one of the multiple sub-pixels SP may include a first transistor T1, a second transistor T2, a storage capacitor Cst, a compensation circuit CC, and a light-emitting element ED.

[0057] For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor.

[0058] The first electrode (e.g., drain electrode) of the first transistor T1 is electrically connected to the data line DL, and the second electrode (e.g., source electrode) of the first transistor T1 is electrically connected to the first node N1. The gate electrode of the first transistor T1 is electrically connected to the gate line GL. In response to a scan signal provided via the gate line GL, the first transistor T1 transmits a data signal provided via the data line DL to the first node N1.

[0059] The storage capacitor Cst is electrically connected to the first node N1 and is therefore charged by the voltage applied to the first node N1.

[0060] The first electrode (e.g., drain electrode) of the second transistor T2 receives a high-level drive voltage EVDD, and the second electrode (e.g., source electrode) of the second transistor T2 is electrically connected to the first electrode (e.g., anode) of the light-emitting element ED. The second transistor T2 can control the amount of drive current flowing through the light-emitting element ED according to the voltage applied to the gate electrode.

[0061] The semiconductor layer of the first transistor T1 and / or the second transistor T2 may include, but is not limited to, silicon such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), low-temperature polycrystalline silicon (LT poly-Si), or oxides such as indium gallium zinc oxide (IGZO). At least one of the first transistor T1 and the second transistor T2 may include an oxide semiconductor layer, thus allowing it to be formed at low temperatures, maintaining amorphous properties, and exhibiting high mobility compared to other materials.

[0062] An LED (Emitting Diode) outputs light corresponding to the driving current. An LED can output light corresponding to one of the following colors: red, green, blue, or white.

[0063] A light-emitting element (ED) may include a first electrode (anode), an intermediate layer disposed on the first electrode, and a second electrode (cathode) configured to receive a common voltage. The intermediate layer may include at least one light-emitting layer, thus enabling the emission of light of the same color, such as white light, on a pixel-by-pixel basis, or the emission of light of different colors, such as red, green, and blue light, on a sub-pixel (SP) basis. The intermediate layer may include various common layers and functional layers to effectively provide holes and electrons to the light-emitting layer.

[0064] The light-emitting element (ED) can be a front-emitting diode or a bottom-emitting diode.

[0065] The first electrode (anode) of the light-emitting element ED is connected to the second transistor T2 and receives the drive current. The second electrode (cathode) is connected to... Figure 1 The low-level voltage line VSSL in the non-active region NA can therefore receive the low-level voltage EVSS or the ground voltage.

[0066] A compensation circuit CC can be separately disposed within the sub-pixel SP to compensate for the threshold voltage of the second transistor T2, etc. The compensation circuit CC can be composed of one or more transistors. The compensation circuit CC may include one or more transistors and capacitors, and can be configured differently depending on the compensation method. The sub-pixel SP including the compensation circuit CC may include circuits with various structures having different numbers of transistors and / or capacitors, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0067] Among the transistors included in a sub-pixel, the switching transistors may require high-speed driving to enable fast switching operations.

[0068] The in-panel gate IP (GIP) included in the non-active region NA outputs a gate signal to the gate line in response to a gate control signal, for example, input from a timing controller. The in-panel gate IP may include multiple transistors, and these transistors may be formed in the same process as the transistors of the sub-pixel SP.

[0069] For example, such as Figure 4 As shown, the in-panel gate GIP may include stages STT1 connected to each other in a non-independent manner, and stages STT1 may sequentially output gate signals to the gate lines.

[0070] like Figure 4 As shown, each stage STT1 includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU, a pull-down transistor TD, and a node controller NC. The pull-up transistor TU is configured to turn on when the pull-up node NQ is charged by a high gate voltage, the pull-down transistor TD is configured to turn on when the pull-down node NQB is charged by a high gate voltage, and the node controller NC is configured to control the charging and discharging of the pull-up node NQ and the pull-down node NQB.

[0071] The node controller NC can be connected to a start signal line and a clock line. The start signal or a carry signal from the upstream stage is input to the start signal line, and one of the gate clock signals is input to the clock line. The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB based on the start signal or carry signal from the upstream stage input to the start signal line and the gate clock signal input to the clock line. To stabilize the output of the control stage STT1, the node controller NC discharges the voltage of the pull-down node NQB to a low gate voltage when the pull-up node NQ is charged with a high gate voltage, and discharges the voltage of the pull-up node NQ to a low gate voltage when the pull-down node NQB is charged with a high gate voltage. The node controller NC may include multiple transistors for these functions.

[0072] When stage STT1 is pulled up, for example when pull-up node NQ is charged with a high gate voltage, pull-up transistor TU turns on, thereby outputting the gate clock signal of clock line CL to output terminal OT. When stage STT1 is pulled down, for example when pull-down node NQB is charged with a high gate voltage, pull-down transistor TD turns on, thereby outputting the gate low voltage of gate low terminal VGLT to output terminal OT.

[0073] exist Figure 4 In this case, each of the multiple transistors in the pull-up transistor TU, pull-down transistor TD, and node controller NC in each stage of the gate GIP in the panel can be a fast-response switching transistor.

[0074] Furthermore, despite Figure 3 and Figure 4 The diagram shows that each of the pull-up transistors TU, pull-down transistors TD, and multiple transistors of the node controller NC in each stage STT1 of the in-panel gate GIP is composed of an N-type semiconductor transistor with N-type semiconductor characteristics. However, embodiments of this disclosure are not limited to this. That is, each of the pull-up transistors TU, pull-down transistors TD, and multiple transistors of the node controller NC in each stage STT1 of the in-panel gate GIP can be composed of a P-type semiconductor transistor with P-type semiconductor characteristics.

[0075] In addition to the in-panel gate IP (GIP), the display panel 110 may also include a data driver. For example, the data driver may include at least one source driver integrated circuit (hereinafter referred to as IC). The source driver IC receives digital video data and source control signals from a timing controller. The source driver IC converts the digital video data into an analog data voltage according to the source control signals, and then provides the analog data voltage to the data line DL.

[0076] When the source driver IC is composed of a driver chip such as an integrated circuit, the source driver IC can be mounted on a flexible film in a chip-on-film (COF) manner. On the flexible film, wiring is formed to connect the source driver IC to pads and wiring is formed to connect the pads to circuit board wiring. The flexible film uses anisotropic conductive films attached to the pads, such as data pads formed in the non-active area NA of the display panel 110; therefore, the pads and the wiring of the flexible film can be interconnected.

[0077] As described above, in the display device according to embodiments of the present disclosure, each sub-pixel SP includes at least one transistor as a switching element, and the in-panel gate GIP, configured as a driver in the inactive region NA, includes multiple transistors to sequentially output gate signals to gate lines. In display devices requiring fast driving due to high resolution, it is desirable for the multiple transistors of the in-panel gate GIP to have increased fast response so that the in-panel gate GIP can output stable gate signals.

[0078] The transistor and a display device including the transistor will be described in detail below. The transistor has a short channel and exhibits minimal variation in effective channel length, making it suitable for easy application of high resolution to the substrate of this disclosure.

[0079] Figure 5 This is a plan view showing a transistor according to a first embodiment of the present disclosure. Figure 6 It is along Figure 5 The cross-sectional view taken from line I-I' in the diagram. Figure 7 It is along Figure 5 The cross-sectional view taken from line II-II' in the diagram.

[0080] like Figures 5 to 7 As shown, the transistor T according to the first embodiment of this disclosure includes an active layer ACT disposed on a substrate 2000, a first metal pattern CM1 and a second metal pattern CM2 disposed below the active layer ACT and spaced apart from each other by a first distance L in a first direction, and a gate electrode G disposed on the active layer ACT, with a gate insulating layer GI between the active layer ACT and the gate electrode G. The gate electrode G has a width greater than the first distance L in the first direction and overlaps with the active layer ACT. The transistor T also includes a first source / drain electrode SD1 connected to the first metal pattern CM1 and a second source / drain electrode SD2 spaced apart from the first source / drain electrode SD1 and connected to the second metal pattern CM2.

[0081] The first metal pattern CM1 and the second metal pattern CM2 are layers disposed below the active layer ACT while simultaneously contacting it. The first metal pattern CM1 and the second metal pattern CM2 are directly connected to the first source / drain electrode SD1 and the second source / drain electrode SD2, respectively. Therefore, the ion impurity doping process or metallization process for the active layer ACT can be omitted.

[0082] The first metal pattern CM1 and the second metal pattern CM2 inherently possess conductive properties, and the surfaces of the active layer ACT facing the first metal pattern CM1 and the second metal pattern CM2 can have low resistance characteristics compared to other regions of the active layer ACT.

[0083] In this case, the first metal pattern CM1 and the second metal pattern CM2 are made of a conductive metal material. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0084] The channel region CH of the active layer ACT may have a channel length L in a first direction (e.g., the X-axis direction) corresponding to a first distance L. The channel region CH of the active layer ACT may have a width W in a second direction (e.g., the Y-axis direction) intersecting the channel length L.

[0085] Here, the first direction can be any direction on the surface of the substrate 2000 in the XY dimension. Therefore, the first direction can correspond to the arrangement direction of the gate line GL or the arrangement direction of the data line DL. Alternatively, the first direction can be a diagonal direction that intersects the gate line GL at an acute angle of less than 90°.

[0086] The first direction described below can refer to the X-axis direction, the Y-axis direction, or the diagonal direction.

[0087] A portion of the lower surface of the active layer ACT can contact the first metal pattern CM1 and the second metal pattern CM2.

[0088] like Figure 6 and Figure 7 As shown in the cross-sectional view, the active layer ACT can be set along the steps of the upper and side surfaces of the first metal pattern CM1 and the second metal pattern CM2. The channel region CH of the active layer ACT is defined as the region between the first metal pattern CM1 and the second metal pattern CM2 that are adjacent to each other. Here, the region of the active layer ACT that directly faces and contacts the first metal pattern CM1 and the second metal pattern CM2 can be defined as the first source / drain region SDA and the second source / drain region SDB. Since the first source / drain region SDA and the second source / drain region SDB are in contact with the first metal pattern CM1 and the second metal pattern CM2, the first source / drain region SDA and the second source / drain region SDB exhibit higher conductivity and lower resistivity than the channel region CH of the active layer ACT in the region that is not in contact with the first metal pattern CM1 and the second metal pattern CM2.

[0089] The active layer ACT can be constructed as a single layer or as a multilayer structure with different mobilities. The active layer ACT may include oxide semiconductors. When the active layer ACT includes a multilayer structure of oxide semiconductor layers, the oxide semiconductor layers can exhibit different mobilities.

[0090] The active layer (ACT) may include, for example, an oxide semiconductor material. The oxide semiconductor material may be composed of a combination of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with an oxide. In some cases, a metal with high conductivity (e.g., iron (Fe)) may be further included in the oxide semiconductor material to increase mobility.

[0091] In each embodiment of the display device according to this disclosure, the active layer ACT can exhibit different mobilities in different regions of the display device to correspond to the response times of different transistors. For example, in a sub-pixel including a switching transistor configured to receive a gate voltage from a gate line or a light emission control signal from a light emission control line and a driving transistor configured to provide a driving current to a light emission element, a high-mobility oxide semiconductor layer can be included in the active layer of the switching transistor to enable different transistors to exhibit different mobilities. For example, in a pixel transistor included in a sub-pixel and a driver transistor disposed in a non-active region, a high-mobility active layer can be applied to the active layer of the driver transistor.

[0092] When the active layer ACT is composed of multiple layers, those layers that do not directly contact the first metal pattern CM1 and the second metal pattern CM2 can be partially used as channel regions in areas disposed on adjacent inner portions of the first metal pattern CM1 and the second metal pattern CM2. In this case, it can be ensured that the channel region CH has a length corresponding to the sum of the lengths of the inner portions of the first metal pattern CM1 and the second metal pattern CM2 and the first distance L between the first metal pattern CM1 and the second metal pattern CM2. Therefore, the channel length of the channel region CH can be greater than the first distance L.

[0093] The gate electrode G can completely overlap with the region between the first metal pattern CM1 and the second metal pattern CM2 in the first direction, and can also overlap with at least one of the first metal pattern CM1 and the second metal pattern CM2. That is, as Figure 5 As shown, the gate electrode G can be configured to have a width greater than the first distance L in the first direction. Since the channel region CH within the active layer ACT is defined by setting the first metal pattern CM1 and the second metal pattern CM2 below the active layer ACT, and is independent of the gate electrode G, the arrangement of the gate electrode G is not limited by the channel region. Therefore, the design freedom of the gate electrode G can be increased.

[0094] Furthermore, with the area of ​​the gate electrode G larger than the area of ​​the channel region CH, the gate electrode G is positioned above the active layer ACT. Therefore, hydrogen remaining in the layer above the gate electrode G can be prevented from affecting the active layer ACT. An interlayer insulating layer (ILD) is disposed on the gate electrode G of the transistor T. Even when residual hydrogen in the interlayer insulating layer ILD diffuses downwards during heat treatment, the gate electrode G, with its larger area than the channel region CH, can effectively prevent hydrogen from diffusing vertically from the interlayer insulating layer ILD into the channel region CH below.

[0095] like Figure 6 and Figure 7 As shown, the first source / drain electrode SD1 and the second source / drain electrode SD2 can be connected to the first metal pattern CM1 and the second metal pattern CM2 respectively through the first contact hole CT1 and the second contact hole CT2 extending through the active layer ACT.

[0096] The light-shielding pattern BSM overlapping the active layer ACT can be included between the active layer ACT and the substrate 2000.

[0097] A light-shielding pattern (BSM) is provided to prevent light introduced upward through the substrate 2000 from affecting the active layer ACT. The light-shielding pattern (BSM) is disposed at least below the active layer ACT.

[0098] A buffer layer BFL is disposed between the light-shielding pattern BSM and the active layer ACT. The gate electrode G, the active layer ACT, and the light-shielding pattern BSM are disposed on different intermediate layers to maintain electrical insulation between them.

[0099] like Figure 6 and Figure 7 As shown, the buffer layer BFL is disposed between the substrate 2000 and the active layer ACT.

[0100] The gate insulating layer GI is disposed between the active layer ACT and the gate electrode G.

[0101] An interlayer insulating layer (ILD) is disposed between the gate electrode G and the first source / drain electrode SD1 and the second source / drain electrode SD2.

[0102] Each of the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD is an inorganic insulating layer. For example, each of the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD may include one or more inorganic insulating layers selected from silicon oxide (SiOx) layers, silicon nitride (SiNx) layers, and silicon oxynitride (SiOxNy) layers, or may include a multilayer structure in which the inorganic insulating layers described above are stacked.

[0103] The first source-drain electrode SD1 and the second source-drain electrode SD2 are disposed above the gate electrode G. The first source-drain electrode SD1 and the second source-drain electrode SD2 can partially overlap with the gate electrode G, thereby improving the integration of the area where the transistor is disposed.

[0104] The first contact hole CT1 is disposed in the region where the first source / drain electrode SD1, the active layer ACT, and the first metal pattern CM1 overlap, and extends vertically through the interlayer insulating layer ILD, the gate insulating layer GI, and the active layer ACT in this region. The second contact hole CT2 is disposed in the region where the second source / drain electrode SD2, the active layer ACT, and the second metal pattern CM2 overlap, and extends vertically through the interlayer insulating layer ILD, the gate insulating layer GI, and the active layer ACT in this region.

[0105] A first contact hole CT1 and a second contact hole CT2 are provided to expose portions of a first metal pattern CM1 and a second metal pattern CM2, respectively. The first contact hole CT1 and the second contact hole CT2 are filled with active / drain electrode material and are spaced apart from each other. Therefore, the first source / drain electrode SD1 and the second source / drain electrode SD2 can be configured to contact the first metal pattern CM1 and the second metal pattern CM2, respectively.

[0106] The light-shielding pattern BSM and the gate electrode G are electrically connected to each other; therefore, the light-shielding pattern BSM can be used as the bottom gate. Thus, the transistor can have a structure including a dual gate. In this case, there is an advantage in high-speed driving of the transistor because the gate voltage is supplied to the transistor in a dual manner through the light-shielding pattern BSM and the gate electrode G.

[0107] The electrical connection between the light-shielding pattern BSM and the gate electrode G can be achieved by providing a connecting metal MC (i.e., a connecting electrode). For example, the connecting metal MC can be configured to overlap with the area of ​​the gate electrode G and the area of ​​the light-shielding pattern BSM protruding from the gate electrode G in a planar view. A third contact hole CT3 can be provided in the area overlapping with the gate electrode G, and a fourth contact hole CT4 can be provided in the area corresponding to the area of ​​the light-shielding pattern BSM protruding from the gate electrode G, thereby electrically connecting the gate electrode G and the light-shielding pattern BSM to each other.

[0108] The fourth contact hole CT4 can be configured to extend vertically through the interlayer insulating layer (ILD), the gate insulating layer (GI), and the buffer layer (BFL). The third contact hole CT3 can be configured to pass through the interlayer insulating layer (ILD). Figure 5 The arrangement and shape of the connecting metal MC shown are exemplary and can be modified as needed. In some cases, the connecting metal MC can be omitted, and the gate electrode G can be directly connected to the light-shielding pattern BSM in a region that does not overlap with the active layer ACT.

[0109] exist Figures 5 to 7In the transistor shown, the first metal pattern CM1 and the second metal pattern CM2 are disposed below the active layer ACT and in direct contact with the active layer ACT. Therefore, the shape of the gate electrode G does not restrict the channel region CH.

[0110] In structures where the gate electrode is used as a mask to define the conductive region of the active layer via plasma processing, or in structures where the gate electrode is used as a mask to form a doped region in the active layer, the size of the channel region is limited by the size of the gate electrode. After defining the conductive region and forming the doped region, the conductive region increases due to lateral diffusion into the overlapping region of the active layer and the gate electrode. Therefore, there is a problem of reduced effective channel length. The diffusion of the conductive region within the active layer occurs from both edges of the gate electrode G. As a result, the conductive region overlaps with the gate electrode G in a region with a length ∆L. Variations in the length ∆L can occur from both edges of the gate electrode G. Therefore, in structures where the gate electrode is used as a mask to define the conductive region of the active layer, the effective channel length differs from the designed channel length by 2ΔL. In short-channel transistors, 2ΔL is a large proportion relative to the designed total channel length, leading to a significant negative shift in the threshold voltage. As a result, it is difficult to obtain stable initial characteristics and dispersion characteristics of the transistor. Furthermore, the problem of reduced effective channel length is further exacerbated when the active layer is made of a high-mobility material. Furthermore, as the channel width of the active layer increases, the sensitivity to negative shifts in the threshold voltage increases. As a result, it becomes difficult to realize devices with wide channels in structures where the gate electrode is used as a mask to define the conductive region.

[0111] The transistors according to various embodiments of this disclosure have conductive regions of an active layer formed independently of a gate electrode, because the conductive regions of the active layer are defined by a first metal pattern CM1 and a second metal pattern CM2 before the gate electrode is formed. Therefore, the process of forming conductive regions or doped regions by plasma processing using a gate electrode as a mask can be omitted, and no additional processing is required. The problem of the effective channel length decreasing from the designed channel length due to diffusion of the conductive regions in the active layer after additional processing can also be prevented. Therefore, according to embodiments of this disclosure, problems related to variations in the effective channel length can be eliminated. Therefore, in structures of transistors having short channels in terms of channel length or wide channels in terms of channel width, negative offset variations in the threshold voltage can be reduced or prevented. Therefore, the initial characteristics of the transistor can be stabilized, thereby improving the reliability of display devices including transistors.

[0112] In the transistor according to the embodiments of the present disclosure, since the conductive region of the active layer is defined by the arrangement of the first metal pattern CM1 and the second metal pattern CM2 that contact the lower surface of the active layer, and is independent of the gate electrode, it is possible to prevent ΔL formed in the structure that uses the gate electrode as a mask to define the conductive region, eliminate problems related to changes in the effective channel length, and prevent or mitigate threshold voltage changes in short-channel or wide-channel transistors.

[0113] When the active layer has a short-length channel, the transistor T according to the first embodiment described above can be used as a reference. Figure 3 The first transistor (switching transistor) of the described sub-pixel. However, the transistor of this disclosure is not limited to the above-described configuration. A transistor in an embodiment of this disclosure, wherein the first metal pattern and the second metal pattern are disposed below the active layer, can be used as a second transistor (driving transistor) in the sub-pixel. In this case, changes in the effective channel length can also be prevented, thereby improving the reliability of the transistor.

[0114] When the transistor T according to the first embodiment described above has a wide channel, the transistor T can be included in a gate drive circuit (in-panel gate) disposed in a portion of the non-active region NA. In this case, there may be advantages in terms of high voltage and high-speed driving due to the inclusion of a transistor with a wide channel.

[0115] Figure 8 This is a plan view showing a transistor according to a second embodiment of the present disclosure. Figure 9 It is along Figure 8 The cross-sectional view taken from line III-III' in the diagram.

[0116] like Figure 8 and Figure 9 As shown, compared with the transistor of the first embodiment described above, the transistor T of the second embodiment of this disclosure may further include a channel auxiliary layer CHM that contacts the active layer ACT between the first metal pattern CM1 and the second metal pattern CM2.

[0117] The channel auxiliary layer CHM can be set on the same layer as the first metal pattern CM1 and the second metal pattern CM2.

[0118] Although the channel auxiliary layer CHM is disposed on the same layer as the first metal pattern CM1 and the second metal pattern CM2, the channel auxiliary layer CHM may include a different material than the first metal pattern CM1 and the second metal pattern CM2. The channel auxiliary layer CHM may include a semiconductor exhibiting higher mobility than the active layer ACT to increase the mobility of the channel region CH.

[0119] The channel auxiliary layer CHM can include, for example, a high-mobility oxide semiconductor. Specifically, the channel auxiliary layer CHM can be made of a compound of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and iron (Fe) with oxygen.

[0120] When the mobility of the active layer ACT is, for example, 5 to 20 cm 2 At / V·s, the mobility of the channel auxiliary layer CHM can be higher than that of the active layer ACT. For example, the mobility of the channel auxiliary layer CHM can be 1.1 to 10 times that of the active layer ACT.

[0121] The channel auxiliary layer CHM can be constructed to overlap with the channel region CH, thus increasing the mobility of the channel region CH. Therefore, the transistor T can be used for high-speed driving.

[0122] A buffer layer BFL is included between the active layer ACT and the substrate 2000. The buffer layer BFL includes at least one inorganic insulating layer.

[0123] The first metal pattern CM1, the second metal pattern CM2, and the channel auxiliary layer CHM can be set on the buffer layer BFL at the same time as the contact active layer ACT.

[0124] Electrical connections can be established in the overlapping region between the light-shielding pattern BSM and the gate electrode G, located outside the active layer ACT in the planar diagram. Therefore, the same gate voltage is supplied to both the light-shielding pattern BSM and the gate electrode G, thus enabling easy high-speed driving.

[0125] The remaining undescribed construction of the transistor according to the second embodiment may be the same as that of the transistor according to the first embodiment.

[0126] In the transistor according to the second embodiment of this disclosure, a first metal pattern CM1 and a second metal pattern CM2, spaced apart from each other, are added below the active layer ACT, such that the region between the first metal pattern CM1 and the second metal pattern CM2 is defined as the channel region of the active layer ACT. Therefore, a separate ion implantation or metallization process for channel formation is not required, thus simplifying the manufacturing process. Furthermore, the addition of a channel auxiliary layer CHM increases the channel mobility, thereby enabling high-speed driving. In particular, stable high-speed driving can be achieved in short-channel transistors without changing the effective channel length.

[0127] By further including a channel auxiliary layer CHM disposed below the active layer ACT and overlapping the channel region CH, such as Figure 8 and Figure 9As shown, the display device according to embodiments of the present disclosure can achieve high-speed driving. Since transistors configured to achieve high-speed driving are selectively disposed in the sub-pixels and gate drivers of the substrate, high-speed driving of various transistors included in the substrate can be realized.

[0128] In the transistor according to the second embodiment of this disclosure, the channel region can be defined by providing a conductive metal, independent of the gate electrode. Therefore, the effective channel length can be stabilized. When transistors including conductive metal are provided in multiple pixels on the substrate, inconsistent variations in the effective channel length between the multiple pixels can be prevented. Transistors disposed in sub-pixels can also have consistent characteristics to each have a stable effective channel. As a result, the dispersion characteristics of transistors disposed on the substrate are stable, thereby reducing process margin and facilitating the design of short-length channels.

[0129] The transistor according to the second embodiment of this disclosure has a gate electrode disposed independently of the channel, thus providing design freedom regarding the overlap of the gate electrode with the active layer. Since the channel region can be defined by a configuration disposed below the active layer, the gate electrode disposed above the active layer, as well as the first and second source / drain electrodes, can have increased overlap area with the active layer. This facilitates the integrated design of the transistor.

[0130] In the transistor according to the second embodiment of this disclosure, the gate electrode can be configured to have a larger size than the channel region of the active layer. Therefore, the active layer can be effectively prevented from being affected by residual hydrogen remaining in the layer above the gate electrode.

[0131] The transistors described in the various embodiments of this disclosure can reduce the defect rate caused by variations in the effective channel length. Therefore, the reliability of the transistors can be improved.

[0132] Figure 10 This is a plan view showing a transistor according to a third embodiment of the present disclosure. Figure 11 It is along Figure 10 The cross-sectional view taken from line IV-IV'.

[0133] like Figure 10 and Figure 11 As shown, in the transistor according to the third embodiment of this disclosure, at least one of the first metal pattern CM1 and the second metal pattern CM2 may include an extension portion that does not overlap with the active layer ACT. (Refer to...) Figure 10 The first metal pattern CM1 and the second metal pattern CM2 respectively include a first extension portion EXT1 and a second extension portion EXT2 disposed on the outside of the active layer ACT.

[0134] The first metal pattern CM1 and the second metal pattern CM2 are constructed as the lower surface of the contact active layer ACT.

[0135] The light-shielding pattern BSM is positioned below the first metal pattern CM1, the second metal pattern CM2, and the active layer ACT, separated by the buffer layer BFL.

[0136] The light-shielding pattern BSM is constructed to have a larger area than the active layer ACT.

[0137] The first metallic pattern CM1 includes a first overlapping portion NEX1 that overlaps with the active layer ACT and a first extension portion EXT1 that protrudes from one end of the active layer ACT.

[0138] The second metallic pattern CM2 includes a second overlapping portion NEX2 that overlaps with the active layer ACT and a second extension portion EXT2 that protrudes from the other end of the active layer ACT.

[0139] exist Figure 10 and Figure 11 In the diagram, the first metal pattern CM1 and the second metal pattern CM2 are shown as extending in the X-axis direction, while the first source / drain electrode SD1 and the second source / drain electrode SD2 are shown as extending in the Y-axis direction.

[0140] The first extension portion EXT1 can be connected to the first source / drain electrode SD1 via the first contact hole CT1, and the second extension portion EXT2 can be connected to the second source / drain electrode SD2 via the second contact hole CT2. The first extension portion EXT1 and the second extension portion EXT2 do not overlap with the active layer ACT, and therefore are directly connected to the first source / drain electrode SD1 and the second source / drain electrode SD2, respectively. The first source / drain electrode SD1 and the second source / drain electrode SD2 do not extend through the active layer ACT.

[0141] The first contact hole CT1 and the second contact hole CT2 can be formed through the interlayer insulating layer ILD and the gate insulating layer GI.

[0142] In this configuration, the gate electrode G completely overlaps with the active layer ACT, and in the region where the first extension portion EXT1 and the second extension portion EXT2 are spaced apart from the gate electrode G, the first extension portion EXT1 and the second extension portion EXT2 are respectively connected to the first source / drain electrode SD1 and the second source / drain electrode SD2. Compared to the first and second embodiments described above, since the gate electrode G completely overlaps with the active layer ACT, the hydrogen shielding effect of the gate electrode G on the active layer ACT can be further enhanced.

[0143] One of the first source-drain electrode SD1 and the second source-drain electrode SD2 can be connected to the light-shielding pattern BSM disposed below via the fifth contact hole CT5. The potential of the light-shielding pattern BSM can be stabilized by applying a voltage signal to either the first source-drain electrode SD1 or the second source-drain electrode SD2 connected to the light-shielding pattern BSM via the fifth contact hole CT5. This is merely an example, and the transistor according to embodiments of this disclosure is not limited to such examples. Figure 10 and Figure 11 The example shown is a fifth contact hole CT5 disposed in the overlapping region between the light-shielding pattern BSM and the first source / drain electrode SD1 or the second source / drain electrode SD2. Similar to the previously described embodiment, it can also be modified to apply the same gate voltage signal as the gate electrode G to the light-shielding pattern BSM via the electrical connection between the light-shielding pattern BSM and the gate electrode G.

[0144] Figure 12 This is a plan view showing a transistor according to a fourth embodiment of the present disclosure. Figure 13 It is along Figure 12 The cross-sectional view taken from line V-V' in the diagram.

[0145] like Figure 12 and Figure 13 As shown, in the transistor according to the fourth embodiment of the present disclosure, at least one of the first metal pattern CM1 and the second metal pattern CM2 may include an extension portion that does not overlap with the active layer ACT. Furthermore, the first metal pattern CM1 and the second metal pattern CM2 may be configured to extend in the Y-axis direction, while the first source / drain electrode SD1 and the second source / drain electrode SD2 may be configured to extend in the X-axis direction.

[0146] The first metal pattern CM1 and the second metal pattern CM2 respectively include a first extension portion EXT1 and a second extension portion EXT2 disposed on the outer side of the active layer ACT.

[0147] The first metal pattern CM1 and the second metal pattern CM2 are constructed as the lower surface of the contact active layer ACT.

[0148] The light-shielding pattern BSM is positioned below the first metal pattern CM1, the second metal pattern CM2, and the active layer ACT, separated by the buffer layer BFL.

[0149] The light-shielding pattern BSM is constructed to have a larger area than the active layer ACT.

[0150] The first metallic pattern CM1 includes a first overlapping portion NEX1 that overlaps with the active layer ACT and a first extension portion EXT1 that protrudes from one end of the active layer ACT.

[0151] The second metallic pattern CM2 includes a second overlapping portion NEX2 that overlaps with the active layer ACT and a second extension portion EXT2 that protrudes from the other end of the active layer ACT.

[0152] The first extension portion EXT1 can be connected to the first source / drain electrode SD1 via the first contact hole CT1, and the second extension portion EXT2 can be connected to the second source / drain electrode SD2 via the second contact hole CT2. The first extension portion EXT1 and the second extension portion EXT2 do not overlap with the active layer ACT, and therefore are directly connected to the first source / drain electrode SD1 and the second source / drain electrode SD2, respectively. The first source / drain electrode SD1 and the second source / drain electrode SD2 do not extend through the active layer ACT.

[0153] The first contact hole CT1 and the second contact hole CT2 can be formed through the interlayer insulating layer ILD and the gate insulating layer GI.

[0154] In this configuration, the gate electrode G completely overlaps with the active layer ACT, and in the region where the first extension portion EXT1 and the second extension portion EXT2 are spaced apart from the gate electrode G, the first extension portion EXT1 and the second extension portion EXT2 are respectively connected to the first source / drain electrode SD1 and the second source / drain electrode SD2. Compared to the first and second embodiments described above, since the gate electrode G completely overlaps with the active layer ACT, the hydrogen shielding effect of the gate electrode G on the active layer ACT can be further enhanced.

[0155] One of the first source-drain electrode SD1 and the second source-drain electrode SD2 can be connected to the light-shielding pattern BSM disposed below via the sixth contact hole CT6. The potential of the light-shielding pattern BSM can be stabilized by applying a voltage signal to either the first source-drain electrode SD1 or the second source-drain electrode SD2 connected to the light-shielding pattern BSM via the sixth contact hole CT6. This is merely an example, and the transistor according to embodiments of this disclosure is not limited to such... Figure 12 and Figure 13 The example shown is a sixth contact hole CT6 disposed in the overlapping region between the light-shielding pattern BSM and the first source / drain electrode SD1 or the second source / drain electrode SD2. Similar to the previously described embodiments, modifications can be made to apply the same gate voltage signal as the gate electrode G to the light-shielding pattern BSM via the electrical connection between the light-shielding pattern BSM and the gate electrode G.

[0156] In the following description, various embodiments of the display device according to the present disclosure will be described with reference to specific examples.

[0157] In each display device described below, the transistors have a configuration corresponding to the configuration of the first transistor for switching operation or the second transistor for providing drive current included in each sub-pixel. However, each display device according to the above embodiments is not limited to the above configuration. Modifications to the transistors according to the above embodiments can be applied not only to the transistors in the sub-pixels but also to the transistors disposed in the gate of the panel in the non-active region NA. Furthermore, such modifications can enhance the high-speed driving of the transistors or the effect of wide-channel transistors.

[0158] Figure 14 This is a cross-sectional view showing a display device 1000A according to an embodiment of the present disclosure.

[0159] Reference Figure 1 The display panel 110 includes an effective area AA and an ineffective area NA. The display panel 110 includes a substrate 111 (see...). Figure 14 ) and array structure on substrate 111.

[0160] Figures 6 to 13 Each of the substrates 2000 shown in the diagram may have the same characteristics as... Figure 14 The substrate 111 has the same structure, or it may have a structure including the substrate 111 and a single insulating layer or multiple insulating layers.

[0161] The effective area AA is set with a reference. Figure 1 The area described for the sub-pixel SP, the inactive area NA is the area where a driver such as the in-panel gate GIP is provided.

[0162] like Figure 14 As shown, the substrate 111 includes multiple sub-pixels SP in the effective area AA, and the multiple sub-pixels SP may also be included in the sensor area.

[0163] The substrate 111 is made of a flexible material, which allows for easier removal of material during laser irradiation to form sensor holes SH1 and SH2. For example, the substrate 111 may consist of a first organic layer 1111 and a second organic layer 1112 overlapping each other, with an inorganic interlayer insulating layer 117 inserted therebetween. The inorganic interlayer insulating layer 117 can be used to prevent the transfer of moisture or impurities between the first organic layer 1111 and the second organic layer 1112. The inorganic interlayer insulating layer 117 is formed on the first organic layer 1111 and may include a partially patterned structure. The inorganic interlayer insulating layer 117 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0164] The first organic layer 1111 and the second organic layer 1112 may include, for example, polyimide. In addition to polyimide, the first organic layer 1111 and the second organic layer 1112 may include different organic films.

[0165] The substrate 111 may include a polyethylene terephthalate (PET) layer as one of the first organic layer 1111 and the second organic layer 1112, and a polyimide layer as the other of the first organic layer 1111 and the second organic layer 1112.

[0166] In another example, substrate 111 may include a thin, flexible glass material.

[0167] The substrate 111 is used to support and protect the components of the display device 1000A disposed on the substrate 111.

[0168] In the effective region AA and ineffective region NA of substrate 111, multiple stacked insulating layers 120 (121, 122, 123, 124, 125, 126) and multiple planarization layers PLN (141, 142, 143) are configured to not only insulate the metal layers G1, SD11, SD12, G2, SD21, SD22, light-shielding patterns BSM1, BSM2 and active layers ACT1, ACT2 of transistors T1 and T2 from each other, but also insulate the first storage electrode ST1 and the second storage electrode ST2 constituting the storage capacitor ST from each other.

[0169] The effective region AA of substrate 111 may include connections to gate line GL. Figure 3 ) and data cable DL ( Figure 3 The first transistor T1 and the second transistor T2 are electrically connected to the light-emitting element ED. The first transistor T1 and the second transistor T2 can be directly connected to each other, and in some cases, they can be connected to each other via a portion of a compensation circuit disposed therebetween. For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor.

[0170] Similar to a reference Figures 5 to 7 The transistor described according to the first embodiment includes a first active layer ACT1 disposed on a substrate 111, a first gate electrode G1 disposed on the first active layer ACT1 while overlapping with the first active layer ACT1 and separated by a fifth insulating layer 125, a first source / drain electrode SD11 connected to one side of the first active layer ACT1, and a second source / drain electrode SD12 connected to the opposite side of the first active layer ACT1 and spaced apart from the first source / drain electrode SD11.

[0171] In addition to the first active layer ACT1 disposed on the substrate 111, the first transistor T1 also includes a first metal pattern CM1 and a second metal pattern CM2 disposed below the first active layer ACT1 and spaced apart from each other in a first direction by a predetermined distance to overlap with the first active layer ACT1. With the fifth insulating layer 125 located between the first active layer ACT1 and the first gate electrode G1, the width of the first gate electrode G1 disposed on the first active layer ACT1 while overlapping with it in the first direction is greater than the distance between the first metal pattern CM1 and the second metal pattern CM2. A first source / drain electrode SD11 is connected to the first metal pattern CM1, and a second source / drain electrode SD12, spaced apart from the first source / drain electrode SD11, is connected to the second metal pattern CM2.

[0172] The first metal pattern CM1 and the second metal pattern CM2 are layers configured to contact the lower surface of the first active layer ACT1. The first metal pattern CM1 and the second metal pattern CM2 are directly connected to the first source / drain electrode SD11 and the second source / drain electrode SD12, respectively. With this structure, the first gate electrode G1 is not limited by the conductive area of ​​the first active layer ACT1, and therefore can be configured to overlap the entire area between the first metal pattern CM1 and the second metal pattern CM2, as well as a portion of the first metal pattern CM1 and the second metal pattern CM2. Therefore, according to... Figure 14 In the display device 1000A, the first transistor T1 omits the metallization process that uses the gate electrode as a mask, thus eliminating the reduction and change in the effective channel region that occurs in structures that require the use of the gate electrode as a mask.

[0173] The first metal pattern CM1 and the second metal pattern CM2 are inherently conductive, and the regions of the first active layer ACT1 that are in contact with the first metal pattern CM1 and the second metal pattern CM2 can have low resistance characteristics compared to other regions of the first active layer ACT1.

[0174] exist Figure 14 In the display device 1000A shown, the first transistor T1 is used as a switching transistor. For this function, the first transistor T1 includes a first active layer ACT1 that contacts the upper surfaces of the first metal pattern CM1 and the second metal pattern CM2.

[0175] exist Figure 14In the display device 1000A shown, the metallization process is omitted for at least the first transistor T1, and the channel length is defined by the distance between the first metal pattern CM1 and the second metal pattern CM2 below the first active layer ACT1, and is independent of the first gate electrode G1. Since the first metal pattern CM1 and the second metal pattern CM2, as conductive materials, are in direct contact with the first active layer ACT1, the effective channel length variation ΔL generated during the metallization process can be prevented, and the effective channel length of the transistor can be stably ensured.

[0176] Since the first gate electrode G1 overlaps with the first metal pattern CM1 and the second metal pattern CM2, the first active layer ACT1 can be protected from the influence of hydrogen present above the first active layer ACT1. A first light-shielding pattern BSM1 can be disposed below the first active layer ACT1. The first light-shielding pattern BSM1 can prevent light introduced upward through the substrate 111 from affecting the first active layer ACT1.

[0177] Multiple insulating layers 122, 123, and 124 can be disposed between the first active layer ACT1 and the first light-shielding pattern BSM1. The multiple insulating layers 122, 123, and 124 between the first active layer ACT1 and the first light-shielding pattern BSM1 can serve as a buffer layer BFL. Figure 6 The buffer layer is used to planarize the surface of the first active layer ACT1, which will be formed in association with the first transistor T1. In some cases, the first light-shielding pattern BSM1 can be connected to the first gate electrode G1 to receive the same gate voltage signal as the first gate electrode G1. In this case, the first transistor T1 has the effect obtained in a dual-gate transistor, which is advantageous for high-speed driving.

[0178] The second transistor T2 includes a second active layer ACT2 disposed on a substrate 111, a second gate electrode G2 disposed on the second active layer ACT2 while overlapping with the second active layer ACT2 and separated by a fifth insulating layer 125, and a third source / drain electrode SD21 and a fourth source / drain electrode SD22 respectively connected to opposite sides of the second active layer ACT2.

[0179] The second light-shielding pattern BSM2 can be disposed below the second active layer ACT2 to prevent light introduced upward through the substrate 111 from affecting the second active layer ACT2.

[0180] The fifth insulating layer 125 is disposed between the first active layer ACT1 and the second active layer ACT2 in the first transistor T1 and the second transistor T2 and the first gate electrode G1 and the second gate electrode G2, and thus serves as a gate insulating layer.

[0181] like Figure 14As shown, in the display device 1000A according to an embodiment of the present disclosure, at least the first transistor T1 of the transistors T1 and T2 disposed in each sub-pixel includes the referenced above. Figures 5 to 13 The first metal pattern CM1 and the second metal pattern CM2 are described, and are configured to contact the first active layer ACT1. This configuration prevents variations in the effective channel length in transistor structures with short channel lengths. Figure 14 As shown, a first transistor T1 including a first metal pattern and a second metal pattern and a second transistor T2 not including a first metal pattern and a second metal pattern can have different channel lengths.

[0182] In the non-active region NA of substrate 111, a third transistor having the same structure as the first transistor T1 may be included. For example, the third transistor may be included in the in-panel gate GIP and may be a buffer transistor with high output. When the third transistor is included in the in-panel gate GIP, the third transistor may be electrically connected to the gate line GL to receive the gate voltage signal.

[0183] Multiple stacked insulating layers 120 (121, 122, 123, 124, 125, 126) are provided on the active region AA and the inactive region NA to insulate the electrodes constituting the first transistor T1 and the second transistor T2 from the active layers ACT1 and ACT2. The insulating layer 120 may include a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a fourth insulating layer 124, a fifth insulating layer 125, and a sixth insulating layer 126.

[0184] In addition to the first transistor T1 and the second transistor T2 shown, another transistor having an active layer disposed on a different layer than the first transistor T1 and the second transistor T2 can be disposed in a portion of the effective region AA or the inactive region NA of the substrate 111. At least one of the first to fourth insulating layers 121, 122, 123, and 124 can be used as a buffer layer or interlayer insulating layer for other active layers (such as active layers including polysilicon) besides the active layers ACT1 and ACT2 of the first transistor T1 and the second transistor T2.

[0185] A first insulating layer 121 is disposed on the effective area AA and the ineffective area NA of the substrate 111. The first insulating layer 121 may be referred to as a buffer layer and may perform the same function as buffer layers known in the art. The first insulating layer 121 is disposed on the substrate 111 to protect the structure disposed above the substrate 111 from moisture penetrating the substrate 111 and to planarize the surface of the substrate 111.

[0186] The first insulating layer 121 is configured to extend to the edge of the substrate 111 to prevent moisture from passing through the edge of the substrate 111. The first insulating layer 121 may be composed of a single inorganic layer or multiple inorganic layers stacked in an alternating manner.

[0187] For example, the first insulating layer 121 may include one or more inorganic layers selected from silicon oxide (SiOx) layers, silicon nitride (SiNx) layers and silicon oxynitride (SiOxNy) layers, or may include a multilayer structure in which the inorganic insulating layers described above are stacked.

[0188] A first light-shielding pattern BSM1 made of a conductive metal material may be disposed on the first insulating layer 121. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0189] The first light-shielding pattern BSM1 can form one electrode of the storage capacitor included in the sub-pixel.

[0190] The second insulating layer 122 may be disposed on the first insulating layer 121 on which the first light-shielding pattern BSM1 is disposed. The second insulating layer 122 may be used as an insulator for a storage capacitor connected to at least one of the first transistor T1 and the second transistor T2. Alternatively, the second insulating layer 122 may be used as an interlayer insulating layer for a transistor comprising a polysilicon semiconductor layer.

[0191] The second insulating layer 122 may include an inorganic material. The inorganic material may include, for example, silicon nitride (SiNx).

[0192] The third insulating layer 123 may be disposed on the second insulating layer 122. The third insulating layer 123 may serve as a buffer layer for the first transistor T1. The third insulating layer 123 may include an inorganic layer, such as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy) layer, or multiple layers thereof. In some cases, the second insulating layer 122 may also serve as a gate insulating layer for a transistor comprising a polysilicon semiconductor layer.

[0193] A second light-shielding pattern BSM2 made of a conductive metal material is disposed on the third insulating layer 123. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0194] The first light-shielding pattern BSM1 and the second light-shielding pattern BSM2 can each be disposed on the same layer as the storage capacitor or one of the first and second electrodes of the capacitor. The first light-shielding pattern BSM1 and the second light-shielding pattern BSM2 can each be a single layer, or each can have a stacked structure of multiple different metal materials.

[0195] The fourth insulating layer 124 can be disposed on the third insulating layer 123 on which the second light-shielding pattern BSM2 is disposed. The fourth insulating layer 124 is disposed below the first active layer ACT1 and the second active layer ACT2, and can be used as a buffer layer. The fourth insulating layer 124 can also be used to planarize the surface of the area on which the first active layer ACT1 and the second active layer ACT2 are disposed.

[0196] The fourth insulating layer 124 may include an inorganic material. The inorganic material may include, for example, a silicon oxide (SiOx) layer or a multilayer structure in which inorganic layers are stacked.

[0197] The first to fourth insulating layers 121, 122, 123, and 124 can be used as buffer layers, gate insulating layers, and interlayer insulating layers for transistors including polysilicon on a substrate.

[0198] On the fourth insulating layer 124, a first metal pattern CM1 and a second metal pattern CM2, spaced apart from each other, are disposed in the area overlapping with the first light-shielding pattern BSM1.

[0199] The first metal pattern CM1 and the second metal pattern CM2 are made of conductive metal material. Specifically, the conductive metal material may include at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), silver-based metals (such as silver (Ag) or silver alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0200] When the oxide semiconductor material is deposited on the fourth insulating layer 124 and then selectively removed, the first active layer ACT1 is disposed along the upper surface of the first metal pattern CM1 and the second metal pattern CM2, the side surfaces of the first metal pattern CM1 and the second metal pattern CM2, and the upper surface of the fourth insulating layer 124 between the adjacent side surfaces of the first metal pattern CM1 and the second metal pattern CM2, and the second active layer ACT2 is disposed on the upper surface of the fourth insulating layer 124 in a region spaced apart from the first active layer ACT1.

[0201] like Figure 5As shown, the channel region CH of the first active layer ACT1 may have a channel length L corresponding to a first distance L in a first direction (e.g., the X-axis direction). The channel region CH of the first active layer ACT1 may also have a width W in a second direction (e.g., the Y-axis direction) intersecting the channel length L.

[0202] Oxide semiconductor materials can be composed of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) combined with oxygen. In some cases, metals with high conductivity (such as iron (Fe)) can be further included in the oxide semiconductor material to increase mobility.

[0203] Examples of oxide semiconductor materials may include zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), iron indium zinc oxide (FIZO), etc.

[0204] The fifth insulating layer 125 is configured to cover the first active layer ACT1 and the second active layer ACT2. The fifth insulating layer 125 serves as a gate insulating layer.

[0205] On the fifth insulating layer 125, the first gate electrode G1 and the second gate electrode G2 are configured to partially overlap with the first active layer ACT1 and the second active layer ACT2, respectively. The first gate electrode G1 and the second gate electrode G2 may each comprise at least one of an aluminum-based metal (such as aluminum (Al) or an aluminum alloy), a copper-based metal (such as copper (Cu) or a copper alloy), a molybdenum-based metal (such as molybdenum (Mo) or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode G1 and the second gate electrode G2 may each be composed of a single layer or multiple layers.

[0206] The first gate electrode G1 is disposed on the first active layer ACT1 with a width greater than the distance between the first metal pattern CM1 and the second metal pattern CM2. The region between the first gate electrode G1 and the first metal pattern CM1 and the second metal pattern CM2 overlaps with the portion of the first active layer ACT1 disposed above the first metal pattern CM1 and the second metal pattern CM2.

[0207] The first gate electrode G1 can be connected to, for example, a reference. Figure 3 The gate line GL is described.

[0208] In embodiments of this disclosure, the first gate electrode G1 is connected to a first light-shielding pattern BSM1 disposed below it, and thus can receive a gate voltage signal having the same potential as the first light-shielding pattern BSM1. In this case, due to the potential stability of the first light-shielding pattern BSM1 and the application of the dual-gate structure of the first light-shielding pattern BSM1 together with the first gate electrode G1, the first transistor T1 can achieve high-speed switching with a small size.

[0209] For example, the first storage electrode ST1 may be further disposed on the first insulating layer 121 in the same layer as the first light-shielding pattern BSM1, and the second storage electrode ST2, which overlaps with the first storage electrode ST1, may be disposed on the second insulating layer 122.

[0210] The sixth insulating layer 126 is disposed on the fifth insulating layer 125 on which the first gate electrode G1 and the second gate electrode G2 are disposed.

[0211] The sixth insulating layer 126 is formed of an inorganic insulating material. In some cases, the sixth insulating layer 126 may be a single layer.

[0212] For example, the sixth insulating layer 126 may include a silicon oxide (SiOx) layer or a silicon nitride (SiNx) layer, or may include a multilayer structure in which inorganic layers are stacked.

[0213] In the region of the second transistor T2, a contact hole is formed by selectively removing the sixth insulating layer 126 and the fifth insulating layer 125 to expose a portion of the second active layer ACT2. Furthermore, in the region of the first transistor T1, a contact hole is formed by selectively removing the sixth insulating layer 126, the fifth insulating layer 125, and the first active layer ACT1 to expose the first metal pattern CM1 and the second metal pattern CM2.

[0214] A metallic material is formed on the sixth insulating layer 126 such that the metallic material fills the corresponding contact holes to provide a third source / drain electrode SD21 and a fourth source / drain electrode SD22 connected to the second active layer ACT2 via the metallic material, and a first source / drain electrode SD11 and a second source / drain electrode SD12 directly connected to the first metal pattern CM1 and the second metal pattern CM2.

[0215] The first to fourth source / drain electrodes SD11, SD12, SD21, and SD22 may comprise at least one of aluminum-based metals (such as aluminum (Al) or aluminum alloys), copper-based metals (such as copper (Cu) or copper alloys), molybdenum-based metals (such as molybdenum (Mo) or molybdenum alloys), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Each of the first to fourth source / drain electrodes SD11, SD12, SD21, and SD22 may be composed of a single layer or multiple layers.

[0216] The storage connection electrode STN connected to the second storage electrode ST2 can also be disposed on the same layer as the first to fourth source-drain electrodes SD11, SD12, SD21, and SD22.

[0217] A first planarization layer 141 can be formed on the first to fourth source-drain electrodes SD11, SD12, SD21, and SD22 to protect the first transistor T1 and the second transistor T2.

[0218] A cover electrode CE and a connection electrode 190 can also be respectively provided on the first planarization layer 141 in the region corresponding to the first transistor T1 and the second transistor T2 to prevent light incident from above the first transistor T1 and the second transistor T2 or the operation of the light-emitting element ED from affecting the transistor.

[0219] The cover electrode CE and the connection electrode 190 can be formed on the same layer of the first planarization layer 141 using the same conductive material. The connection electrode 190 can be electrically connected to the light-emitting element ED disposed thereon. In some cases, the cover electrode CE and the connection electrode 190 can be omitted. When the connection electrode 190 is omitted, the fourth source-drain electrode SD22 of the second transistor T2 can be connected to the light-emitting element ED.

[0220] The second planarization layer 142 and the third planarization layer 143 can be sequentially disposed on the cover electrode CE and the connecting electrode 190.

[0221] The first planarization layer 141, the second planarization layer 142, and the third planarization layer 143 may comprise organic materials. These organic materials may include one or more of the following: acryloyl resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, benzocyclobutene, polyphenylene resin, and polyphenylene sulfide resin. The first planarization layer 141, the second planarization layer 142, and the third planarization layer 143 may be collectively referred to as planarization layer PLN in terms of their planarization function.

[0222] The first electrode E1, which serves as the anode, can be further disposed on the planarization layer PLN. The first electrode E1 can be connected to the fourth source / drain electrode SD22 via the contact hole PCT in the third planarization layer 143 and the second planarization layer 142 and via the connection electrode 190.

[0223] The first electrode E1, the intermediate layer EL, and the second electrode E2, which are sequentially stacked on the planarization layer PLN, constitute the light-emitting element ED.

[0224] One of the first electrode E1 and the second electrode E2 may include a reflective electrode, while the other of the first electrode E1 and the second electrode E2 may include a transparent electrode or a transmissive-reflective electrode.

[0225] When the first electrode E1 includes a reflective electrode, the first electrode E1 can be used to prevent light from entering the transistor disposed below it.

[0226] The first electrode E1 can be constructed from a stacked structure, for example, a first transparent electrode, a reflective electrode, and a second transparent electrode. In this case, the second transparent electrode, which is the uppermost electrode of the first electrode E1, can serve as a dielectric to reduce the energy barrier for hole injection at the interface between the first electrode E1 and the intermediate layer EL. In this case, the first and second transparent electrodes can each be transparent oxide electrodes made of indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The reflective electrode can include materials such as silver, silver-based alloys (e.g., Ag-Pd-Cu (APC) alloys), aluminum, or aluminum alloys.

[0227] For example, the first electrode E1 can be formed as a multilayer structure, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), a stacked structure of Ag-Pd-Cu (APC) alloy and ITO (ITO / APC / ITO), a stacked structure of silver (Ag) and molybdenum-titanium alloy (Ag / MoTi), or may include a single-layer structure composed of one or more alloys of silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca) and barium (Ba).

[0228] The pixel defining layer 160 is configured to surround the edge of the first electrode E1. The light-emitting portion may be defined in the opening region of the pixel defining layer 160. The pixel defining layer 160 may extend into the inactive region NA and may have a region that at least partially overlaps with the in-panel gate GIP.

[0229] The pixel defining layer 160 may include inorganic or organic materials. For example, the pixel defining layer 160 may include a first dam layer 161, a second dam layer 162, and a spacer 163. For example, at least one of the first dam layer 161, the second dam layer 162, and the spacer 163 may include an opaque material (e.g., a black material) to prevent light interference between adjacent sub-pixels SP. In this case, the opaque material may include a light-shielding material composed of at least one of colored pigments, organic black, and carbon. For example, the first dam layer 161 may be formed of an opaque organic material (organic black), while the second dam layer 162 and the spacer 163 may be formed of a transparent material. The second dam layer 162 may be configured to completely cover the first dam layer 161. The spacer 163 may be disposed on a portion of the second dam layer 162.

[0230] In the portion of the third planarization layer 143 that overlaps with the pixel defining layer 160, the third planarization layer 143 may have a recess RS extending downward from its upper surface. In some cases, the recess RS may extend through the entire thickness of the second planarization layer 142 beneath the third planarization layer 143, or may extend to a portion of the thickness of the second planarization layer 142. Additionally, the first dam layer 161 of the pixel defining layer 160 may fill the recess RS. In some cases, the recess RS may extend through the entire thickness of the second planarization layer 142. The material of the first dam layer 161 disposed in the recess RS can shield light subject to total internal reflection on the substrate.

[0231] The intermediate layer EL may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The intermediate layer EL may be formed as a series structure comprising multiple stacks, each stack including a hole transport layer, a light-emitting layer, and an electron transport layer, with charge generation layers disposed between adjacent stacks. The charge generation layers may include, for example, n-type charge generation layers and p-type charge generation layers.

[0232] The light-emitting layer included in the intermediate layer EL can be configured such that the light-emitting layer is different for each sub-pixel. The light-emitting layer can be composed of a red light-emitting layer configured to emit red light, a green light-emitting layer configured to emit green light, or a blue light-emitting layer configured to emit blue light. For example, patterned red, green, and blue light-emitting layers can be respectively disposed on the first electrode E1 of different sub-pixels SP.

[0233] For example, a red emitting layer can be patterned in a red sub-pixel, a green emitting layer can be patterned in a green sub-pixel, and a blue emitting layer can be patterned in a blue sub-pixel. However, the embodiments of this disclosure are not limited to the above conditions, and at least two of the organic emitting layers among the red, green, and blue emitting layers can be stacked in a single sub-pixel SP.

[0234] In some cases, the emissive layer can be a white emissive layer configured to emit white light. In this case, the emissive layer may not take the form of a pattern of sub-pixels SP, but may take the form of a common layer set together in the sub-pixels SP, and may include one or more layers.

[0235] As described above, the intermediate layer EL can be configured as a series structure with two or more stacks. In this case, each light-emitting element ED can include a charge-generating layer disposed between adjacent stacks. The charge-generating layer can take the form of a common layer disposed on the top surface of the active region AA.

[0236] The second electrode E2 can be formed by stacking transmissive electrodes made of materials such as ITO or IZO, or transmissive / reflective electrodes made of materials such as silver, silver alloys, magnesium, magnesium alloys, ytterbium (Yb), or ytterbium alloys. The second electrode E2 can be formed with a small thickness to increase transmittance. The second electrode E2 can be a common layer disposed together with the sub-pixel SP to receive the same voltage. For this purpose, the second electrode E2 can be configured to extend from the effective region AA to a portion of the ineffective region NA.

[0237] The second electrode E2 can be a transmission electrode. The second electrode E2 can comprise a transparent conductive material, such as ITO or IZO, through which light can pass (e.g., transparent conductive oxide (TCO)), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode E2 is composed of a semi-transmissive conductive material, the luminous efficiency can be improved through the microcavity effect.

[0238] So far, an example of a top-emitting type light-emitting element as a light-emitting element ED has been described. However, the light-emitting element ED of this disclosure is not limited to the type described above, and may also have a bottom-emitting type where light emitted from the intermediate layer ED is directed toward the substrate 111. In this case, the first electrode E1 may be made of a transparent or translucent electrode material, and the second electrode E2 may be made of a reflective electrode material.

[0239] A cover layer (not shown) may be formed on the second electrode E2 to protect the second electrode E2 of the light-emitting element ED and enhance the light extraction efficiency towards the upper side.

[0240] An encapsulation layer 220 can be disposed on the light-emitting element ED. The encapsulation layer 220 covers the active area AA and the inactive area NA, thus preventing oxygen or moisture from penetrating the light-emitting element ED. If necessary, other layers, such as a cover layer, can be inserted between the encapsulation layer 220 and the second electrode E2.

[0241] The encapsulation layer 220 may be composed of multiple layers. The encapsulation layer 220 may be composed of an alternating stack of inorganic layers comprising inorganic insulating materials and organic layers comprising organic insulating materials. For example, the inorganic insulating materials may include one or more materials such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0242] Organic insulating materials may include one or more materials selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate and hexamethyldisiloxane.

[0243] A touch sensor can be further configured on the encapsulation layer 220.

[0244] The touch sensor may include a touch buffer layer 231, a bridging electrode 232, a touch intermediate insulating layer 233, a sensor electrode layer 234, and a touch protective layer 235.

[0245] A light-shielding layer 241 corresponding to the non-light-emitting portion, a color filter 242 corresponding to the light-emitting portion, and an upper protective layer 250 can be further configured on the upper surface of the touch protection layer 235 of the touch sensor.

[0246] The effective region AA of substrate 111 may include connections to gate line GL. Figure 3 ) and data cable DL ( Figure 3 The first transistor T1 is electrically connected to the light-emitting element ED, and the second transistor T2 is electrically connected to the light-emitting element ED. The first transistor T1 and the second transistor T2 can be directly connected to each other, and in some cases, they can be connected to each other via a portion of a compensation circuit disposed therebetween. For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor.

[0247] although Figure 14 The transistor according to the first embodiment is shown as a structure of the first transistor T1, but this disclosure is not limited to this example. For example, as Figures 10 to 13 As shown, in the structure of the first transistor T1, the first metal pattern CM1 and the second metal pattern CM2 may include a first extension portion EXT1 and a second extension portion EXT2 protruding to the outside of the first active layer ACT1, such that the first metal pattern CM1 and the second metal pattern CM2 are respectively connected to the first source / drain electrode SD11 and the second source / drain electrode SD12 at the first extension portion EXT1 and the second extension portion EXT2.

[0248] In the following text, reference will be made to Figure 15 Description of display device 1000B, wherein according to Figure 8 and Figure 9 The transistor in the second embodiment is applied to the second transistor T2.

[0249] according to Figure 15 The display device 1000B of the embodiment further includes a first metal pattern CM1 and a second metal pattern CM2 disposed below the second active layer ACT2 of the second transistor T2, and a channel auxiliary layer CHM in the region between the first metal pattern CM1 and the second metal pattern CM2.

[0250] Figure 15 The display device 1000B differs from the first transistor T1 and the second transistor T2 in that... Figure 14 The display device 1000A, and in terms of its structure, which is positioned above and below the first transistor T1 and the second transistor T2, is similar to... Figure 14The display device is the same as the 1000A. Therefore, a description of the same construction will not be given.

[0251] exist Figure 15 In the display device 1000B shown, the first transistor T1 is used as a switching transistor, and the second transistor T2 can be used as a driving transistor.

[0252] According to Figure 15 In the display device 1000B of the embodiment, the first transistor T1 includes a first active layer ACT1 disposed on a substrate 111, a first gate electrode G1 disposed on the first active layer ACT1 while overlapping with the first active layer ACT1 and separated by a fifth insulating layer 125, a first source / drain electrode SD11 connected to one side of the first active layer ACT1, and a second source / drain electrode SD12 connected to the opposite side of the first active layer ACT1 and spaced apart from the first source / drain electrode SD11.

[0253] The second transistor T2 includes a second active layer ACT2 disposed on a substrate 111, a first metal pattern CM1 and a second metal pattern CM2 disposed below the second active layer ACT2 while overlapping with the second active layer ACT2 and spaced apart from each other by a first distance L in a first direction, a second gate electrode G2 disposed on the second active layer ACT2 while overlapping with the second active layer ACT2 and separated by a fifth insulating layer 125 and having a width greater than the first distance L in a first direction, a third source / drain electrode SD21 connected to the first metal pattern CM1, and a fourth source / drain electrode SD22 connected to the second metal pattern CM2 and spaced apart from the third source / drain electrode SD21.

[0254] Furthermore, the second transistor T2 may also include a channel auxiliary layer CHM, which is disposed below the second active layer ACT2 and spaced apart from the first metal pattern CM1 and the second metal pattern CM2 in the region between them. The channel auxiliary layer CHM may include a high-mobility oxide semiconductor.

[0255] The first metal pattern CM1 and the second metal pattern CM2 are layers disposed below the second active layer ACT2 to contact the second active layer ACT2. The first metal pattern CM1 and the second metal pattern CM2 are directly connected to the third source / drain electrode SD21 and the fourth source / drain electrode SD22, respectively. With this structure, the second gate electrode G2 is not limited by the conductive area of ​​the second active layer ACT2, and can therefore be configured to overlap the entire area between the first metal pattern CM1 and the second metal pattern CM2, as well as a portion of the first metal pattern CM1 and the second metal pattern CM2. Therefore, the metallization process using the gate electrode as a mask can be omitted, thus eliminating the reduction and variation of the effective channel region that occurs in structures that require a metallization process using the gate electrode as a mask.

[0256] The first metal pattern CM1 and the second metal pattern CM2 are inherently conductive, and the surfaces of the second active layer ACT2 that contact the first metal pattern CM1 and the second metal pattern CM2 can have low resistance characteristics compared to other areas of the second active layer ACT2.

[0257] The channel auxiliary layer CHM may include an oxide semiconductor material that exhibits a higher mobility than the second active layer ACT2 disposed on the channel auxiliary layer CHM.

[0258] In the second transistor T2, the second active layer ACT2 is configured such that its lower surface contacts the first metal pattern CM1 and the second metal pattern CM2, as well as the channel auxiliary layer CHM, in different regions. The channel auxiliary layer CHM in the channel region can enhance the high-speed performance of the second transistor T2 and can increase the on-state current (Ion) of the second transistor T2 as a driving transistor.

[0259] The first active layer ACT1 and the second active layer ACT2 can include the same oxide semiconductor material and therefore can be formed by the same process.

[0260] When the oxide semiconductor material is deposited on the fourth insulating layer 124 and then selectively removed, the second active layer ACT2 is disposed along the upper and side surfaces of the first metal pattern CM1, the second metal pattern CM2 and the channel auxiliary layer CHM, and the upper surface of the fourth insulating layer 124 between the adjacent side surfaces of the first metal pattern CM1, the second metal pattern CM2 and the channel auxiliary layer CHM, and the first active layer ACT1 is disposed spaced apart from the second active layer ACT2.

[0261] In the second transistor T2, which includes a first metal pattern CM1 and a second metal pattern CM2, as Figures 10 to 13As shown, the first metal pattern CM1 and the second metal pattern CM2 may include a first extension EXT1 and a second extension EXT2 protruding to the outside of the second active layer ACT2, such that the first metal pattern CM1 and the second metal pattern CM2 are connected to the third source / drain electrode SD21 and the fourth source / drain electrode SD22 at the first extension EXT1 and the second extension EXT2, respectively. In this case, the second active layer ACT2 can be designed to have a length corresponding to the desired channel length, and both the first active layer ACT1 and the second active layer ACT2 can be easily implemented to have a minimum length.

[0262] In some cases, the display device can be implemented by... Figure 14 The structure of the first transistor T1 shown is applied to a transistor used as a switching transistor, and... Figure 15 The structure of the second transistor T2 shown is applied to a transistor used as a driving transistor to construct a sub-pixel comprising two transistors with metal patterns. In this case, since the metal patterns of the transistors can be manufactured using the same process, the manufacturing process is simplified, and the amount of materials such as gases and etchants used throughout the manufacturing process is reduced, thereby reducing greenhouse gas emissions generated by the manufacturing process.

[0263] Figure 16 This is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0264] according to Figure 16 The display device 1000C of the embodiment and Figure 14 The difference between the display device 1000A and the reference is that... Figure 8 and Figure 9 The transistor described according to the second embodiment is applied to the first transistor T1.

[0265] Figure 16 The display device 1000C differs from the first transistor T1 in that... Figure 14 The display device 1000A, and in terms of its structure, being positioned above and below the first transistor T1 and the second transistor T2, is similar to... Figure 14 The display device is the same as the 1000A. Therefore, a description of the same construction will not be given.

[0266] The first transistor T1 includes a first metal pattern CM1 and a second metal pattern CM2 disposed below the first active layer ACT1, and an additional channel auxiliary layer CHM disposed in the region between the first metal pattern CM1 and the second metal pattern CM2.

[0267] exist Figure 16In the display device 1000C shown, the first transistor T1 can be used as a switching transistor, and the second transistor T2 can be used as a driving transistor.

[0268] In this configuration, the first transistor T1 includes a first active layer ACT1 disposed on a substrate 111, a first metal pattern CM1 and a second metal pattern CM2 disposed below the first active layer ACT1 while overlapping with it and spaced apart from each other by a first distance L in a first direction, a first gate electrode G1 disposed on the first active layer ACT1 while overlapping with it and separated by a fifth insulating layer 125 and having a width greater than the first distance L in a first direction, a first source / drain electrode SD11 connected to the first metal pattern CM1, and a second source / drain electrode SD12 connected to the second metal pattern CM2 and spaced apart from the first source / drain electrode SD11.

[0269] Additionally, the first transistor T1 may include a central portion of a channel region disposed on the same layer as the first metal pattern CM1 and the second metal pattern CM2 to contact the channel auxiliary layer CHM of the first active layer ACT1.

[0270] The first metal pattern CM1 and the second metal pattern CM2 are layers disposed below the first active layer ACT1 to contact the first active layer ACT1. The first metal pattern CM1 and the second metal pattern CM2 are directly connected to the first source / drain electrode SD11 and the second source / drain electrode SD12, respectively. With this structure, the first gate electrode G1 is not limited by the conductive area of ​​the first active layer ACT1, and therefore can be configured to overlap with the entire area between the first metal pattern CM1 and the second metal pattern CM2, as well as a portion of the first metal pattern CM1 and the second metal pattern CM2.

[0271] In some cases, such as Figures 10 to 13 As shown, the first metal pattern CM1 and the second metal pattern CM2 may include a first extension portion EXT1 and a second extension portion EXT2 protruding to the outside of the first active layer ACT1, such that the first metal pattern CM1 and the second metal pattern CM2 are respectively connected to the first source / drain electrode SD11 and the second source / drain electrode SD12 at the first extension portion EXT1 and the second extension portion EXT2.

[0272] The first metal pattern CM1 and the second metal pattern CM2 inherently possess conductive properties, and the surface of the first active layer ACT1 facing the first metal pattern CM1 and the second metal pattern CM2 can have low resistance characteristics compared to other regions of the first active layer ACT1.

[0273] In the illustrated embodiment, the first transistor T1, used as a switching transistor, includes a first active layer ACT1, which is configured to contact a first metal pattern CM1 and a second metal pattern CM2 on its lower surface. The first transistor T1 also includes a channel auxiliary layer CHM, thereby enhancing the high-speed driving of the first transistor T1.

[0274] A first light-shielding pattern BSM1 may be disposed below the first active layer ACT1. Multiple insulating layers 122, 123, and 124 may be disposed between the first active layer ACT1 and the first light-shielding pattern BSM1. The multiple insulating layers 122, 123, and 124 between the first active layer ACT1 and the first light-shielding pattern BSM1 may serve as a buffer layer for planarizing the surface of the first active layer ACT1, which will be associated with the first transistor T1.

[0275] The first light-shielding pattern BSM1 can be connected to the first gate electrode G1 to receive the same gate voltage signal as the first gate electrode G1. According to this connection structure, the first light-shielding pattern BSM1 and the first gate electrode G1 can each be used as a gate electrode. Therefore, the high-speed driving of the first transistor T1 can be enhanced.

[0276] The second transistor T2 includes a second active layer ACT2 disposed on a substrate 111, a second gate electrode G2 disposed on the second active layer ACT2 while overlapping with the second active layer ACT2 and separated by a fifth insulating layer 125, and a third source / drain electrode SD21 and a fourth source / drain electrode SD22 respectively connected to opposite sides of the second active layer ACT2.

[0277] As described above, for at least one of the first transistor T1 and the second transistor T2 disposed in each sub-pixel, Figures 14 to 16 The transistors in each of the display devices 1000A, 1000B, and 1000C shown include those as referenced. Figures 5 to 13 The aforementioned configuration refers to the first and second metal patterns contacting the active layer. This configuration enables short channel lengths and prevents variations in the effective channel length within the transistor structure. For a designed channel length, forming a conductive region (ΔL) overlapping the gate electrode leads to an increased negative offset in the threshold voltage because the proportion of the conductive region (ΔL) to the total designed channel length increases as the designed channel length decreases. Consequently, it becomes difficult to obtain stable initial and dispersion characteristics in the transistor.

[0278] In the display device according to embodiments of the present disclosure, the metallization process is omitted, and the channel length is defined by the distance between the first and second metal patterns disposed below the active layer, independent of the gate electrode. Furthermore, the conductive structure directly contacts the active layer. Therefore, the characteristics of the short-channel transistor can be reliably ensured.

[0279] Since the first gate electrode G1 overlaps with the first metal pattern CM1 and the second metal pattern CM2, it can help eliminate the effects caused by hydrogen remaining above the first gate electrode G1.

[0280] A channel auxiliary layer (CHM) comprising semiconductor material is added to the central portion of the channel region CH as a high-mobility oxide for high-speed driving. Therefore, high-speed driving can be achieved through the conductive portion when a gate bias is applied.

[0281] As is apparent from the foregoing description, in the transistors and display devices according to various embodiments of the present disclosure, a first conductive metal and a second conductive metal spaced apart from each other are provided below the active layer. Therefore, the region between the first conductive metal and the second conductive metal is defined as the channel region of the active layer. Consequently, a separate ion implantation or metallization process for forming the channel region is not required, thereby simplifying the manufacturing process.

[0282] In structures where the channel region is defined by an additional metallization process after the gate electrode is formed, significant variations in the effective channel length can occur. Therefore, considering these variations in effective channel length, the channel region is designed to have a large process margin. Consequently, limitations exist in designs with short-length channels. Unlike this structure, in the transistors and display devices according to various embodiments of this disclosure, the channel region can be defined by providing a conductive metal, independent of the gate electrode. Therefore, the effective channel length can be stabilized. When transistors with conductive metal are provided in multiple pixels on the substrate, inconsistent variations in the effective channel length between the multiple pixels can be prevented. Transistors disposed in sub-pixels can also have consistent characteristics to each have a stable effective channel. As a result, the dispersion characteristics of transistors disposed on the substrate are stable, thereby reducing process margins and facilitating designs with short-length channels.

[0283] In the transistors and display devices according to various embodiments of the present disclosure, the transistors can be configured to include a gate electrode disposed independently of the channel, thus providing design freedom regarding the overlap of the gate electrode with the active layer. Since the channel region can be defined by a configuration disposed below the active layer, the gate electrode disposed above the active layer, as well as the first and second source / drain electrodes, can have an increased area overlapping the active layer. This facilitates the integrated design of the transistor.

[0284] In the transistors and display devices according to various embodiments of the present disclosure, the gate electrode can be configured to completely cover the active layer. Therefore, the active layer can be effectively prevented from being affected by residual hydrogen in the layer disposed above the gate electrode.

[0285] In the transistors and display devices according to various embodiments of the present disclosure, the transistors may further include a channel auxiliary layer overlapping the channel region to achieve high-speed driving. Since the transistors capable of high-speed driving are selectively disposed on the substrate as sub-pixels and gate drivers, various transistors included in the substrate can achieve high-speed driving.

[0286] In the transistors and display devices according to various embodiments of the present disclosure, the defect rate of the transistors can be reduced and the amount of materials such as gases and etchants used in the entire manufacturing process of the display device can be reduced, thereby reducing greenhouse gas emissions generated by the manufacturing process.

[0287] A transistor according to one embodiment of the present disclosure may include: an active layer; a first metal pattern and a second metal pattern disposed below the active layer while overlapping the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; a gate electrode disposed on the active layer while overlapping the active layer, the gate electrode having a width greater than the first distance in the first direction; a gate insulating layer between the active layer and the gate electrode; a first source / drain electrode connected to the first metal pattern; and a second source / drain electrode connected to the second metal pattern and spaced apart from the first source / drain electrode.

[0288] In a transistor according to one embodiment of the present disclosure, the channel region of the active layer may have a channel length corresponding to a first distance in a first direction.

[0289] In a transistor according to one embodiment of the present disclosure, the active layer may be in contact with a first metal pattern and a second metal pattern.

[0290] In a transistor according to one embodiment of the present disclosure, in a cross-sectional view, the active layer may be disposed along the steps of the upper and side surfaces of the first metal pattern and the second metal pattern.

[0291] In a transistor according to one embodiment of the present disclosure, the gate electrode may completely overlap with a region between a first metal pattern and a second metal pattern in a first direction, and overlap with a portion of at least one of the first metal pattern or the second metal pattern.

[0292] In a transistor according to one embodiment of the present disclosure, a first source / drain electrode and a second source / drain electrode may extend through the active layer and contact a first metal pattern and a second metal pattern, respectively.

[0293] In a transistor according to one embodiment of the present disclosure, at least one of a first metal pattern and a second metal pattern may include an extension that does not overlap with the active layer.

[0294] In a transistor according to one embodiment of the present disclosure, the gate electrode may completely cover the active layer.

[0295] In a transistor according to one embodiment of the present disclosure, the extension portion may include a first extension portion and a second extension portion protruding from opposite ends of the active layer. The first extension portion may be connected to a first source / drain electrode, and the second extension portion may be connected to a second source / drain electrode.

[0296] According to one embodiment of the present disclosure, the transistor may further include a light-shielding pattern overlapping the active layer between the active layer and the substrate. The light-shielding pattern and the gate electrode may be electrically connected to each other.

[0297] The transistor according to one embodiment of this disclosure may further include a light-shielding pattern overlapping the active layer between the active layer and the substrate. The light-shielding pattern may be electrically connected to one of the first source / drain electrodes and the second source / drain electrode.

[0298] In a transistor according to one embodiment of the present disclosure, a buffer layer may be provided between the substrate and the active layer. An interlayer insulating layer may be provided between the gate electrode and the first source / drain electrode and the second source / drain electrode. A first contact hole that overlaps with the first metal pattern and the first source / drain electrode, respectively, and a second contact hole that overlaps with the second metal pattern and the second source / drain electrode, respectively, may be provided in the interlayer insulating layer and the gate insulating layer.

[0299] In a transistor according to one embodiment of the present disclosure, a first contact hole and a second contact hole may be spaced apart from the gate electrode in a plan view, and at least one of the first source / drain electrode and the second source / drain electrode may include a portion overlapping with the gate electrode.

[0300] In a transistor according to one embodiment of the present disclosure, the active layer may include an oxide semiconductor.

[0301] According to one embodiment of the present disclosure, the transistor may further include a channel auxiliary layer configured as a contact active layer between a first metal pattern and a second metal pattern.

[0302] In a transistor according to one embodiment of the present disclosure, the channel auxiliary layer may include a semiconductor having a higher mobility than the active layer.

[0303] The transistor according to one embodiment of the present disclosure may further include at least one insulating layer between the active layer and the substrate. A first metal pattern, a second metal pattern, and a channel auxiliary layer may be disposed on at least one insulating layer to contact the active layer.

[0304] A display device according to one embodiment of the present disclosure may include: a substrate including a plurality of sub-pixels; a transistor disposed in at least one sub-pixel of the plurality of sub-pixels; a planarization layer covering the transistor; and a light-emitting element disposed on the planarization layer and electrically connected to the transistor.

[0305] A display device according to one embodiment of the present disclosure may include: a substrate including an effective region and an ineffective region surrounding the effective region, the effective region including a plurality of sub-pixels; a plurality of gate lines and a plurality of data lines intersecting each other at the plurality of sub-pixels; a light-emitting element at each of the plurality of sub-pixels; a pixel transistor at at least one of the plurality of sub-pixels; and a driver transistor connected to the plurality of gate lines and disposed in the ineffective region. At least one of the pixel transistor and the driver transistor may include: an active layer; a first metal pattern and a second metal pattern disposed below the active layer while overlapping with the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; a gate electrode disposed on the active layer while overlapping with the active layer, the gate electrode having a width greater than the first distance in the first direction; a gate insulating layer between the active layer and the gate electrode; and source and drain electrodes respectively connected to the first metal pattern and the second metal pattern.

[0306] In a display device according to one embodiment of the present disclosure, a first metal pattern and a second metal pattern may contact an active layer on the same layer, and the active layer may include an oxide semiconductor.

[0307] The display device according to one embodiment of the present disclosure may further include a channel auxiliary layer configured as a contact active layer between the first metal pattern and the second metal pattern. The active layer may include an oxide semiconductor.

[0308] The channel auxiliary layer may include a semiconductor that exhibits higher mobility than the active layer.

[0309] Display devices incorporating transistors according to embodiments of the present disclosure can minimize the channel length margin of the active layer. This allows for reduced manufacturing energy, decreased generation of harmful substances, and lighter display devices to provide wide-width transistors. The display device can also control variations in the effective channel length and reduce threshold voltage sensitivity to apply high-power-side wide transistors with small dimensions. Therefore, when implementing wide transistors in a display device, the channel length margin can be minimized, resulting in lower power consumption compared to structures with long channel length margins.

[0310] The display device according to the embodiments of this disclosure has the advantages of environmental and social sustainability, thereby enabling ESG (Environmental / Social / Governmental) sustainability.

[0311] Although preferred embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the appended claims.

Claims

1. A transistor, comprising: Active layer on substrate; A first metal pattern and a second metal pattern are disposed below the active layer while overlapping with the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; A gate electrode is disposed on the active layer while overlapping with the active layer, and the gate electrode has a width in the first direction greater than the first distance; A gate insulating layer between the active layer and the gate electrode; The first source / drain electrode is connected to the first metal pattern; and A second source / drain electrode connected to the second metal pattern and spaced apart from the first source / drain electrode.

2. The transistor according to claim 1, wherein, The active layer has a channel length in the first direction corresponding to the first distance.

3. The transistor according to claim 1, wherein, The active layer is in contact with the first metal pattern and the second metal pattern.

4. The transistor according to claim 1, wherein, In the cross-sectional view, the active layer is disposed along the steps of the upper and side surfaces of the first and second metal patterns.

5. The transistor according to claim 1, wherein, The gate electrode completely overlaps with the region in the first direction between the first metal pattern and the second metal pattern, and also overlaps with a portion of at least one of the first metal pattern and the second metal pattern.

6. The transistor according to claim 2, wherein, The area of ​​the gate electrode is larger than the area of ​​the channel region.

7. The transistor according to claim 1, wherein, In a second direction intersecting the first direction, the width of the gate electrode is greater than the width of the active layer.

8. The transistor according to claim 1, wherein, The first source / drain electrode and the second source / drain electrode are disposed above the gate electrode.

9. The transistor according to claim 8, wherein, The first source / drain electrode and the second source / drain electrode extend through the gate insulating layer and the active layer and respectively contact the first metal pattern and the second metal pattern.

10. The transistor according to claim 1, wherein, At least one of the first metal pattern and the second metal pattern includes an extension that does not overlap with the active layer.

11. The transistor of claim 10, wherein, The gate electrode completely covers the active layer.

12. The transistor of claim 10, wherein: The first metal pattern includes a first extension protruding from one end of the active layer, and the second metal pattern includes a second extension protruding from the other end of the active layer; The first extension portion is connected to the first source / drain electrode, and the second extension portion is connected to the second source / drain electrode.

13. The transistor of claim 1, further comprising: The light-shielding pattern overlapping the active layer between the active layer and the substrate. The light-shielding pattern and the gate electrode are electrically connected to each other.

14. The transistor of claim 1, further comprising: The light-shielding pattern overlapping the active layer between the active layer and the substrate. The light-shielding pattern is electrically connected to one of the first source / drain electrode and the second source / drain electrode.

15. The transistor of claim 8, further comprising: A buffer layer between the substrate and the active layer; Interlayer insulating layer between the gate electrode and the first source / drain electrode and the second source / drain electrode; The first contact hole in the interlayer insulating layer and the second contact hole in the gate insulating layer overlaps with the first metal pattern and the first source / drain electrode, respectively.

16. The transistor of claim 15, wherein, The first contact hole and the second contact hole are spaced apart from the gate electrode in the plan view.

17. The transistor according to claim 8, wherein, At least one of the first source / drain electrode and the second source / drain electrode includes a portion that overlaps with the gate electrode.

18. The transistor according to claim 1, wherein, The active layer includes an oxide semiconductor.

19. The transistor of claim 1, further comprising: The structure between the first metal pattern and the second metal pattern is a channel auxiliary layer that contacts the active layer.

20. The transistor of claim 19, wherein, The channel auxiliary layer includes a semiconductor having a higher mobility than the active layer.

21. The transistor of claim 19, wherein, The channel auxiliary layer is disposed on the same layer as the first metal pattern and the second metal pattern.

22. The transistor of claim 19, further comprising: At least one insulating layer between the active layer and the substrate, The first metal pattern, the second metal pattern, and the channel auxiliary layer are disposed on the at least one insulating layer to contact the active layer.

23. A display device, comprising: Multiple sub-pixels; The transistor according to claim 1, wherein the transistor is disposed in at least one sub-pixel of the plurality of sub-pixels; A planarization layer covering the transistor; and Light-emitting elements disposed on the planarization layer.

24. A display device, comprising: A substrate, the substrate including an effective region and an ineffective region surrounding the effective region, the effective region including a plurality of sub-pixels; Multiple gate lines and multiple data lines intersecting each other at the multiple sub-pixels; Light-emitting element at each of the plurality of sub-pixels; A pixel transistor in at least one sub-pixel of the plurality of sub-pixels; A driver connected to the plurality of gate lines and disposed in the non-active region; and The driver transistor in the driver, Wherein, at least one of the pixel transistor and the driver transistor includes: The active layer on the substrate; A first metal pattern and a second metal pattern are disposed below the active layer while overlapping with the active layer, the first metal pattern and the second metal pattern being spaced apart from each other by a first distance in a first direction; A gate electrode is disposed on the active layer while overlapping with the active layer, and the gate electrode has a width in the first direction greater than the first distance; The gate insulating layer between the active layer and the gate electrode; and The source and drain electrodes are respectively connected to the first metal pattern and the second metal pattern.

25. The display device according to claim 24, wherein: The first metal pattern and the second metal pattern are in contact with the active layer on the same layer; The active layer includes an oxide semiconductor.

26. The display device according to claim 24, further comprising: A channel auxiliary layer is provided between the first metal pattern and the second metal pattern, the channel auxiliary layer being configured to contact the active layer. The active layer includes an oxide semiconductor. The channel auxiliary layer includes a semiconductor that exhibits a higher mobility than the active layer.

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