Base-floating triode triggered thyristor device and method of making same

Abstract

The application provides a base floating triode triggered thyristor device and a preparation method thereof. The thyristor device comprises a semiconductor layer, a gate structure, source-drain regions, contact regions and electrodes. The semiconductor layer comprises a substrate, a deep well region and a surface layer on the deep well region and adjacent to a first, second and third well region. The gate structure is on the surface of the first well region. The source-drain regions are respectively on the surface of the first well region on both sides of the gate structure. The first and second contact regions are respectively on the surface of the first well region. The third and fourth contact regions are on the surface of the second well region. The fifth contact region is on the surface of the region where the second well region and the third well region meet. The sixth contact region is on the surface of the third well region. The first electrode is electrically connected with the third, fourth and fifth contact regions. The interconnection electrode interconnects the second and sixth contact regions and a source-drain region. The second electrode is electrically connected with the first contact region, the gate structure and another source-drain region. The application reduces the trigger voltage of the device and improves the holding voltage of the device by using the above scheme.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a thyristor device triggered by a base-floating transistor and its preparation method. Background Technology

[0002] With the development of integrated circuits, the feature size of semiconductor devices continues to shrink and the gate oxide layer becomes thinner, drastically reducing the chip's tolerance to electrostatic discharge (ESD). The transient high current generated by ESD can easily break down the oxide layer, burn out the PN junction, and cause chip failure. Currently, commonly used ESD devices include diodes, bipolar transistors, MOSFETs, and silicon controlled rectifiers (SCRs). Compared to other ESD devices, SCRs have a strong current discharge capacity per unit area, low on-resistance, small parasitic capacitance, and high robustness, gradually becoming the mainstream choice for high-end ESD protection.

[0003] Key performance parameters of ESD protection devices include trigger voltage, sustaining voltage, and failure current. The trigger voltage must be lower than the highest withstand voltage of the protected port in the core circuit, i.e., the minimum of the drain-source breakdown voltage and gate oxide breakdown voltage of the MOSFET. Typically, the trigger voltage should be 10% to 20% lower than the highest withstand voltage. The sustaining voltage of the device should be 1.1 to 1.2 times higher than the normal operating voltage of the protected circuit to ensure that the device only conducts discharge current during an electrostatic event. For example, at a 3.3V operating voltage, the trigger voltage of an ESD device should be lower than 9V, and the sustaining voltage should be higher than 3.63V. However, currently, the trigger surface of SCR devices is an N-well / P-well junction (e.g., Figure 1 and Figure 2 As shown in the diagram, if the trigger voltage is too high, the internal components of the circuit will be damaged by the transient high current before the SCR starts working when an ESD event occurs. At the same time, the SCR will generate a significant conductivity modulation effect when it is turned on, which will form a strong hysteresis characteristic, resulting in a holding voltage that is too low (the holding voltage is only about 2V), which cannot be higher than the normal operating voltage of the core circuit. This can easily lead to latch-up risk, causing the chip to fail to work properly or even burn out after power-on.

[0004] Therefore, there is an urgent need to find a thyristor device that can reduce the trigger voltage of the SCR device and increase the sustain voltage of the device by triggering the base floating transistor. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a base-floating transistor-triggered silicon controlled rectifier (SCR) device and its fabrication method, which solves the problem of high trigger voltage and low sustaining voltage in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a base-floating transistor-triggered thyristor, comprising:

[0007] The semiconductor layer includes a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region, a second conductivity type second well region and a first conductivity type third well region located on the upper surface of the deep well region and sequentially adjacent to the first conductivity type first well region, the second conductivity type second well region and the first conductivity type third well region;

[0008] The gate structure is located on the upper surface of the first well region;

[0009] The second conductivity type source and drain regions are respectively located on the upper surface of the first well region on both sides of the gate structure along the arrangement direction of the first well region and the second well region;

[0010] The first contact area and the second contact area of ​​the first conductivity type are respectively located on the upper surface of the first well region on the side of the source / drain region away from the gate structure, and the second contact area is close to the second well region.

[0011] The third contact area of ​​the first conductivity type and the fourth contact area of ​​the second conductivity type are both located on the upper surface of the second well area and are arranged at intervals along the arrangement direction of the first well area and the second well area.

[0012] The fifth contact area of ​​the second conductivity type is located on the upper surface of the region where the second well region and the third well region meet, and the two side walls that are arranged opposite to each other extend into the second well region and the third well region, respectively.

[0013] The sixth contact area of ​​the second conductivity type is located on the upper surface of the third well area and is separated from the fifth contact area by a predetermined distance.

[0014] The first electrode is electrically connected to the third contact area, the fourth contact area, and the fifth contact area, respectively;

[0015] Interconnect electrodes interconnect the sixth contact region, the second contact region, and the source / drain regions near the second well region.

[0016] The second electrode is electrically connected to the first contact area, the gate structure, and the source / drain region on the side away from the second well region, respectively.

[0017] Optionally, the device further includes an isolation structure, which includes a first isolation structure, a second isolation structure, and a third isolation structure. The first isolation structure is embedded at the edge of the regions where the first well region, the second well region, and the third well region are located. The second isolation structure is embedded in the upper surface layer of the boundary region between the first well region and the second well region, and its two side walls, which are arranged opposite to each other, extend into the first well region and the second well region, respectively. The third isolation structure is embedded in the upper surface layer of the first well region between the source / drain region and the first contact region, the upper surface layer of the first well region between the second contact region and the source / drain region, the upper surface layer of the second well region between the third contact region and the fourth contact region, the upper surface layer of the second well region between the fourth contact region and the fifth contact region, and the upper surface layer of the third well region between the fifth contact region and the sixth contact region.

[0018] Optionally, the isolation structure includes shallow trenches and a filling layer that fills the shallow trenches.

[0019] Optionally, the bottom surface of the isolation structure is lower than the bottom surfaces of the first contact area, the second contact area, the third contact area, the fourth contact area, the fifth contact area, the sixth contact area, and the source / drain area.

[0020] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer stacked sequentially, the gate dielectric layer being located on the upper surface of the first well region between the source and drain regions, and the second electrode being electrically connected to the gate conductive layer.

[0021] Optionally, the doping concentration of the first contact region and the second contact region is greater than the doping concentration of the first well region, and the contact type between the first contact region and the second electrode is an ohmic contact.

[0022] Optionally, the doping concentration of the fourth contact region and the fifth contact region is greater than the doping concentration of the second well region, and the contact type between the fourth contact region and the fifth contact region and the first electrode is an ohmic contact.

[0023] Optionally, the contact type between the third contact area and the first electrode is an ohmic contact, and the contact type between the sixth contact area and the interconnect electrode is an ohmic contact.

[0024] Optionally, the device further includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor layer and the exposed surface of the gate structure. The first contact hole penetrates the interlayer dielectric layer and exposes the upper surfaces of the third contact region, the fourth contact region, and the fifth contact region on its bottom surface. The second contact hole penetrates the interlayer dielectric layer and exposes the first contact region, the source / drain region of the gate structure on the side away from the second well region, and the upper surface of the gate conductive layer in the gate structure on its bottom surface. The third contact hole penetrates the interlayer dielectric layer and exposes the second contact region, the source / drain region of the gate structure on the side near the second well region, and the upper surface of the sixth contact region on its bottom surface.

[0025] This invention also provides a method for fabricating a thyristor device triggered by a base-floating transistor, comprising the following steps:

[0026] A semiconductor layer is provided, the semiconductor layer comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region, a second conductivity type second well region and a first conductivity type third well region located on the upper surface of the deep well region and sequentially adjacent to the first conductivity type first well region, the second conductivity type second well region and the first conductivity type third well region;

[0027] A gate structure is formed on the upper surface of the first well region, and a second conductivity type source / drain region, a first conductivity type first contact region, a first conductivity type second contact region, a first conductivity type third contact region, a second conductivity type fourth contact region, a second conductivity type fifth contact region, and a second conductivity type sixth contact region are formed. The source / drain regions are respectively located on the upper surface of the first well region on both sides of the gate structure along the arrangement direction of the first well region and the second well region. The first contact region and the second contact region are respectively located on the upper surface of the first well region on the side of the source / drain region away from the gate structure, and the second contact region is close to the second well region. The third contact region and the fourth contact region are both located on the upper surface of the second well region and are arranged at intervals along the arrangement direction of the first well region and the second well region. The fifth contact region is located on the upper surface of the boundary region between the second well region and the third well region, and its two side walls extend into the second well region and the third well region respectively. The sixth contact region is located on the upper surface of the third well region and is spaced at a predetermined distance from the fifth contact region.

[0028] A first electrode, a second electrode, and an interconnect electrode are formed. The first electrode is electrically connected to the third contact region, the fourth contact region, and the fifth contact region, respectively. The interconnect electrode interconnects the sixth contact region, the second contact region, and the source / drain region near the second well region. The second electrode is electrically connected to the first contact region, the gate structure, and the source / drain region away from the second well region, respectively.

[0029] As described above, the base-floating transistor-triggered thyristor device and its fabrication method of the present invention, by setting a third well region on the side of the second well region away from the first well region, and setting a sixth contact region and a fifth contact region located at the junction of the third well region and the second well region and electrically connected to the first electrode in the third well region, an NPN transistor Qn2 composed of the sixth contact region, the third well region and the fifth contact region is formed in the device to trigger the base-floating transistor of the device, thereby reducing the trigger voltage of the device. At the same time, a gate structure located on the upper surface of the first well region and the sixth contact region are provided. The second contact area, which is electrically connected to the sixth contact area, and the source / drain area, which is electrically connected to the gate structure and located on the side closer to the second well region, form an NPN transistor Qn3 in the device. This is achieved by the source / drain area on the side of the gate structure closer to the second well region, the first well region, and the source / drain area on the side of the gate structure away from the second well region. This creates a shunt path for the NPN transistor Qn3 in the first well region, effectively weakening the positive feedback effect of the SCR, improving the device's sustaining voltage, keeping the device away from latch-up risk, and enhancing the device's protection performance. This design has high industrial application value. Attached Figure Description

[0030] Figure 1 The diagram shows a cross-sectional view of an SCR device.

[0031] Figure 2 The diagram shows the equivalent circuit of an SCR device.

[0032] Figure 3 The diagram shown is a cross-sectional view of the thyristor device triggered by the base-floating transistor of the present invention.

[0033] Figure 4 The diagram shown is an equivalent circuit diagram of the thyristor device triggered by the base-floating transistor of the present invention.

[0034] Figure 5 The diagram shows a simulation of the total current density distribution at the trigger point of the thyristor device triggered by the base-floating transistor of the present invention.

[0035] Figure 6 The figure shown is a simulation diagram of the total current density distribution at the sustaining point of the thyristor device triggered by the base floating transistor of the present invention.

[0036] Figure 7 The diagram shows a process flow chart of the fabrication method of the base-floating transistor-triggered thyristor device of the present invention.

[0037] Figure 8 The diagram shows a cross-sectional view of the semiconductor layer in the fabrication method of the base-floating transistor-triggered thyristor device of the present invention.

[0038] Figure 9The diagram shows a cross-sectional view of the silicon controlled rectifier device triggered by a base-floating transistor according to the present invention after the isolation structure is formed.

[0039] Figure 10 The diagram shows a cross-sectional view of the prepared gate structure of the base-floating transistor-triggered silicon controlled rectifier device according to the present invention.

[0040] Figure 11 The diagram shows a cross-sectional view of the source / drain region and each contact region after forming the base-floating transistor-triggered silicon-controlled device according to the present invention.

[0041] Explanation of reference numerals: 01 P-type substrate, 011 N-type deep well, 012 P-well, 013 N-well, 014 P+ anode region, 015 N+ anode region, 016 N+ cathode region, 017 P+ cathode region, 018 STI, 02 anode, 021 cathode, 1 substrate, 11 deep well region, 12 first well region, 13 second well region, 14 third well region, 15 isolation structure, 16 gate dielectric layer, 17 gate conductive layer, 2 first contact region, 21 source / drain region, 22 second contact region, 23 third contact region, 24 fourth contact region, 25 fifth contact region, 26 sixth contact region, 3 first electrode, 31 interconnect electrode, 32 second electrode. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] Please see Figures 3 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] Example 1

[0045] This embodiment provides a thyristor device triggered by a base-floating transistor, such as... Figure 3 and Figure 4The figures shown are a cross-sectional view of the base-floating transistor-triggered SCR device and an equivalent circuit diagram of the SCR device. The device includes a semiconductor layer, a gate structure, a second conductivity type source / drain region 21, a first conductivity type first contact region 2, a first conductivity type second contact region 22, a first conductivity type third contact region 23, a second conductivity type fourth contact region 24, a second conductivity type fifth contact region 25, a second conductivity type sixth contact region 26, a first electrode 3, an interconnect electrode 31, and a second electrode 32. The semiconductor layer includes a first conductivity type substrate 1 and a second conductivity type deep well region 11 stacked sequentially, and a first conductivity type first well region 12, a second conductivity type second well region 13, and a first conductivity type third well region 14 located on the upper surface of the deep well region 11 and sequentially adjacent to them. The gate structure is located on the upper surface of the first well region 12. The source / drain regions 21 are located on both sides of the first well region along the arrangement direction of the gate structure along the first well region 12 and the second well region 13. The upper surface of 12; the first contact area 2 and the second contact area 22 are respectively located on the upper surface of the first well region 12 on the side of the source / drain region 21 away from the gate structure, and the second contact area 22 is close to the second well region 13; the third contact area 23 and the fourth contact area 24 are both located on the upper surface of the second well region 13 and are arranged at intervals along the arrangement direction of the first well region 12 and the second well region 13; the fifth contact area 25 is located on the upper surface of the boundary area between the second well region 13 and the third well region 14 and the two side walls of the opposite arrangement extend into the second well region 13 and the third well region 14 respectively; the sixth contact area 26 is located on the upper surface of the third well region 14 and is spaced at a predetermined distance from the fifth contact area 25; the first electrode 3 is electrically connected to the third contact area 23, the fourth contact area 24 and the fifth contact area 25 respectively; the interconnect electrode 31 interconnects the sixth contact area 26, the second contact area 22 and the source / drain region 21 on the side close to the second well region 13; the second electrode 32 is electrically connected to the first contact area 2, the gate structure and the source / drain region 21 on the side away from the second well region 13 respectively.

[0046] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type. The doping types of the first and second conductivity types are opposite; that is, when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

[0047] Specifically, the substrate 1 in the semiconductor layer is made of silicon, silicon germanium, or other suitable semiconductor materials. Preferably, a silicon wafer is used as the substrate 1.

[0048] Specifically, the deep well region 11 is used to achieve electrical isolation between the substrate 1 and the first well region 12 and the third well region 14. While ensuring device performance, the doping concentration and thickness of the deep well region 11 can be selected according to the actual situation.

[0049] Specifically, while ensuring device performance, the size, shape, thickness, and doping concentration of the first well region 12 can be selected according to actual conditions; the size, shape, thickness, and doping concentration of the second well region 13 can be selected according to actual conditions; and the size, shape, thickness, and doping concentration of the third well region 14 can be selected according to actual conditions. In this embodiment, the thicknesses of the first well region 12, the second well region 13, and the third well region 14 are the same, that is, the bottom surfaces of the first well region 12, the second well region 13, and the third well region 14 are flush. Here, the thickness refers to the distance between the bottom surface and the top surface of each well region.

[0050] As an example, the device also includes an isolation structure 15, which includes a first isolation structure, a second isolation structure, and a third isolation structure. The first isolation structure is embedded at the edge of the region where the first well region 12, the second well region 13, and the third well region 14 are located. The second isolation structure is embedded in the upper surface of the region where the first well region 12 and the second well region 13 meet, and its two side walls extend into the first well region 12 and the second well region 13 respectively. The third isolation structure is embedded in the upper surface of the first well region 12 between the source / drain region 21 and the first contact region 2, the upper surface of the first well region 12 between the second contact region 22 and the source / drain region 21, the upper surface of the second well region 13 between the third contact region 23 and the fourth contact region 24, the upper surface of the second well region 13 between the fourth contact region 24 and the fifth contact region 25, and the upper surface of the third well region 14 between the fifth contact region 25 and the sixth contact region 26.

[0051] Specifically, the first isolation structure is typically used to isolate the influence of devices outside the regions where the first well region 12, the second well region 13, and the third well region 14 (the regions used to fabricate thyristor devices) have on the thyristor devices in the well regions (i.e., the first well region 12, the second well region 13, and the third well region 14); the second and third isolation structures are typically used to improve the device's failure resistance.

[0052] As an example, the isolation structure 15 includes shallow trenches and filling layers that fill the shallow trenches. Specifically, the first isolation structure is composed of shallow trenches embedded at the edges of the areas where the first well region 12, the second well region 13, and the third well region 14 are located, and filling layers that fill the shallow trenches. The second isolation structure is composed of shallow trenches embedded in the upper surface layer of the area where the first well region 12 and the second well region 13 meet, and filling layers that fill the shallow trenches. The third isolation layer is composed of shallow trenches embedded in the upper surface layer of the well regions between each contact region, and filling layers that fill the shallow trenches.

[0053] Specifically, while ensuring device performance, the opening size and depth of the shallow trench can be selected according to the actual situation.

[0054] Specifically, the filler layer may be made of silicon oxide, silicon oxynitride, silicon nitride, or other suitable dielectric materials. Preferably, a silicon oxide layer is used as the filler layer.

[0055] As an example, the doping concentration of the first contact region 2 and the second contact region 22 is greater than the doping concentration of the first well region 12, and the contact type between the first contact region 2 and the second electrode 32 is an ohmic contact, and the contact type between the second contact region 22 and the interconnect electrode 31 is an ohmic contact, i.e., the first contact region 2 and the second contact region 22.

[0056] Specifically, while ensuring device performance, the size and doping concentration of the first contact region 2 can be selected according to the actual situation; the size and doping concentration of the second contact region 22 can be selected according to the actual situation.

[0057] Specifically, the contact type between the source / drain region 21 on the side of the gate structure closest to the first contact region 2 and the second electrode 32 is an ohmic contact, and the contact type between the source / drain region 21 on the side of the gate structure closest to the second contact region 22 and the interconnect electrode 31 is an ohmic contact.

[0058] Specifically, while ensuring device performance, the size and doping concentration of the source / drain regions 21 can be selected according to the actual situation.

[0059] As an example, the doping concentration of the fourth contact region 24 and the fifth contact region 25 is greater than the doping concentration of the second well region 13, and the contact type between the fourth contact region 24 and the fifth contact region 25 and the first electrode 3 is ohmic contact, that is, the fourth contact region 24 and the fifth contact region 25 are both heavily doped regions.

[0060] Specifically, while ensuring device performance, the size and doping concentration of the fourth contact region 24 can be selected according to the actual situation; the size and doping concentration of the fifth contact region 25 can be selected according to the actual situation.

[0061] As an example, the contact type between the third contact region 23 and the first electrode 3 is an ohmic contact, and the contact type between the sixth contact region 26 and the interconnect electrode 31 is an ohmic contact, that is, both the third contact region 23 and the sixth contact region 26 are heavily doped regions.

[0062] Specifically, while ensuring device performance, the size and doping concentration of the third contact region 23 can be selected according to the actual situation; the size and doping concentration of the sixth contact region 26 can be selected according to the actual situation.

[0063] As an example, the bottom surface of the isolation structure 15 is lower than the bottom surfaces of the first contact area 2, the second contact area 22, the third contact area 23, the fourth contact area 24, the fifth contact area 25, the sixth contact area 26, and the source / drain area 21.

[0064] Specifically, while ensuring device performance, the thickness of each contact area (first contact area 2, second contact area 22, third contact area 23, fourth contact area 24, fifth contact area 25, and sixth contact area 26) can be selected according to actual conditions. Here, thickness refers to the distance between the bottom surface of each contact area and the upper surface of the semiconductor layer.

[0065] As an example, the gate structure includes a gate dielectric layer 16 and a gate conductive layer 17 stacked sequentially. The gate dielectric layer 16 is located on the upper surface of the first well region 12 between the source and drain regions 21, and the second electrode 32 is electrically connected to the gate conductive layer 17.

[0066] Specifically, the gate dielectric layer 16 is made of silicon oxide or other suitable dielectric materials; the gate conductive layer 17 is made of polysilicon or other suitable conductive materials.

[0067] Specifically, the thickness of the gate dielectric layer 16 can be selected according to the actual situation, while ensuring device performance.

[0068] As an example, the device also includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor layer and the exposed surface of the gate structure. The first contact hole penetrates the interlayer dielectric layer and exposes the upper surfaces of the third contact region 23, the fourth contact region 24, and the fifth contact region 25 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer and exposes the first contact region 2, the source / drain region 21 of the gate structure away from the second well region 13, and the upper surface of the gate conductive layer 17 in the gate structure on its bottom surface. The third contact hole penetrates the interlayer dielectric layer and exposes the second contact region 22, the source / drain region 21 of the gate structure near the second well region 13, and the upper surface of the sixth contact region 26 on its bottom surface.

[0069] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer can be selected according to the actual situation; the opening size and opening shape of each contact hole (first contact hole, second contact hole and third contact hole) can be selected according to the actual situation.

[0070] Specifically, the interlayer dielectric layer is used to protect the semiconductor layer while achieving electrical insulation between the first electrode 3, the second electrode 32 and the interconnect electrode 31. The material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0071] Specifically, the first electrode 3 is typically the anode of the device, the second electrode 32 is typically the cathode of the device, the first electrode 3 fills the first contact hole, the second electrode 32 fills the second contact hole, and the interconnect electrode 31 fills the third contact hole. The material of the first electrode 3 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the second electrode 32 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; and the interconnect electrode 31 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0072] It should be noted that the first electrode 3 is electrically connected to the third contact region 23, the fourth contact region 24, and the fifth contact region 25, respectively. The second electrode 32 is electrically connected to the first contact region 2 and the source / drain region 21 on the side away from the second well region 13, respectively. The interconnect electrode 31 is electrically connected to the sixth contact region 26, the second contact region 22, and the source / drain region 21 on the side close to the second well region 13, respectively. This makes the first well region 12, the second well region 13, and the third contact region 23 in the device form a PNP transistor Qp. The second well region 13 in the device is connected to the first well region 12 and the gate structure. The source-drain region 21 on the side away from the second well region 13 forms an NPN transistor Qn1. The sixth contact region 26, the third well region 14, and the fifth contact region 25 in the device form an NPN transistor Qn2 with the base floating. The source-drain region 21 on the side of the gate structure close to the second well region 13, together with the first well region 12 and the source-drain region 21 on the side of the gate structure away from the second well region 13, forms an NPN transistor Qn3. The gate structure electrically connected to the second electrode 32, together with the first well region 12 and the source-drain regions 21 on both sides of the gate structure, forms a gate-grounded NMOS (GGNMOS) structure.

[0073] Specifically, when an ESD pulse is applied to the first electrode 3 and the second electrode 32 is grounded, the NPN transistor Qn2, which is floating in the base region, will turn on first (e.g., Figure 5 As shown), current is provided to the bases of NPN transistors Qn1 and Qn3 in the SCR (Silicon Controlled Rectifier) ​​path to assist in turning on the parasitic transistors. When the voltage drop across the parasitic resistor in the first well region 12 is greater than 0.7V, NPN transistor Qn1 turns on, which in turn provides current to the base of PNP transistor Qp. After both NPN transistor Qn1 and PNP transistor Qp are turned on, a positive feedback mechanism is formed. The device discharges large ESD currents (such as...) through the SCR path formed by NPN transistor Qn1 and PNP transistor Qp. Figure 6 (As shown). At the same time, the parasitic NPN transistor Qn3 at the GGNMOS structure turns on, forming a shunt path on the device surface.

[0074] Specifically, due to the arrangement of the third well region 14, the fifth contact region 25, and the sixth contact region 26, a base-floating NPN transistor Qn2 for triggering the device is formed in the device, which reduces the trigger voltage of the device.

[0075] Specifically, due to the arrangement of the gate structure and the source / drain region 21, and the fact that the gate structure and the source / drain region 21 on the side of the gate structure away from the second well region 13 are electrically connected to the second electrode 32, the source / drain region 21 and the second contact region 22 on the side of the gate structure close to the second well region 13 are electrically connected to the sixth electrode through the interconnecting electrode 31, forming an NPN transistor Qn3 shunt path in the first well region 12, which effectively weakens the positive feedback effect of the SCR, improves the sustaining voltage of the device, keeps the device away from latch-up risk, and improves the protection performance of the device.

[0076] In this embodiment, the base-floating transistor-triggered silicon controlled rectifier (SCR) device forms an NPN transistor Qn2 with a base floating, which is formed by the second well region 13 away from the first well region 12. A third well region 14 is provided on the side of the second well region 13 away from the first well region 12. A sixth contact region 26 and a fifth contact region 25, located at the junction of the third well region 14 and the second well region 13 and electrically connected to the first electrode 3, are provided in the third well region 14. This reduces the trigger voltage of the device. Simultaneously, a gate structure is provided on the upper surface of the first well region 12, and the sixth contact region 26, third well region 14, and fifth contact region 25 are connected to the first electrode 3. The second contact region 22, which is electrically connected to the sixth contact region 26, and the source / drain region 21, which is electrically connected to the sixth contact region 26 and located on the side of the gate structure near the second well region 13, form an NPN transistor Qn3 in the device. This results in an NPN transistor Qn3 formed by the source / drain region 21 on the side of the gate structure near the second well region 13, the first well region 12, and the source / drain region 21 on the side of the gate structure away from the second well region 13. Consequently, an NPN transistor Qn3 shunt path is formed in the first well region 12, which effectively weakens the positive feedback effect of the SCR, improves the holding voltage of the device, keeps the device away from latch-up risk, and enhances the protection performance of the device.

[0077] Example 2

[0078] This embodiment also provides a method for fabricating a thyristor device triggered by a base-floating transistor, such as... Figure 7 The diagram shown is a process flow chart of the fabrication method of the base-floating transistor-triggered silicon controlled rectifier device, including the following steps:

[0079] S1: A semiconductor layer is provided, the semiconductor layer comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region, a second conductivity type second well region and a first conductivity type third well region located on the upper surface of the deep well region and sequentially adjacent to the first conductivity type first well region, the second conductivity type second well region and the first conductivity type third well region;

[0080] S2: A gate structure is formed on the upper surface of the first well region, and a second conductivity type source / drain region, a first conductivity type first contact region, a first conductivity type second contact region, a first conductivity type third contact region, a second conductivity type fourth contact region, a second conductivity type fifth contact region, and a second conductivity type sixth contact region are formed. The source / drain regions are respectively located on the upper surface of the first well region on both sides of the gate structure along the arrangement direction of the first well region and the second well region. The first contact region and the second contact region are respectively located on the upper surface of the first well region on the side of the source / drain region away from the gate structure, and the second contact region is close to the second well region. The third contact region and the fourth contact region are both located on the upper surface of the second well region and are arranged at intervals along the arrangement direction of the first well region and the second well region. The fifth contact region is located on the upper surface of the boundary region between the second well region and the third well region, and its two side walls are respectively extended into the second well region and the third well region. The sixth contact region is located on the upper surface of the third well region and is spaced at a predetermined distance from the fifth contact region.

[0081] S3: Form a first electrode, a second electrode, and an interconnect electrode. The first electrode is electrically connected to the third contact region, the fourth contact region, and the fifth contact region, respectively. The interconnect electrode interconnects the sixth contact region, the second contact region, and the source / drain region on the side near the second well region. The second electrode is electrically connected to the first contact region, the gate structure, and the source / drain region on the side away from the second well region, respectively.

[0082] Please see Figure 8 Steps S1 and S2 are executed: a semiconductor layer is provided, the semiconductor layer comprising a first conductivity type substrate 1 and a second conductivity type deep well region 11 stacked sequentially, and a first conductivity type first well region 12, a second conductivity type second well region 13 and a first conductivity type third well region 14 located on the upper surface of the deep well region 11 and sequentially adjacent to the first conductivity type first well region 12, the second conductivity type second well region 13 and the first conductivity type third well region 14.

[0083] Specifically, the substrate 1 in the semiconductor layer is usually the process platform for fabricating the deep well region 11. While ensuring device performance, the thickness, size, shape and doping concentration of the substrate 1 can be selected according to the actual situation.

[0084] Specifically, the deep well region 11 in the semiconductor layer can be formed on the upper surface of the substrate 1 by epitaxial process or by ion implantation process.

[0085] Specifically, the formation methods of each well region (first well region 12, second well region 13 and third well region 14) on the upper surface of the deep well region 11 include ion implantation or other suitable methods.

[0086] Please see Figures 9 to 11Step S2: A gate structure is formed on the upper surface of the first well region 12, and a second conductivity type source / drain region 21, a first conductivity type first contact region 2, a first conductivity type second contact region 22, a first conductivity type third contact region 23, a second conductivity type fourth contact region 24, a second conductivity type fifth contact region 25, and a second conductivity type sixth contact region 26 are formed. The source / drain region 21 is located on the upper surface of the first well region 12 on both sides of the gate structure along the arrangement direction of the first well region 12 and the second well region 13. The first contact region 2 and the second contact region 22 are respectively located on the upper surface of the first well region 12. The first well region 12 is located on the upper surface of the source / drain region 21 on the side away from the gate structure, and the second contact region 22 is close to the second well region 13. The third contact region 23 and the fourth contact region 24 are both located on the upper surface of the second well region 13 and are arranged at intervals along the arrangement direction of the first well region 12 and the second well region 13. The fifth contact region 25 is located on the upper surface of the boundary area between the second well region 13 and the third well region 14, and the two side walls of the opposite arrangement extend into the second well region 13 and the third well region 14 respectively. The sixth contact region 26 is located on the upper surface of the third well region 14 and is spaced at a predetermined distance from the fifth contact region 25.

[0087] Specifically, such as Figure 9 The diagram shows a cross-sectional view of the isolation structure 15 after its formation. Before forming the gate structure, the process includes forming the isolation structure 15. The isolation structure 15 includes a first isolation structure, a second isolation structure, and a third isolation structure that are spaced apart. The first isolation structure is embedded at the edge of the region where the first well region 12, the second well region 13, and the third well region 14 are located (i.e., the region surrounded by the first isolation structure is used to fabricate SCR devices). The second isolation structure is embedded in the upper surface of the region where the first well region 12 and the second well region 13 meet, and its two side walls extend into the first well region 12 and the second well region 13 respectively. The third isolation structure is embedded in the predetermined region of the upper surface of the first well region 12, the second well region 13, and the third well region 14 respectively. Two third isolation structures are formed in both the first well region 12 and the second well region 13, which are spaced apart in the direction of the arrangement of the first well region 12 and the second well region 13.

[0088] Specifically, the isolation structure 15 includes shallow trenches and filling layers that fill the shallow trenches. The first isolation structure is composed of shallow trenches embedded at the edges of the areas where the first well region 12, the second well region 13, and the third well region 14 are located, and filling layers that fill the shallow trenches. The second isolation structure is composed of shallow trenches embedded in the upper surface layer of the area where the first well region 12 and the second well region 13 meet, and filling layers that fill the shallow trenches. The third isolation layer is composed of shallow trenches embedded in the upper surface layer of the well regions between each contact region, and filling layers that fill the shallow trenches.

[0089] It should be noted that the various parts of the isolation structure 15 can be formed step by step or simultaneously. In this embodiment, the first isolation structure, the second isolation structure, and the third isolation structure are formed simultaneously.

[0090] Specifically, methods for forming shallow trenches include dry etching, wet etching, or other suitable methods; methods for forming filling layers include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0091] Specifically, such as Figure 10 The diagram shows a cross-sectional view of the gate structure after its formation. The formation of the gate structure includes the following steps: a gate dielectric layer 16 covering the exposed surfaces of each well region and a gate conductive material layer located on the upper surface of the gate dielectric layer 16; a patterned masking layer is formed on the upper surface of the gate conductive material layer, and a gate conductive layer 17 is formed on the patterned masking layer directly above the region between the third isolation structures in the first well region 12. The gate dielectric layer 16 and the gate conductive layer 17, which are stacked sequentially on the upper surface of the region between the third isolation structures in the first well region 12, constitute the gate structure, and the gate structure is spaced apart from the third isolation structures in the first well region 12.

[0092] Specifically, the methods for forming the gate dielectric layer 16 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the gate conductive material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the gate dielectric layer 16 is formed using a thermal oxidation process.

[0093] Specifically, the masking layer can be a photoresist layer, a hard mask layer, or a stacked structure composed of a hard mask layer and a photoresist layer. The method of forming a patterned masking layer is a commonly used photolithography process, which will not be elaborated here.

[0094] Specifically, the method for forming the gate conductive layer 17 based on the patterned masking layer includes dry etching, wet etching, or other suitable methods.

[0095] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the source / drain region 21 and each contact region after its formation. The methods for forming the source / drain region 21 and each contact region (first contact region 2, second contact region 22, third contact region 23, fourth contact region 24, fifth contact region 25 and sixth contact region 26) include ion implantation or other suitable methods.

[0096] It should be noted that regions with the same doping type in each contact region can be formed simultaneously or in stages. In this embodiment, the source / drain region 21, the fourth contact region 24, the fifth contact region 25, and the sixth contact region 26 are formed simultaneously using an ion implantation process. The source / drain region 21 is located on the upper surface of the first well region 12 on both sides of the gate structure along the arrangement direction of the first well region 12 and the second well region 13. The fourth contact region 24 is located on the upper surface of the second well region 13 between the two third isolation structures in the second well region 13. The fifth contact region 25 is located on the upper surface of the region between the third isolation structure near the third well region 14 and the third isolation structure in the third well region 14. The sixth contact region 26 is located on the upper surface of the first well region 14. The upper surface of the third well region 14 between the isolation structure and the third isolation structure in the third well region 14 is formed by ion implantation process, and the first contact region 2, the second contact region 22 and the third contact region 23 are formed simultaneously. The first contact region 2 is located on the upper surface of the first well region 12 between the first isolation structure and the adjacent third isolation structure in the first well region 12. The second contact region 22 is located on the upper surface of the first well region 12 between the second isolation structure and the adjacent third isolation structure. The third contact region 23 is located on the upper surface of the second well region 13 between the second isolation structure and the adjacent third isolation structure.

[0097] It should be noted that each contact area is usually adjacent to the side wall of the nearby isolation structure 15, and the side wall of the source / drain area 21 near the gate structure is adjacent to the area directly below the gate structure. Furthermore, the bottom surface of each contact area and the bottom surface of the source / drain area 21 is higher than the bottom surface of the isolation structure 15.

[0098] Specifically, step S3 is performed: forming a first electrode 3, a second electrode 32 and an interconnecting electrode 31. The first electrode 3 is electrically connected to the third contact region 23, the fourth contact region 24 and the fifth contact region 25 respectively. The interconnecting electrode 31 interconnects the sixth contact region 26, the second contact region 22 and the source / drain region 21 near the second well region 13. The second electrode 32 is electrically connected to the first contact region 2, the gate structure and the source / drain region 21 away from the second well region 13 respectively.

[0099] Specifically, after forming the source / drain regions 21 and each contact region, and before forming the first electrode 3, the second electrode 32 and the interconnect electrode 31, the process also includes forming an interlayer dielectric layer, a first contact hole, a second contact hole and a third contact hole. The interlayer dielectric layer covers each contact region and the exposed upper surface of the isolation structure 15. The first contact hole penetrates the interlayer dielectric layer and exposes the third contact region 23, the fourth contact region 24 and the fifth contact region 25 on its bottom surface. The second contact hole penetrates the interlayer dielectric layer and exposes the upper surface of the first contact region 2 and the source / drain region 21 of the gate structure near the first contact region 2, as well as the upper surface of the gate conductive layer 17 in the gate structure on its bottom surface. The third contact hole penetrates the interlayer dielectric layer and exposes the second contact region 22, the sixth contact region 26 and the upper surface of the source / drain region 21 of the gate structure near the second contact region 22 on its bottom surface.

[0100] Specifically, the methods for forming the interlayer dielectric layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming each contact hole (first contact hole, second contact hole, and third contact hole) include dry etching, wet etching, or other suitable methods.

[0101] Specifically, forming each electrode (first electrode 3, second electrode 32, interconnect electrode 31) includes the following steps: forming an electrode material layer that fills each contact hole and covers the upper surface of the interlayer dielectric layer; removing the electrode material layer covering the upper surface of the interlayer dielectric layer to obtain the first electrode 3 filling the first contact hole, the second electrode 32 filling the second contact hole, and the interconnect electrode 31 filling the third contact hole.

[0102] Specifically, methods for forming electrode material layers include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for removing electrode material layers from the surface of the interlayer dielectric layer include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0103] Specifically, by forming a third well region 14 on the side of the second well region 13 away from the first well region 12, a sixth contact region 26 located in the third well region 14, a fifth contact region 25 located on the upper surface of the boundary region between the third well region 14 and the second well region 13, and forming a second contact region 22 located on the side of the first well region 12 close to the second well region 13, and interconnecting the sixth contact region 26 with the second contact region 22, an NPN transistor Qn2 with a base floating and a low trigger voltage is formed, thereby reducing the trigger voltage of the device.

[0104] Specifically, a gate structure and source / drain regions 21 located on both sides of the gate structure are formed on the upper surface of the first well region 12. The source / drain region 21 near the second contact region 22 is electrically connected to the sixth contact region 26 through the interconnect electrode 31. The source / drain region 21 near the first contact region 2 and the gate conductive layer 17 in the gate structure are electrically connected to the second electrode 32. Subsequently, an NPN transistor Qn3 shunt path is added in the first well region 12, which effectively weakens the positive feedback effect of the SCR, improves the device's holding voltage, avoids latch-up risk, effectively protects the circuit, and can be applied to ESD protection of I / O ports under a 3.3V operating voltage, while maintaining good ESD robustness of the device.

[0105] The method for fabricating a base-floating transistor-triggered SCR device in this embodiment involves embedding a GGNMOS and a second contact region 22 in a first well region 12, and forming a third well region 14, a sixth contact region 26 located in the third well region 14, and a fifth contact region 25 located on the upper surface of the boundary region between the second well region 13 and the third well region 14 in the second well region 13 away from the first well region 12. At the same time, the drain of the GGNMOS is electrically connected to the second contact region 22 and the sixth contact region 26, and the fifth contact region 25 is electrically connected to the first electrode. This forms a low-voltage triggered NPN transistor Qn2 in the device, reducing the trigger voltage of the device. At the same time, it forms a shunt path for an NPN transistor Qn3 in the device, effectively weakening the positive feedback effect of the SCR and improving the sustaining voltage of the device.

[0106] In summary, the base-floating transistor-triggered thyristor device and its fabrication method of the present invention improve the device structure by setting a third well region on the side of the second well region away from the first well region, and setting a sixth contact region and a fifth contact region located at the junction of the third well region and the second well region and electrically connected to the first electrode in the third well region. This forms an NPN transistor Qn2 for triggering the device, which is composed of the sixth contact region, the third well region and the fifth contact region, and constitutes a base-floating transistor, thereby reducing the trigger voltage of the device. Furthermore, the method also improves the device by setting a sixth contact region and a fifth contact region located on the upper surface of the first well region. The gate structure, the second contact region electrically connected to the sixth contact region, and the source / drain region electrically connected to the sixth contact region and located on the side of the gate structure closer to the second well region form an NPN transistor Qn3 in the device. This forms an NPN transistor Qn3, consisting of the source / drain region on the side of the gate structure closer to the second well region, the first well region, and the source / drain region on the side of the gate structure farther from the second well region. This creates a shunt path for the NPN transistor Qn3 in the first well region, weakening the positive feedback effect of the SCR, increasing the device's holding voltage, protecting the device from latch-up risk, and enhancing its protection performance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A thyristor device triggered by a base-floating transistor, characterized in that, include: The semiconductor layer includes a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region, a second conductivity type second well region and a first conductivity type third well region located on the upper surface of the deep well region and sequentially adjacent to the first conductivity type first well region, the second conductivity type second well region and the first conductivity type third well region; The gate structure is located on the upper surface of the first well region; The second conductivity type source and drain regions are respectively located on the upper surface of the first well region on both sides of the gate structure along the arrangement direction of the first well region and the second well region; The first contact area and the second contact area of ​​the first conductivity type are respectively located on the upper surface of the first well region on the side of the source / drain region away from the gate structure, and the second contact area is close to the second well region. The third contact area of ​​the first conductivity type and the fourth contact area of ​​the second conductivity type are both located on the upper surface of the second well area and are arranged at intervals along the arrangement direction of the first well area and the second well area. The fifth contact area of ​​the second conductivity type is located on the upper surface of the region where the second well region and the third well region meet, and the two side walls that are arranged opposite to each other extend into the second well region and the third well region, respectively. The sixth contact area of ​​the second conductivity type is located on the upper surface of the third well area and is separated from the fifth contact area by a predetermined distance. The first electrode is electrically connected to the third contact area, the fourth contact area, and the fifth contact area, respectively; Interconnect electrodes interconnect the sixth contact region, the second contact region, and the source / drain regions near the second well region. The second electrode is electrically connected to the first contact area, the gate structure, and the source / drain region on the side away from the second well region. The device also includes an isolation structure, which includes a first isolation structure, a second isolation structure, and a third isolation structure. The first isolation structure is embedded at the edge of the regions where the first well region, the second well region, and the third well region are located. The second isolation structure is embedded in the upper surface of the boundary region between the first well region and the second well region, and its two side walls extend into the first well region and the second well region, respectively. The third isolation structure is embedded in the upper surface of the first well region between the source / drain region and the first contact area, the upper surface of the first well region between the second contact area and the source / drain region, the upper surface of the second well region between the third contact area and the fourth contact area, the upper surface of the second well region between the fourth contact area and the fifth contact area, and the upper surface of the third well region between the fifth contact area and the sixth contact area.

2. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The isolation structure includes shallow trenches and a filling layer that fills the shallow trenches.

3. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The bottom surface of the isolation structure is lower than the bottom surfaces of the first contact area, the second contact area, the third contact area, the fourth contact area, the fifth contact area, the sixth contact area, and the source / drain area.

4. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer stacked sequentially. The gate dielectric layer is located on the upper surface of the first well region between the source and drain regions, and the second electrode is electrically connected to the gate conductive layer.

5. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The doping concentration of the first contact region and the second contact region is greater than the doping concentration of the first well region, and the contact type between the first contact region and the second electrode is an ohmic contact.

6. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The doping concentration of the fourth contact region and the fifth contact region is greater than the doping concentration of the second well region, and the contact type between the fourth contact region and the fifth contact region and the first electrode is an ohmic contact.

7. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The contact type between the third contact area and the first electrode is an ohmic contact, and the contact type between the sixth contact area and the interconnect electrode is an ohmic contact.

8. The thyristor device triggered by a base-floating transistor according to claim 1, characterized in that: The device also includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the exposed upper surface of the semiconductor layer and the exposed surface of the gate structure. The first contact hole penetrates the interlayer dielectric layer and exposes the upper surfaces of the third contact region, the fourth contact region, and the fifth contact region on its bottom surface. The second contact hole penetrates the interlayer dielectric layer and exposes the first contact region, the source / drain region of the gate structure on the side away from the second well region, and the upper surface of the gate conductive layer in the gate structure on its bottom surface. The third contact hole penetrates the interlayer dielectric layer and exposes the second contact region, the source / drain region of the gate structure on the side closer to the second well region, and the upper surface of the sixth contact region on its bottom surface.

9. A method for fabricating a thyristor device triggered by a base-floating transistor, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region, a second conductivity type second well region and a first conductivity type third well region located on the upper surface of the deep well region and sequentially adjacent to the first conductivity type first well region, the second conductivity type second well region and the first conductivity type third well region; A gate structure is formed on the upper surface of the first well region, and a second conductivity type source / drain region, a first conductivity type first contact region, a first conductivity type second contact region, a first conductivity type third contact region, a second conductivity type fourth contact region, a second conductivity type fifth contact region, and a second conductivity type sixth contact region are formed. The source / drain regions are respectively located on the upper surface of the first well region on both sides of the gate structure along the arrangement direction of the first and second well regions. The first and second contact regions are respectively located on the upper surface of the first well region on the side of the source / drain region away from the gate structure, and the second contact region is close to the second well region. The third and fourth contact regions are both located on the upper surface of the second well region and are spaced apart along the arrangement direction of the first and second well regions. The fifth contact region is located on the upper surface of the boundary region between the second and third well regions, and its oppositely arranged sidewalls extend into the second and third well regions, respectively. The sixth contact region is located on the upper surface of the boundary region between the second and third well regions. Before forming the gate structure on the upper surface of the third well region and at a predetermined distance from the fifth contact region, the method further includes forming an isolation structure. The isolation structure includes a first isolation structure, a second isolation structure, and a third isolation structure. The first isolation structure is embedded at the edge of the region where the first well region, the second well region, and the third well region are located. The second isolation structure is embedded on the upper surface of the region where the first well region and the second well region meet, and its two side walls extend into the first well region and the second well region, respectively. The third isolation structure is embedded on the upper surface of the first well region between the source / drain region and the first contact region, the upper surface of the first well region between the second contact region and the source / drain region, the upper surface of the second well region between the third contact region and the fourth contact region, the upper surface of the second well region between the fourth contact region and the fifth contact region, and the upper surface of the third well region between the fifth contact region and the sixth contact region. A first electrode, a second electrode, and an interconnect electrode are formed. The first electrode is electrically connected to the third contact region, the fourth contact region, and the fifth contact region, respectively. The interconnect electrode interconnects the sixth contact region, the second contact region, and the source / drain region near the second well region. The second electrode is electrically connected to the first contact region, the gate structure, and the source / drain region away from the second well region, respectively.

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