A wide-bandgap semiconductor-based photodetection diode and a method of fabricating the same

Abstract

The application provides a wide-bandgap semiconductor-based photodetector diode and a preparation method thereof, and belongs to the technical field of semiconductors. The photodetector diode comprises a back electrode, a wide-bandgap semiconductor epitaxial structure and a dielectric insulation layer. The wide-bandgap semiconductor epitaxial structure comprises a substrate and a lightly doped epitaxial layer, the back electrode is located below the substrate and is in ohmic contact with the back surface of the substrate, the dielectric insulation layer is covered on the lightly doped epitaxial layer and is provided with an oxide layer window, a Schottky contact layer is arranged in the oxide layer window and forms a rectifying barrier with the lightly doped epitaxial layer, the Schottky contact layer and the lightly doped epitaxial layer have a metal-semiconductor contact interface reconstructed through an interface state, and a signal electrode electrically interconnected with the Schottky contact layer is arranged on the dielectric insulation layer and part of the Schottky contact layer. Through differential structure and process design, the application fills the technical gap of speed, noise and power consumption optimization in the existing high-performance wide-bandgap semiconductor photodetector system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wide-bandgap semiconductor-based photodetector diode and its fabrication method. Background Technology

[0002] As the core optocoupler in optoelectronic information conversion systems, photodetectors are responsible for accurately and with low noise converting modulated optical signals transmitted in free space or waveguide media into processable electrical signals. With the rapid evolution of cutting-edge technologies such as next-generation ultra-high-speed, high-capacity optical communication networks, deep ultraviolet to infrared broadband precision detection, and microwave photonic links, terminal systems are placing increasingly stringent performance requirements on photodetectors, including transient response speed, resistance to complex electromagnetic interference, and intrinsic operational stability under extreme temperature and high-energy radiation environments.

[0003] Among related technologies, wide bandgap semiconductor materials, represented by silicon carbide (SiC), are considered ideal platforms for building next-generation high-performance optoelectronic devices for extreme environments due to their wider bandgap, order-of-magnitude increase in critical breakdown field strength, excellent anisotropic thermal conductivity, and higher carrier saturation drift velocity.

[0004] Despite the significant physical advantages of wide-bandgap semiconductor materials, existing Schottky barrier photodetectors still exhibit several common technical challenges in practical micro / nano fabrication and system engineering applications. The primary issue lies in the inherent physical contradiction of their electrical characteristics: to suppress leakage current under reverse bias, conventional designs tend to use barrier metals with high work functions. However, this inevitably leads to a higher forward turn-on voltage, significantly increasing the static power consumption of the front-end readout circuit and reducing its compatibility with modern low-voltage deep submicron complementary metal-oxide-semiconductor (CMOS) readout integrated circuits. Secondly, the excessively large photosensitive area in traditional vertical mesa diode structures induces considerable parasitic junction capacitance, which, from the physical nature of the RC time constant, limits the device's distortion-free tracking capability for high-frequency modulated optical signals. Furthermore, because the effective photocurrent signal generated by ultra-high-speed photoelectric conversion is extremely weak and its spectral components extend into the microwave band, the traditional simplified single-ended pad packaging and bonding wire structure are easily coupled with external radio frequency interference through conduction and radiation paths in complex spatial electromagnetic environments. This results in severe waveform distortion of the extracted effective signal, or even complete submersion by background noise. Summary of the Invention

[0005] This invention provides a wide-bandgap semiconductor-based photodetector diode and its fabrication method. Through differentiated structural and process design, it comprehensively fills the technical gap in the existing high-performance wide-bandgap semiconductor optoelectronic device system regarding the coordinated optimization of speed, noise, and power consumption. The technical solution is as follows: In a first aspect, embodiments of the present invention provide a wide bandgap semiconductor-based photodetector diode, comprising a back electrode, a wide bandgap semiconductor epitaxial structure, and a dielectric insulating layer stacked from bottom to top; The wide bandgap semiconductor epitaxial structure includes a substrate and a lightly doped epitaxial layer located above the substrate; The back electrode is located below the substrate and is alloyed with the substrate to form an ohmic contact; The dielectric insulating layer covers the lightly doped epitaxial layer, and has an oxide layer window on it that exposes the surface of the lightly doped epitaxial layer. A Schottky contact layer is disposed within the oxide layer window, and the Schottky contact layer is in direct contact with the lightly doped epitaxial layer to form a rectifying barrier; there is a metal-semiconductor contact interface with interface state reconstruction between the Schottky contact layer and the lightly doped epitaxial layer. Signal electrodes electrically interconnected with the Schottky contact layer are disposed on the dielectric insulating layer and a portion of the Schottky contact layer.

[0006] Optionally, the alloyed ohmic contact between the back electrode and the substrate is an interface phase formed by high-temperature alloying, and the metal-semiconductor contact interface between the Schottky contact layer and the lightly doped epitaxial layer is an ordered bonding interface formed by medium-low temperature interface reconstruction, and the formation temperature of the ordered bonding interface is lower than the formation temperature of the interface phase.

[0007] Optionally, the Schottky contact layer comprises at least one of a transition metal, a noble metal, and a transparent conductive oxide, or is an alloy or stacked structure formed of the transition metal, the noble metal, and the transparent conductive oxide.

[0008] Optionally, the Schottky contact layer is an ultrathin conductive layer with a thickness ranging from 2 nm to 15 nm.

[0009] Optionally, the signal electrode includes a bottom layer, an intermediate layer and a top layer stacked from bottom to top. The bottom layer is made of one of Ti, Cr, Ni or an alloy thereof, the intermediate layer is made of one of Ti, Au, Cu, Al, Ag, and the top layer is made of one of Au and Pt.

[0010] Optionally, it also includes a ground electrode, wherein the signal electrode and the ground electrode form a radio frequency coplanar waveguide structure, the signal electrode is located in the central region and extends into the oxide layer window and is connected to the Schottky contact layer, and the ground electrode is symmetrically distributed on both sides of the signal electrode and physically isolated from the signal electrode.

[0011] Optionally, the back electrode includes a surface anti-oxidation coating layer, a metal conductive layer, a diffusion barrier layer, and an adhesion transition layer, which are stacked from bottom to top by a variety of conductive materials.

[0012] Optionally, multiple wide-bandgap semiconductor-based photodetectors are provided and integrated on the same substrate in an array, with multiple device units sharing the wide-bandgap semiconductor epitaxial structure and the back electrode as a reference potential terminal.

[0013] In a second aspect, embodiments of the present invention provide a preparation method for fabricating the wide-bandgap semiconductor-based photodetector diode described in the first aspect, comprising: Step 1: The dielectric insulating layer is formed on the surface of the lightly doped epitaxial layer by a thin film deposition process; Step 2: A conductive material layer is deposited under the substrate and subjected to a first thermal annealing treatment to promote the interdiffusion and solid-state reaction between the conductive material and the semiconductor lattice, thereby forming the back electrode. Step 3: Perform a first photolithography process on the dielectric insulating layer, selectively etching away the dielectric insulating material in a designated area to create the oxide layer window, exposing the underlying lightly doped epitaxial layer to define the lateral size of the oxide layer window; Step four: Perform a second photolithography process to deposit an ultrathin conductive layer within the oxide layer window, followed by a second thermal annealing process to form the Schottky contact layer, which has both optical transmission and electrical rectification functions. The temperature of the second thermal annealing process is lower than that of the first thermal annealing process. The first thermal annealing process is configured to alloy the conductive material of the back electrode with the substrate to form a low resistivity ohmic contact. The second thermal annealing process is configured to control the interface state density of the metal-semiconductor contact interface without disrupting the continuity of the ultrathin conductive layer. Step 5: Perform the third photolithography process to deposit a thick conductive material layer on the front side of the device. After removing excess conductive material through a patterning process, the signal electrode is formed.

[0014] Optionally, the first heat annealing treatment is a high-temperature rapid heat annealing with a temperature range of 750°C to 950°C; the second heat annealing treatment is a medium-low temperature heat annealing with a temperature range of 150°C to 500°C.

[0015] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: This invention, by confining photoelectric conversion within a small active region defined by an oxide layer window and employing a low-doping epitaxial layer, reduces the intrinsic junction capacitance and geometric parasitic capacitance within the device's depletion region. Simultaneously, the low-resistance ohmic contact formed by alloying the back electrode and the metal-semiconductor contact interface formed by interface state reconstruction of the Schottky contact layer work together to suppress reverse leakage current while lowering the forward turn-on voltage. Therefore, this invention provides a systematic solution at the structural level to the technical pain points commonly found in existing Schottky barrier photodetectors, such as the difficulty in coordinating turn-on voltage and reverse leakage current, and the limitation of response bandwidth due to excessive parasitic junction capacitance. It fills the technical gap in the existing high-performance wide-bandgap semiconductor optoelectronic device system for speed-noise-power synergistic optimization. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor-based photodetector diode provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the device structure of the wide bandgap semiconductor epitaxial structure provided in an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the device structure after the dielectric insulating layer is formed on the device structure; Figure 4 yes Figure 3 A schematic diagram of the device structure after the back electrode is applied and the device is annealed at high temperature. Figure 5 yes Figure 4 A schematic diagram of the device structure after etching out the oxide layer window in the device structure; Figure 6 yes Figure 5 A schematic diagram of the device structure after etching and depositing an ultrathin conductive layer to form a Schottky contact in the device structure; Figure 7 yes Figure 6 A schematic diagram of the device structure after etching and deposition of signal electrodes; Figure 8 This is a schematic diagram of the layout of the signal electrode and the ground electrode provided in an embodiment of the present invention; Figure 9 This is a flowchart of the preparation method provided in the embodiments of the present invention; Figure 10These are the forward and reverse current-voltage (IV) characteristic curves of the device provided in the embodiments of the present invention; Figure 11 This is a capacitance-voltage (CV) characteristic curve of the device provided in an embodiment of the present invention.

[0018] In the figure: 1-back electrode; 11-surface anti-oxidation capping layer; 12-metal conductive layer; 13-diffusion barrier layer; 14-adhesion transition layer; 2-wide bandgap semiconductor epitaxial structure; 21-substrate; 22-lightly doped epitaxial layer; 3-dielectric insulating layer; 31-oxide window; 4-Schottky contact layer; 5-signal electrode; 6-ground electrode. Detailed Implementation To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0019] See Figures 1 to 8 This embodiment provides a wide bandgap semiconductor-based photodetector diode, which adopts a vertical conductivity structure and includes a back electrode 1, a wide bandgap semiconductor epitaxial structure 2, and a dielectric insulating layer 3 stacked from bottom to top.

[0020] Specifically, the wide bandgap semiconductor epitaxial structure 2 includes a substrate 21 and a lightly doped epitaxial layer 22 located on top of the substrate 21, i.e., on the front side. The substrate 21 is selected from wide bandgap semiconductor single crystal materials with wide bandgap width, order-of-magnitude increase in critical breakdown field strength, excellent anisotropic thermal conductivity, and higher carrier saturation drift velocity, including but not limited to various crystal forms of silicon carbide (e.g., 4H-SiC, 6H-SiC), gallium nitride and related group III nitride alloys, gallium oxide, etc. Those skilled in the art will understand that the specific material system of the substrate 21 can be reasonably adjusted according to the target detection band and working environment: for example, for deep ultraviolet detection applications, high-aluminum group III nitrides such as aluminum gallium nitride can be preferred; for high-speed detection in the visible to near-infrared band, silicon carbide crystal forms such as 4H-SiC or 6H-SiC can be preferred; for the solar-blind ultraviolet region, ultra-wide bandgap materials such as gallium oxide can be preferred. In a preferred embodiment, the substrate 21 is selected from conductive 4H-SiC single crystal wafers.

[0021] The lightly doped epitaxial layer 22 is a low-doped semiconductor layer doped with a first conductivity type dopant, and it is epitaxially grown on the front side of the substrate 21, that is... Figures 1 to 8 The lightly doped epitaxial layer 22 is located above the substrate 21. In a preferred embodiment, the thickness of the lightly doped epitaxial layer 22 is preferably configured to be on the order of 5 μm, and the doping concentration is preferably controlled at 1 × 10⁻⁶. 15 cm -The thickness and concentration are on the order of 3. This combination aims to utilize the high critical breakdown electric field of the wide bandgap material to minimize the forward conduction resistance while ensuring a sufficient reverse blocking voltage. At the same time, the doping concentration of the lightly doped epitaxial layer 22 is configured to match the lateral size of the oxide window 31 (described later), so that the space charge region can be fully extended and approach or reach the substrate interface under the rated reverse working bias, thereby maximizing the sweep efficiency of photogenerated carriers and minimizing the junction capacitance while ensuring a sufficient reverse breakdown voltage.

[0022] The back electrode 1 is located below the substrate 21, i.e., on the back side, and is alloyed with the substrate 21 to form an ohmic contact. The back electrode 1 adopts a low-resistivity composite conductive structure consisting of multiple conductive material layers or formed by high-temperature alloying. It forms a low work function metal carbide or silicide interface phase on the back side of the substrate 21, completely eliminating the back-side Schottky barrier and forming an ohmic contact base with extremely low specific contact resistivity, providing the device with a unified and stable reference potential terminal and a low-resistivity current output path.

[0023] A dielectric insulating layer 3 covers the lightly doped epitaxial layer 22, and an oxide window 31 is formed thereon to expose the surface of the lightly doped epitaxial layer 22. The dielectric insulating layer 3 is made of at least one of silicon oxide, silicon nitride, silicon oxide nitride, and metal oxide dielectric materials. The dielectric insulating layer 3, on the one hand, seals the free dangling bonds on the semiconductor surface, reducing the surface recombination rate to suppress surface leakage; on the other hand, it serves as a physical isolation layer between the subsequent signal electrode and the semiconductor, and between the signal electrode and the ground electrode. Its thickness and dielectric constant together determine the characteristic impedance of the RF electrode and the parasitic coupling capacitance between the electrodes. The oxide window 31 extends through the dielectric insulating layer 3 to the surface of the lightly doped epitaxial layer 22, and its bottom surface exposes part of the lightly doped epitaxial layer 22 to define the active region of the device and constrain the geometric region directly involved in photoelectric conversion.

[0024] A Schottky contact layer 4 is disposed within the oxide window 31, and the Schottky contact layer 4 directly contacts the lightly doped epitaxial layer 22 to form a rectifying barrier. A metal-semiconductor interface with interface state reconstruction exists between the Schottky contact layer 4 and the lightly doped epitaxial layer 22. The Schottky contact layer 4 is also configured as the optical incident window layer of the device: its physical thickness is designed to be significantly smaller than the optical absorption depth of photons in the selected material at the operating wavelength, thereby ensuring extremely high vertical transmittance of the incident light signal while maintaining a continuous in-plane conductive network. This design greatly improves the vertical collection efficiency of photogenerated carriers and eliminates the electric field accumulation effect caused by traditional ring or interdigitated edge electrodes, fundamentally suppressing edge-enhanced dark current.

[0025] A signal electrode 5, electrically interconnected with the Schottky contact layer 4, is disposed on the dielectric insulating layer 3 and a portion of the Schottky contact layer 4. The signal electrode 5 covers a portion of the Schottky contact layer 4 and is vertically interconnected downwards with it, serving as a collection end for photogenerated carriers. The area of ​​the Schottky contact layer 4 not covered by the signal electrode 5 is exposed in the incident light path, constituting the light-transmitting window of the device, i.e., the optical incident window, allowing photons in the probe band to penetrate into the lightly doped epitaxial layer 22 to excite photogenerated electron-hole pairs.

[0026] The working principle of the device in this embodiment is as follows: the incident photons in the detection band are vertically transmitted into the lightly doped epitaxial layer 22 through the light-transmitting window formed by the Schottky contact layer 4. They are absorbed in and near the depletion region and excited to generate photogenerated electron-hole pairs. Under the combined action of the built-in electric field established by the Schottky rectification barrier and the applied reverse bias voltage, the photogenerated carriers are rapidly separated and swept out in the vertical direction. One type of carrier is collected and output by the signal electrode 5 through the Schottky contact layer 4, and the other type of carrier is led out by the back electrode 1 through the lightly doped epitaxial layer 22 and the substrate 21 in sequence, thereby completing the conversion of optical signal to electrical signal.

[0027] Therefore, this embodiment, by confining photoelectric conversion within a small active region defined by the oxide layer window 31 and combining this with the low doping concentration of the lightly doped epitaxial layer 22, reduces the intrinsic junction capacitance and geometric parasitic capacitance within the device's depletion region. Simultaneously, the low-resistance ohmic contact formed by alloying the back electrode 1 and the metal-semiconductor contact interface formed by interface state reconstruction of the Schottky contact layer 4 work together to suppress reverse leakage current while reducing the forward turn-on voltage. Thus, this embodiment provides a systematic solution at the structural level to the technical pain points commonly found in existing Schottky barrier photodetectors, such as the difficulty in coordinating turn-on voltage and reverse leakage current, and the limitation of response bandwidth due to excessive parasitic junction capacitance. It fills the technical gap in the existing high-performance wide-bandgap semiconductor optoelectronic device system for speed-noise-power consumption co-optimization.

[0028] Furthermore, the alloyed ohmic contact between the back electrode 1 and the substrate 21 is an interface phase formed by high-temperature alloying, and the metal-semiconductor contact interface between the Schottky contact layer 4 and the lightly doped epitaxial layer 22 is an ordered bonding interface formed by medium-low temperature interface reconstruction, and the formation temperature of the ordered bonding interface is lower than the formation temperature of the ohmic contact interface phase.

[0029] This invention breaks away from the traditional thermal treatment paradigm of using a single uniform thermal annealing curve in conventional wafer manufacturing. Instead, it applies a spatially separated, differentiated temperature-time annealing kinetic process to the two types of contact interfaces on the front and back sides of the device. For the back electrode 1 located on the back side of the substrate 21, a high-temperature rapid alloying annealing is applied to promote sufficient interdiffusion and interfacial solid-state reaction between the conductive material and the semiconductor lattice, thus forming an ohmic contact interface phase with extremely low specific contact resistivity. For the Schottky contact layer 4 located on the front side, which has both optical transmission and electrical barrier modulation functions, a significantly lower medium-low temperature interface reconstruction annealing is applied independently. Under the premise of strictly avoiding thermally induced atomic migration, clustering, or film shrinkage and other micromorphological degradation of the ultrathin conductive layer, this effectively promotes the orderly bonding of the conductive material and the dangling bonds on the semiconductor surface, and finely controls the interface state density and its energy distribution in the band gap.

[0030] Since the formation temperature of the ordered bonding interface is lower than that of the ohmic contact interface phase, the subsequent low-temperature annealing applied to the front side will not cause thermal budget conflicts with the already formed back-side ohmic contact. This enables independent and synchronous optimization of the low-resistance back-side ohmic contact and the ideal Schottky rectifier contact on the front side in the same process flow. The precise interface state thermodynamic reconstruction process selectively eliminates deep-level interface defects that induce carrier tunneling-recombination leakage channels, alleviates the intensity of the Fermi level pinning effect, and enables the device to simultaneously achieve an extremely low forward turn-on voltage threshold in the subvolt range and an extremely low reverse dark current effectively clamped in the picoampere to sub-picoampere range in terms of macroscopic electrical characteristics. It also makes the device's ideality factor approach the theoretical value of thermionic emission, thus achieving, for the first time, synergistic optimization of forward turn-on characteristics and reverse leakage suppression on a single device.

[0031] Optionally, based on the aforementioned embodiments, this embodiment further defines the material and thickness of the Schottky contact layer 4 to fully realize its dual functions of optical transmission and electrical rectification.

[0032] The Schottky contact layer 4 comprises at least one of transition metals, noble metals, and transparent conductive oxides, or an alloy or stacked structure formed from the above materials. The transition metals include, but are not limited to, at least one of Ni, Pt, Pd, Ir, Mo, and W; the noble metals include, but are not limited to, at least one of Au and Ag; and the transparent conductive oxides include, but are not limited to, at least one of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), and fluorine-doped tin oxide (FTO). Those skilled in the art can rationally select or combine the above material systems based on the work function difference between the selected barrier material and the lightly doped epitaxial layer 22, the target barrier height, and the target detection band.

[0033] Furthermore, the Schottky contact layer 4 is an ultrathin conductive layer with a thickness ranging from 2 nm to 15 nm. Its specific thickness depends on the matching relationship between the intrinsic absorption coefficient of the selected material and the target detection wavelength. The core design principle is that the thickness should be significantly smaller than the optical absorption depth of photons in the selected material at the operating wavelength, ensuring that a sufficient proportion of incident photons can penetrate the ultrathin conductive layer and enter the lightly doped epitaxial layer 22 below to excite photogenerated electron-hole pairs; simultaneously, the thickness must be sufficient to form an in-plane continuous conductive network to ensure efficient lateral carrier collection and low series resistance. In a preferred embodiment, the Schottky contact layer 4 is made of metallic Ni, with a deposition thickness of approximately 5 nm.

[0034] By configuring the Schottky contact layer 4 as an ultrathin conductive layer with a nanometer-scale thickness, it simultaneously possesses optical transmittance and electrical rectification functions: on the one hand, the ultrathin thickness ensures high vertical transmittance of incident light, improving the vertical absorption depth and collection efficiency of photogenerated carriers; on the other hand, the continuous in-plane conductive network ensures efficient collection of lateral carriers and low series resistance, while avoiding the electric field aggregation effect caused by edge electrodes. When a transparent conductive oxide system is selected, transmittance and conductivity can be balanced over a wider spectral range, thereby further expanding the operating wavelength of the device and improving photoelectric response efficiency.

[0035] Optionally, based on the aforementioned embodiments, this embodiment further defines the stacked structure of the signal electrode 5 to balance the electrode's adhesion reliability, low-resistance high-frequency transmission characteristics, and antioxidant bonding characteristics.

[0036] The signal electrode 5 comprises a bottom layer, an intermediate layer, and a top layer stacked from bottom to top. The bottom layer is made of one of Ti, Cr, Ni, or Cr or an alloy thereof; the intermediate layer is made of one of Ti, Au, Cu, Al, or Ag; and the top layer is made of one of Au or Pt.

[0037] The design principles of the above-mentioned stacked structure are as follows: the bottom layer is selected from a transition metal or its alloy that has good adhesion to both the Schottky contact layer 4 and the dielectric insulating layer 3 below, so as to ensure reliable adhesion between the electrode and the device surface and avoid film peeling; the middle layer is selected from a metal that has good process compatibility with both the upper and lower layers and excellent conductivity, as the main conductor to reduce the series resistance of the electrode and carry high-frequency signal transmission; the top layer is selected from a protective metal with excellent resistance to environmental oxidation and bonding compatibility, so as to ensure the stability and reliability of the electrode in the subsequent on-chip probe testing and modular packaging process.

[0038] In a preferred embodiment, the signal electrode 5 adopts a Ni / Ti / Au stacked structure, i.e., the bottom layer is Ni, the middle layer is Ti, and the top layer is Au, with the thicknesses of each layer being approximately 70 nm, 430 nm, and 500 nm, respectively, and the total thickness of the stacked structure being in the range of hundreds of nanometers to several micrometers. Through the above-mentioned layered design, the signal electrode 5 provides a low-resistivity high-frequency signal transmission path while ensuring reliable adhesion to the device surface and good compatibility with external bonding processes. This is beneficial for high-fidelity extraction of photogenerated signals with extremely weak amplitudes and spectral components extending into the microwave band to the back-end readout link.

[0039] Optionally, based on the aforementioned embodiments, this embodiment further provides a grounding electrode 6, and the signal electrode 5 and the grounding electrode 6 together form a radio frequency coplanar waveguide structure to provide broadband impedance matching and near-field electromagnetic shielding.

[0040] Specifically, the wide-bandgap semiconductor-based photodetector diode also includes a ground electrode 6, and the signal electrode 5 and the ground electrode 6 form a radio frequency coplanar waveguide structure. The signal electrode 5 is located in the central region and extends into the oxide window 31, connecting to the Schottky contact layer 4, serving as a collection end for photogenerated carriers; the ground electrode 6 is symmetrically distributed on both sides of the signal electrode 5 and is physically isolated from the signal electrode 5. In a preferred embodiment, the ground electrode 6 includes two parts that are mirror-symmetrically distributed on both sides of the signal electrode 5, thereby forming a ground-signal-ground coplanar waveguide topology with the central signal electrode 5 in a planar layout. The ground electrode 6 is configured to achieve physical and electrical interconnection with the reference ground terminal of an external system in the operating state.

[0041] When operating at microwave frequencies, the ground electrodes 6, symmetrically distributed on both sides of the signal electrode 5, establish a low-impedance connection with the precision reference ground plane of the external test system or the low-inductance ground layer of the package substrate. On the one hand, this provides precise broadband characteristic impedance matching, such as matching to 50Ω or other target characteristic impedances, maximizing the suppression of mode-field mismatch reflections and insertion losses of high-frequency signals. On the other hand, it forms a quasi-static equipotential electromagnetic shielding boundary around the main signal transmission channel, actively bypassing and discharging common-mode and differential-mode RF interference that intrudes through spatial electromagnetic coupling. This RF coplanar waveguide structure creates a pure electromagnetic isolation transmission region for the effective photogenerated microwave signal, approximating an ideal microstrip transmission line. It significantly reduces waveform distortion and channel crosstalk caused by bonding wire parasitic inductance, package resonant modes, and complex far-field electromagnetic radiation, ensuring that the weak photogenerated microwave signal extracted from the broadband noise background maintains high-fidelity signal integrity throughout the entire transmission path from the chip to the back-end amplification link. This provides an effective solution to the technical pain points of traditional single-ended pad packages, which are prone to RF interference coupling, resulting in signal waveform distortion or even being submerged by noise.

[0042] Optionally, the back electrode 1 includes a surface anti-oxidation capping layer 11, a metal conductive layer 12, a diffusion barrier layer 13, and an adhesion transition layer 14, which are stacked from bottom to top by various conductive materials. The adhesion transition layer 14 is located at the top and is in direct contact with the back side of the substrate 21, the surface anti-oxidation capping layer 11 is located at the bottom and forms the outermost surface of the back electrode 1, and the metal conductive layer 12 and the diffusion barrier layer 13 are stacked sequentially between the two.

[0043] The functions of the above-mentioned functional layers are as follows: the adhesion transition layer 14 is in direct contact with the back side of the substrate 21, providing good adhesion between the conductive material and the semiconductor, and undergoing sufficient interdiffusion and solid-state reaction with the semiconductor lattice during the high-temperature alloying process; the diffusion barrier layer 13 is used to prevent excessive interdiffusion between the upper and lower metal atoms, ensuring the stability of the stacked structure during high-temperature processes and long-term operation; the metal conductive layer 12 serves as the main conductor of the back electrode 1, providing a low-resistivity lateral current transport path; the surface anti-oxidation capping layer 11 constitutes the outermost protective layer of the back electrode 1, preventing the internal metal layer from oxidizing in the atmospheric environment, and providing good solderability and bonding properties.

[0044] In a preferred embodiment, the back electrode 1 adopts a four-layer composite conductive stack structure with gradient work function and interdiffusion characteristics. From the back side of the substrate 21 outwards, it consists of an adhesion transition layer 14, a diffusion barrier layer 13, a metal conductive layer 12, and a surface anti-oxidation capping layer 11, which can be made of Ni, Ti, Al, and Au, respectively, with thicknesses of approximately tens of nanometers, tens of nanometers, approximately one hundred nanometers, and approximately one hundred nanometers, respectively. Through the above multilayer conductive stack design, the back electrode 1 can form a uniform, dense, and extremely low specific contact resistivity ohmic contact interface phase on the back side of the substrate 21 after high-temperature alloying annealing, providing a stable and reliable common reference potential terminal and a low-resistivity current output path for the device.

[0045] Optionally, based on the aforementioned embodiments, this embodiment provides a wide bandgap semiconductor-based photodetector diode structure with multiple diodes integrated on-chip in an array on the same substrate 21 to meet application requirements such as high-resolution imaging, multispectral synchronous detection, and spatial diversity reception.

[0046] Multiple device units share a wide-bandgap semiconductor epitaxial structure 2 and a back electrode 1 as a common reference potential terminal, and each unit independently leads out a signal electrode 5 and a ground electrode 6 on the front side of the device for multi-channel photoelectric signal parallel detection. This array-based implementation scheme can simultaneously fabricate multiple independently functional detection units arranged arbitrarily, such as 2×2, 4×4, or N×M, on a single wafer. The spacing and arrangement of each unit can be customized according to specific application requirements. Electrical crosstalk between units can be effectively suppressed through the self-shielding effect of the RF coplanar waveguide electrode and the physical isolation trenches between units.

[0047] This array-based monolithic integrated architecture has significant technical advantages in applications such as focal plane imaging detection, multispectral synchronous analysis, and spatial diversity reception in free-space optical communication, providing a monolithic integrated solution for high-resolution, multi-channel, spatially resolved photoelectric signal detection and readout.

[0048] Figure 9 A flowchart of a preparation method provided in an embodiment of the present invention. For example... Figure 9 As shown, this embodiment provides a method for fabricating a wide-bandgap semiconductor-based photodetector diode as described in any of the preceding embodiments. This method breaks away from the traditional thermal treatment paradigm of using a single uniform thermal annealing curve in conventional wafer fabrication. It innovatively employs a spatially separated annealing kinetics process with differentiated temperature-time curves for the front and back sides, enabling independent and synchronous optimization of the low-resistance ohmic contact on the back side and the ideal Schottky rectifier contact on the front side within the same process flow. The method is implemented sequentially according to the following steps.

[0049] S1. A dielectric insulating layer 3 is formed on the surface of the lightly doped epitaxial layer 22 by a thin film deposition process.

[0050] Specifically, refer to Figures 2 to 3 On the front side surface of the lightly doped epitaxial layer 22, which has undergone standard surface cleaning, a dielectric insulating film is uniformly grown across the entire surface using a thin film deposition process to form the dielectric insulating layer 3. The thin film deposition process includes, but is not limited to, at least one of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), high-temperature thermal oxidation, or wet thermal oxidation. In a preferred embodiment, a silicon dioxide dielectric film is deposited using PECVD with silane and nitrous oxide or oxygen as the precursor gas. The thickness of the dielectric insulating layer 3 is precisely controlled to the order of hundreds of nanometers, preferably around 200 nm. This step, on the one hand, seals the free dangling bonds on the semiconductor surface, reducing the surface recombination rate to suppress surface leakage; on the other hand, it provides a physical isolation layer for subsequent RF electrodes. The thickness and dielectric constant of this layer together determine the characteristic impedance of the coplanar waveguide and the parasitic coupling capacitance between the electrodes.

[0051] S2. A conductive material layer is deposited under the substrate 21 and subjected to a first thermal annealing treatment to promote the interdiffusion and solid-state reaction between the conductive material and the semiconductor lattice, forming the back electrode 1.

[0052] Specifically, refer to Figure 4The wafer is flipped to the back side, and a physical vapor deposition (PVD) process is used, including but not limited to at least one of electron beam evaporation, thermal evaporation, magnetron sputtering, or pulsed laser deposition, to sequentially deposit a multilayer conductive material stack with gradient work function and interdiffusion characteristics on the back side of the substrate 21. Specifically, an adhesion transition layer 14, a diffusion barrier layer 13, a metal conductive layer 12, and a surface anti-oxidation capping layer 11 constituting the back electrode 1 are deposited sequentially. In a preferred embodiment, a Ni / Ti / Al / Au four-layer composite conductive stack structure is used, with the thicknesses of each layer being approximately tens of nanometers, tens of nanometers, approximately one hundred nanometers, and approximately one hundred nanometers, respectively. After deposition, the wafer is placed in a rapid thermal annealing (RTA) apparatus for high-temperature transient alloying in a thermodynamic environment protected by an inert gas, i.e., the first thermal annealing treatment. The first thermal annealing treatment is a high-temperature rapid thermal annealing, with a temperature range of 750°C to 950°C and a holding time configured on the order of several minutes, preferably in the range of 1 to 10 minutes; in a preferred embodiment, the annealing temperature is preferably set to 850°C, and the holding time is preferably 3 minutes. The first thermal annealing process is configured to alloy the conductive material of the back electrode 1 with the substrate 21 to form a low resistivity ohmic contact: under this high-temperature thermodynamic drive, sufficient atomic interdiffusion occurs at the interface to form an interface phase of low work function metal carbide or silicide, completely eliminating the back-side Schottky barrier and forming a back electrode 1 with extremely low specific contact resistivity.

[0053] S3. Perform the first photolithography process on the dielectric insulating layer 3, selectively etch away the dielectric insulating material in a specified area, open the oxide layer window 31, and expose the lightly doped epitaxial layer 22 below to limit the lateral size of the oxide layer window 31.

[0054] Specifically, refer to Figure 5Returning to the front side of the wafer, a photoresist is spin-coated onto the surface of the dielectric insulating layer 3, and the first precision photolithography process is performed, including standard steps such as pre-baking, alignment exposure, post-baking, and development. Under the physical protection of the photoresist mask, a selective etching process is used to completely remove the dielectric insulating material in the designated area, creating an oxide layer window 31 that exposes the clean surface of the lightly doped epitaxial layer 22 below. Simultaneously, photolithographic alignment marks can be fabricated in non-device areas of the wafer for subsequent interlayer alignment in photolithography. The selective etching process includes at least one of dry plasma etching or wet chemical etching: dry plasma etching includes, but is not limited to, at least one of reactive ion etching (RIE), inductively coupled plasma (ICP), and electron cyclotron resonance (ECR) plasma etching, using a halogen-containing reactive gas system. The etching gas can be one or more combinations of fluorine-containing gases such as CF4, CHF3, SF6, and C4F8, and a mixed gas system with auxiliary gases such as O2 and Ar; wet chemical etching can use a buffered oxide etchant (BOE) or dilute hydrofluoric acid (DHF) solution system. In a preferred embodiment, ICP dry etching with a CF4 / O2 mixed gas is used to achieve highly selective and anisotropic etching of the silicon dioxide dielectric insulating layer to obtain a vertical and smooth window sidewall morphology. To achieve extremely low parasitic capacitance at the sub-picoscale level, the lateral geometric area of ​​the oxide window 31 is strictly constrained within a two-dimensional scale on the order of micrometers to tens of micrometers. In a preferred embodiment, its area is approximately 50 μm × 50 μm. In a more aggressive miniaturization scheme, the active region area can be further reduced to 30 μm × 30 μm or even smaller to achieve lower parasitic capacitance and higher response bandwidth.

[0055] S4. Perform the second photolithography process to deposit an ultrathin conductive layer in the oxide window 31, followed by a second thermal annealing process to form a Schottky contact layer 4 that has both optical transmission and electrical rectification functions.

[0056] Specifically, refer to Figure 6A second photolithography process is performed on the exposed surface of the oxide layer window 31 to define the pattern of the Schottky contact region. Subsequently, a high-vacuum physical vapor deposition (PVD) or atomic layer deposition (ALD) process is used to deposit an ultrathin conductive layer with both optical transmittance and electrical rectification functions within the window after photolithography development to form the Schottky contact layer 4. After the deposition of the ultrathin conductive layer is completed, a separate second thermal annealing process is performed. The temperature of the second thermal annealing process is lower than that of the first thermal annealing process; the second thermal annealing process is a medium-low temperature thermal annealing, with a temperature range of 150°C to 500°C, and the holding time is configured to be on the order of several minutes, typically ranging from 1 to 10 minutes; in a preferred embodiment, the annealing temperature is preferably 300°C, and the holding time is preferably 2 minutes. The second thermal annealing process is configured to regulate the interface state density at the metal-semiconductor interface without disrupting the continuity of the ultrathin conductive layer. This low-temperature annealing process must strictly adhere to the following thermodynamic constraints: the annealing temperature must be below the critical temperature that causes thermally induced clustering, film discontinuity, or significant coarsening of the ultrathin conductive layer, while simultaneously providing sufficient thermal activation energy to overcome the short-range rearrangement barrier of interface atoms. Under these conditions, the conductive material and semiconductor surface atoms form an ordered chemical bonding configuration at the interface, effectively eliminating interface defect states introduced by dry etching and conductive material deposition processes, reducing the integrated state density of interface states in the bandgap, and thus mitigating the intensity of the Fermi level pinning effect. Macroscopically, this step manifests as a moderately reduced forward Schottky barrier height, significant suppression of leakage current components contributed by interface defect-assisted tunneling and generation-recombination processes under reverse bias, and a device ideality factor approaching the theoretical value of thermionic emission.

[0057] S5. Perform the third photolithography process to deposit a thick conductive material layer on the front side of the device. After removing excess conductive material through a patterning process, the signal electrode 5 is formed.

[0058] Specifically, refer to Figure 7 and Figure 8The third photolithography process is performed on the front side of the device. A thick photoresist layer is applied and exposed for development to define the negative pattern of the electrode. Subsequently, a high-power physical vapor deposition process is used to deposit a stack of low-resistivity composite conductive materials with a total thickness of several hundred nanometers to several micrometers. This stack sequentially deposits the bottom, middle, and top layers that constitute the signal electrode 5. In a preferred embodiment, a Ni / Ti / Au stack is deposited with thicknesses of approximately 70 nm, 430 nm, and 500 nm, respectively. After deposition, excess conductive material is removed using a lift-off process or selective chemical etching to form the signal electrode 5 on the device surface. When the device includes a ground electrode 6, this step can be combined with the patterned design of the mask to simultaneously form the physically isolated central signal electrode 5 and the symmetrically distributed peripheral ground electrode 6 in the same photolithography and deposition process. A light-transmitting window for photon incidence is simultaneously defined on the surfaces of the dielectric insulating layer 3 and the Schottky contact layer 4, thus completing the three-dimensional integrated structure of the RF coplanar waveguide topology. In a preferred embodiment, the lateral dimensions of both the signal electrode 5 and the two ground electrodes 6 are approximately 50 μm × 50 μm. The spacing between the signal electrode and the ground electrode is optimized to meet the coplanar waveguide design formula for 50 Ω or other target characteristic impedances. During on-chip microwave probe testing or final modular packaging, the ground probe of the external test system or the buried ground plane of the package shell is physically connected to the ground electrode 6 with low inductance, thereby achieving the shielding function of absorbing and efficiently bypassing high-frequency electromagnetic stray energy nearby.

[0059] It should be noted that the first and second thermal annealing processes are applied to the back and front sides of the device, respectively, in terms of space. In terms of temperature, the second thermal annealing process is subject to the constraint that the temperature of the second thermal annealing process is lower than that of the first thermal annealing process. This allows for the independent optimization of the low-resistance ohmic contact on the back side and the ideal Schottky rectifier contact on the front side within the same process flow, without any thermal budget conflict between them. This is the core difference between the fabrication method of this invention and the conventional single uniform thermal annealing paradigm.

[0060] Optionally, in some alternative process embodiments, the execution order of S1 and S2 can be reasonably interchanged. That is, the ohmic contact back electrode 1 on the back side can be prepared first and high-temperature alloying annealing can be performed, and then the dielectric insulating layer 3 can be deposited on the front side. The advantage of this alternative process is that it avoids unnecessary thermal stress and potential thermally induced densification shrinkage of the front dielectric insulating layer 3 during the high-temperature annealing process on the back side, and it can ensure that the initial deposition quality of the insulating layer is not affected by subsequent high-temperature processes. However, it should be noted that this alternative process requires temporary protection measures to be implemented on the front side before the high-temperature alloying on the back side, and the surface of the epitaxial layer on the front side needs to be re-cleaned before the insulating layer is deposited to ensure interface quality. The two process flows have their own focuses, and those skilled in the art can make a reasonable choice according to the specific process equipment conditions and wafer specifications.

[0061] Figure 10 These are the forward and reverse current-voltage (IV) characteristic curves of the device provided in the embodiments of the present invention; Figure 11 This is a capacitance-voltage (CV) characteristic curve of the device provided in an embodiment of the present invention. Finally, based on the above structural design and fabrication method, the wide-bandgap semiconductor-based photodetector diode provided by the present invention is combined with... Figure 10 and Figure 11 The precise DC and AC electrical characteristics were characterized, demonstrating a number of excellent comprehensive performance indicators.

[0062] For reverse bias electrical characteristics, see [link to relevant documentation]. Figure 10 The device exhibits excellent insulation. When a reverse bias voltage of -10V to -20V is applied across the cathode and anode of the device, the reverse leakage current does not experience a catastrophic surge due to soft or hard breakdown, but is stably clamped at an extremely low picoampere to sub-picoampere level, thanks to the effective passivation of deep-level defects at the interface by the low-to-medium temperature thermodynamic reconstruction treatment of the interface between the ultrathin Schottky contact layer 4 and the lightly doped epitaxial layer 22. This provides the necessary high signal-to-noise ratio basis for highly sensitive weak light detection.

[0063] Regarding forward conduction characteristics, see [link to relevant documentation]. Figure 10 Thanks to the optimized barrier-conducting material selected for the target material system and the effective barrier height after interface state modulation, the energy required for the device to cross the conduction threshold is extremely low. Its typical forward turn-on voltage threshold is in the sub-volt range, exhibiting significant forward current injection, for example, between approximately 0.5V and 0.9V. After crossing the threshold voltage, the current increases exponentially with a small voltage increment. When the forward bias continues to rise to several volts, such as 3V to 5V, the device quickly switches to a fully conduction state limited by the series resistance, and the forward current tends to level off and stabilize into a high-capacity saturation carrying platform. Its measured saturation current limit remains in the milliampere range, for example, 5mA to 20mA. The combined electrical performance of low forward turn-on voltage, low reverse leakage current, and high current carrying capacity gives this device a high throughput of up to 10... 9 The ultra-high rectification-to-switching ratio provides a solid physical foundation for achieving linear detection with a wide dynamic range, from extremely weak light to strong light.

[0064] Regarding dynamic small-signal and high-frequency response characteristics, see [link to relevant documentation]. Figure 11 By utilizing the electromagnetic field confinement of the RF coplanar waveguide topology and the extremely low parasitic capacitance design of the miniaturized active region, the traditional physical barrier of the RC time constant limiting the high-frequency response bandwidth is effectively eliminated, and the intrinsic parasitic junction capacitance of the device is successfully suppressed to the sub-picofarad level. In the reverse-biased operating range, the equivalent small-signal junction capacitance of the device may vary within a range of 0.2 pF to 0.6 pF. Figure 11The measured CV curves, in this embodiment of the invention, show a capacitance of approximately 0.6 pF to 0.9 pF near zero bias. This extremely low capacitive reactance parameter is directly converted into a picosecond-level RC response time constant, fundamentally eliminating the high-frequency pulse response tailing and waveform distortion caused by the junction capacitance charging and discharging process. This enables the diode to track and linearly respond to ultra-high-speed optical modulation transient signals with carrier frequencies reaching the microwave level without loss.

[0065] In summary, this invention, through the extreme miniaturization of the active region area by the oxide layer window 31, the low-doping design of the lightly doped epitaxial layer 22, the differentiated annealing process on the front and back sides, and the synergistic cooperation of the radio frequency coplanar waveguide anti-interference electrode structure composed of the signal electrode 5 and the ground electrode 6, simultaneously achieves sub-picofarad-level extremely low parasitic junction capacitance, microwave radio frequency-level ultrafast photoelectric response speed, sub-volt-level low forward turn-on voltage, and picoampere-level extremely low reverse dark current on a single device. This comprehensively fills the technical gap in the existing high-performance wide-bandgap semiconductor optoelectronic device system for speed-noise-power synergistic optimization, and establishes its technical position in applications such as next-generation high-capacity high-speed free-space optical communication, high-power laser pulse precision time-domain diagnostics, and anti-electromagnetic interference microwave photonic links.

[0066] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0067] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a wide-bandgap semiconductor-based photodetector diode, characterized in that, The wide bandgap semiconductor-based photodetector includes a back electrode (1), a wide bandgap semiconductor epitaxial structure (2), and a dielectric insulating layer (3) stacked from bottom to top. The wide bandgap semiconductor epitaxial structure (2) includes a substrate (21) and a lightly doped epitaxial layer (22) located above the substrate (21). The back electrode (1) is located below the substrate (21) and is alloyed with the substrate (21) to form an ohmic contact; The dielectric insulating layer (3) covers the lightly doped epitaxial layer (22) and has an oxide window (31) on it that exposes the surface of the lightly doped epitaxial layer (22). A Schottky contact layer (4) is disposed in the oxide window (31), and the Schottky contact layer (4) is in direct contact with the lightly doped epitaxial layer (22) to form a rectification barrier; there is a metal-semiconductor contact interface reconstructed by interface state between the Schottky contact layer (4) and the lightly doped epitaxial layer (22); Signal electrodes (5) electrically interconnected with the Schottky contact layer (4) are disposed on the dielectric insulating layer (3) and part of the Schottky contact layer (4). The area of ​​the Schottky contact layer (4) not covered by the signal electrodes (5) is exposed in the incident light path, forming an optical incident window. It also includes a ground electrode (6), the signal electrode (5) and the ground electrode (6) form a radio frequency coplanar waveguide structure, the signal electrode (5) is located in the central region and extends into the oxide layer window (31) and is connected to the Schottky contact layer (4), the ground electrode (6) is symmetrically distributed on both sides of the signal electrode (5) and is physically isolated from the signal electrode (5). The preparation method includes: Step 1, forming the dielectric insulating layer (3) on the surface of the lightly doped epitaxial layer (22) by a thin film deposition process. Step 2: A conductive material layer is deposited under the substrate (21) and a first thermal annealing treatment is performed to promote the interdiffusion and solid-state reaction between the conductive material and the semiconductor lattice, thereby forming the back electrode (1). Step 3: Perform the first photolithography process on the dielectric insulating layer (3), selectively etch away the dielectric insulating material in the specified area, open the oxide layer window (31), and expose the lightly doped epitaxial layer (22) below to limit the lateral size of the oxide layer window (31); Step four, perform the second photolithography process to deposit an ultrathin conductive layer in the oxide window (31), and then perform a second thermal annealing process to form the Schottky contact layer (4) which has both optical transmission and electrical rectification functions. The temperature of the second thermal annealing process is lower than the temperature of the first thermal annealing process. The first thermal annealing process is configured to alloy the conductive material of the back electrode (1) with the substrate (21) to form a low resistivity ohmic contact. The second thermal annealing process is configured to control the interface state density of the metal-semiconductor contact interface without destroying the continuity of the ultrathin conductive layer. Step 5: Perform the third photolithography process to deposit a thick conductive material layer on the front side of the device. After removing the excess conductive material through a patterning process, the signal electrode (5) is formed. The first heat annealing process is a high-temperature rapid heat annealing, with a temperature range of 750°C to 950°C and a holding time of 1 to 10 minutes; the second heat annealing process is a medium-low temperature heat annealing, with a temperature range of 150°C to 500°C and a holding time of 1 to 10 minutes.

2. The preparation method according to claim 1, characterized in that, The alloyed ohmic contact between the back electrode (1) and the substrate (21) is an interface phase formed by high-temperature alloying. The metal-semiconductor contact interface between the Schottky contact layer (4) and the lightly doped epitaxial layer (22) is an ordered bonding interface formed by medium-low temperature interface reconstruction, and the formation temperature of the ordered bonding interface is lower than the formation temperature of the interface phase.

3. The preparation method according to claim 2, characterized in that, The Schottky contact layer (4) includes at least one of a transition metal, a noble metal, and a transparent conductive oxide, or is an alloy or stacked structure formed by the transition metal, the noble metal, and the transparent conductive oxide.

4. The preparation method according to claim 3, characterized in that, The Schottky contact layer (4) is an ultrathin conductive layer with a thickness ranging from 2 nm to 15 nm.

5. The preparation method according to claim 1, characterized in that, The signal electrode (5) includes a bottom layer, an intermediate layer and a top layer stacked from bottom to top. The bottom layer is made of one of Ti, Cr, Ni or an alloy thereof. The intermediate layer is made of one of Ti, Au, Cu, Al, Ag. The top layer is made of one of Au or Pt.

6. The preparation method according to claim 1, characterized in that, The back electrode (1) includes a surface anti-oxidation coating layer (11), a metal conductive layer (12), a diffusion barrier layer (13), and an adhesion transition layer (14) stacked from bottom to top by a variety of conductive materials.

7. The preparation method according to claim 1, characterized in that, The wide bandgap semiconductor photodetector diodes are arranged in multiples and integrated on the same substrate (21) in an array. The multiple device units share the wide bandgap semiconductor epitaxial structure (2) and the back electrode (1) as reference potential terminals.

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