Floating gate optoelectronic memory device without persistent photoconductivity and method of fabrication thereof

Abstract

The application provides a floating gate optoelectronic memory device without persistent photoconductivity and a preparation method thereof, and belongs to the technical field of semiconductor optoelectronic devices and neuromorphic computing. The device comprises a substrate support layer, a floating gate layer arranged on the substrate support layer, a tunneling dielectric layer arranged on the floating gate layer, a channel region and a control region which are isolated from each other and arranged on the tunneling dielectric layer, a two-dimensional material channel layer arranged in the channel region, a source and a drain which are respectively in contact with two ends of the two-dimensional material channel layer, and a control gate arranged in the control region. The control gate, the source, the drain and the two-dimensional material channel layer are in a coplanar distribution, the control gate is laterally capacitively coupled with the two-dimensional material channel layer through the floating gate layer, and a space above the two-dimensional material channel layer is exposed. The floating gate optoelectronic memory device can work as a dark-state multi-bit information memory, an optoelectronic composite dynamic modulator and a high-frequency real-time dynamic computing unit.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor optoelectronic devices and neuromorphic computing technology, and in particular to a floating-gate optoelectronic memory device without continuous photoconductivity and its fabrication method. Background Technology

[0002] In the post-Moore's Law era, to overcome the computational bottlenecks and power consumption limitations faced by traditional von Neumann architectures when processing massive amounts of unstructured data, neuromorphic computing, based on artificial synaptic devices, has become a focal point in the industry. To accurately map the synaptic weights of complex neural networks, such as convolutional neural networks and spiking neural networks, synaptic devices must possess high-density, multi-bit non-volatile storage capabilities. In recent years, two-dimensional semiconductor materials, such as molybdenum disulfide and molybdenum ditelluride, have been widely used in constructing floating-gate polymorphic memories due to their atomic-level thickness, absence of surface dangling bonds, and excellent electrostatic control properties. These devices, by controlling the discrete capture of charge in the floating gate layer, can achieve stable, multi-order conductance state regulation, thus providing a solid electrical foundation for high-precision hardware neural networks.

[0003] With the development of machine vision and edge computing, introducing optical signals as presynaptic stimuli or modulation dimensions into devices to construct integrated photoelectric synapses has become an evolutionary trend in this field. However, when introducing optical signals for modulation into existing two-dimensional floating gate devices, a persistent physical bottleneck is generally encountered: the persistent photoconductivity effect. Numerous cutting-edge studies and patents indicate that two-dimensional materials and their dielectric layer interfaces often contain a large number of shallow energy level defects. Under illumination, photogenerated carriers are easily captured by these interface defects, causing them to fail to recombine rapidly after the illumination is removed. This phenomenon results in the device conductivity remaining high for a long time, unable to quickly return to its initial state. Although some existing technologies utilize the slow decay of the persistent photoconductivity effect to simulate the plasticity of biological synapses, this is a fatal flaw in recombination modulation scenarios based on multistate weights. Specifically, the photogenerated carriers that cannot recombine rapidly due to persistent photoconductivity irreversibly change the multi-bit electrical weights pre-written precisely in the dark state, leading to the loss of the network's pre-set long-term memory. The device cannot instantly return to its initial reference conductivity state after the illumination is removed, resulting in severe physical crosstalk between the underlying electrical weights and the surface optical stimulation. This makes existing two-dimensional floating-gate optoelectronic devices unable to respond to high-frequency continuous photoelectric pulses, completely eliminating their feasibility for application in dynamic visual processing and high-frequency real-time computing. In summary, how to overcome the inherent continuous photoconductivity effect in two-dimensional optoelectronic memories, and simultaneously achieve stable multi-bit electrical storage while ensuring lossless and rapidly recoverable photoelectric dynamic composite modulation, is a core technical challenge that urgently needs to be solved in the current field of neuromorphic computing hardware. Summary of the Invention

[0004] This invention provides a floating gate opto-memory device without continuous photoconductivity and its fabrication method. The floating gate opto-memory device can function as a dark-state multi-bit information memory, an opto-electric composite dynamic modulator, and a high-frequency real-time dynamic computing unit.

[0005] In a first aspect, the present invention provides a floating-gate opto-storage device without continuous photoconductivity, comprising: Substrate support layer; A floating gate layer disposed on the substrate support layer; A tunneling dielectric layer disposed on the floating gate layer; The tunneling dielectric layer is provided with mutually isolated channel areas and control areas; The channel region is provided with a two-dimensional material channel layer and a source and a drain that are respectively in contact with both ends of the two-dimensional material channel layer; the control region is provided with a control gate. The control gate is coplanar with the source, the drain, and the two-dimensional material channel layer. The control gate is laterally capacitively coupled to the two-dimensional material channel layer through the floating gate layer. The space above the two-dimensional material channel layer is exposed.

[0006] In some embodiments, the tunneling dielectric layer is a silicon dioxide thin film prepared by atomic layer deposition.

[0007] In some embodiments, the tunneling dielectric layer is a multilayer composite dielectric layer, including at least two insulator layers of different materials, wherein the at least two insulator layers of different materials have different band structures to form a stepped or asymmetric tunneling barrier between the floating gate layer and the two-dimensional material channel layer.

[0008] In some embodiments, the two-dimensional material channel layer is a bipolar molybdenum distellide nanosheet.

[0009] In some embodiments, the substrate support layer is a silicon wafer with thermally oxidized silicon dioxide on its surface, and the floating gate layer is a platinum thin film.

[0010] In some embodiments, the floating gate layer is made of a conductive material with an adjustable work function.

[0011] In a second aspect, the present invention also provides a method for fabricating a floating-gate opto-memory device without continuous photoconductivity, for fabricating the floating-gate opto-memory device without continuous photoconductivity as described in the first aspect, the method comprising: Provide a substrate support layer; A floating gate layer is formed on the substrate support layer by a deposition process; A tunneling dielectric layer is formed on the floating gate layer by a deposition process; Two-dimensional material is transferred to the channel region on the tunneling dielectric layer by a transfer process to form a two-dimensional material channel layer. The source, drain, and control gate are simultaneously formed on the tunneling dielectric layer using a deposition process.

[0012] In some embodiments, the formation of a tunneling dielectric layer on the floating gate layer by a deposition process includes: A silicon dioxide thin film is deposited on the floating gate layer as the tunneling dielectric layer using a plasma-enhanced atomic layer deposition process.

[0013] In some embodiments, the transfer process of transferring two-dimensional material to the channel region on the tunneling dielectric layer to form a two-dimensional material channel layer includes: Few-layer two-dimensional material nanosheets were obtained by mechanical exfoliation; Using polydimethylsiloxane as a transfer medium, the few-layer two-dimensional material nanosheets are transferred from polyimide tape to the surface of the polydimethylsiloxane. The few-layer two-dimensional material nanosheets on the surface of the polydimethylsiloxane are aligned and transferred to the channel region of the tunneling dielectric layer using a precision alignment and transfer platform.

[0014] Thirdly, the present invention also provides a neuromorphic computing unit, including a floating gate photoelectric memory device without continuous photoconductivity as described in the first aspect, for real-time dynamic calculation in response to high-frequency light pulse signals.

[0015] This invention achieves physical spatial separation between the control gate and the light incident path, ensuring complete photosensitivity of the channel layer. Simultaneously, it constructs functional partitions and physical isolation between electrical storage and photoelectric response, enabling lossless parallel operation of both. This lays the structural foundation for subsequently eliminating persistent photoconductivity effects and improves device reliability and design flexibility. Furthermore, the coplanar structure ensures the programming form of the floating gate layer information, avoiding channel injection and enabling gate injection. This is suitable for optoelectronic devices, simplifies the device manufacturing process, avoids alignment accuracy issues caused by multi-layer stacking, improves device manufacturability and consistency, and facilitates high-frequency operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1This is a three-dimensional structural schematic diagram of a floating gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention; Figure 2 This is a top view of a floating gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention under an optical microscope; Figure 3 This is a schematic flowchart of a method for fabricating a floating gate opto-storage device without continuous photoconductivity according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the storage function of a floating gate photoelectric storage device without continuous photoconductivity, which stores multi-bit weight information by gradually editing it with electrical pulses in the dark state, according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the conductivity state of a floating gate photoelectric storage device without continuous photoconductivity provided in an embodiment of the present invention when stimulated by continuous external light pulses; Figure 6 This is a schematic diagram illustrating the short-term detailed changes of a floating-gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention when stimulated by continuous external light pulses; Figure 7 This is a schematic diagram illustrating the light response speed of a floating gate photoelectric storage device without continuous photoconductivity when illuminated and when the light is removed, according to an embodiment of the present invention. Figure 8 This is a bidirectional scanning transfer curve diagram of a floating gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention under gate source driving. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0019] Figure 1 This is a three-dimensional structural schematic diagram of a floating gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention. Figure 2 This is a top-view schematic diagram under an optical microscope of a floating-gate opto-storage device without continuous photoconductivity provided in an embodiment of the present invention. Combined with... Figure 1 and Figure 2A floating gate optoelectronic memory device without continuous photoconductivity includes a substrate support layer 1, a floating gate layer 2 disposed on the substrate support layer 1, and a tunneling dielectric layer 3 disposed on the floating gate layer 2. A channel region and a control region are disposed on the tunneling dielectric layer 3 and are isolated from each other. A two-dimensional material channel layer 4 is disposed in the channel region and a source electrode 5 and a drain electrode 6 respectively contacting the two ends of the two-dimensional material channel layer 4. A control gate 7 is disposed in the control region. The control gate 7 is coplanarly distributed with the source electrode 5, the drain electrode 6 and the two-dimensional material channel layer 4. The control gate 7 is laterally capacitively coupled to the two-dimensional material channel layer 4 through the floating gate layer 2. The space above the two-dimensional material channel layer 4 is exposed.

[0020] Specifically, substrate support layer 1 refers to the base material used to support the entire device structure, providing mechanical support and necessary electrical isolation. Floating gate layer 2 refers to the conductive layer located above substrate support layer 1, used for storing charge. It is completely surrounded by insulating material, utilizing charge storage to achieve non-volatile storage functionality. Tunneling dielectric layer 3 refers to an insulating thin film layer located above floating gate layer 2, thin enough to allow charge to pass through under specific conditions via tunneling, while forming a barrier to prevent charge leakage under normal conditions. Channel region refers to a specific area above tunneling dielectric layer 3, used to house the conductive channel layer. Control region refers to another specific area above tunneling dielectric layer 3, physically isolated from the channel region, used to house the control gate 7. Two-dimensional material channel layer 4 refers to a conductive channel made of two-dimensional material, used to carry the current between source 5 and drain 6. Source 5 and drain 6 refer to the metal electrodes in contact with both ends of the two-dimensional material channel layer 4, used to apply voltage to drive current flow through the channel layer. The control gate 7 refers to the metal electrode located in the control region, used to regulate the potential of the floating gate layer 2 via capacitive coupling, thereby affecting the conductivity of the channel layer. Coplanar distribution means that the control gate 7, source 5, drain 6, and two-dimensional material channel layer 4 are all located on the same horizontal surface of the tunneling dielectric layer 3. Lateral capacitive coupling means that the control gate 7 is not directly stacked vertically above the channel, but rather uses the continuous floating gate layer 2 below as a coupling medium to achieve electrical regulation of the lateral channel layer. Specifically, the control gate 7 forms a vertical capacitive coupling with the floating gate layer 2 below, and the floating gate layer 2 then transfers the potential to the area below the channel region, ultimately forming a vertical capacitive coupling with the channel layer. Exposed upper space means that there are no obstructions directly above the two-dimensional material channel layer 4, allowing light to directly illuminate its surface.

[0021] When a voltage is applied to the control gate 7, a first vertical capacitor is formed between the control gate 7 and the extended portion of the floating gate layer 2 directly below it. This voltage changes the potential of the entire floating gate layer 2 through capacitive coupling. The floating gate layer 2 is a continuous conductor, and its portion below the channel region forms a second vertical capacitor with the upper two-dimensional material channel layer 4. Therefore, the voltage of the control gate 7, transmitted through the floating gate layer 2, ultimately regulates the carrier concentration in the two-dimensional material channel layer 4 via capacitive coupling, thereby changing the channel current between the source 5 and the drain 6. Since the control gate 7 is coplanar with the source 5, drain 6, and channel layer, and there are no electrodes obstructing the channel layer, light can directly illuminate the surface of the two-dimensional material channel layer 4. When illuminated, the two-dimensional material channel layer 4 absorbs photons to generate photogenerated electron-hole pairs. These photogenerated carriers directly change the channel conductivity, achieving photoelectric response.

[0022] Thus, this embodiment of the invention achieves physical spatial separation between the control gate 7 and the light incident path, ensuring complete photosensitivity of the channel layer. Since the control gate 7 is moved away from the conventional top of the channel and is coplanarly disposed on the surface of the tunneling dielectric layer 3 with the source and drain electrodes, there are no longer any opaque metal electrodes obstructing the top of the two-dimensional material channel layer 4. This allows incident light to directly illuminate the entire channel region without loss or obstruction, maximizing the light absorption efficiency of the channel material and providing a physical basis for subsequent high-sensitivity photoelectric detection or modulation. Simultaneously, functional partitioning and physical isolation of electrical storage and photoelectric response are constructed, enabling lossless parallel operation of both. The tunneling dielectric layer 3 in the middle acts as a physical barrier between these two functional areas. Although the control gate 7 is located at the top, it regulates the storage state through lateral capacitive coupling via the bottom floating gate layer 2. Its operating path and the light incident path are separated by different paths in physical space, achieving long-term stable electrical storage and transient response photoelectric modulation. Both can operate independently and in parallel within the same device without interference. Furthermore, this structure lays the structural foundation for eliminating the persistent photoconductivity effect and improves the reliability and design flexibility of the device. Due to the implementation of the aforementioned functional partitioning, photogenerated carriers generated in the channel during illumination are confined above the dielectric layer. They cannot cross the high barrier formed by the high-quality dielectric layer to interfere with the pre-stored charge state in the floating gate layer 2, fundamentally avoiding the problem of photogenerated carriers injecting into the floating gate or interacting with interface defects in complex ways, leading to weight drift, as is common in traditional structures. Simultaneously, the coplanar structure simplifies the device manufacturing process, avoids alignment accuracy issues caused by multi-layer stacking, improves the manufacturability and consistency of the device, and enables self-alignment by controlling the co-fabrication of the gate 7 and source / drain 6, reducing parasitic capacitance and facilitating high-frequency operation of the device.

[0023] In some embodiments, the tunneling dielectric layer 3 is a silicon dioxide thin film prepared by atomic layer deposition.

[0024] Specifically, atomic layer deposition (ALD) refers to a thin film deposition technique based on continuous self-limiting surface reactions. It achieves atomic-level thickness control of thin film growth by alternately introducing precursor gases. Silica thin films refer to insulating films composed of silica material. An ALD is used to grow a silica thin film as a tunneling dielectric layer 3 on a floating gate layer 2. This process achieves precise angstrom-level control of the film thickness by cyclically and alternately introducing silicon and oxygen precursors, growing only a single atomic layer in each cycle. Simultaneously, due to the self-limiting nature of the reaction, the grown silica thin film exhibits extremely high density, excellent thickness uniformity, and extremely low pinhole defect density.

[0025] Therefore, this embodiment of the invention obtains a high-quality dielectric layer by using atomic layer deposition to prepare a silicon dioxide thin film as the tunneling dielectric layer 3. This dielectric layer has an extremely low interface defect state density, effectively reducing the probability of photogenerated carriers being trapped by interface traps, and fundamentally suppressing the causes of persistent photoconductivity. At the same time, the high-density dielectric layer provides a higher tunneling barrier for the stored charge in the floating gate layer 2, significantly enhancing the charge retention capability of the device and ensuring the stability of non-volatile storage.

[0026] In some embodiments, the tunneling dielectric layer 3 is a multilayer composite dielectric layer, including at least two insulator layers of different materials, which have different band structures to form a stepped or asymmetric tunneling barrier between the floating gate layer 2 and the two-dimensional material channel layer 4.

[0027] Specifically, a multilayer composite dielectric layer refers to a composite dielectric layer structure composed of two or more different insulating materials stacked together. An insulator layer refers to each individual insulating film that makes up the multilayer composite dielectric layer. Band structure refers to the distribution of allowed energy states for electrons in a solid material, mainly including parameters such as the conduction band bottom, valence band top, and band gap. A tunneling barrier refers to the potential energy barrier that electrons need to cross; its height is determined by the band shift of the dielectric layer material. A stepped tunneling barrier refers to a composite barrier composed of multiple layers of materials with different band structures, where the barrier height changes in a stepped manner. An asymmetric tunneling barrier refers to a barrier whose shape or height differs when electrons cross from the floating gate layer 2 towards the channel layer versus when they cross from the channel layer towards the floating gate layer 2.

[0028] A first insulator layer, a second insulator layer, or one or more insulator layers with different band structures are sequentially deposited on the floating gate layer 2. The conduction band bottom and valence band top positions of these different materials differ, creating a band discontinuity at the interlayer interface. When an electron attempts to cross this composite dielectric layer, it does not face a single rectangular potential barrier, but rather a stepped potential barrier composed of multiple barrier segments of varying heights. By selecting the band arrangement of the materials, an asymmetric characteristic can be achieved where the barrier is lower when electrons cross from one side to the other, and higher when crossing in the opposite direction.

[0029] Therefore, this embodiment of the invention achieves fine-grained control of tunneling behavior by setting up a multilayer composite dielectric layer to form a stepped or asymmetric tunneling barrier. Compared to a single-layer silicon dioxide dielectric layer, the multilayer composite structure can provide a more optimized tunneling path for electrical write and erase operations while ensuring a high barrier to prevent photogenerated carriers from entering the floating gate layer 2. For example, a stepped barrier can reduce the write voltage, or an asymmetric barrier can achieve a faster erase speed and a longer hold time, thereby further optimizing the overall performance of the device.

[0030] In some embodiments, the two-dimensional material channel layer 4 is a bipolar molybdenum distellide nanosheet.

[0031] Specifically, bipolar refers to materials with high mobility for both electrons and holes, and the values ​​of both are close, enabling the effective conduction of both types of charge carriers simultaneously within the same material. Molybdenum ditelluride (MoTe2) is a transition metal chalcogenide semiconductor material. Nanosheets refer to two-dimensional sheet-like materials with a thickness at the nanoscale. When illuminated, they absorb photon energy to generate electron-hole pairs. Due to the bipolar nature of molybdenum ditelluride, the effective masses of its electrons and holes are close, and their mobility values ​​are comparable and both high. Photogenerated electrons and holes can move rapidly in the channel, resulting in a high probability and speed of recombination. After the illumination is removed, the excess electrons and holes in the channel recombine within a very short time, and the channel conductivity quickly returns to its pre-illumination state.

[0032] Therefore, this embodiment of the invention utilizes bipolar molybdenum ditelluride nanosheets as the channel layer, taking advantage of their high and balanced electron-hole mobility. This characteristic allows photogenerated electrons and holes to recombine rapidly, achieving rapid recovery on the order of hundreds of microseconds after illumination is removed. This fundamentally eliminates the physical basis for the persistent photoconductivity effect caused by the low mobility or trapping of single charge carriers in traditional two-dimensional materials. Simultaneously, the excellent absorption of visible light by molybdenum ditelluride ensures that the device has high photoelectric responsivity. It should be noted that the two-dimensional channel layer 4 can be composed of other bipolar two-dimensional semiconductor materials; this embodiment of the invention does not specifically limit its composition.

[0033] In some embodiments, the substrate support layer 1 is a silicon wafer with thermally oxidized silicon dioxide on its surface, and the floating gate layer 2 is a platinum thin film.

[0034] Specifically, thermally oxidized silicon dioxide refers to a silicon dioxide layer grown on the surface of a single-crystal silicon wafer through a high-temperature thermal oxidation process. The silicon wafer refers to a single-crystal silicon substrate. The platinum thin film refers to a continuous thin film layer composed of metallic platinum. A silicon wafer with thermally oxidized silicon dioxide on its surface is used as the substrate support layer 1, where the thermally oxidized silicon dioxide provides electrical isolation from the silicon wafer. A platinum thin film is formed on the surface of the thermally oxidized silicon dioxide as a floating gate layer 2 through a deposition process. Platinum has a high work function, which, combined with the high-quality silicon dioxide dielectric layer, enables the formation of a deep potential well structure in the floating gate layer 2. When charge is written into the platinum floating gate layer 2, due to the combined effect of the high work function of platinum and the high potential barrier of silicon dioxide, the charge is difficult to escape, achieving non-volatile storage.

[0035] Therefore, this embodiment of the invention obtains a flat, clean substrate with good electrical isolation by using thermally oxidized silicon dioxide / silicon wafer as the substrate. A platinum thin film is used as the floating gate layer 2, and its high work function characteristics, together with the silicon dioxide dielectric layer, are used to construct a deep potential well structure, significantly enhancing the charge storage capability of the floating gate layer 2. Experiments show that this combination maintains excellent charge retention characteristics even at a high temperature of 85°C, providing a material basis for achieving highly stable multi-bit non-volatile storage.

[0036] In some embodiments, the floating gate layer 2 is made of a conductive material with an adjustable work function.

[0037] Specifically, tunable work function refers to the ability to adjust the interface characteristics between the floating gate layer 2 and the tunneling dielectric layer 3 during the device design and fabrication stage by selecting conductive materials with different work functions as the floating gate layer 2, thereby optimizing the device's storage performance. The work function of the floating gate layer 2 is one of the key parameters determining the interface barrier height between it and the tunneling dielectric layer 3. The interface barrier height, i.e., the energy barrier that electrons must overcome to transition from the floating gate layer 2 to the tunneling dielectric layer 3, directly affects two core performance characteristics: the ability to retain stored charge and the programming and erasing efficiency.

[0038] By appropriately selecting the work function of the floating gate layer 2, the aforementioned performance can be balanced and optimized. For example, when a high work function conductive material is used, a high interface barrier is formed between the floating gate layer 2 and the tunneling dielectric layer 3. This high barrier effectively suppresses thermionic emission and tunneling leakage of stored charges, significantly enhancing the non-volatile storage capability of the device, making it particularly suitable for applications requiring long-term data retention. When a medium or low work function conductive material is used, the interface barrier is relatively lower, which can reduce the programming and erasing voltage, improve the device's operating speed and energy efficiency, and is suitable for applications requiring rapid dynamic updates.

[0039] Therefore, embodiments of the present invention can optimize the design by selecting a floating gate material with a suitable work function according to different requirements for data retention time, operating voltage, and programming speed in different application scenarios. When a high work function material is selected, it is used in conjunction with a high-quality tunneling dielectric layer to construct a deep potential well structure, achieving excellent non-volatile storage capability. This breaks through the limitations of a single material and provides a material-level control dimension for continuous optimization of device performance. Combined with a high-quality tunneling dielectric layer and a bipolar two-dimensional material channel layer, it achieves optoelectronic storage characteristics without continuous photoconductivity.

[0040] In summary, this invention realizes a floating-gate optoelectronic memory device with multi-state storage capability and no continuous photoconductivity. The device adopts a lateral capacitive coupling architecture with an extended floating gate. In the dark state, due to the deep potential well structure constructed by the tunneling dielectric layer 3 and the floating gate layer 2, the device can achieve highly stable multi-bit non-volatile electrical weighted storage. Under illumination, due to the high barrier of the tunneling dielectric layer 3, photogenerated carriers in the two-dimensional material channel layer 4 cannot enter the floating gate layer 2 to change the pre-stored charge state, realizing lossless superposition of non-volatile pulse editing and transient photoconductivity modulation. Thanks to the high and balanced electron and hole mobility of the bipolar molybdenum ditelluride nanosheets, photogenerated carriers can recombine rapidly on the order of hundreds of microseconds after the light is removed. This floating-gate device eliminates the relaxation phenomenon caused by continuous photoconductivity, effectively solving the problems of insufficient stability and photoelectric crosstalk in existing two-dimensional floating-gate optoelectronic devices, and providing a new direction for high-frequency real-time dynamic visual computing. Floating gate opto-memory devices can function as dark-state multi-bit non-volatile memory, light-illuminated volatile dynamic composite modulators, and real-time dynamic computing units that execute high-frequency pulses.

[0041] Figure 3 This is a schematic flowchart illustrating a method for fabricating a floating-gate optoelectronic memory device without continuous photoconductivity, according to an embodiment of the present invention. The method for fabricating a floating-gate optoelectronic memory device without continuous photoconductivity is used to fabricate the floating-gate optoelectronic memory device without continuous photoconductivity as described in the above embodiment. Figure 3 As shown, the fabrication method of a floating-gate optoelectronic memory device without continuous photoconductivity includes the following steps: S101, Provide a substrate support layer.

[0042] S102. A floating gate layer is formed on the substrate support layer by a deposition process.

[0043] S103. A tunneling dielectric layer is formed on the floating gate layer through a deposition process.

[0044] S104. The two-dimensional material is transferred to the channel region on the tunnel dielectric layer by a transfer process to form a two-dimensional material channel layer.

[0045] S105. The source, drain and control gate are simultaneously formed on the tunnel dielectric layer by a deposition process.

[0046] Specifically, deposition processes refer to various techniques for forming thin films on a substrate surface, including but not limited to physical vapor deposition (PVD), such as electron beam evaporation, thermal evaporation, and sputtering, and chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD). Transfer processes refer to techniques for peeling pre-prepared materials from the original growth substrate or support medium and repositioning them onto the target substrate. Simultaneous formation refers to the simultaneous fabrication of three electrode structures—source 5, drain 6, and control gate 7—in a single patterning and deposition process step.

[0047] First, a clean substrate support layer 1 is provided as the base. A floating gate layer 2 is formed on the substrate support layer 1 through a deposition process to provide a carrier for charge storage. Next, a tunneling dielectric layer 3 is formed on the floating gate layer 2 through a deposition process. This layer completely covers the floating gate layer 2 and provides a tunneling barrier and top-to-bottom isolation. Then, a pre-prepared two-dimensional material is precisely placed into the pre-designed channel region position on the tunneling dielectric layer 3 through a transfer process to form a two-dimensional material channel layer 4. Finally, the patterns of the source electrode 5, drain electrode 6, and control gate 7 are defined through a patterning process, and metal material is simultaneously deposited through a deposition process to simultaneously form the source electrode 5, drain electrode 6, and control gate 7 on the tunneling dielectric layer 3.

[0048] Therefore, this embodiment of the invention avoids the high-temperature process or lattice mismatch problems that may be introduced by directly growing two-dimensional materials on the tunneling dielectric layer 3 by using a transfer process to form the two-dimensional material channel layer 4, thus protecting the quality of the underlying floating gate and dielectric layer. By simultaneously forming the source 5, drain 6, and control gate 7, the process flow is simplified, the number of photolithography alignments is reduced, and the geometric relationship of the control gate 7, source 5, drain 6, and channel layer on the same plane is ensured, providing process assurance for realizing the lateral capacitive coupling architecture.

[0049] In some embodiments, forming a tunneling dielectric layer 3 on the floating gate layer 2 by a deposition process includes: depositing a silicon dioxide thin film on the floating gate layer 2 as the tunneling dielectric layer 3 using a plasma-enhanced atomic layer deposition process.

[0050] Specifically, plasma-enhanced atomic layer deposition (PEALD) is a technique that introduces plasma into the atomic layer deposition process to enhance reactivity, enabling high-quality thin film growth at lower temperatures. On the surface of a sample where a floating gate layer 2 has already been formed, a silicon dioxide thin film is deposited using PALD. This process involves placing the sample in a deposition chamber and alternately introducing silicon precursor and oxygen plasma. In each cycle, silicon precursor molecules are chemisorbed onto the sample surface to form a monolayer, and then the oxygen plasma oxidizes the adsorbed precursor to silicon dioxide, regenerating surface active sites. The film thickness is precisely controlled to the target value by controlling the number of cycles.

[0051] Therefore, this invention employs plasma-enhanced atomic layer deposition (PEALD) to grow silicon dioxide thin films with extremely high density, extremely low defect state density, and excellent thickness uniformity at relatively low temperatures. The silicon dioxide grown by this process forms a high-quality interface with the underlying platinum floating gate, jointly constructing a deep potential well structure and ensuring the non-volatility of stored information. The low-temperature process avoids thermal damage to the existing structure caused by high temperatures.

[0052] In some embodiments, a two-dimensional material is transferred to a channel region on a tunneling dielectric layer 3 by a transfer process to form a two-dimensional material channel layer 4, including: obtaining few-layer two-dimensional material nanosheets by mechanical peeling; using polydimethylsiloxane as a transfer medium, transferring the few-layer two-dimensional material nanosheets from a polyimide tape to the surface of polydimethylsiloxane; and aligning and transferring the few-layer two-dimensional material nanosheets on the surface of polydimethylsiloxane to the channel region of the tunneling dielectric layer 3 using a precision alignment transfer platform.

[0053] Specifically, mechanical peeling refers to the physical method of repeatedly sticking and peeling adhesive tape from bulk crystals to obtain thin nanosheets. Few-layer two-dimensional material nanosheets refer to thin sheets of two-dimensional material with a thickness of several atomic layers. Polydimethylsiloxane is a transparent, elastic, and adhesive polymer material used as a medium for the transfer of two-dimensional materials. Polyimide tape is a high-temperature resistant tape used in the mechanical peeling process of two-dimensional materials. A precision alignment and transfer platform is a device equipped with a microscope and a precision displacement stage, enabling micron- or even nanometer-level alignment and transfer operations.

[0054] First, polyimide tape was repeatedly adhered to and peeled off from molybdenum ditelluride (MoD) block crystals to obtain dispersed few-layer MoD nanosheets on the tape. Under a microscope, nanosheets with suitable morphology and thickness were selected. A piece of polydimethylsiloxane was attached to a glass slide, and after contacting the selected nanosheet, it was slowly lifted. Due to the stronger adhesion between polydimethylsiloxane and MoD, which is greater than that of the polyimide tape, the nanosheet transferred from the tape to the polydimethylsiloxane surface. The polydimethylsiloxane slide with the nanosheets was mounted on a precision alignment and transfer platform, with a sample containing a pre-prepared floating gate and dielectric layer placed below. Under a microscope, the platform was precisely moved to align the nanosheets on the polydimethylsiloxane with the channel region on the sample, and then slowly lowered to bring the nanosheets into contact with the dielectric layer surface. After heating or allowing it to stand, the slide was lifted very slowly, causing the polydimethylsiloxane to detach and the nanosheets to remain in the channel region.

[0055] Therefore, this invention, through mechanical exfoliation and a polydimethylsiloxane-mediated dry transfer process, yielded high-quality few-layer molybdenum ditelluride nanosheets and achieved precise positioning within the channel region. This process avoids contamination of the interface between the two-dimensional material and the dielectric layer by chemical etching or solution processes, maintaining interface cleanliness. A clean interface further reduces defect state density, helping to suppress persistent photoconductivity. Simultaneously, precise positioning ensures the integrity of the device structure.

[0056] The present invention also provides a neuromorphic computing unit, including a floating gate photoelectric memory device without continuous photoconductivity as described in the above embodiments, for real-time dynamic calculation in response to high-frequency light pulse signals.

[0057] Specifically, a neuromorphic computing unit refers to a hardware computing unit that mimics the functions of biological neurons and synapses, and is a fundamental module for building a neuromorphic computing system. High-frequency optical pulse signals refer to repetitive optical pulse sequences with high frequencies, such as those above kilohertz. Real-time dynamic computing refers to a computing mode that responds to and processes input signals instantly, keeping pace with the speed of signal changes.

[0058] The floating-gate opto-storage device described in the above embodiments is used as the core device of the neuromorphic computing unit. This device has two parallel operating dimensions: in the electrical dimension, non-volatile weight information is stored through the floating gate layer, representing the long-term connection strength of synapses; in the optical dimension, high-frequency light pulse signals are sensed through the channel layer, representing presynaptic input. When a high-frequency light pulse sequence illuminates the exposed channel layer of the device, each light pulse excites transient photogenerated carriers in the channel, causing a momentary increase in channel conductance. This transient photoconductivity is linearly superimposed with the static electrical weights pre-stored in the floating gate layer, jointly determining the output source-drain current. Since the device has no continuous photoconductivity effect, the conductance recovers rapidly after each light pulse ends, without affecting the response to subsequent pulses, thus enabling accurate response to continuous high-frequency light pulses. By assembling multiple such devices into an array and designing corresponding peripheral circuits, multiplication and accumulation operations based on optical input and electrical weights can be implemented to complete real-time dynamic visual computing tasks.

[0059] Therefore, this embodiment of the invention, through a floating-gate opto-memory device with non-continuous photoconductivity, enables the neuromorphic computing unit to simultaneously achieve non-volatile electrical weight storage and transient photoconductivity response. Due to the device's fast recovery characteristics, this unit can respond to high-frequency light pulse sequences without inter-pulse crosstalk, meeting the high temporal resolution requirements of real-time dynamic visual computing. Simultaneously, the lossless superposition of electrical weights and optical inputs allows the unit to directly perform multiplication and accumulation operations in the analog domain, avoiding frequent analog-to-digital conversions and data transfers, and potentially realizing highly energy-efficient sensor-memory-computing integrated neuromorphic hardware.

[0060] The technical solution of the present invention will be further illustrated below through specific embodiments. It should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0061] The fabrication method of a floating gate optoelectronic memory device without continuous photoconductivity is implemented according to the following steps. First, the substrate support layer 1 is prepared. Specifically, a silicon wafer with 300 nm thermally oxidized silicon dioxide on its surface is provided as the substrate support layer 1. The silicon wafer is ultrasonically cleaned sequentially in acetone, isopropanol, and deionized water to remove surface organic contaminants and particles, and then dried with nitrogen. Next, the floating gate layer 2 is prepared. Specifically, polymethyl methacrylate photoresist is spin-coated onto the cleaned substrate support layer 1, and the pattern of the floating gate layer 2 is exposed by electron beam evaporation. The exposed sample is placed in an electron beam evaporation device to deposit, for example, a 5 nm thick platinum thin film. After deposition, a stripping process is performed to remove the photoresist and excess metal, leaving the patterned platinum thin film as the floating gate layer 2. Next, the tunneling dielectric layer 3 is prepared. The sample with the platinum floating gate layer 2 is transferred to a plasma-enhanced atomic layer deposition device. Deposition is performed at 250 °C using bis(diethylamino)silane as the silicon precursor and oxygen plasma as the oxygen source. By controlling the number of deposition cycles, a silicon dioxide film, for example 8 nanometers thick, is grown on the platinum floating gate layer 2 as a tunneling dielectric layer 3. The silicon dioxide film grown by this plasma-enhanced atomic layer deposition process has extremely high density and extremely low interface defect states, which can provide a sufficiently high tunneling barrier for charge carriers, thereby forming a deep potential well structure together with the bottom floating gate layer 2 to ensure the non-volatile and stable storage of information.

[0062] Next, the two-dimensional material channel layer 4 is prepared. Specifically, a blocky molybdenum ditelluride crystal is taken and mechanically peeled off using polyimide tape. By repeatedly sticking and pasting, a few layers of molybdenum ditelluride nanosheets dispersed on the tape are obtained. Nanosheets of suitable thickness are selected under an optical microscope. A piece of polydimethylsiloxane is attached to a glass slide. Under the microscope, the target nanosheet on the tape is aligned, gently pressed, and then lifted to transfer the nanosheet from the polyimide tape to the surface of the polydimethylsiloxane. The polydimethylsiloxane slide carrying the nanosheet is mounted on a precision alignment and transfer platform. The sample with the prepared floating gate layer 2 and tunneling dielectric layer 3 is placed below. Through microscopic observation, the platform is precisely moved to align the nanosheet on the polydimethylsiloxane with the preset channel region position on the sample. The glass slide is slowly lowered to bring the nanosheets into contact with the silica surface. For example, it can be heated to 70°C and held for 5 seconds, and then the glass slide is lifted at a very slow speed. The polydimethylsiloxane detaches, and the few-layer molybdenum distellide nanosheets remain in the channel region, forming a two-dimensional material channel layer 4.

[0063] Finally, source electrode 5, drain electrode 6, and control gate electrode 7 are fabricated. Specifically, on the sample surface after the transfer of the two-dimensional material channel layer 4, a double layer of methyl methacrylate and polymethyl methacrylate photoresist is spin-coated, and the patterns of source electrode 5, drain electrode 6, and control gate electrode 7 are simultaneously defined using an electron beam exposure process. The exposed sample is placed in a thermal evaporation deposition apparatus, and for example, an 8 nm thick layer of chromium and a 60 nm thick layer of gold are deposited sequentially. After deposition, a lift-off process is performed to remove the photoresist and excess metal on it, and source electrode 5, drain electrode 6, and control gate electrode 7 are simultaneously formed on the tunneling dielectric layer 3. Among them, source electrode 5 and drain electrode 6 are located in the channel region and are in contact with the two ends of the molybdenum ditelluride nanosheet, respectively; control gate electrode 7 is located in the control region and is coplanarly distributed with source electrode 5, drain electrode 6, and channel layer.

[0064] The device prepared in this embodiment was subjected to performance testing. Figure 4 This is a schematic diagram illustrating the storage function of a floating gate photoelectric storage device without continuous photoconductivity, which stores multi-bit weight information by gradually editing it with electrical pulses in the dark state, according to an embodiment of the present invention. Figure 4 The horizontal axis represents time, and the vertical axis represents source and leakage current. Figure 4 The test results show that the device achieves editing of 134 discrete weighted states within a source-drain current range of 1 nanoamp to 100 nanoamp. Adjacent states strictly conform to the 3σ criterion, meaning the difference between the average values ​​of two adjacent states exceeds three times the sum of their standard deviations. This indicates that the device can store 7 bits of electrical information through electrical pulse editing in the dark state, demonstrating high-density non-volatile storage capability.

[0065] Figure 5 This is a schematic diagram of the conductivity state of a floating gate photoelectric memory device without continuous photoconductivity provided by an embodiment of the present invention when stimulated by continuous external light pulses. Specifically, it is a schematic diagram of the conductivity state at the level of tens of thousands of seconds when the device is stimulated by continuous external light pulses, showing the gain when light is added and the recovery when light is removed. Figure 5 The horizontal axis represents time, and the vertical axis represents source and drain current. The device is first programmed with an electrical pulse to a current state of, for example, about 88 nanoamps, and then a series of light pulses with a wavelength of, for example, 473 nanometers are applied. Figure 5 The test results show that when the device is edited to a certain conductivity state by electrical pulses, due to the high barrier effect of the high-quality tunneling dielectric layer 3, the photo-excited charge carriers cannot cross the barrier to enter the floating gate layer 2. Therefore, the pre-stored non-volatile storage weights still maintain extremely high stability under long-term, high-frequency optoelectronic interactions at the tens of thousands of seconds level, proving that the device can perfectly realize long-term and optoelectronic composite modulation of electrical pre-edited data.

[0066] Figure 6This is a schematic diagram of the short-term detailed changes of a floating gate opto-retention device without continuous photoconductivity provided by an embodiment of the present invention when stimulated by continuous external light pulses. Specifically, it is a schematic diagram of the short-term detailed changes of the device's conductivity value when stimulated by continuous external light pulses, showing the gain when light is applied and the recovery when light is removed. Figure 6 The horizontal axis represents time, and the vertical axis represents source and leakage current. Figure 6 The test results show that when external light is applied, the transient photogenerated carriers in the two-dimensional material channel layer 4 can be effectively coupled and superimposed with the pre-stored electrostatic field in the floating gate layer 2, realizing the instantaneous dynamic gain of the device conductivity. Moreover, after the light is removed, the device does not produce relaxation phenomenon caused by continuous photoconductivity. The device conductivity value can accurately and without delay fall back to the initial weight state set by the dark state electrical editing, demonstrating excellent optoelectronic composite dynamic modulation characteristics.

[0067] Figure 7 This is a schematic diagram illustrating the light response speed of a floating gate photoelectric storage device without continuous photoconductivity when illuminated and when the light is removed, according to an embodiment of the present invention. Figure 7 The horizontal axis represents time, and the vertical axis represents the normalized photocurrent. Figure 7 The test results show that, thanks to the high electron and hole mobility of the bipolar molybdenum ditelluride nanosheets, excess charge carriers in the two-dimensional channel layer 4 can recombine rapidly after the light is removed, effectively avoiding transport hysteresis caused by deep-level trapping due to defects. The device conductivity can rapidly recover within a timescale of hundreds of microseconds, strongly demonstrating that the device possesses excellent high-frequency photoelectric pulse response capability and the potential to perform real-time dynamic visual computing.

[0068] Figure 8 This is a bidirectional scanning transfer curve of a floating gate opto-memory device without continuous photoconductivity provided in an embodiment of the present invention under gate-source driving, demonstrating the counterclockwise hysteresis characteristic under bidirectional scanning of gate-source voltage. Figure 8 The horizontal axis represents the gate-source voltage, and the vertical axis represents the source-drain current. The transfer characteristics of the device fabricated in this embodiment were tested. Figure 8 The transfer curves measured when the gate-source voltage is scanned from -10V to +10V and then scanned back from +10V to -10V are shown. Figure 8It can be concluded that the transfer curve of the device exhibits a counterclockwise hysteresis window. When a sufficiently large positive gate-source voltage is applied, electrons in the floating gate layer are erased. Due to the electrostatic regulation of the charge carriers in the channel by the charge in the floating gate layer, the number of electrons in the two-dimensional material channel layer increases, and the current in the two-dimensional material channel layer increases. Conversely, when a sufficiently large negative gate-source voltage is applied, electrons are injected from the control gate into the floating gate layer. Due to electrostatic regulation, the number of electrons in the two-dimensional material channel layer decreases, and the current in the two-dimensional material channel layer decreases. This counterclockwise hysteresis characteristic directly proves that the charge programming mechanism of the device of the present invention is gate injection, rather than channel hot carrier injection. This confirms the original intention of the structural design of the present invention, that is, by physically isolating the control gate from the channel region and using the lateral capacitance coupling of the extended floating gate, independent and precise control of the charge in the floating gate layer is achieved, avoiding damage to the channel region during the programming process. Furthermore, from Figure 8 As can be seen, the device has a large storage window and a high switching ratio, further confirming its excellent non-volatile storage capability and multi-bit storage potential.

[0069] In summary, the floating-gate opto-memory device without continuous photoconductivity provided by this invention has the following characteristics: First, the two-dimensional material channel layer is completely exposed directly above it, ensuring unobstructed full absorption of incident external light signals, thus providing a foundation for efficient photoelectric response. Second, in the dark state, thanks to the deep potential well structure jointly constructed by the high work function floating gate layer and the high-quality tunneling dielectric layer, the device can achieve well-defined and stable multi-level non-volatile weight editing, and maintain excellent charge retention characteristics even at high temperatures. Third, under illumination, the device exhibits excellent characteristics of no persistent photoconductivity due to the synergistic effect of the following three factors: First, the suppression of high interface barrier. The high barrier formed between the high-quality tunneling dielectric layer and the floating gate layer and channel layer effectively blocks the injection of photogenerated carriers into the floating gate layer, avoiding changes in the pre-stored charge state in the floating gate. Second, low defect state density. The silicon dioxide thin film grown by plasma-enhanced atomic layer deposition has an extremely low interface defect state density, which greatly reduces the probability of photogenerated carriers being trapped, eliminating trap-induced persistent photoconductivity. Third, rapid recombination in the bipolar channel. Using bipolar molybdenum ditelluride nanosheets as the channel layer, its high and balanced electron and hole mobility allows photogenerated carriers to recombine rapidly within hundreds of microseconds after light removal, completely eliminating the relaxation phenomenon caused by carrier lifetime differences. The combined effect of these mechanisms enables the device of this invention to achieve instantaneous dynamic gain of conductance under illumination, and to accurately and without delay return to the initial dark-state weight after the light is removed. This perfectly solves the instability and photoelectric crosstalk problems caused by continuous photoconductivity in existing two-dimensional floating-gate optoelectronic devices, providing a new hardware foundation for high-frequency real-time dynamic visual computing. This floating-gate optoelectronic memory device can function as a dark-state multi-bit non-volatile memory, an illumination-volatile dynamic composite modulator, and a real-time dynamic computing unit that executes high-frequency pulses.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A floating-gate opto-storage device without continuous photoconductivity, characterized in that, include: Substrate support layer; A floating gate layer disposed on the substrate support layer; A tunneling dielectric layer disposed on the floating gate layer; The tunneling dielectric layer is provided with mutually isolated channel areas and control areas; The channel region is provided with a two-dimensional material channel layer and a source and a drain that are respectively in contact with both ends of the two-dimensional material channel layer; the control region is provided with a control gate. The control gate is coplanar with the source, the drain, and the two-dimensional material channel layer. The control gate is laterally capacitively coupled to the two-dimensional material channel layer through the floating gate layer. The space above the two-dimensional material channel layer is exposed.

2. The floating-gate opto-storage device without continuous photoconductivity according to claim 1, characterized in that, The tunneling dielectric layer is a silicon dioxide thin film prepared by atomic layer deposition.

3. The floating gate photoelectric memory device without continuous photoconductivity according to claim 1, characterized in that, The tunneling dielectric layer is a multilayer composite dielectric layer, including at least two insulator layers of different materials. The at least two insulator layers of different materials have different band structures to form a stepped or asymmetric tunneling barrier between the floating gate layer and the two-dimensional material channel layer.

4. The floating-gate opto-storage device without continuous photoconductivity according to claim 1, characterized in that, The two-dimensional material channel layer is a bipolar molybdenum distellide nanosheet.

5. The floating-gate opto-storage device without continuous photoconductivity according to claim 1, characterized in that, The substrate support layer is a silicon wafer with thermally oxidized silicon dioxide on its surface, and the floating gate layer is a platinum thin film.

6. The floating-gate opto-storage device without continuous photoconductivity according to claim 1, characterized in that, The floating gate layer is made of a conductive material with an adjustable work function.

7. A method for fabricating a floating-gate opto-retention device without continuous photoconductivity, characterized in that, The method for fabricating a floating-gate photoconductorless photoconductor memory device as described in any one of claims 1-6 includes: Provide a substrate support layer; A floating gate layer is formed on the substrate support layer by a deposition process; A tunneling dielectric layer is formed on the floating gate layer by a deposition process; Two-dimensional material is transferred to the channel region on the tunneling dielectric layer by a transfer process to form a two-dimensional material channel layer. The source, drain, and control gate are simultaneously formed on the tunneling dielectric layer using a deposition process.

8. The method for fabricating a floating-gate opto-retention device without continuous photoconductivity according to claim 7, characterized in that, The process of forming a tunneling dielectric layer on the floating gate layer by deposition includes: A silicon dioxide thin film is deposited on the floating gate layer as the tunneling dielectric layer using a plasma-enhanced atomic layer deposition process.

9. The method for fabricating a floating-gate opto-retention device without continuous photoconductivity according to claim 7, characterized in that, The process of transferring two-dimensional material to the channel region on the tunneling dielectric layer to form a two-dimensional material channel layer includes: Few-layer two-dimensional material nanosheets were obtained by mechanical exfoliation; Using polydimethylsiloxane as a transfer medium, the few-layer two-dimensional material nanosheets are transferred from polyimide tape to the surface of the polydimethylsiloxane. The few-layer two-dimensional material nanosheets on the surface of the polydimethylsiloxane are aligned and transferred to the channel region of the tunneling dielectric layer using a precision alignment and transfer platform.

10. A neuromorphic computing unit, characterized in that, Including the floating gate photoconductorless photoconductor as described in any one of claims 1-6, used to realize real-time dynamic calculation in response to high-frequency optical pulse signals.

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