Isolation structure of backside illumination CIS and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-05-19
- Publication Date
- 2026-08-07
AI Technical Summary
[0005]随着像素101的尺寸缩小，小尺寸光电二极管的背部深沟槽刻蚀过程中不仅会对其感光区域造成晶格损伤，加大光电二极管的暗电流，也为小尺寸光刻和刻蚀工艺带来较大的挑战，同时由于单个小尺寸像素被刻蚀完的深沟槽包围，存在着剥落（peeling）风险
[0035]本发明通过在像素阵列中设置共享像素，背部深沟槽隔离结构仅设置在共享像素之间，在共享像素内部的各像素之间则采用背面注入隔离区，由于共享像素是由多个像素如2X2个像素组合而成，故共享像素的面积得到增加，所以，即使像素的尺寸缩小，共享像素依然能保持较大的尺寸，这样背部深沟槽隔离结构所环绕区域的尺寸能保持较大，故能减少背部深沟槽隔离结构的工艺难度，还能改善背部深沟槽隔离结构所环绕区域的尺寸过小所带来的剥落问题；而在共享像素内部的背面注入隔离区，能在实现隔离功能的同时，消除背部深沟槽隔离结构中的背部深沟槽工艺所带来的缺陷并减少由背部深沟槽缺陷所带来的暗电流，故最后能降低各像素的暗电流，所以本发明能降低工艺难度和改善小尺寸像素剥落问题，还能降低像素的暗电流。
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Figure CN122534992A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an isolation structure for a back-illuminated (BSI) CMOS image sensor (CIS). The invention also relates to a method for manufacturing the isolation structure of a back-illuminated CIS. Background Technology
[0002] The main working principle of CIS is that when light shines into a photodiode, it is converted into photoelectrons, and then, through some auxiliary circuit structures, these photoelectrons are converted into other types of electrical signals for output. In recent years, mobile phone image sensors have been developing towards high pixel counts and small sizes. Back-illuminated image sensors, due to their structural characteristics, allow for almost lossless reception of incident light and are gradually replacing front-illuminated image sensors as the mainstream trend.
[0003] To ensure image quality, back-illuminated image sensors use deep trench isolation (BDTI) between pixels to reduce crosstalk between optical and electrical signals. Most mainstream mobile phone image sensors support pixel binning, which combines four adjacent pixels into one large pixel based on lighting conditions, producing bright and clear images even in low-light environments.
[0004] like Figure 1 The diagram shown is a schematic of the rear view structure of the isolation structure of an existing back-illuminated CIS. Figure 1 The structure of a portion of the pixel area is shown in the image. It can be seen that the pixel area includes multiple pixels 101 arranged in two dimensions, and a back deep trench isolation 102 is formed on the periphery of each pixel 101.
[0005] As the size of pixel 101 shrinks, the deep trench etching process on the back of small-sized photodiodes not only causes lattice damage to their photosensitive areas and increases the dark current of the photodiodes, but also poses a significant challenge to small-sized photolithography and etching processes. At the same time, since each small-sized pixel is surrounded by the etched deep trench, there is a risk of peeling. Summary of the Invention
[0006] The technical problem to be solved by this invention is to provide an isolation structure for a back-illuminated CIS that can reduce manufacturing difficulty, improve the problem of small-sized pixel peeling, and reduce pixel dark current. To this end, this invention also provides a method for manufacturing the isolation structure of a back-illuminated CIS.
[0007] To solve the above-mentioned technical problems, the isolation structure of the back-illuminated CIS provided by the present invention includes a pixel region comprising multiple pixels, and each pixel is arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel array.
[0008] Adjacent xXy pixels form a shared pixel, where x represents the number of pixels in the shared pixel along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels in the shared pixel along the second direction and is an integer greater than or equal to 2.
[0009] A back-side deep trench isolation structure is used between the shared pixels; a back-side injection isolation region is used between each pixel within the shared pixels.
[0010] A front injection isolation area is formed on the front side of both the back deep groove isolation structure and the front side of the back injection isolation area.
[0011] Both the back-side implanted isolation region and the front-side implanted isolation region have a second conductivity type doped structure.
[0012] A further improvement is that a photodiode is formed in each of the pixels, the photodiode including a first doped region formed in the top region of the first epitaxial layer with a first conductivity type doping and a second doped region composed of the first epitaxial layer located at the bottom of the first doped region, the first epitaxial layer having intrinsic doping or second conductivity type doping, and the first doped region serving as a first conductivity type carrier collection region.
[0013] A further improvement is that the front-side implantation isolation region extends through the first doped region from the front.
[0014] A further improvement is that the back-side implanted isolation region extends from the back side of the second doped region through the second doped region and contacts the front-side implanted isolation region.
[0015] A further improvement is that the back deep trench isolation structure penetrates the second doped region from the back side of the second doped region and enters the first doped region, and the front implantation isolation region in the first doped region inserted by the back deep trench isolation structure is removed.
[0016] A further improvement is that in the shared pixels, both x and y are equal to 2.
[0017] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the isolation structure of a back-illuminated CIS, comprising: Step 1: Provide a first wafer with completed backside thinning. The pixel region of the first wafer includes multiple pixels. The pixels are arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel array. A front-side implantation isolation region doped with a second conductivity type is formed on the front side of each pixel. Shared pixels are set in the pixel array. The shared pixels are composed of x×y adjacent pixels, where x represents the number of pixels in the shared pixels along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels in the shared pixels along the second direction and is an integer greater than or equal to 2.
[0018] Step 2: Perform back-side patterning implantation to form a back-side implantation isolation region doped with a second conductivity type. The back-side implantation isolation region is located between each pixel within the shared pixel, and the front side of the back-side implantation isolation region is in contact with the front-side implantation isolation region.
[0019] Step 3: Perform back-side patterning etching to form back-side deep trenches, which are located between the shared pixels.
[0020] Step 4: Fill the back deep trench with a material layer to form a back deep trench isolation structure, wherein the front side of the back deep trench isolation structure is in contact with the corresponding front injection isolation area.
[0021] A further improvement is that, in step one, the first wafer includes a first semiconductor substrate, on which a first epitaxial layer having intrinsic doping or second conductivity type doping is formed.
[0022] Each pixel has a photodiode and a front-side injection isolation region located around the photodiode. The photodiode includes a first doped region formed in the top region of the first epitaxial layer with a first conductivity type doped and a second doped region composed of the first epitaxial layer located at the bottom of the first doped region. The first doped region serves as a carrier collection region with a first conductivity type.
[0023] A further improvement is that the front-side implantation isolation region extends through the first doped region from the front.
[0024] A further improvement is that the back-side implanted isolation region extends from the back side of the second doped region through the second doped region and contacts the front-side implanted isolation region.
[0025] A further improvement is that, in step three, the back deep trench extends from the back side of the second doped region through the second doped region and into the first doped region, and the front implantation isolation region in the first doped region inserted by the back deep trench is removed.
[0026] A further improvement is that in the shared pixels, both x and y are equal to 2.
[0027] A further improvement is that, in step one, the first semiconductor substrate is removed after the back side is thinned.
[0028] Prior to the back-side thinning, the process includes a step of bonding the front side of the first wafer to a second wafer, the second wafer serving as a carrier.
[0029] A further improvement is that, in step two, before the backside patterning injection, a step of forming a first mask layer on the backside of the first wafer is included.
[0030] A further improvement is that the backside patterning injection includes: The first photolithography process defines the formation area of the back-side injection isolation region.
[0031] The back-side implantation isolation region is formed by performing a second type of conductivity back-side implantation.
[0032] A further improvement is that, in step three, the steps for forming the deep back groove include: A second photolithography process is performed to define the formation area of the deep trench on the back.
[0033] The first mask layer and the first epitaxial layer are etched sequentially to form a back deep trench.
[0034] A further improvement is that, in step four, the material layer filling the deep trench isolation structure on the back includes an oxide sidewall layer, a metal passivation layer, an anti-reflective layer, and an oxide filling layer, and an air gap also exists in the center of the deep trench on the back.
[0035] This invention sets shared pixels in a pixel array, with the back trench isolation structure only placed between the shared pixels. A back-injected isolation region is used between the pixels within each shared pixel. Since the shared pixel is composed of multiple pixels, such as 2x2 pixels, the area of the shared pixel is increased. Therefore, even if the pixel size is reduced, the shared pixel can still maintain a large size. This allows the area surrounded by the back trench isolation structure to remain large, reducing the manufacturing difficulty of the back trench isolation structure and improving the peeling problem caused by an excessively small surrounding area. The back-injected isolation region within the shared pixel achieves isolation while eliminating defects caused by the back trench process and reducing dark current caused by these defects. Therefore, the dark current of each pixel is reduced. Thus, this invention reduces manufacturing difficulty, improves the peeling problem of small pixels, and reduces pixel dark current. Attached Figure Description
[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the rear view structure of the isolation structure of an existing back-illuminated CIS; Figure 2 This is a schematic diagram of the back-side view of the isolation structure of the back-illuminated CIS according to an embodiment of the present invention; Figure 3 yes Figure 2 A cross-sectional view of a shared pixel. Figures 4-18 This is a schematic diagram of the device structure in each step of the manufacturing method of the isolation structure of the back-illuminated CIS according to an embodiment of the present invention. Detailed Implementation
[0037] like Figure 2 The diagram shown is a schematic representation of the rear view of the isolation structure of the back-illuminated CIS according to an embodiment of the present invention. Figure 2 The diagram shows a schematic representation of the back-side structure of a portion of the pixel area. Figure 3 yes Figure 2 A cross-sectional structural diagram of a shared pixel 202 is shown in the embodiment of the present invention. In the isolation structure of the back-illuminated CIS, the pixel area includes multiple pixels 201, and each pixel 201 is arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel 201 array.
[0038] Adjacent xXy pixels 201 form a shared pixel 202, where x represents the number of pixels 201 in the shared pixel 202 along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels 201 in the shared pixel 202 along the second direction and is an integer greater than or equal to 2.
[0039] exist Figure 2 In the example, in the shared pixel 202, both x and y are equal to 2. In other embodiments, x and y can also take other values as needed.
[0040] A back deep trench isolation structure 203 is used between the shared pixels 202; a back injection isolation region 204 is used between each pixel 201 inside the shared pixels 202.
[0041] like Figure 3 As shown, a front injection isolation region 205 is formed on the front side of the back deep trench isolation structure 203 and on the front side of the back injection isolation region 204. Figure 3 In the middle, the front of the back deep groove isolation structure 203 is located in Figure 3 As shown below.
[0042] Both the back-side implanted isolation region 204 and the front-side implanted isolation region 205 have a second conductivity type doped structure.
[0043] In this embodiment of the invention, a photodiode is formed in each pixel 201. The photodiode includes a first doped region 207 formed in the top region of the first epitaxial layer 206, doped with a first conductivity type, and a second doped region composed of the first epitaxial layer 206 located at the bottom of the first doped region 207. The first epitaxial layer 206 has intrinsic doping or second conductivity type doping, and the first doped region 207 serves as a carrier collection region of the first conductivity type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In this case, the first doped region 207 is the N-type region of the photodiode, and the second doped region is the P-type region of the photodiode. In other embodiments, the first conductivity type can also be P-type, and the second conductivity type can be N-type.
[0044] The front-side implantation isolation region 205 extends through the first doped region 207 from the front.
[0045] The back-side implanted isolation region 204 extends from the back side of the second doped region through the second doped region and contacts the front-side implanted isolation region 205. Figure 3 In this embodiment, the contact position between the back-side implanted isolation region 204 and the front-side implanted isolation region 205 is level with the contact position between the second doped region and the first doped region 207. In other embodiments, the contact position between the back-side implanted isolation region 204 and the front-side implanted isolation region 205 may also be higher or lower than the contact position between the second doped region and the first doped region 207.
[0046] The back deep trench isolation structure 203 penetrates the second doped region from the back side of the second doped region and enters the first doped region 207, and the front implantation isolation region 205 in the first doped region 207 that is inserted by the back deep trench isolation structure 203 is removed.
[0047] In this embodiment of the invention, shared pixels 202 are set in the pixel array 201, and the back deep trench isolation structure 203 is only set between the shared pixels 202. A back-injected isolation region 204 is used between each pixel 201 within the shared pixels 202. Since the shared pixels 202 are composed of multiple pixels 201, such as 2x2 pixels 201, the area of the shared pixels 202 is increased. Therefore, even if the size of the pixels 201 is reduced, the shared pixels 202 can still maintain a large size. This allows the area surrounded by the back deep trench isolation structure 203 to remain large, thus reducing the back... The manufacturing difficulty of the deep trench isolation structure 203 can also improve the peeling problem caused by the small size of the area surrounded by the deep trench isolation structure 203. The back injection isolation area 204 inside the shared pixel 202 can achieve the isolation function, eliminate the defects caused by the back deep trench 406 process in the back deep trench isolation structure 203 and reduce the dark current caused by the defects of the back deep trench 406. Therefore, the dark current of each pixel 201 can be reduced. Thus, the embodiment of the present invention can reduce the manufacturing difficulty and improve the peeling problem of small-sized pixels 201, and also reduce the dark current of pixels 201.
[0048] The manufacturing method of the isolation structure of the back-illuminated CIS according to the embodiments of the present invention includes: Step 1, such as Figure 7 As shown, a first wafer 301 with completed backside thinning is provided.
[0049] Simultaneously combined Figure 2 As shown, the pixel region of the first wafer 301 includes a plurality of pixels 201. Each pixel 201 is arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel 201 array. A front implantation isolation region 205 doped with a second conductivity type is formed on the front side of each pixel 201. Shared pixels 202 are set in the pixel 201 array. The shared pixels 202 are composed of x×y adjacent pixels 201, where x represents the number of pixels 201 in the shared pixels 202 along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels 201 in the shared pixels 202 along the second direction and is an integer greater than or equal to 2.
[0050] In the method of this embodiment of the invention, in the shared pixel 202, both x and y are equal to 2. In other embodiments, x and y can also be set to other values as needed, such as 1x2, 2x3, 3x3, etc.
[0051] In the method of the embodiments of the present invention, such as Figure 4As shown, the first wafer 301 includes a first semiconductor substrate 302, on which a first epitaxial layer 206 having intrinsic doping or second conductivity type doping is formed. In some embodiments, the first semiconductor substrate 302 includes a silicon substrate.
[0052] Each pixel 201 has a photodiode and a front injection isolation region 205 located on the periphery of the photodiode. The photodiode includes a first doped region 207 formed in the top region of the first epitaxial layer 206 with a first conductivity type doped and a second doped region composed of the first epitaxial layer 206 located at the bottom of the first doped region 207. The first doped region 207 serves as a carrier collection region with a first conductivity type.
[0053] The front-side implantation isolation region 205 extends through the first doped region 207 from the front.
[0054] Figure 4 In this configuration, the pixel region is located in region 302a, and a peripheral region 302b is also provided around the pixel region. A peripheral circuit 303 is formed in the peripheral region 302b. The peripheral circuit 303 includes multiple semiconductor devices, each including a polysilicon gate 304 and source / drain regions 305 self-aligned on both sides of the polysilicon gate 304. It also includes a multilayer interlayer film 308, contact holes 306, and a front-side metal layer 307.
[0055] Prior to the back-side thinning, it also includes: such as Figure 6 The diagram illustrates the step of bonding the front side of the first wafer 301 to the second wafer 401, where the second wafer 401 serves as a carrier. The bonding step includes: like Figure 5 As shown, a bonding material layer 309 is formed on the front side of the first wafer 301. For example, the bonding material layer 309 is an oxide layer with a thickness of 1.5µm to 2.5µm.
[0056] like Figure 6 As shown, a bonding material layer 402 is formed on the bonding surface of the second wafer 401. For example, the bonding material layer 402 is an oxide layer with a thickness of 1.5µm to 2.5µm.
[0057] The bonding between the first wafer 301 and the second wafer 401 is achieved by bonding the bonding material layers 309 and 402.
[0058] like Figure 7 As shown, the first semiconductor substrate 302 is removed after the back side thinning. The back side thinning process includes grinding, wet etching, chemical mechanical polishing, wet etching, etc.
[0059] Step 2: Perform back-side patterning implantation to form a back-side implantation isolation region 204 doped with a second conductivity type. The back-side implantation isolation region 204 is located between each of the pixels 201 inside the shared pixel 202, and the front side of the back-side implantation isolation region 204 is in contact with the front-side implantation isolation region 205.
[0060] like Figure 8 As shown, prior to the back-side patterning implantation, a step of forming a first mask layer 403 on the back side of the first wafer 301 is included. The growth methods for the first mask layer 403 include, but are not limited to, cryogenic furnace tubes, chemical vapor deposition, and wet growth. The thickness of the first mask layer 403 is approximately 50 Å to 100 Å.
[0061] The backside graphicization injection includes: like Figure 9 As shown, the first photolithography process forms the pattern of photoresist 404, defining the formation area of the back-side injection isolation region 204. Figure 9 This is a top view of the rear side; Figure 10 Then it shows Figure 9 The corresponding cross-sectional view.
[0062] The back-side implantation of the second conductivity type is performed to form the back-side implantation isolation region 204.
[0063] After that, as Figure 11 As shown, the photoresist 404 is removed. Figure 12 Showing Figure 11 The corresponding cross-sectional view.
[0064] In the method of this embodiment of the invention, the back-side implanted isolation region 204 extends from the back side of the second doped region through the second doped region and contacts the front-side implanted isolation region 205.
[0065] In the method of this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In this case, the first doped region 207 is the N-type region of the photodiode, and the second doped region is the P-type region of the photodiode. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.
[0066] Step 3: Perform back-side patterning etching to form a back-side deep trench 406, which is located between each of the shared pixels 202.
[0067] In the method of this embodiment of the invention, the step of forming the back deep groove 406 includes: like Figure 13 As shown, the second photolithography process forms the pattern of photoresist 405, defining the formation area of the back deep trench 406. Figure 13This is a top view of the rear side; Figure 14 Then it shows Figure 13 The corresponding cross-sectional view.
[0068] The first mask layer 403 and the first epitaxial layer 206 are etched sequentially to form the back deep trench 406.
[0069] After that, as Figure 15 As shown, the photoresist 405 is removed. Figure 16 Showing Figure 15 The corresponding cross-sectional view.
[0070] In the method of this embodiment of the invention, the back deep trench 406 penetrates the second doped region from the back side of the second doped region and enters the first doped region 207, and the front implantation isolation region 205 in the first doped region 207 that is inserted by the back deep trench 406 is removed.
[0071] Step 4, as follows Figure 18 As shown, a material layer 407 is filled in the back deep trench 406 to form a back deep trench isolation structure 203, the front side of the back deep trench isolation structure 203 being in contact with the corresponding front injection isolation area 205. Figure 17 This is a top view of the back side.
[0072] In the method of this embodiment of the invention, the material layer 407 filled by the back deep trench isolation structure 203 includes an oxide sidewall layer, a metal passivation layer, an anti-reflection layer and an oxide filling layer, and an air gap 408 also exists in the center of the back deep trench 406.
[0073] This invention, through back trench etching and filling isolation around 2x2 shared pixels, and P-type ion implantation isolation between 2x2 shared pixels, not only improves the dark current during single photodiode imaging, but also reduces the challenge of small-size processes and improves peeling issues due to the equivalent process of increasing pixel size. At the same time, it provides good isolation effect during pixel binning.
[0074] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. An isolation structure for a back-illuminated CIS, characterized in that: The pixel region includes multiple pixels, and the pixels are arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel array; Adjacent xXy pixels form a shared pixel, where x represents the number of pixels in the shared pixel along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels in the shared pixel along the second direction and is an integer greater than or equal to 2. A back-side deep trench isolation structure is used between the shared pixels; a back-side injection isolation region is used between each pixel within the shared pixels; A front injection isolation area is formed on the front side of the back deep trench isolation structure and on the front side of the back injection isolation area; Both the back-side implanted isolation region and the front-side implanted isolation region have a second conductivity type doped structure.
2. The isolation structure of the back-illuminated CIS as described in claim 1, characterized in that: Each of the pixels forms a photodiode, the photodiode including a first doped region formed in the top region of the first epitaxial layer with a first conductivity type doping and a second doped region composed of the first epitaxial layer located at the bottom of the first doped region, the first epitaxial layer having intrinsic doping or second conductivity type doping, and the first doped region serving as a first conductivity type carrier collection region.
3. The isolation structure of the back-illuminated CIS as described in claim 2, characterized in that: The front-side implantation isolation region extends through the first doped region from the front.
4. The isolation structure of the back-illuminated CIS as described in claim 3, characterized in that: The back-side implanted isolation region extends from the back of the second doped region through the second doped region and contacts the front-side implanted isolation region.
5. The isolation structure of the back-illuminated CIS as described in claim 3, characterized in that: The back deep trench isolation structure penetrates the second doped region from the back side of the second doped region and enters the first doped region, and the front implantation isolation region in the first doped region that is inserted by the back deep trench isolation structure is removed.
6. The isolation structure of the back-illuminated CIS as described in claim 1, characterized in that: In the shared pixels, both x and y are equal to 2.
7. A method for manufacturing an isolation structure for a back-illuminated CIS, characterized in that, include: Step 1: Provide a first wafer with completed backside thinning. The pixel region of the first wafer includes multiple pixels. The pixels are arranged in two dimensions along a first direction and a second direction that are perpendicular to each other to form a pixel array. A front-side implantation isolation region doped with a second conductivity type is formed on the front side of each pixel. Shared pixels are set in the pixel array. The shared pixels are composed of x×y adjacent pixels, where x represents the number of pixels in the shared pixels along the first direction and is an integer greater than or equal to 1, and y represents the number of pixels in the shared pixels along the second direction and is an integer greater than or equal to 2. Step 2: Perform back-side patterning implantation to form a back-side implantation isolation region doped with a second conductivity type. The back-side implantation isolation region is located between each pixel within the shared pixel, and the front side of the back-side implantation isolation region is in contact with the front-side implantation isolation region. Step 3: Perform back-side patterning etching to form back-side deep trenches, which are located between each of the shared pixels; Step 4: Fill the back deep trench with a material layer to form a back deep trench isolation structure, wherein the front side of the back deep trench isolation structure is in contact with the corresponding front injection isolation area.
8. The method for manufacturing the isolation structure of the back-illuminated CIS as described in claim 7, characterized in that: In step one, the first wafer includes a first semiconductor substrate, on which a first epitaxial layer having intrinsic doping or second conductivity type doping is formed; Each pixel has a photodiode and a front-side injection isolation region located around the photodiode. The photodiode includes a first doped region formed in the top region of the first epitaxial layer with a first conductivity type doped and a second doped region composed of the first epitaxial layer located at the bottom of the first doped region. The first doped region serves as a carrier collection region with a first conductivity type.
9. The isolation structure of the back-illuminated CIS as described in claim 8, characterized in that: The front-side implantation isolation region extends through the first doped region from the front.
10. The isolation structure of the back-illuminated CIS as described in claim 9, characterized in that: The back-side implanted isolation region extends from the back of the second doped region through the second doped region and contacts the front-side implanted isolation region.
11. The isolation structure of the back-illuminated CIS as described in claim 9, characterized in that: In step three, the back deep trench penetrates the second doped region from the back side of the second doped region and enters the first doped region, and the front implantation isolation region in the first doped region inserted by the back deep trench is removed.
12. The isolation structure of the back-illuminated CIS as described in claim 7, characterized in that: In the shared pixels, both x and y are equal to 2.
13. The isolation structure of the back-illuminated CIS as described in claim 8, characterized in that: In step one, the first semiconductor substrate is removed after the back side is thinned; Prior to the back-side thinning, the process includes a step of bonding the front side of the first wafer to a second wafer, the second wafer serving as a carrier.
14. The isolation structure of the back-illuminated CIS as described in claim 13, characterized in that: In step two, prior to the backside patterning implantation, a first mask layer is formed on the backside of the first wafer.
15. The isolation structure of the back-illuminated CIS as described in claim 13, characterized in that: The backside graphicization injection includes: The first photolithography process defines the formation area of the back-side injection isolation region; The back-side implantation isolation region is formed by performing a second type of conductivity back-side implantation.
16. The isolation structure of the back-illuminated CIS as described in claim 13, characterized in that: Step three, the steps for forming the deep back groove, include: A second photolithography process is performed to define the formation area of the back deep trench; The first mask layer and the first epitaxial layer are etched sequentially to form a back deep trench.
17. The isolation structure of the back-illuminated CIS as described in claim 16, characterized in that: In step four, the material layer filling the deep trench isolation structure on the back includes an oxide sidewall layer, a metal passivation layer, an anti-reflective layer, and an oxide filling layer, and an air gap also exists in the center of the deep trench on the back.