A method for improving phosphorus epitaxial crystallization rate

Abstract

The application provides a method for improving phosphorus crystal growth rate, comprising the following steps: after forming a tunneling oxide layer with a thickness of 1-2 nm and an amorphous silicon layer with a thickness of 100-150 nm on the back surface of a silicon substrate in sequence: S1, performing first heat treatment on the silicon substrate in a phosphorus-free atmosphere, so that the amorphous silicon layer is crystallized to form a polysilicon layer; S2, performing second heat treatment in a phosphorus-containing atmosphere, so that phosphorus atoms diffuse into the polysilicon layer for doping. The application adopts a step-by-step process of high-temperature phosphorus-free crystallization and low-temperature phosphorus diffusion, completely decouples crystallization and doping, and completely solves the problem of phosphorus diffusion through the thin POLY layer. The crystallization rate reaches 95-97%, the phosphorus concentration of the tunneling oxide layer is ≤5*10 16 cm ‑3 , which is much lower than the passivation failure threshold. The process is realized based on the existing RTP and diffusion furnace, the modification cost is low, the crystallization and phosphorus diffusion parameters can be independently regulated, it is suitable for different POLY thicknesses and battery specifications, the process window is wide, and the universality is strong.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic technology, specifically relating to a method for preparing solar cells, and more particularly to a method for improving phosphorus diffusivity. Background Technology

[0002] The core of a tunnel oxide passivated contact (TOPCon) solar cell lies in its back-side structure, typically composed of an ultrathin tunnel oxide layer (SiO2) and a layer of doped polycrystalline silicon (POLY-Si). This structure utilizes the chemical passivation effect of the tunnel oxide layer on the dangling bonds of the saturated silicon substrate surface, while simultaneously leveraging the Fermi level difference between the doped polycrystalline silicon layer and the silicon substrate to create a field passivation effect. This enables selective transport of one type of charge carrier, thereby significantly reducing the recombination current in the metal contact region and improving the cell's open-circuit voltage and conversion efficiency.

[0003] In the fabrication process of TOPCon cells, the doped polycrystalline silicon layer on the back side is typically obtained through two mainstream technical routes: one is to directly deposit an in-situ doped amorphous silicon layer using plasma-enhanced chemical vapor deposition (PECVD), followed by high-temperature annealing to achieve crystallization and impurity activation; the other is to first deposit an intrinsic amorphous silicon layer using low-pressure chemical vapor deposition (LPCVD), and then simultaneously achieve amorphous silicon crystallization and phosphorus doping through subsequent high-temperature phosphorus diffusion. This process, which simultaneously completes amorphous silicon crystallization and phosphorus atom diffusion doping at high temperatures, suffers from a core drawback stemming from the contradiction between high temperature and a thin POLY layer: high temperature is a necessary condition for ensuring sufficient crystallization of amorphous silicon, but the diffusion coefficient of phosphorus in polycrystalline silicon at high temperatures is 5-8 times that at low temperatures (600℃), and a POLY layer with a thickness of 100-150 nm cannot form an effective diffusion barrier; the tunneling oxide layer is extremely sensitive to phosphorus doping, and when the phosphorus concentration in the oxide layer exceeds 1×10⁻⁶, the diffusion coefficient becomes significantly higher. 17 cm -3 At that time, the passivation effect will decrease by more than 40%, and the concentration threshold is easily exceeded in the synchronous process.

[0004] To address this problem, existing technologies have proposed several improvements. For example, by depositing two amorphous silicon layers of different densities, the difference in phosphorus diffusion rates can be utilized to reduce the number of phosphorus atoms penetrating the tunneling oxide layer. Temperature control during phosphorus diffusion can be achieved by extending the heating, isothermal, and cooling processes to optimize phosphorus doping distribution. However, these solutions essentially still seek a balance between crystallization and doping within the same thermal process, representing optimizations and improvements to the coupled process. Their process parameters (such as temperature and time) still need to consider both crystallization degree and diffusion depth, failing to fundamentally resolve the inherent contradiction between the two. Therefore, their effectiveness in suppressing tunneling is limited, and the process window is relatively narrow, requiring extremely high control precision, which is detrimental to yield improvement in large-scale production.

[0005] Therefore, how to break the coupling relationship between crystallization and doping in the existing technology, fundamentally avoid the diffusion of phosphorus atoms through the tunneling oxide layer, and at the same time ensure the high crystallization of the polycrystalline silicon layer has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a method for improving the phosphorus diffusion crystallization rate to solve the problem caused by the coupling between the crystallization process of the amorphous silicon layer and the diffusion doping process of phosphorus atoms in the prior art, fundamentally avoiding the diffusion penetration of phosphorus atoms through the tunneling oxide layer, while ensuring the high crystallization of the polycrystalline silicon layer.

[0007] A method for improving phosphorus diffusion crystallization rate includes the following steps: After sequentially forming a tunneling oxide layer with a thickness of 1-2 nm and an amorphous silicon layer with a thickness of 100-150 nm on the back side of a silicon substrate: S1, under a phosphorus-free atmosphere, the silicon substrate is subjected to a first heat treatment at a temperature of 900-920℃ for a holding time of 40-80 s to crystallize the amorphous silicon layer and form a polycrystalline silicon layer; S2, under a phosphorus-containing atmosphere, the silicon substrate treated in step S1 is subjected to a second heat treatment at a temperature of 700-720℃ for a holding time of 150-180 s to diffuse phosphorus atoms into the polycrystalline silicon layer for doping.

[0008] This solution decouples the crystallization process of the amorphous silicon layer from the diffusion doping process of phosphorus atoms through a step-by-step process. By optimizing independent parameters, it simultaneously meets the dual requirements of high crystallinity and no diffusion penetration.

[0009] Furthermore, step S1 is performed in a rapid heat treatment furnace (RTP); step S2 is performed in a diffusion furnace.

[0010] Furthermore, after the first heat treatment, the crystallinity of the polycrystalline silicon layer is not less than 95%; after the second heat treatment, the peak concentration of phosphorus atoms in the tunneling oxide layer near the silicon substrate is not higher than 5 × 10⁻⁶. 16 atoms / cm 3 Furthermore, the average phosphorus concentration in the tunneling oxide layer is no higher than 5 × 10⁻⁶. 16 atoms / cm 3 .

[0011] Further, step S1 includes: a heating stage: under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is raised from the initial temperature to the first heat treatment temperature at a heating rate of 50-80℃ / s; wherein the nitrogen flow rate is 20-30L / min; a holding stage: under a continuous phosphorus-free source atmosphere, the first heat treatment temperature is maintained for more than 40s to crystallize the polycrystalline silicon layer; a cooling stage: under a nitrogen atmosphere, the temperature is lowered from the first heat treatment temperature to below 650℃ at a cooling rate of 40-60℃ / s.

[0012] Furthermore, step S2 includes: a heating stage: under a mixed atmosphere of nitrogen and oxygen, the temperature is raised from below the second heat treatment temperature to the second heat treatment temperature at a heating rate of 10-20℃ / s; wherein the volume fraction of oxygen in the mixed atmosphere is 5-10%, and the total flow rate of nitrogen and oxygen is 15-25L / min; a holding stage: maintaining the second heat treatment temperature, introducing a phosphorus source, and performing heat-holding doping; the flow rate of the phosphorus source is controlled at 50-80 sccm; and a cooling stage: natural cooling under a nitrogen atmosphere at a cooling rate of 5-10℃ / s.

[0013] Furthermore, after the first and second heat treatments, step S3 is included, in which the temperature is raised to 800-820℃ and held for 30-40s in a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source to repair lattice defects; wherein the flow rate of nitrogen is 25-30L / min; and then it is naturally cooled to room temperature to obtain the phosphorus-expanded solar cell.

[0014] Furthermore, the first heat treatment temperature is 910℃, and the holding time is 50s.

[0015] Furthermore, the second heat treatment temperature is 710°C, and the holding time is 160 seconds.

[0016] This solution also provides a TOPCon battery, which is prepared using the above-mentioned method for improving phosphorus crystallization rate. This solution also provides a solar cell module, which includes at least one TOPCon cell.

[0017] Compared with existing technologies, the method for improving phosphorus crystallization rate described in this invention has the following advantages: (1) This invention decouples the coupled crystallization and doping processes in traditional processes into two independent steps. Through the first step of high-temperature phosphorus-free crystallization, the crystallization rate of the polycrystalline silicon layer can be increased to over 95% without considering doping limitations, ensuring excellent conductivity and field passivation effects. Through the second step of low-temperature phosphorus-based doping, phosphorus diffusion can be precisely controlled in the fully crystallized polycrystalline silicon layer, controlling the peak phosphorus atom concentration on the side of the tunneling oxide layer near the silicon substrate to 5 × 10⁻⁶.16 atoms / cm 3 Below that, far below 1×10 17 cm -3 The passivation performance degradation threshold is precisely controlled, eliminating the risk of passivation failure caused by phosphorus atoms penetrating the oxide layer. The synergistic effect of these two technologies significantly improves the passivation quality (iVoc) on the back of the battery, ensuring breakthroughs in the final open-circuit voltage and conversion efficiency.

[0018] (2) By decoupling crystallization and doping, the process parameters of the two steps, such as temperature, time, and atmosphere, can be optimized independently, greatly relaxing the control precision requirements for a single process. This reduces the process sensitivity during production and effectively improves the stability and yield of large-scale production.

[0019] (3) The method provided by the present invention is based on the mature rapid heat treatment equipment (RTP) and tubular diffusion furnace in the industry. It does not require the introduction of expensive special equipment, is highly compatible with the existing TOPCon production line, has low technical upgrade and transformation costs, and is easy to promote quickly. Attached Figure Description

[0020] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a high-resolution transmission electron microscope image of the sample from Example 1 of the present invention; Figure 2 This is a high-resolution transmission electron microscope image of sample 1 in the comparative example of this invention; Figure 3 This is a high-resolution transmission electron microscope image of sample 2 in the comparative example of this invention. Detailed Implementation

[0021] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides a method to improve phosphorus diffusion crystallization rate, which solves the problem in the prior art where the parameter contradiction caused by the coupling between amorphous silicon layer crystallization and phosphorus diffusion makes it impossible to simultaneously achieve high crystallization rate and low diffusion penetration risk.

[0023] A method for improving phosphorus diffraction rate includes the following steps: A tunneling oxide layer with a thickness of 1-2 nm and an amorphous silicon layer with a thickness of 100-150 nm are sequentially formed on the back side of a silicon substrate, specifically including: The substrate is an N-type single-crystal silicon wafer; an ultrathin tunneling oxide layer with a thickness of 1-2 nm is prepared on the substrate surface by thermal oxidation; an amorphous silicon POLY layer with a thickness of 100-150 nm is deposited on the surface of the tunneling oxide layer by LP process; the silicon wafer after LP is transferred to a tooling fixture and sent into a rapid thermal processing furnace (RTP) for crystallization treatment.

[0024] S1: Under a phosphorus-free atmosphere, the above-mentioned silicon substrate undergoes a first heat treatment to crystallize the amorphous silicon layer and form a polycrystalline silicon layer, specifically including: Heating stage: Under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is raised from the initial temperature to the first heat treatment temperature of 900-920℃ at a heating rate of 50-80℃ / s; wherein the nitrogen flow rate is 20-30L / min. During the heat preservation stage, the first heat treatment temperature is maintained for 40-60 seconds under a continuous phosphorus-free atmosphere to ensure that the POLY layer is crystallized throughout its thickness without any local amorphous areas. Cooling stage: Under a nitrogen atmosphere, the temperature is cooled from the first heat treatment temperature to 600-650℃ at a cooling rate of 40-60℃ / s to obtain a crystallized polycrystalline silicon POLY layer; the crystallization rate of the polycrystalline silicon layer is not less than 95%.

[0025] S2: Under a phosphorus-containing source atmosphere, the silicon substrate treated in step S1 undergoes a second heat treatment to allow phosphorus atoms to diffuse into the polycrystalline silicon layer for doping. Specifically, this includes: Heating stage: Under a mixed atmosphere of nitrogen and oxygen, the temperature is raised from below 650℃ to the second heat treatment temperature of 700-720℃ at a heating rate of 10-20℃ / s; wherein the volume fraction of oxygen in the mixed atmosphere is 5-10%, and the total flow rate of nitrogen and oxygen is 15-25L / min. Heat preservation stage: Maintain the second heat treatment temperature for 150-180s, introduce phosphorus source, and carry out heat preservation doping; control the phosphorus source flow rate at 50-80sccm; Cooling stage: Natural cooling under a nitrogen atmosphere at a cooling rate of 5-10℃ / s; obtaining phosphorus-doped N. + Type POLY layer; the peak concentration of phosphorus atoms on the side of the tunneling oxide layer closest to the silicon substrate is no higher than 5 × 10⁻⁶. 16 atoms / cm 3 .

[0026] S3. Subsequent activation: Under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is raised to 800-820℃ and held for 30-40 seconds to repair lattice defects; the nitrogen flow rate is 25-30 L / min; then it is naturally cooled to room temperature; thus obtaining the phosphorus-expanded solar cell.

[0027] The diffusion furnace used in the following examples has a furnace tube length of 4363 mm and a diameter of 560 mm.

[0028] Example 1: A method for improving phosphorus dilatation crystallization rate includes the following steps: Step 1: Prepare an N-type TOPCon solar cell wafer with a tunneling oxide layer thickness of 1.5nm and an amorphous silicon layer thickness of 120nm. Step 2: Transfer the silicon wafer to a fixture and place it in a rapid thermal processing (RTP) furnace. Under a phosphorus-free atmosphere, perform a first heat treatment on the silicon substrate to crystallize the amorphous silicon layer, forming a polycrystalline silicon layer. Specifically, this includes: Heating stage: Under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is raised from the initial temperature to the first heat treatment temperature of 910℃ at a heating rate of 60℃ / s; wherein the nitrogen flow rate is 25L / min. During the heat preservation stage, the first heat treatment temperature is maintained for 50 seconds under a continuous phosphorus-free atmosphere to ensure that the POLY layer is crystallized throughout its thickness without any local amorphous areas. Cooling stage: Under a nitrogen atmosphere, the temperature is cooled from the first heat treatment temperature to 620℃ at a cooling rate of 50℃ / s to obtain a crystallized polycrystalline silicon POLY layer. Step 3: Transfer the cooled silicon wafer to a diffusion furnace. Under a phosphorus-containing atmosphere, perform a second heat treatment on the silicon substrate after step S1 to diffuse phosphorus atoms into the polycrystalline silicon layer for doping. Specifically, this includes: Heating stage: Under a mixed atmosphere of nitrogen and oxygen, the temperature is raised from below 620℃ to the second heat treatment temperature of 710℃ at a heating rate of 15℃ / s; wherein the volume fraction of oxygen in the mixed atmosphere is 8%, and the total flow rate of nitrogen and oxygen is 20L / min. Heat preservation stage: Maintain the second heat treatment temperature for 160s, introduce phosphorus source POCl3, and carry out heat preservation doping; the phosphorus source flow rate is controlled at 60sccm; Cooling stage: Natural cooling under nitrogen atmosphere at a cooling rate of 8℃ / s; phosphorus-doped POLY layer obtained; Step 4: Subsequent activation: Under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is raised to 810℃ and held for 35 seconds to repair lattice defects; the nitrogen flow rate is 28L / min; then it is naturally cooled to room temperature; the silicon wafer is then removed. Step 5: The phosphorus-dielectric TOPCon cell silicon wafers are subjected to phosphorus-dielectric glass cleaning, double-sided coating, screen printing, and sintering to produce TOPCon cells for subsequent performance testing.

[0029] Example 2: Optimization of Low-Temperature Phosphorus Diffusion Temperature Except for the second heat treatment temperature in step 3, which is set to 690℃, 700℃, 720℃ and 750℃ respectively, the other process steps are exactly the same as in Example 1.

[0030] Example 3: Time Optimization Except for the heat preservation stage in step 3, which is set to 130s, 150s, 180s, and 220s respectively, the other process steps are exactly the same as in Example 1.

[0031] Example 4: Universality Verification Except for the amorphous silicon layer thicknesses of 100nm, 130nm, and 150nm in step 1, the other process steps are exactly the same as in Example 1.

[0032] Comparative Example 1: Control Group The traditional one-step method for producing N-type TOPCon cells with a tunnel oxide layer of 1.5nm and an amorphous silicon layer thickness of 120nm involves: depositing intrinsic amorphous silicon using LPCVD, followed by a one-step high-temperature (880℃) phosphorus diffusion process in a tubular diffusion furnace for 60 minutes, simultaneously completing crystallization and doping.

[0033] Comparative Example 2: In-furnace preheating and gradient diffusion process This comparative example refers to the method disclosed in Chinese patent application CN113808927A, which completes the crystallization and phosphorus doping of the amorphous silicon layer in a single step in a tube diffusion furnace. The specific process steps are as follows: (1) Silicon wafer loading and heating preparation: N-type TOPCon cell silicon wafers with a tunnel oxide layer thickness of 1.5 nm and an amorphous silicon layer thickness of 120 nm are loaded into the quartz boat of the tube diffusion furnace, the furnace door is closed, the furnace is evacuated to a pressure of 100 mbar, high-purity nitrogen (purity ≥ 99.999%, flow rate 10 L / min) is introduced, and the furnace temperature is raised to 880 °C at a heating rate of 10 °C / min.

[0034] (2) Phosphorus-free preheating stage: After the furnace temperature stabilizes at 880℃, maintain this temperature and continue to introduce nitrogen gas (flow rate 10L / min) to maintain a phosphorus-free atmosphere and preheat at a constant temperature for 10 minutes. This stage aims to initially crystallize the amorphous silicon layer and uniformize the furnace temperature.

[0035] (3) After the first phosphorus diffusion (low-temperature deposition) preheating is completed, the furnace temperature is reduced to 820℃ at a cooling rate of 5℃ / min. After the temperature stabilizes, a POCl3 phosphorus source carried by nitrogen (flow rate 60 sccm, source bottle temperature 25℃) and oxygen (flow rate 400 sccm) are introduced, while maintaining the nitrogen flow rate at 8L / min and the furnace pressure at 200mbar. The first phosphorus diffusion is carried out under these conditions and held at the temperature for 20 minutes.

[0036] (4) Second phosphorus diffusion (high temperature propulsion): After the first diffusion is completed, the furnace temperature is increased to 860°C at a rate of 8°C / min. During the heating process, phosphorus source and oxygen are continuously supplied. After the temperature stabilizes, the second phosphorus diffusion is continued at this temperature for 30 minutes.

[0037] (5) Cooling and unloading: Stop the flow of POCl3 and oxygen, continue to flow nitrogen (flow rate 15L / min), and reduce the temperature inside the furnace to below 700℃ at a cooling rate of 5℃ / min. Then, allow it to cool naturally to room temperature and remove the silicon wafer.

[0038] (6) Subsequent processing: The silicon wafers prepared in Comparative Example 2 were subjected to the same process as those in Examples 1-4, including dephosphosilicate glass cleaning, double-sided coating, screen printing and sintering, to make TOPCon cells for subsequent performance testing.

[0039] Comparative Example 3: Low-temperature phosphorus expansion only Except for step 2, the remaining process steps are exactly the same as in Example 1.

[0040] Comparative Example 4: First, low-temperature phosphorus expansion, then high-temperature crystallization Except for reversing the order of steps 2 and 3, the remaining process steps are exactly the same as in Example 1.

[0041] Test method: 1. Crystallization rate test method Instrument: Raman spectrometer Laser wavelength: 532nm; Laser power: 5mW (to avoid damaging the POLY layer); Test range: wavenumber 400-600cm -1 ; Calculation method: Xc=I 520 / (I 520 +0.8×I 480 )×100% Among them, I 520 I represents the integral intensity of the characteristic peak of polycrystalline silicon. 480 The integral intensity of the characteristic peak of amorphous silicon is given, with a correction factor of 0.8.

[0042] 2. Test method for phosphorus concentration in tunnel oxide layer Test instrument: SIMS Ion source: O2 + ; Sputtering rate: 0.5 nm / s; Test depth: 20nm from the surface of the POLY layer to the interior of the silicon substrate (covering the full thickness of the tunneling oxide layer). Concentration calibration: Phosphorus-doped standard samples (concentration range 1×10⁻⁶) were used. 16 -1×10 18 atoms / cm 3 Calibrate.

[0043] 3. Battery electrical performance testing Testing instrument: Solar cell IV tester Test conditions: AM1.5, 25℃, 1000W / m 2 Standard light intensity; Test parameters: Open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), conversion efficiency (Eff); Number of tests: 30 pieces were tested for each sample, and the average value was taken as the final result.

[0044] Results analysis: 1. The crystallization rate, phosphorus concentration in the tunneling oxide layer, and electrical performance of the TOPCon cell samples obtained in Example 2 were tested, and the results are shown in Table 1 below. Table 1 shows that when the temperature is in the range of 700-720℃, the crystallization rate of the POLY layer can be kept stable above 96%, and the phosphorus concentration in the tunneling oxide layer can be controlled within a safe threshold. Among these, the sample obtained at a phosphorus diffusion temperature of 710℃ exhibits the best overall performance.

[0045] Table 1. Test results of samples with optimized low-temperature phosphorus diffusion temperature Specifically, when the low-temperature phosphorus diffusion temperature is set to 690℃ (below 700℃), the crystallization rate of the POLY layer reaches 96.1%, and the phosphorus concentration in the tunneling oxide layer is 3.2 × 10⁻⁶. 16 atoms / cm 3 Within the safety threshold, the sample's electrical properties were slightly insufficient; when the low-temperature phosphorus diffusion temperature was set to 750℃ (above 720℃), the crystallinity of the POLY layer reached 96.5%, but the phosphorus concentration in the tunneling oxide layer was 6.3 × 10⁻⁶. 16 atoms / cm 3The sample exceeded the safety threshold, and its electrical performance also declined, with the open-circuit voltage decreasing from 705 mV at 720℃ to 678 mV, and the conversion efficiency decreasing from 25.2% to 24.5%. This may be because when the phosphorus diffusion temperature is below 700℃, phosphorus doping is insufficient; when the phosphorus diffusion temperature is above 720℃, the phosphorus atom diffusion rate is too fast, partially breaking through the tunnel oxide layer and causing a decrease in passivation performance.

[0046] In summary, the preferred low-temperature phosphorus diffusion temperature for this scheme is determined to be in the range of 700-720℃, with 710℃ being the optimal temperature.

[0047] 2. The crystallinity, phosphorus concentration in the tunneling oxide layer, and electrical performance of the TOPCon solar cell samples obtained in Example 3 were tested, and the results are shown in Table 2 below. Table 2 shows that when the low-temperature phosphorus diffusion was maintained at 710℃, and the holding time was varied, phosphorus atoms diffused uniformly within the POLY layer when the holding time was between 150-180s, with no risk of diffusion penetration. The optimal holding time was 160s, at which point the phosphorus doping concentration and lattice integrity reached a balance, resulting in the best overall performance of the sample.

[0048] Table 2. Test results of samples with optimized low-temperature phosphorus diffusion time Specifically, with a low-temperature phosphorus diffusion temperature of 710℃ and a holding time of less than 150s (set to 130s), the crystallization rate of the POLY layer reached 96.2%, and the phosphorus concentration in the tunneling oxide layer was 3.5×10⁻⁶. 16 atoms / cm 3 Within the safety threshold, the electrical properties of the sample were slightly insufficient; when the low-temperature phosphorus diffusion holding time was set to 220s instead of 180s, the crystallization rate of the POLY layer reached 96.3%, and the phosphorus concentration in the tunneling oxide layer was 5.8×10⁻⁶. 16 atoms / cm 3 While still within the safety threshold, the electrical performance of the sample decreased, with the open-circuit voltage dropping from 703mV at 180s to 683mV, and the conversion efficiency decreasing from 25.2% to 24.6%. This may be because a holding time shorter than 150s leads to insufficient doping and low carrier collection efficiency; while a holding time longer than 180s tends to accumulate phosphorus atoms at the bottom of the POLY layer, approaching the safety threshold for tunneling oxide, resulting in a decrease in passivation effect.

[0049] In summary, it can be determined that when the low-temperature phosphorus expansion temperature is 710℃, the preferred temperature holding time for low-temperature phosphorus expansion is within the range of 150-180s, with 160s being the optimal holding time.

[0050] 3. The crystallinity, phosphorus concentration in the tunneling oxide layer, and yield of the TOPCon solar cell samples obtained in Example 4 were tested, and the results are shown in Table 3 below. Table 3 shows that when the low-temperature phosphorus diffusion was maintained at 710℃ and the holding time was controlled at 160s, the crystallinity of the samples remained above 95% when the amorphous silicon layer thickness was in the range of 100-150nm, and the peak phosphorus concentration in the tunneling oxide layer was below 5×10⁻⁶. 16 atoms / cm 3 Comparing the performance of samples with different thicknesses, it can be seen that the crystallinity increases slightly with the increase of POLY layer thickness, but the difference in cell conversion efficiency is small, proving that the process window is wide and can meet the mass production requirements of TOPCon cells of different specifications.

[0051] Table 3. Test Results of the Universality Verification of this Solution 4. The crystallinity, phosphorus concentration in the tunneling oxide layer, and electrical performance of the battery samples obtained in Example 1 and Comparative Examples 1-4 were tested. The results are shown in Table 4 below. A comparison of the data in the table shows that Example 1 exhibits the best overall performance: crystallinity of 96.2% and peak phosphorus concentration in the tunneling oxide layer of 4.8 × 10⁻⁶. 16 atoms / cm 3 It has an open-circuit voltage of 708mV, a conversion efficiency of 25.3%, and a yield rate of 95.8%.

[0052] Table 4. Performance Comparison Table of This Scheme and Comparative Samples Specifically, in Comparative Example 1, the sample was prepared using a traditional one-step method. Due to the coupling of crystallization and doping, the crystallization rate was only 84.7%, and phosphorus atoms extensively tunneled through the oxide layer, resulting in significantly lower battery performance and yield than in this invention. Comparative Example 2 uses an incompletely decoupled process of preheating followed by gradient phosphorus diffusion, which still carries the risk of over-penetration and results in limited performance improvement. Comparative Example 3 only used low-temperature phosphorus diffusion without a high-temperature crystallization process. The amorphous silicon crystallization of the sample was insufficient, the carrier mobility was extremely low, and the battery efficiency was the worst. Comparative Example 4 first used low-temperature phosphorus diffusion followed by high-temperature crystallization. The high-temperature stage caused the already doped phosphorus atoms to diffuse secondary, breaking through the tunnel oxide layer and impairing the passivation performance, thus failing to achieve the technical effect of the present invention.

[0053] In summary, through this performance comparison test of the TOPCon battery phosphorus diffusion stepwise process and the traditional coupling process, it can be seen that the stepwise process of this invention, which first performs phosphorus-free high-temperature crystallization at 900-920℃ and then low-temperature phosphorus diffusion at 700-720℃, can stabilize the crystallization rate of the POLY layer at 95.3%-97.1%, and the peak phosphorus concentration of the tunneling oxide layer is ≤4.9×10⁻⁶.16 atoms / cm 3 The efficiency is far below the passivation decay threshold, completely eliminating the risk of phosphorus burn-through, while traditional processes suffer from low crystallinity and phosphorus concentrations exceeding safety thresholds. The optimal parameter group for the step-by-step process achieves a conversion efficiency of 25.3%, an improvement of 2.2 percentage points compared to the traditional one-step method. All embodiments have a conversion efficiency ≥24.5%, and the mass production yield is ≥93.8%, with the optimal group reaching 95.8%, significantly better than the comparative examples. This process is highly adaptable to POLY layers with a thickness of 100-150nm, has a wide process window, and can be implemented on existing equipment with low modification costs. It combines high performance with mass production feasibility, showing significant advantages over existing technologies and can be widely applied to the large-scale mass production of TOPCon batteries.

[0054] 5. Tunneling Oxide Layer Morphology Test The tunneling oxide morphology of the TOPCon battery samples prepared in Comparative Examples 1, 2 and Example 1 was observed using high-resolution transmission electron microscopy (HRTEM). The results are as follows: Figure 1-3 As shown: Figure 1 These are the observation results of the sample from Example 1, from... Figure 1 It can be seen that the tunneling oxide layer of the sample has a uniform thickness, maintaining the design value of 1.5nm, and there are no defects such as grain boundary cracks or pores between the layers; the interface between the oxide layer and the silicon substrate and polycrystalline silicon layer is flat and continuous, without impurities formed by the aggregation of phosphorus atoms, the lattice arrangement is regular, there is no obvious lattice distortion at the interface, and the passivation structure has good integrity.

[0055] Figure 2 The observation results for the sample in Comparative Example 1 were obtained from... Figure 2 It can be seen that the thickness of the tunneling oxide layer in the sample is uneven, with some areas as thin as 0.8 nm, and there is obvious damage to the oxide layer caused by phosphorus atom penetration. The interface between the oxide layer and the silicon substrate is rough, with a large number of lattice defects and dislocations. Furthermore, an amorphous phase formed by phosphorus doping was detected at the interface, and the passivation structure was severely damaged.

[0056] Figure 3 The observation results for Comparative Example 2 were obtained from... Figure 3 It can be seen that the thickness of the tunneling oxide layer of the sample is generally uniform, but there are microcracks in some areas. The flatness of the interface with the silicon substrate is generally poor. There are a small amount of phosphorus atoms aggregated at the interface to form a small impurity phase. There is slight lattice distortion. The passivation structure integrity is improved compared with Comparative Example 1, but it is still inferior to Example 1.

[0057] In summary, this method employs a step-by-step fabrication approach, decoupling the crystallization process of the amorphous silicon layer from the diffusion doping process of phosphorus atoms. While ensuring a high degree of crystallinity in the polycrystalline silicon layer, it fundamentally prevents phosphorus atoms from diffusing and tunneling through the oxide layer, thus improving the passivation quality (iVoc) on the back of the battery. This provides a guarantee for breakthroughs in the final battery's open-circuit voltage and conversion efficiency. This step-by-step fabrication method reduces process sensitivity during production and effectively improves the stability and yield of large-scale production.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving the phosphorus dilatation crystallization rate, characterized in that, Includes the following steps: After sequentially forming a tunneling oxide layer with a thickness of 1-2 nm and an amorphous silicon layer with a thickness of 100-150 nm on the back side of a silicon substrate: S1. Under a phosphorus-free atmosphere, the silicon substrate is subjected to a first heat treatment at a temperature of 900-920℃ and a holding time of 40s-80s to crystallize the amorphous silicon layer and form a polycrystalline silicon layer. S2. Under a phosphorus-containing atmosphere, the silicon substrate after step S1 is subjected to a second heat treatment at a temperature of 700-720℃ and a holding time of 150-180s, so that phosphorus atoms diffuse into the polycrystalline silicon layer for doping.

2. The method for improving phosphorus dilatation rate according to claim 1, characterized in that: Step S1 is performed in a rapid heat treatment furnace (RTP); step S2 is performed in a diffusion furnace.

3. The method for improving phosphorus dilatation rate according to claim 1, characterized in that: After the first heat treatment, the crystallinity of the polycrystalline silicon layer is not less than 95%; After the second heat treatment, the peak concentration of phosphorus atoms in the tunnel oxide layer near the silicon substrate is no higher than 5 × 10⁻⁶. 16 atoms / cm 3 Furthermore, the average phosphorus concentration in the tunneling oxide layer is no higher than 5 × 10⁻⁶. 16 atoms / cm 3 .

4. The method for improving phosphorus dilatation rate according to claim 1, characterized in that, Step S1 includes: Heating stage: Under a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source, the temperature is increased from the initial temperature to the first heat treatment temperature at a heating rate of 50-80℃ / s; wherein the nitrogen flow rate is 20-30L / min. During the heat preservation stage, the polycrystalline silicon layer is crystallized by maintaining the first heat treatment temperature for more than 40 seconds under a continuous phosphorus-free atmosphere. Cooling stage: Under a nitrogen atmosphere, the temperature is reduced from the first heat treatment temperature to below 650℃ at a cooling rate of 40-60℃ / s.

5. The method for improving phosphorus dilatation rate according to claim 1, characterized in that, Step S2 includes: Heating stage: Under a mixed atmosphere of nitrogen and oxygen, the temperature is raised from below 650℃ to the second heat treatment temperature at a heating rate of 10-20℃ / s; wherein the volume fraction of oxygen in the mixed atmosphere is 5-10%, and the total flow rate of nitrogen and oxygen is 15-25L / min. Heat preservation stage: Maintain the second heat treatment temperature, introduce phosphorus source, and carry out heat preservation doping; control the phosphorus source flow rate at 50-80 sccm; Cooling stage: Natural cooling under nitrogen atmosphere, with a cooling rate of 5-10℃ / s.

6. The method for improving phosphorus dilatation rate according to claim 1, characterized in that, After the first and second heat treatments, step S3 is included, in which the temperature is raised to 800-820℃ and held for 30-40s in a nitrogen atmosphere with a volume fraction of not less than 99.999% phosphorus-free source to repair lattice defects; wherein the flow rate of nitrogen is 25-30L / min; and then the silicon wafer is naturally cooled to room temperature and removed.

7. The method for improving phosphorus dilatation rate according to claim 1, characterized in that, The first heat treatment temperature is 910℃, and the holding time is 50s.

8. The method for improving phosphorus dilatation rate according to claim 1, characterized in that, The second heat treatment temperature is 710s, and the holding time is 160s.

9. A TOPCon battery, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 8.

10. A solar cell module, characterized in that, It includes at least one TOPCon solar cell as described in claim 9.

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