A method for preparing a silicon carbide-based monolithic integrated ultraviolet photoelectric sensing chip

Abstract

The application discloses a preparation method of a silicon carbide-based monolithic integrated ultraviolet photoelectric sensing chip and relates to the field of wide-bandgap semiconductor ultraviolet photoelectric sensing chip manufacturing technologies. The application provides a wafer comprising an n-type 4H-SiC substrate and an n-type 4H-SiC epitaxial layer, a composite hard mask composed of an oxygen-containing SiO X layer and a Ni layer is formed on the front surface of the wafer, a main window penetrating the Ni layer and the oxygen-containing SiO X layer is formed through a first photoetching pattern, an oxygen-containing reaction shoulder window penetrating the Ni layer and remaining the oxygen-containing SiO X layer is formed at the edge of the main window through a second photoetching pattern, and SF6 / O2 / Ar pulse bias etching is performed after the second photoresist is removed, so that an isolated mesa surrounding the active pixel area and the dark reference pixel area is formed. The oxygen-containing SiO X layer remaining below the oxygen-containing reaction shoulder window is activated and locally consumed under the action of plasma bombardment and fluorine-based active particles, so that an oxygen-containing reaction interface is formed near the edge of the mesa, thereby adjusting the carbon residue removal near the bottom corner of the mesa and the reaction balance of the sidewall.

Description

Technical Field

[0001] This invention relates to the field of wide bandgap semiconductor ultraviolet photoelectric sensor chip manufacturing technology, specifically a method for preparing a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip. Background Technology

[0002] Silicon carbide (SiC) materials possess wide bandgap, temperature resistance, radiation resistance, corrosion resistance, and intrinsic visible light suppression capabilities, making them suitable for fabricating ultraviolet (UV) optoelectronic sensor chips. 4H-SiC materials, due to their large bandgap, can form a stable photoelectric conversion basis for UV detection, flame monitoring, arc identification, UV communication reception, and monitoring of strong UV radiation environments. In SiC-based UV optoelectronic sensor chips, active pixels, dark reference pixels, isolation mesa, photosensitive windows, anti-reflection textures, passivation layers, Schottky metal electrodes, interconnect metals, dark reference shielding layers, and backside ohmic contacts typically need to be formed on the same wafer. Because SiC materials have strong chemical stability and high bond energy, conventional wet etching is insufficient to form stable mesa and microtexture structures; therefore, isolation mesa and anti-reflection textures usually require photolithography and dry plasma etching.

[0003] Existing dry etching processes for SiC typically employ fluorine-containing plasma systems such as SF6 / O2, CF4 / O2, or SF6 / Ar. While these systems can achieve SiC etching, they still present challenges in the fabrication of ultraviolet optoelectronic sensor chips. Microgrooves are prone to form at the bottom corners of the isolation mesa. During mesa etching, issues such as ion reflection, local electric field distortion, and uneven migration of reaction products exist near the hard mask edges and mesa sidewalls, easily leading to localized etching enhancement at the bottom corners of the mesa. This localized etching enhancement forms groove-like depressions, making the electric field distribution at the mesa edges unstable and increasing the risk of edge leakage. Carbon enrichment residues are prone to occur during fluorine-containing etching. SF6 plasma reacts with Si in SiC to generate volatile silicon fluorides, and the removal of carbon-related residues depends on oxygen participation in the reaction. When O2 participation is insufficient, carbon enrichment residues easily appear at the bottom and sidewalls of the etching process; when the overall O2 flow rate increases, the reaction state throughout the cavity changes, potentially leading to a decrease in etching rate, sidewall reaction imbalance, or surface oxide layer accumulation. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides the following technical solution: a method for fabricating a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip, comprising the following steps: S1, providing a wafer, the wafer comprising an n-type 4H-SiC substrate and an n-type 4H-SiC epitaxial layer located on the front side of the n-type 4H-SiC substrate; S2, dividing the front side of the wafer into an active pixel region, a dark reference pixel region, a photosensitive texture region located within the active pixel region, and a pad region; S3, forming a composite hard mask on the surface of the n-type 4H-SiC epitaxial layer, the composite hard mask comprising oxygen-containing SiO2.X Layer and located in the oxygen-containing SiO X S4. A main window is formed in the composite hard mask by the first photolithography pattern, the main window penetrating the Ni layer and the oxygen-containing SiO layer. X S5. A second photolithographic pattern is formed using a second photoresist, and an oxygen-containing reaction shoulder is formed at the edge of the main window. The oxygen-containing reaction shoulder penetrates the Ni layer and retains the oxygen-containing SiO2. X S6. Remove the second photoresist and clean and dry; S7. Perform pulse bias etching on the n-type 4H-SiC epitaxial layer exposed by the main window in SF6 / O2 / Ar plasma to form isolation mesa located at the boundary between the active pixel region and the dark reference pixel region, and on the periphery of the active pixel region and the dark reference pixel region; S8. Remove the composite hard mask; S9. Form a textured composite hard mask in the photosensitive texture area, and form a micro-honeycomb anti-reflection texture through a third photolithography pattern and shallow etching; S10. Remove the textured composite hard mask; S11. Form a passivation layer on the front side of the wafer; S12. Form a passivation layer on the front side of the wafer. A Ni back metal layer is formed on the back side of the round surface and annealed to form an ohmic contact between the Ni back metal layer and the n-type 4H-SiC substrate; S13, an active pixel window and a pad window are formed in the passivation layer using a fourth photolithography pattern; the active pixel window exposes the n-type 4H-SiC epitaxial layer surface corresponding to the photosensitive texture area, and the pad window corresponds to the subsequent bus bar or external connection area; S14, a semi-transparent Schottky metal mesh electrode, a bus bar, and a dark reference shielding layer are formed using a fifth photolithography pattern to obtain a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip.

[0005] Furthermore, the wafer is a 100mm double-sided polished wafer, the thickness of the n-type 4H-SiC substrate is 330μm to 370μm, and the carrier concentration of the n-type 4H-SiC substrate is 1×10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 The thickness of the n-type 4H-SiC epitaxial layer is 4.5 μm to 5.5 μm, and the carrier concentration of the n-type 4H-SiC epitaxial layer is 1 × 10⁻⁶. 15 cm -3 Up to 8×10 15 cm -3 .

[0006] Furthermore, the oxygen-containing SiO X The thickness of the layer is 140 nm to 180 nm, and the oxygen-containing SiOX The O / Si atomic ratio of the layer is 1.85 to 2.00, the thickness of the Ni layer is 70 nm to 90 nm, and the oxygen-containing SiO₂ layer... X The Ni layer is formed by plasma-enhanced chemical vapor deposition, and the Ni layer is formed by magnetron sputtering.

[0007] Furthermore, the oxygen-containing reaction shoulder window is an array of slits arranged along the edge of the main window. Each slit in the array has a width of 0.30 μm to 0.40 μm, a slit pitch of 0.90 μm to 1.10 μm, and a distance from the center line of the slit to the edge of the main window of 0.55 μm to 0.65 μm. The oxygen-containing SiO₂ retained below the oxygen-containing reaction shoulder window... X The layer forms an oxygen-containing reaction interface under the action of plasma bombardment and fluorine-based active particles.

[0008] Furthermore, the layout boundary of the main window is set with crystal orientation compensation amount according to the 4° off-axis 4H-SiC crystal orientation, wherein the linewidth compensation amount of the [11-20] boundary is 0.15μm to 0.30μm, the linewidth compensation amount of the [1-100] boundary is 0.00μm to 0.10μm, and the corner radius of the main window is 1.5μm to 2.5μm.

[0009] Furthermore, the pulsed bias etching process uses an SF6 flow rate of 20 sccm to 26 sccm, an O2 flow rate of 1.6 sccm to 2.4 sccm, an Ar flow rate of 6 sccm to 10 sccm, a pressure of 0.9 Pa to 1.1 Pa, an ICP power of 800 W to 950 W, a bias power of 150 W to 190 W, a pulse frequency of 0.5 kHz to 2.0 kHz, a duty cycle of 40% to 60%, a mesa temperature of 120 °C to 150 °C, an etching depth of 1.00 μm to 1.30 μm, and a sidewall angle of 80 °C to 84 °C.

[0010] Furthermore, the textured composite hard mask comprises oxygen-containing SiO₂ with a thickness of 100 nm to 130 nm. X The micro-cell anti-reflective texture consists of a textured layer and a Ni textured layer with a thickness of 50 nm to 70 nm. The micro-cell anti-reflective texture is a hexagonal concave texture with a period of 1.15 μm to 1.25 μm, a cell rib width of 0.50 μm to 0.60 μm, and a texture depth of 0.18 μm to 0.24 μm.

[0011] Furthermore, the passivation layer is a SiO2 layer with a thickness of 160nm to 200nm, the Ni back metal layer has a thickness of 90nm to 110nm, and the annealing is carried out in a nitrogen atmosphere at a temperature of 900℃ to 980℃ for a time of 60s to 120s.

[0012] Furthermore, the semi-transparent Schottky metal mesh electrode comprises a continuous Ni Schottky base layer and a Ni mesh-reinforced conductive layer located on the surface of the continuous Ni Schottky base layer. The thickness of the continuous Ni Schottky base layer is 2 nm to 5 nm, the thickness of the Ni mesh-reinforced conductive layer is 10 nm to 15 nm, the mesh width of the Ni mesh-reinforced conductive layer is 2 μm to 4 μm, and the mesh period is 25 μm to 40 μm. The busbar is a Ti / Au stack, wherein the thickness of Ti in the Ti / Au stack is 15 nm to 25 nm, and the thickness of Au is 180 nm to 220 nm. The dark reference shielding layer is an Al layer with a thickness of 120 nm to 180 nm.

[0013] Compared with the prior art, the present invention has the following advantages: (1) Traditional SiC etching mainly relies on changing the O2 flow rate in the cavity to adjust the reaction environment. This method acts on the entire wafer surface and cannot perform differentiated control on the bottom corner and center of the mesa. The present invention retains oxygen-containing SiO near the edge of the main window through an oxygen-containing reaction shoulder window. X (1) Layer, so that an oxygen-containing reaction interface defined by the photolithography pattern is formed at the edge of the platform, thereby achieving local reaction regulation; (2) Oxygen-containing SiO below the oxygen-containing reaction shoulder window XThe layer undergoes surface activation and local consumption under plasma bombardment and fluorine-based active particles, resulting in an oxygen-related reactant participation region near the mesa edge. This region helps to regulate the removal process of carbon-related residues and reduce the tendency of the microgrooves at the bottom corner of the mesa to continue to develop. Therefore, the groove-like depressions caused by local etching enhancement at the bottom corner of the mesa are weakened, and the degree of electric field change at the edge of the mesa is reduced, which helps to reduce the risk of edge leakage between the active pixel region and the dark reference pixel region; (3) In the main window layout, the present invention sets different linewidth compensation amounts for the [11-20] direction boundary and the [1-100] direction boundary, so that the etching boundary difference of the 4° offset 4H-SiC wafer in different crystal directions is pre-compensated, thereby improving the structural consistency between the active pixel region and the dark reference pixel region; (4) The present invention uses pulsed bias etching to make the ion bombardment periodic Periodic input avoids continuous bias etching forming a continuous enhanced bombardment at the bottom corner of the mesa, which helps to reduce bottom corner trenches, sidewall damage and edge defects; (5) Before forming the front continuous Ni Schottky base layer, Ni grid reinforced conductive layer, Ti / Au bus bar and Al dark reference shielding layer, the present invention first completes the back Ni ohmic contact and annealing at 900°C to 980°C, avoiding high temperature annealing from causing metal diffusion, interface reaction, morphology deterioration and Schottky barrier drift to the front fine metal; (6) The semi-transparent Schottky metal mesh electrode of the present invention includes a continuous Ni Schottky base layer and a Ni grid reinforced conductive layer. The continuous Ni Schottky base layer forms a continuous Schottky contact interface in the active pixel area, and the Ni grid reinforced conductive layer reduces the lateral resistance and retains the ultraviolet incident opening, thereby taking into account both the uniformity of light response and the charge collection efficiency. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall process flow of the method of the present invention. Detailed Implementation

[0015] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0016] This invention provides a method for fabricating a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip, which involves designing a Ni layer penetrating the edge of the main window while retaining oxygen-containing SiO. X The oxygen-containing reaction shoulder window of the layer allows oxygen-containing SiO below the oxygen-containing reaction shoulder window to... X The layer undergoes surface activation and localized consumption under plasma bombardment and the action of fluorine-based reactive particles, thereby forming an oxygen-containing reaction interface (referring to oxygen-containing SiO₂) near the edge of the mesa. XThe layer, after being exposed to SF6 / O2 / Ar plasma at the oxygen-containing reaction shoulder window, forms an interface region (or region involving oxygen-related reactants) that can participate in the regulation of mesa edge reactions through ion bombardment, the action of fluorine-based active particles, and local oxygen-related reactions. This local reaction interface is used to regulate the removal of carbon residues and the sidewall reaction balance near the bottom corner of the mesa. The difference in etching evolution of different crystal orientation boundaries of 4H-SiC with 4° offset is offset by crystal orientation compensation patterning, the risk of bottom corner micro-trenches caused by continuous ion bombardment is reduced by pulsed bias etching, micro-honeycomb anti-reflection texture is formed by independent shallow etching, and the back Ni ohmic contact and annealing steps are placed before the formation of fine metal on the front side to avoid damage to the front Schottky metal, busbars, and dark reference shielding layer by annealing at 900°C to 980°C.

[0017] Wafer Preparation: A 100mm double-sided polished n-type 4H-SiC wafer is provided. The wafer comprises an n-type 4H-SiC substrate and an n-type 4H-SiC epitaxial layer on the front side of the substrate. The n-type 4H-SiC substrate has a thickness of 350μm and a carrier concentration of 5×10⁻⁶. 18 cm -3 The n-type 4H-SiC epitaxial layer has a thickness of 5.0 μm and a carrier concentration of 5 × 10⁻⁶. 15 cm -3 An n-type 4H-SiC substrate serves as the basis for forming the back-side ohmic contact. An n-type 4H-SiC epitaxial layer forms the basis for the active pixel region, dark reference pixel region, isolation mesa, and micro-cell anti-reflection texture. The active pixel region, dark reference pixel region, photosensitive texture region, and pad region are defined on the front side of the wafer. The active pixel region receives ultraviolet light and generates photocurrent; the dark reference pixel region generates dark current reference signals; the photosensitive texture region is located within the active pixel region; and the pad region is used for subsequent external electrical connections.

[0018] Wafer Cleaning and Dehydration: The wafers were sequentially cleaned with acetone, isopropanol, rinsed with deionized water, acidic cleaned, rinsed again with deionized water, and dried with nitrogen. After cleaning, dehydration baking was performed at 140°C for 10 minutes. Dehydration baking reduces adsorbed water on the surface of the n-type 4H-SiC epitaxial layer, improving the subsequent oxygen-containing SiO₂ production. X Uniformity of layer deposition and adhesion of photoresist.

[0019] Formation of composite hard mask: Oxygen-containing SiO2 was deposited on the surface of an n-type 4H-SiC epitaxial layer using plasma-enhanced chemical vapor deposition. X Layer. Oxygen-containing SiO X The layer thickness was 160 nm, and the O / Si atomic ratio was 1.92. Subsequently, magnetron sputtering was used to deposit the layer onto oxygen-containing SiO₂. X A Ni layer is deposited on the surface of the layer. The Ni layer is 80 nm thick. Oxygen-containing SiO₂ XThe Ni layer and the Ni layer together constitute a composite hard mask. The Ni layer serves as the upper hard mask to resist fluorine-based plasma etching, and the oxygen-containing SiO₂ layer... X The layer serves as the lower hard mask and also as the source of the oxygen-containing reaction interface at the bottom of the subsequent oxygen-containing reaction shoulder window.

[0020] The first photolithographic pattern forms the main window: Positive photoresist is spin-coated onto the Ni layer surface, followed by soft baking, exposure, development, and post-baking to form the first photolithographic pattern. The first photolithographic pattern corresponds to the main window area of ​​the isolation mesa. The main window is used to define the main etching area of ​​the n-type 4H-SiC epitaxial layer. The Ni layer and oxygen-containing SiO are then etched sequentially through the first photolithographic pattern. X The layer allows the main window to penetrate the Ni layer and the oxygen-containing SiO layer. X The n-type 4H-SiC epitaxial layer is exposed. The main window layout boundary is compensated for crystal orientation according to a 4° offset 4H-SiC crystal orientation. Specifically, the linewidth compensation for the [11-20] direction boundary is set to 0.22 μm, the linewidth compensation for the [1-100] direction boundary is set to 0.05 μm, and the corner radius of the main window is set to 2.0 μm. The purpose of crystal orientation compensation is to preemptively offset the differences in sidewall evolution of different crystal orientation boundaries during SF6 / O2 / Ar plasma etching, so that the etched isolation mesa boundary is closer to the designed shape.

[0021] The second photolithographic pattern forms an oxygen-containing reaction shoulder window: After removing the first photoresist, a second photoresist is recoated onto the Ni layer surface, and a second photolithographic pattern is formed through exposure and development. The second photolithographic pattern is located near the edge of the main window and is used to form the oxygen-containing reaction shoulder window. The Ni layer is etched using the second photolithographic pattern to form the oxygen-containing reaction shoulder window at the edge of the main window. The oxygen-containing reaction shoulder window penetrates the Ni layer but does not penetrate the oxygen-containing SiO2 layer. X Layer. Therefore, oxygen-containing SiO2 is retained at the bottom of the oxygen-containing reaction shoulder window. X The oxygen-containing reactive shoulder is an array of slits arranged along the edge of the main window. Each slit in the array has a width of 0.35 μm, a slit pitch of 1.00 μm, and a distance of 0.60 μm from the centerline of the slit to the edge of the main window. After the oxygen-containing reactive shoulder is formed, the second photoresist is removed, and the wafer is cleaned and dried. This process re-exposes the n-type 4H-SiC epitaxial layer in the main window area and allows the oxygen-containing SiO2 retained at the bottom of the oxygen-containing reactive shoulder to be exposed. X The layer is exposed to participate in subsequent plasma reactions. It should be noted that the oxygen-containing reaction shoulder is not a typical etching window; its bottom retains oxygen-containing SiO₂. X Therefore, the n-type 4H-SiC epitaxial layer will not be directly etched at this location. The function of the oxygen-containing reaction shoulder window is to allow the oxygen-containing SiO2 layer to pass through. XThe layer is exposed to the plasma environment near the edge of the platform and undergoes surface activation and local consumption under the action of plasma bombardment and fluorine-based active particles, thereby forming an oxygen-containing reaction interface or a region where oxygen-related reactants participate.

[0022] Pulsed bias etching to form isolation mesa: The wafer is fed into an ICP etching apparatus, and pulsed bias etching is performed on the n-type 4H-SiC epitaxial layer exposed in the main window in an SF6 / O2 / Ar plasma. The etching parameters are as follows: SF6 flow rate 24 sccm; O2 flow rate 2.0 sccm; Ar flow rate 8 sccm; pressure 1.0 Pa; ICP power 900 W; bias power 170 W; pulse frequency 1.0 kHz; duty cycle 55%; mesa temperature 140 °C; etching time 175 s. After etching, isolation mesa are formed at the boundary between the active pixel region and the dark reference pixel region, and on the outer periphery of the pixels. The etching depth of the isolation mesa is 1.20 μm, and the sidewall angle is 82°. During this etching process, the n-type 4H-SiC epitaxial layer exposed in the main window region is etched; the oxygen-containing reaction shoulder region retains oxygen-containing SiO2. X The isolation mesa layer, instead of serving as the main etching window for SiC, acts as a source of oxygen-containing reaction interfaces near the mesa edge. Since the n-type 4H-SiC epitaxial layer thickness is 5.0 μm and the isolation mesa etching depth is 1.20 μm, the isolation mesa does not belong to the electrically isolated trenches that completely penetrate the epitaxial layer. Its function is to reduce lateral leakage current, edge electric field coupling, and surface crosstalk between the active pixel region and the dark reference pixel region through the mesa morphology.

[0023] Removal of the composite hard mask: After etching the isolation mesa, remove the Ni layer and oxygen-containing SiO. X The wafer is then subjected to a layering process followed by deionized water rinsing and drying. After removing the composite hard mask, the formed isolation mesa structure remains on the front side of the wafer. At this point, the active pixel region, the dark reference pixel region, and the isolation mesa edge structure have been formed.

[0024] Forming a textured composite hard mask: A textured composite hard mask is formed on the front side of the wafer. The textured composite hard mask includes oxygen-containing SiO₂. X Textured layers and Ni textured layers. Oxygen-containing SiO₂ X The texture layer thickness is 120 nm, and the Ni texture layer thickness is 60 nm. The textured composite hard mask is used to form micro-cell anti-reflection textures, and its function differs from that of the composite hard mask used for isolating mesa etching. The composite hard mask is used for the main window and oxygen-containing reaction shoulder window; the textured composite hard mask is used for shallow microstructure etching.

[0025] The third lithography pattern forms the micro-honeycomb anti-reflection texture: Photoresist is coated on the surface of the textured composite hard mask, and a third lithography pattern is formed through exposure and development. The third lithography pattern defines the micro-honeycomb anti-reflection texture within the photosensitive texture area. The textured composite hard mask is patterned using the third lithography pattern, and then the n-type 4H-SiC epitaxial layer is shallowly etched to form the micro-honeycomb anti-reflection texture. The micro-honeycomb anti-reflection texture is a hexagonal concave texture. The period of the hexagonal concave texture is 1.20 μm, the width of the honeycomb ribs is 0.55 μm, and the texture depth is 0.22 μm. The micro-honeycomb anti-reflection texture is used to change the equivalent refractive index transition path when ultraviolet light enters the SiC surface from air, reducing interface reflection on the flat SiC surface. At the same time, limiting the texture depth to 0.22 μm can avoid the introduction of excessive surface states by excessively deep surface structures, thereby reducing the risk of dark current degradation.

[0026] Removal of the composite hard mask: After the micro-cell anti-reflection texture etching is completed, the Ni texture layer and oxygen-containing SiO are removed. X The texture layer is then applied, and the front side of the wafer is cleaned and dried. At this point, isolation mesa and micro-honeycomb anti-reflection textures have been formed on the front side of the wafer.

[0027] Passivation layer formation: A SiO2 passivation layer is deposited on the front side of the wafer. The SiO2 passivation layer is 180 nm thick. The passivation layer is formed in a full-surface coverage manner, covering the isolation mesa, micro-cell anti-reflection texture, active pixel area, dark reference pixel area, and pad area. The front-side Ni Schottky metal, Ti / Au busbar, and Al dark reference shielding layer are not formed in this step. Placing the passivation layer before the back-side ohmic annealing provides protection for the surface structure of the already formed n-type 4H-SiC epitaxial layer during the subsequent back-side annealing process.

[0028] Forming a Ni ohmic contact on the back side and annealing: A Ni backside metal layer with a thickness of 100 nm was deposited on the back side of the wafer. This was followed by rapid annealing in a nitrogen atmosphere at 950 °C for 90 s, forming an ohmic contact between the Ni backside metal layer and the n-type 4H-SiC substrate. Because this step occurs before the formation of the continuous Ni Schottky layer, Ni mesh-reinforced conductive layer, Ti / Au busbar, and Al dark reference shielding layer on the front side, it avoids the metal diffusion, interface reactions, morphology degradation, Schottky barrier drift, and dark reference shielding layer failure that can occur with annealing at 900 °C to 980 °C on the front side. The carrier concentration of the n-type 4H-SiC substrate was 5 × 10⁻⁶. 18 cm -3 This doping level is beneficial for the formation of a stable ohmic contact between the Ni back metal layer and the n-type 4H-SiC substrate.

[0029] The fourth photolithography pattern forms the active pixel window and pad window: After the back-side Ni ohmic contact annealing is completed, photoresist is coated on the passivation layer surface, and the fourth photolithography pattern is formed through exposure and development. The SiO2 passivation layer is etched using the fourth photolithography pattern to form the active pixel window and pad window. The active pixel window is located above the photosensitive texture area and is used to form a Schottky contact between the subsequent continuous Ni Schottky base layer and the n-type 4H-SiC epitaxial layer. The pad window is located in the pad area and is used for the subsequent formation of busbars and external interconnect structures. An area corresponding to the subsequent dark reference shielding layer is reserved above the dark reference pixel area to form a shielding cover.

[0030] The fifth photolithography pattern forms the front-side metal structure: a semi-transparent Schottky metal mesh electrode, busbars, and a dark reference shielding layer are formed through the fifth photolithography pattern. The semi-transparent Schottky metal mesh electrode includes a continuous Ni Schottky substrate and a Ni mesh-reinforced conductive layer located on the surface of the continuous Ni Schottky substrate. The continuous Ni Schottky substrate has a thickness of 3 nm. The continuous Ni Schottky substrate covers the photosensitive texture region within the active pixel window and forms a continuous Schottky contact interface with the n-type 4H-SiC epitaxial layer. The relatively thin thickness of the continuous Ni Schottky substrate maintains ultraviolet incident capability while improving the continuity of charge collection within the photosensitive texture region. The Ni mesh-reinforced conductive layer has a thickness of 12 nm, a mesh width of 3 μm, and a mesh period of 32 μm. The Ni mesh-reinforced conductive layer is located on the surface of the continuous Ni Schottky substrate to reduce the lateral resistance of the active pixel region and maintain the ultraviolet light incident path through the mesh openings. The busbar uses a Ti / Au stack. The Ti layer has a thickness of 20 nm, and the Au layer has a thickness of 200 nm. The Ti layer is used to improve metal adhesion, and the Au layer is used to reduce interconnect resistance. The dark reference shielding layer is an Al layer with a thickness of 150 nm. This layer covers the dark reference pixel region, preventing it from receiving external ultraviolet light and thus providing a dark current reference signal. The active pixel region and the dark reference pixel region share the same n-type 4H-SiC epitaxial layer base and similar Schottky electrical structures. The difference lies in that the active pixel region receives ultraviolet light, while the dark reference pixel region is covered by the dark reference shielding layer. The fifth lithography pattern is also used to form a Schottky contact structure in the dark reference pixel region corresponding to that in the active pixel region, and then form the dark reference shielding layer on top of it.

[0031] Wafer-level testing, dicing, and packaging: After completing the front-side metal structure, wafer-level testing is performed on the wafer. Test items include dark current, UV response current, matching between active and dark reference pixel areas, leakage current at the isolation mesa edge, pad continuity, and pixel consistency. After wafer testing, the wafer is diced to obtain a single silicon carbide-based monolithic integrated UV photoelectric sensor chip. Packaging is then performed according to the application environment. The packaging window material uses a UV-transmitting material to allow external UV light to enter the active pixel area.

Claims

1. A method for fabricating a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip, characterized in that, Includes the following steps: S1. Provide a wafer, the wafer comprising an n-type 4H-SiC substrate and an n-type 4H-SiC epitaxial layer located on the front side of the n-type 4H-SiC substrate; S2. Divide the front side of the wafer into an active pixel area, a dark reference pixel area, a photosensitive texture area located within the active pixel area, and a pad area. S3. A composite hard mask is formed on the surface of the n-type 4H-SiC epitaxial layer, the composite hard mask comprising oxygen-containing SiO₂. X Layer and located in the oxygen-containing SiO X Ni layer on the surface of the layer; S4. A main window is formed in the composite hard mask using the first photolithographic pattern, the main window penetrating the Ni layer and the oxygen-containing SiO layer. X The n-type 4H-SiC epitaxial layer is then exposed. S5. A second photolithographic pattern is formed using a second photoresist, and an oxygen-containing reaction shoulder window is formed at the edge of the main window. The oxygen-containing reaction shoulder window penetrates the Ni layer and retains the oxygen-containing SiO. X layer; S6. Remove the second photoresist and clean and dry; S7. The n-type 4H-SiC epitaxial layer exposed by the main window is pulsedly etched in SF6 / O2 / Ar plasma to form isolation mesa located at the boundary between the active pixel region and the dark reference pixel region, and at the periphery of the active pixel region and the dark reference pixel region. S8. Remove the composite hard mask; S9. A textured composite hard mask is formed in the photosensitive texture area, and a micro-honeycomb anti-reflection texture is formed by a third photolithography pattern and shallow etching. S10. Remove the textured composite hard mask; S11. A passivation layer is formed on the front side of the wafer; S12. A Ni back metal layer is formed on the back side of the wafer and annealed to form an ohmic contact between the Ni back metal layer and the n-type 4H-SiC substrate. S13. An active pixel window and a pad window are formed in the passivation layer by the fourth photolithography pattern; S14. A semi-transparent Schottky metal mesh electrode, busbar, and dark reference shielding layer are formed through the fifth photolithography pattern to obtain a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip.

2. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The wafer is a 100mm double-sided polished wafer, the n-type 4H-SiC substrate has a thickness of 330μm to 370μm, and the carrier concentration of the n-type 4H-SiC substrate is 1×10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 The thickness of the n-type 4H-SiC epitaxial layer is 4.5 μm to 5.5 μm, and the carrier concentration of the n-type 4H-SiC epitaxial layer is 1 × 10⁻⁶. 15 cm -3 Up to 8×10 15 cm -3 .

3. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The oxygen-containing SiO X The thickness of the layer is 140 nm to 180 nm, and the oxygen-containing SiO X The O / Si atomic ratio of the layer is 1.85 to 2.00, the thickness of the Ni layer is 70 nm to 90 nm, and the oxygen-containing SiO₂ layer... X The Ni layer is formed by plasma-enhanced chemical vapor deposition, and the Ni layer is formed by magnetron sputtering.

4. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The oxygen-containing reaction shoulder window is an array of slits arranged along the edge of the main window. Each slit in the array has a width of 0.30 μm to 0.40 μm, a slit pitch of 0.90 μm to 1.10 μm, and a distance from the centerline of the slit to the edge of the main window of 0.55 μm to 0.65 μm. The oxygen-containing SiO₂ is retained below the oxygen-containing reaction shoulder window. X The layer forms an oxygen-containing reaction interface under the action of plasma bombardment and fluorine-based active particles.

5. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The layout boundary of the main window is set with crystal orientation compensation amount according to 4° offset 4H-SiC crystal orientation, wherein the linewidth compensation amount of the boundary in the [11-20] direction is 0.15μm to 0.30μm, the linewidth compensation amount of the boundary in the [1-100] direction is 0.00μm to 0.10μm, and the corner radius of the main window is 1.5μm to 2.5μm.

6. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The pulsed bias etching process uses an SF6 concentration of 20 sccm to 26 sccm, an O2 flow rate of 1.6 sccm to 2.4 sccm, an Ar flow rate of 6 sccm to 10 sccm, a pressure of 0.9 Pa to 1.1 Pa, an ICP power of 800 W to 950 W, a bias power of 150 W to 190 W, a pulse frequency of 0.5 kHz to 2.0 kHz, a duty cycle of 40% to 60%, a mesa temperature of 120°C to 150°C, an etching depth of 1.00 μm to 1.30 μm, and a sidewall angle of 80° to 84°.

7. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The textured composite hard mask comprises oxygen-containing SiO₂ with a thickness of 100 nm to 130 nm. X The micro-cell anti-reflective texture consists of a textured layer and a Ni textured layer with a thickness of 50 nm to 70 nm. The micro-cell anti-reflective texture is a hexagonal concave texture with a period of 1.15 μm to 1.25 μm, a cell rib width of 0.50 μm to 0.60 μm, and a texture depth of 0.18 μm to 0.24 μm.

8. The method for fabricating a silicon carbide-based monolithically integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The passivation layer is a SiO2 layer with a thickness of 160nm to 200nm, the Ni back metal layer has a thickness of 90nm to 110nm, and the annealing is carried out in a nitrogen atmosphere at a temperature of 900℃ to 980℃ for a time of 60s to 120s.

9. The method for fabricating a silicon carbide-based monolithic integrated ultraviolet photoelectric sensor chip according to claim 1, characterized in that: The translucent Schottky metal mesh electrode comprises a continuous Ni Schottky substrate and a Ni mesh-reinforced conductive layer located on the surface of the continuous Ni Schottky substrate. The thickness of the continuous Ni Schottky substrate is 2 nm to 5 nm, the thickness of the Ni mesh-reinforced conductive layer is 10 nm to 15 nm, the mesh width of the Ni mesh-reinforced conductive layer is 2 μm to 4 μm, and the mesh period is 25 μm to 40 μm. The busbar is a Ti / Au stack, in which the thickness of Ti is 15 nm to 25 nm and the thickness of Au is 180 nm to 220 nm. The dark reference shielding layer is an Al layer with a thickness of 120 nm to 180 nm.

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