Optoelectronic synapse device and preparation method thereof

Abstract

The application provides an optoelectronic synapse device and a preparation method thereof, and the preparation method comprises the following steps: providing a gate electrode, forming a hafnium oxide dielectric layer on the gate electrode, forming a molybdenum disulfide channel layer on the hafnium oxide dielectric layer, performing chemical passivation on the molybdenum disulfide channel layer by using bistrifluoromethanesulfonimide, and forming a source electrode and a drain electrode on the chemically passivated molybdenum disulfide channel layer. By using the hafnium oxide dielectric layer with a thickness of 10 nm, the application realizes low-voltage driving of the optoelectronic synapse device by using the high dielectric constant of the hafnium oxide dielectric layer; by using the electrochemical intercalation, ultrasonic exfoliation and gradient centrifugation processes, a high-quality molybdenum disulfide channel layer with uniform size and a carrier mobility not less than 7.58 cm²V⁻¹s⁻¹ is obtained; by using the bistrifluoromethanesulfonimide passivation combined with 300 DEG C annealing, sulfur vacancies are effectively repaired, lattice stress is eliminated, and interface contact is optimized, and the above processes are synergistically combined to realize the optoelectronic synapse device with low-voltage driving, high response speed and excellent synaptic plasticity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a photoelectric synapse device and its fabrication method. Background Technology

[0002] With the rapid development of neuromorphic computing technology, phototransistors, as core devices capable of simultaneously simulating the photoelectric response and signal processing functions of biological synapses, have shown enormous application potential in cutting-edge fields such as artificial intelligence, machine vision, and biomimetic sensing. Among them, molybdenum disulfide (MoS2) is an ideal channel material, while the choice of gate dielectric layer and interface quality directly determine the operating voltage and stability of the device.

[0003] However, current gate dielectric layer technology still widely uses traditional silicon dioxide (SiO2), which has significant drawbacks. SiO2 has a dielectric constant of only 3.9, resulting in weak gate capacitance coupling. Effective channel control often requires gate voltages of tens of volts, leading to high device power consumption and making it difficult to meet the demands of low-power neuromorphic computing. Simultaneously, the interface compatibility between SiO2 and MoS2 is poor, easily generating numerous interface trap states, causing hysteresis and signal instability. Furthermore, the strong chemical inertness of SiO2 and poor wettability with MoS2 lead to problems such as agglomeration, uneven thickness, and low crystallinity in the channel film, resulting in weak film-substrate adhesion and easy damage during subsequent processes, severely restricting yield and consistency. Even though some studies have attempted to introduce high-κ materials such as hafnium oxide (HfO2), the incompatibility between the surface properties of MoS2 and the direct deposition process of high-κ dielectrics still presents challenges such as high interface defect density.

[0004] In summary, the gate dielectric layer technology based on silicon dioxide has become a key bottleneck restricting the performance improvement of molybdenum disulfide phototransistors due to its low dielectric constant, poor interface quality, and insufficient process compatibility. Summary of the Invention

[0005] The purpose of this invention is to provide a photoelectric synapse device and its fabrication method to solve the problems existing in the background art.

[0006] The technical solution of the present invention includes: a method for preparing a photoelectric synaptic device, comprising the following steps:

[0007] A gate is provided, and a hafnium oxide dielectric layer is formed on the gate;

[0008] A molybdenum disulfide channel layer is formed on the hafnium oxide dielectric layer;

[0009] The molybdenum disulfide channel layer was chemically passivated using bis(trifluoromethanesulfonyl)imide.

[0010] The source and drain are formed on the chemically passivated molybdenum disulfide channel layer.

[0011] Preferably, the step of forming the molybdenum disulfide channel layer includes:

[0012] An electrolytic cell was constructed using molybdenum disulfide as the cathode and graphite as the anode, and an electrochemical intercalation reaction was carried out using the first solution.

[0013] The cathode after electrochemical intercalation reaction was mixed with the first solution, and then subjected to ultrasonic treatment and gradient centrifugation to obtain a molybdenum disulfide dispersion.

[0014] The molybdenum disulfide dispersion was spin-coated onto the hafnium oxide dielectric layer to obtain the molybdenum disulfide channel layer;

[0015] The first solution contains tetraheptylammonium bromide and polyvinylpyrrolidone.

[0016] Preferably, the solvent of the first solution is N,N-dimethylformamide, the concentration of tetraheptylammonium bromide in the first solution is 5 mg / mL, and the concentration of polyvinylpyrrolidone in the first solution is 20 mg / mL.

[0017] Preferably, during the electrochemical intercalation reaction, a constant DC voltage of 3.5~4.2V is applied to the electrolytic cell, and the reaction time is 3h.

[0018] Preferably, when performing ultrasonic treatment, the ultrasonic frequency is 35~45kHz and the ultrasonic time is 15min.

[0019] Preferably, during gradient centrifugation, isopropanol is used to replace the dispersion medium of the coarse dispersion obtained by ultrasonic treatment, so that the dispersion medium of the molybdenum disulfide dispersion is isopropanol.

[0020] Preferably, the chemical passivation step includes: immersing the molybdenum disulfide channel layer in a second solution and holding it at a second temperature; removing the second solution and annealing it in an inert atmosphere at a third temperature; wherein the second solution contains bis(trifluoromethanesulfonyl)imide, the second temperature is 60~80°C, and the third temperature is 275~300°C.

[0021] Preferably, before chemical passivation, the molybdenum disulfide channel layer is immersed in acetone at a first temperature and then dried; wherein, the first temperature is 50~60℃.

[0022] Preferably, the source electrode and the drain electrode are chromium-gold composite electrodes, and the gold layer in the chromium-gold composite electrode is located on the side of the chromium layer away from the molybdenum disulfide channel layer.

[0023] The technical solution of the present invention also includes: a photoelectric synapse device, which is prepared by the above-described method for preparing a photoelectric synapse device.

[0024] The beneficial effects of this invention include: by employing a hafnium oxide dielectric layer with a controlled thickness of 10 nm, its high dielectric constant enables low-voltage driving of the photoelectric synaptic device; through electrochemical intercalation, ultrasonic exfoliation, and gradient centrifugation processes, a high-quality molybdenum disulfide channel layer with uniform size and a carrier mobility of not less than 7.58 cm²V⁻¹s⁻¹ is obtained; by using bis(trifluoromethanesulfonyl)imide passivation combined with 300°C annealing, sulfur vacancies are effectively repaired, lattice stress is eliminated, and interface contact is optimized; the source and drain electrodes are made of chromium-gold composite electrodes and deposited at room temperature to avoid high-temperature damage and improve device stability. The above processes synergistically realize a photoelectric synaptic device with low-voltage driving, high response speed, and excellent synaptic plasticity. Attached Figure Description

[0025] Figure 1 This is a schematic flowchart of the fabrication method of the photoelectric synaptic device according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the structure of the photoelectric synapse device according to an embodiment of the present invention;

[0027] Figure 3 These are the transfer characteristic curves of the photoelectric synaptic device of Embodiment 1 of the present invention under different optical power densities;

[0028] Figure 4 These are the output characteristic curves of the photoelectric synaptic device of Embodiment 1 of the present invention under different optical power densities;

[0029] Figure 5 This is a comparison diagram of the photocurrent response of the photoelectric synaptic devices of Embodiment 1 and Comparative Example 1 under single light pulse stimulation.

[0030] Figure 6 This is a comparison diagram of the synaptic facilitation characteristics of the photoelectric synaptic devices of Embodiment 1 and Comparative Example 1 under continuous light pulse stimulation.

[0031] In the picture:

[0032] 1. Gate; 2. Hafnium oxide dielectric layer; 3. Molybdenum disulfide channel layer; 4. Source; 5. Drain. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] This invention provides a method for preparing a photoelectric synaptic device and a photoelectric synaptic device prepared by the method.

[0035] Figure 1 This is a schematic diagram of the fabrication method of the photoelectric synapse device provided in an embodiment of the present invention. Referring to this figure, the fabrication method includes steps 100 to 400.

[0036] Step 100: Provide a gate 1 and form a hafnium oxide dielectric layer 2 on the gate 1.

[0037] Combination Figure 2 As shown, gate 1 is provided first in this step. In a preferred embodiment, gate 1 is a highly doped silicon semiconductor layer with a clean surface. The doping type can be N-type or P-type. This highly doped silicon semiconductor layer has a dual function in the device fabrication process: on the one hand, it serves as a supporting substrate for the device structure, and on the other hand, it directly acts as the bottom gate electrode. There is no need to fabricate an additional gate metal layer, which helps to simplify the process and reduce the fabrication cost.

[0038] In this embodiment, gate 1 is selected from a P-type doped single-crystal silicon wafer, and its crystal phase is... <100> The thickness is 500~600μm. <100> The uniform atomic arrangement on the surface of the crystal-oriented single-crystal silicon wafer ensures good consistency of nucleation sites in the atomic layer deposition process, which helps to achieve dense growth and enhanced adhesion of hafnium oxide thin films. At the same time, it enables controllability of the interface transition layer, resulting in extremely low defect density and excellent electrical compatibility. In addition, the P-type doped (resistivity 1~10Ω·cm) single-crystal silicon wafer can ensure good conductivity and interface stability of the gate, and achieve optimal band matching with hafnium oxide and N-type molybdenum disulfide, effectively suppressing interface charge traps and leakage current.

[0039] Before depositing the hafnium oxide dielectric layer 2, the gate 1 was ultrasonically cleaned for 15 minutes each with acetone, ethanol and deionized water to remove oil and impurities from its surface. Then it was dried with nitrogen gas for later use to ensure the cleanliness of the silicon wafer surface and lay the foundation for the subsequent film formation quality and interfacial adhesion of the hafnium oxide dielectric layer 2.

[0040] Then, a hafnium oxide (HfO2) thin film was deposited on the surface of gate 1 using an atomic layer deposition process. This process uses conventional hafnium and oxygen sources as raw materials, and the thickness of the dielectric layer is controlled to 10 nm by adjusting the deposition cycle number. After deposition, the film is annealed at 200-300℃ for 30 min to transform the hafnium oxide thin film into a highly crystalline monoclinic hafnium oxide dielectric layer, wherein the purity of HfO2 is ≥99.99%.

[0041] Hafnium oxide (HfO2) is a high dielectric constant material with a relative dielectric constant κ ranging from 18 to 25. Compared to traditional silicon dioxide dielectric layers (κ≈3.9, with a thickness typically ranging from tens to hundreds of nanometers), this approach reduces the dielectric layer thickness to 10 nm while ensuring the insulation reliability of the dielectric layer. This significantly increases the gate capacitance. The larger gate capacitance enhances the ability of the gate voltage to regulate channel carriers. Combined with the direct control advantages of silicon gates, it enables effective switching and synaptic weight adjustment of the device with a lower gate voltage, laying the foundation for low-voltage drive and low-power operation.

[0042] In addition, the hafnium oxide dielectric layer 2 prepared by atomic layer deposition has the characteristics of smooth surface, dense and free of pinholes, which can form a good interface contact with the gate 1, and also provides a high-quality substrate surface for the subsequent formation of molybdenum disulfide channel layer 3.

[0043] Step 200: Form a molybdenum disulfide channel layer 3 on the hafnium oxide dielectric layer 2.

[0044] Combination Figure 2 As shown, this step employs a liquid-phase stripping-spin-coating process to form a molybdenum disulfide channel layer 3 on the surface of the hafnium oxide dielectric layer 2 away from the gate 1. This step specifically includes the following sub-steps:

[0045] Step 210: Using molybdenum disulfide as the cathode and graphite as the anode, an electrolytic cell is constructed using the first solution to carry out an electrochemical intercalation reaction.

[0046] In this step, the cathode is preferably made of molybdenum disulfide crystal with a purity greater than 99.99% to ensure a complete crystal structure and low impurity content, thereby reducing additional defects introduced by impurities and laying the foundation for obtaining high-quality molybdenum disulfide nanosheets. Simultaneously, this embodiment directly uses high-purity crystals and simplifies the cleaning process (eliminating the need for ethanol cleaning) to reduce the risk of residual impurities introduced by organic solvents and to simplify the pretreatment process.

[0047] The first solution preferably uses N,N-dimethylformamide as a solvent and a solute containing tetraheptylammonium bromide and polyvinylpyrrolidone. Tetraheptylammonium bromide acts as an intercalating agent, dissociating into large-radius tetraheptylammonium ions under an electric field, which can effectively embed into the interlayer space of molybdenum disulfide and widen the interlayer spacing. Polyvinylpyrrolidone acts as a dispersant, adsorbing onto the surface or interlayer edge of molybdenum disulfide during the intercalation stage. On the one hand, it assists in layer expansion, and on the other hand, it prepares the layers in advance to prevent re-agglomeration during subsequent ultrasonic exfoliation. The synergistic effect of the two is beneficial to obtaining molybdenum disulfide nanosheets with uniform size and good dispersibility.

[0048] During the electrochemical intercalation reaction, a constant DC voltage of 3.5~4.2V is preferably applied, and the reaction is carried out at room temperature for 3 hours. This voltage can provide sufficient driving force to effectively insert tetraheptylammonium ions into the interlayer, while avoiding excessive lattice damage caused by excessive voltage. The reaction time of 3 hours can ensure that the intercalation is fully carried out, allowing the molybdenum disulfide crystal volume to expand to a suitable state. No additional heating is required at room temperature, the process is simple, energy consumption is low, and it is beneficial to maintain the integrity of the molybdenum disulfide lattice.

[0049] Preferably, the concentration of tetraheptylammonium bromide in the first solution is 5 mg / mL, and the concentration of polyvinylpyrrolidone is 20 mg / mL, that is, the concentration ratio of tetraheptylammonium bromide to polyvinylpyrrolidone is 1:4. In this electrolyte, the number of tetraheptylammonium ions dissociated from tetraheptylammonium bromide is sufficient to fully intercalate between molybdenum disulfide layers to achieve effective layer expansion; while polyvinylpyrrolidone can be uniformly adsorbed on the surface of molybdenum disulfide to form a stable steric hindrance layer, which can not only help to open up the interlayer during the intercalation stage, but also effectively prevent the re-agglomeration of the sheets during subsequent ultrasonic exfoliation. The synergistic effect of the two at this concentration is optimal, which can improve the yield of molybdenum disulfide of the target size.

[0050] Step 220: The cathode product after electrochemical intercalation reaction is mixed with the first solution, and then subjected to ultrasonic treatment and gradient centrifugation to obtain a molybdenum disulfide dispersion.

[0051] When performing ultrasonic treatment, the ultrasonic frequency is preferably 35~45kHz and the ultrasonic time is 15min. At this frequency, the cavitation effect is sufficient and uniform, which can effectively peel the expanded molybdenum disulfide crystals into nanosheets, while avoiding excessive damage to the sheet structure caused by excessive frequency. The ultrasonic time of 15min can ensure that the peeling is fully carried out, so that most of the molybdenum disulfide is dissociated into nanosheets of the target size (thickness of about 500nm).

[0052] After ultrasonic treatment, the obtained coarse dispersion was subjected to gradient centrifugation. The layer size was screened and the solvent was replaced by 4 to 6 centrifugation operations: the first gradient centrifugation was performed at a high speed of 8500 rpm to separate the solid and liquid into layers. The upper layer was removed, an appropriate amount of isopropanol was added, and the first gradient centrifugation was repeated several times to remove polyvinylpyrrolidone and other substances that had accumulated in the supernatant. The solid after the first gradient centrifugation was taken, an appropriate amount of isopropanol was added, and the second gradient centrifugation was performed at a speed of 3000 rpm to separate the large molybdenum disulfide particles and molybdenum disulfide nanosheets. The molybdenum disulfide nanosheets accumulated in the upper layer. The lower layer of large molybdenum disulfide particles was removed, an appropriate amount of isopropanol was added, and the second gradient centrifugation was repeated several times. Finally, the upper layer containing few-layer molybdenum disulfide of the target size was collected. The few-layer molybdenum disulfide is molybdenum disulfide nanosheets with 2 to 5 layers. During centrifugation, the substances to be separated are washed multiple times with isopropanol to replace the dispersion medium, so that the dispersion medium of the final molybdenum disulfide dispersion is replaced by isopropanol instead of N,N-dimethylformamide, while removing residual polyvinylpyrrolidone and organic ions.

[0053] Step 230: Spin-coat the molybdenum disulfide dispersion onto the hafnium oxide dielectric layer 2, and heat at 80°C for 3 minutes to evaporate the isopropanol, thereby obtaining the molybdenum disulfide channel layer 3.

[0054] During spin coating, the spin coating speed is 2000~3000 r / min and the spin coating time is 40s. Under these conditions, the molybdenum disulfide dispersion can be spread evenly to form a molybdenum disulfide film with uniform thickness and complete coverage.

[0055] The molybdenum disulfide channel layer 3 prepared by the above method has a lateral dimensional uniformity deviation of ≤10%, no obvious agglomeration, and a carrier mobility ≥7.58 cm⁻¹. 2 V -1 s -1 The molybdenum disulfide channel layer 3 covers the surface of the hafnium oxide dielectric layer 2 and forms a conductive channel in contact with the subsequently fabricated source electrode 4 and drain electrode 5. Due to its high carrier mobility, the channel responds to the gate voltage faster. At the same time, the uniform and dense film morphology ensures good interfacial contact with the source electrode 4, drain electrode 5 and dielectric layer. These characteristics together lay the material foundation for the subsequent realization of low-voltage drive, high response speed and excellent synaptic plasticity opto-synaptic performance.

[0056] Step 300: Chemical passivation of molybdenum disulfide channel layer 3 is performed using bis(trifluoromethanesulfonyl)imide.

[0057] In this step, the molybdenum disulfide channel layer 3 is first immersed in a second solution, which is a dichloroethane solution of bis(trifluoromethanesulfonyl)imide. The concentration of bis(trifluoromethanesulfonyl)imide in the second solution is 5 mg / mL to 10 mg / mL. The mixture is then kept at a second temperature to allow the passivation solution to fully wet the surface and react chemically with the sulfur vacancies on the surface of the molybdenum disulfide, thereby repairing the defects. After the heat treatment is completed, the passivation solution is removed, and the molybdenum disulfide channel layer 3 is placed in an inert atmosphere and annealed at a third temperature.

[0058] The second temperature is preferably 60~80℃, which provides sufficient activation energy for the passivation reaction, allowing the bis(trifluoromethanesulfonyl)imide molecules to fully react with the sulfur vacancies on the molybdenum disulfide surface, effectively repairing defects and reducing the defect state density of the molybdenum disulfide channel layer. At the same time, it avoids excessively high temperatures that could cause the passivation solution to evaporate too quickly or damage the molybdenum disulfide lattice. The third temperature is preferably 275~300℃, which, on the one hand, further solidifies the passivation effect, ensuring that the atoms or molecules filling the sulfur vacancies are stably bonded in the lattice. On the other hand, it can eliminate the lattice stress introduced by the molybdenum disulfide film during electrochemical intercalation and ultrasonic exfoliation, improving the crystallinity of the film. At the same time, this temperature can promote atomic diffusion and bonding at the interface between the molybdenum disulfide channel layer 3 and the hafnium oxide dielectric layer 2, forming atomically close contact, thereby reducing the interface state density and ensuring that the device can achieve low-voltage drive and excellent synaptic performance.

[0059] The preferred holding time is 1 hour; during annealing, the inert atmosphere can be argon atmosphere, and the preferred process is: heat to 300°C at a heating rate of 5°C / min, hold for 1 hour, and then cool naturally with the furnace.

[0060] To further improve the film quality and interfacial adhesion, a cleaning step 240 can be added before step 300.

[0061] Step 240: Immerse the molybdenum disulfide channel layer 3 in acetone at a first temperature, and then dry it. The first temperature is preferably 50~60℃. Immersion in hot acetone at this temperature can dissolve and remove trace amounts of organic colloids that may remain on the surface of the molybdenum disulfide film. After immersion, dry the molybdenum disulfide channel layer 3 at 80℃ for 30 minutes to remove residual solvent molecules on the surface and between layers, improve the cleanliness of the molybdenum disulfide film surface, and thus improve the film quality and interfacial adhesion.

[0062] Step 400: Form source 4 and drain 5 on chemically passivated molybdenum disulfide channel layer 3.

[0063] In this embodiment, the source 4 and drain 5 are respectively adopted as chromium-gold composite electrodes. The chromium-gold composite electrode includes a chromium layer and a gold layer stacked along the thickness direction of the device, wherein the gold layer is located on the side of the chromium layer away from the molybdenum disulfide channel layer 3.

[0064] The fabrication process of source 4 and drain 5 is as follows: First, the patterns of source 4 and drain 5 are defined on the molybdenum disulfide channel layer 3 using negative photoresist photolithography; then, a chromium layer and a gold layer are deposited sequentially using physical vapor deposition, with a chromium layer thickness of 5 nm and a deposition rate of 0.1 nm / s, and a gold layer thickness of 35 nm and a deposition rate of 0.5 nm / s; finally, excess photoresist and metal layers are removed by immersion in acetone to form patterned source 4 and drain 5, thus obtaining a complete opto-synaptic device.

[0065] In this step, source 4 and drain 5 are deposited at room temperature, which avoids damage to molybdenum disulfide channel layer 3 caused by high temperature. At the same time, chromium is selected as the adhesion layer, which has better adhesion performance to molybdenum disulfide and hafnium oxide than titanium, which is beneficial to improving the stability of the device and the yield.

[0066] Example 1

[0067] Step 100: Using a thickness of 500 μm and a crystal phase of <100> A highly doped single-crystal silicon wafer with P-type doping was used as gate 1. Gate 1 was ultrasonically cleaned for 15 minutes each with acetone, ethanol and deionized water to remove oil and impurities from its surface. Then it was dried with nitrogen for later use.

[0068] A hafnium oxide (HfO2) thin film was deposited on the surface of gate 1 using atomic layer deposition (ALD). The process used tetra(ethylmethylamino)hafnium as the hafnium source and water as the oxygen source. The thickness of the dielectric layer was controlled to 10 nm by adjusting the deposition cycle number. After deposition, the film was annealed at 300 °C for 30 min to transform the hafnium oxide thin film into a highly crystalline monoclinic hafnium oxide dielectric layer 2, wherein the purity of HfO2 was ≥99.99%.

[0069] Step 200: Using a liquid phase stripping-spin-coating process, a molybdenum disulfide channel layer 3 is formed on the surface of the hafnium oxide dielectric layer 2 away from the gate 1, specifically including:

[0070] Step 210: Using molybdenum disulfide crystals with a purity greater than 99.99% as the cathode and graphite as the anode, an electrolytic cell is constructed using the first solution to carry out an electrochemical intercalation reaction.

[0071] The solvent of the first solution is N,N-dimethylformamide, and the solutes include tetraheptylammonium bromide and polyvinylpyrrolidone. The concentration of tetraheptylammonium bromide in the first solution is 5 mg / mL, and the concentration of polyvinylpyrrolidone is 20 mg / mL.

[0072] During the electrochemical intercalation reaction, a constant DC voltage of 4.0V was applied, and the reaction was carried out at room temperature for 3 hours.

[0073] Step 220: The cathode after electrochemical intercalation reaction is mixed with the first solution, and then subjected to ultrasonic treatment and gradient centrifugation to obtain a molybdenum disulfide dispersion.

[0074] When performing ultrasonic treatment, the preferred ultrasonic frequency is 40kHz and the ultrasonic time is 15min.

[0075] After ultrasonic treatment, the obtained coarse dispersion was subjected to gradient centrifugation. The layer size was screened and the solvent was replaced by 4 to 6 centrifugation operations: the first gradient centrifugation was performed at a high speed of 8500 rpm to separate the solid and liquid into layers. The upper layer was removed, an appropriate amount of isopropanol was added, and the first gradient centrifugation was repeated several times to remove polyvinylpyrrolidone and other substances that had accumulated in the supernatant. The solid after the first gradient centrifugation was taken, an appropriate amount of isopropanol was added, and the second gradient centrifugation was performed at a speed of 3000 rpm to separate the large molybdenum disulfide particles and molybdenum disulfide nanosheets. The molybdenum disulfide nanosheets accumulated in the upper layer. The lower layer of large molybdenum disulfide particles was removed, an appropriate amount of isopropanol was added, and the second gradient centrifugation was repeated several times. Finally, the upper layer containing few-layer molybdenum disulfide of the target size was collected. The few-layer molybdenum disulfide is molybdenum disulfide nanosheets with 2 to 5 layers. During centrifugation, the substances to be separated are washed multiple times with isopropanol to replace the dispersion medium, so that the dispersion medium of the final molybdenum disulfide dispersion is replaced by isopropanol instead of N,N-dimethylformamide.

[0076] Step 230: Spin-coat the molybdenum disulfide dispersion onto the hafnium oxide dielectric layer 2, and heat at 80°C for 3 minutes to obtain the molybdenum disulfide channel layer 3. The spin-coating speed is 2000~3000 r / min, and the spin-coating time is 40 s.

[0077] Step 240: Soak the molybdenum disulfide channel layer 3 in acetone at 60°C for 1 hour. After soaking, dry the molybdenum disulfide channel layer at 80°C for 30 minutes.

[0078] Step 300: First, immerse the molybdenum disulfide channel layer 3 in the second solution, which is a dichloroethane solution of bis(trifluoromethanesulfonyl)imide with a concentration of 10 mg / mL. Hold the mixture at 80°C for 1 hour. After the holding period, remove the passivation solution and place the molybdenum disulfide channel layer 3 in an argon atmosphere for annealing. Heat the layer to 300°C at a heating rate of 5°C / min and hold for 1 hour. Then, allow it to cool naturally in the furnace.

[0079] Step 400: First, the source electrode 4 and drain electrode 5 are patterned on the molybdenum disulfide channel layer 3 using negative photoresist photolithography. Then, a chromium layer and a gold layer are deposited sequentially using physical vapor deposition. The chromium layer has a thickness of 5 nm and a deposition rate of 0.1 nm / s, and the gold layer has a thickness of 35 nm and a deposition rate of 0.5 nm / s. Finally, excess photoresist and metal layers are removed by immersion in acetone to form the patterned source electrode 4 and drain electrode 5, thus obtaining a complete opto-synaptic device.

[0080] Comparative Example 1

[0081] The only difference from Example 1 is that the dielectric layer in Comparative Example 1 is a silicon dioxide dielectric layer.

[0082] To evaluate the photoelectric response characteristics of the photoelectric synaptic device prepared according to the embodiments of the present invention, static photoelectric performance characterization was performed, including testing the transfer characteristic curves and output characteristic curves at different optical power densities. The test results are as follows: Figure 3 and Figure 4 As shown.

[0083] When testing the transfer characteristic curve, first set the source-drain voltage (V) DS The gate voltage (V) is fixed at 0.1V, and then the gate voltage (V) is adjusted. GS A bidirectional scan was performed: first, the voltage was gradually increased from -1.8V to 1.8V (forward scan), then gradually decreased back to -1.8V (backward scan). Based on this, the scans were performed under conditions of no light (dark state) and different optical power densities (specifically 33.22 μW / cm²). 2 67.90 μW / cm 2 120.68 μW / cm 2 242.63 μW / cm 2 1mW / cm 2 2mW / cm 2 3mW / cm 2 ), measuring drain current (I DS ) with gate voltage (V GS The relationship between the changes of ) is obtained. Figure 3 The transfer characteristic curve of the device is shown. The test results show that as the optical power density increases, the channel current increases significantly in the negative gate voltage range, and the threshold voltage (V) shifts in the negative direction, proving that illumination effectively introduces carriers and reduces the conduction barrier, and the device has a significant photoinduced gate control effect.

[0084] When testing the output characteristic curve, the gate voltage (V) is respectively... GS The source-drain voltage (V) is fixed at three different operating states: 1.0V, 0V, and -1.0V. DSThe voltage was gradually increased from 0V to 1.2V. Based on this, tests were conducted under conditions of no light (dark state) and different light power densities (specifically 33.22 μW / cm²). 2 67.90 μW / cm 2 120.68 μW / cm 2 242.63 μW / cm 2 1mW / cm 2 2mW / cm 2 3mW / cm 2 ), measuring drain current (I DS Source-drain voltage (V) DS The relationship between the changes of ) is obtained. Figure 4 The output characteristic curve of the device is shown. Test results show that the drain current (I) exhibits a good linear relationship with the source-drain voltage (V), especially in the low bias region, indicating that a good ohmic contact is formed between the molybdenum disulfide channel layer and the metal electrode. As the optical power density increases, the slope of the output curve (i.e., the channel conductance) increases stepwise, and the current stratification under different light intensities is clear and without obvious overlap, indicating that the device can accurately convert optical signals of different intensities into differentiated conductance states, providing a stable hardware foundation for the subsequent simulation of the "sensing" function of biological vision systems.

[0085] To verify the application potential of the device in neuromorphic computing, this invention simulated the dynamic temporal response of biological synapses and explored the influence of the dielectric layer on synaptic performance. The same dynamic synaptic function simulation tests were performed on the photoelectric synaptic devices of Example 1 (hafnium oxide dielectric layer) and Comparative Example 1 (silicon dioxide dielectric layer), including single-pulse response and synaptic facilitation behavior tests under continuous light pulse stimulation. The test results are as follows: Figure 5 and Figure 6 As shown.

[0086] like Figure 5 As shown, in the single-pulse response test, a wavelength of 520 nm and an optical power density of 1 mW / cm² were used. 2A light pulse was used as a presynaptic stimulus. A constant gate voltage of -1V and a source-drain voltage of 0.1V were applied to the device under test, and the change in drain current (I) was observed as the postsynaptic current (PSC). When a single light pulse with a duration of 1 second was applied, the current in both the device of Embodiment 1 and Comparative Example 1 rose rapidly, corresponding to the excitatory postsynaptic current (PSC) of a biological synapse. After the light pulse ended, the current did not immediately return to the initial dark current state, but instead showed a slow decay. This sustained photoconductivity (PPC) successfully simulated the short-term memory behavior of a biological synapse. It is worth noting that, compared with the device of Comparative Example 1, Embodiment 1, based on a hafnium oxide dielectric layer, exhibited a higher photocurrent response amplitude (peak current of approximately 65nA) and a longer relaxation time. This is attributed to the presence of more abundant defect energy levels at the hafnium oxide interface or in the bulk, which can more effectively capture and release photogenerated carriers, thereby enhancing the memory retention capability of the device.

[0087] like Figure 6 As shown, in the multi-pulse facilitation test, a wavelength of 520 nm and an optical power density of 1 mW / cm² were used. 2 Using optical pulses as presynaptic stimuli, a constant gate voltage of -1V and a source-drain voltage of 0.1V were applied to the device under test, and the change in drain current (I) was observed as the postsynaptic current (PSC). However, to simulate the "learning" process of biological neurons, the presynaptic stimulus applied to the device was a series of continuous optical pulse stimuli with a frequency of 0.5Hz. Experimental results showed that as the number of pulses increased, the postsynaptic current (PSC) exhibited a step-like cumulative increase, with the peak current induced by each subsequent pulse being higher than that of the previous pulse, successfully simulating the learning behavior of synaptic facilitation. Comparative results showed that the current accumulation effect of Embodiment 1 under continuous pulses was significantly stronger than that of the device in Comparative Example 1, and its final-state current gain was higher. This indicates that using a high dielectric constant dielectric layer material can effectively adjust the synaptic weight update efficiency of the device, making it more suitable for simulating neural network learning tasks that require high dynamic range weights.

[0088] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a photoelectric synaptic device, characterized in that, Including the following steps: A gate is provided, and a hafnium oxide dielectric layer is formed on the gate; A molybdenum disulfide channel layer is formed on the hafnium oxide dielectric layer; The molybdenum disulfide channel layer was chemically passivated using bis(trifluoromethanesulfonyl)imide. The source and drain are formed on the chemically passivated molybdenum disulfide channel layer.

2. The method for fabricating the photoelectric synaptic device according to claim 1, characterized in that, The steps for forming the molybdenum disulfide channel layer include: An electrolytic cell was constructed using molybdenum disulfide as the cathode and graphite as the anode, and an electrochemical intercalation reaction was carried out using the first solution. The cathode after electrochemical intercalation reaction was mixed with the first solution, and then subjected to ultrasonic treatment and gradient centrifugation to obtain a molybdenum disulfide dispersion. The molybdenum disulfide dispersion was spin-coated onto the hafnium oxide dielectric layer to obtain the molybdenum disulfide channel layer; The first solution contains tetraheptylammonium bromide and polyvinylpyrrolidone.

3. The method for fabricating the photoelectric synaptic device according to claim 2, characterized in that, The solvent of the first solution is N,N-dimethylformamide, the concentration of tetraheptylammonium bromide in the first solution is 5 mg / mL, and the concentration of polyvinylpyrrolidone in the first solution is 20 mg / mL.

4. The method for fabricating the photoelectric synaptic device according to claim 2, characterized in that, During the electrochemical intercalation reaction, a constant DC voltage of 3.5~4.2V is applied to the electrolytic cell, and the reaction time is 3h.

5. The method for fabricating the photoelectric synaptic device according to claim 2, characterized in that, When performing ultrasonic treatment, the ultrasonic frequency is 35~45kHz and the ultrasonic time is 15min.

6. The method for fabricating the photoelectric synaptic device according to claim 2, characterized in that, During gradient centrifugation, isopropanol is used to replace the dispersion medium of the coarse dispersion obtained by ultrasonic treatment, so that the dispersion medium of the molybdenum disulfide dispersion is isopropanol.

7. The method for fabricating the photoelectric synaptic device according to claim 1, characterized in that, The chemical passivation steps include: immersing the molybdenum disulfide channel layer in a second solution and holding it at a second temperature; removing the second solution and annealing it at a third temperature in an inert atmosphere; wherein the second solution contains bis(trifluoromethanesulfonyl)imide, the second temperature is 60~80°C, and the third temperature is 275~300°C.

8. The method for fabricating the photoelectric synaptic device according to claim 7, characterized in that, Before chemical passivation, the molybdenum disulfide channel layer is immersed in acetone at a first temperature and then dried; wherein, the first temperature is 50~60℃.

9. The method for fabricating the photoelectric synaptic device according to claim 1, characterized in that, The source and the drain are chromium-gold composite electrodes, with the gold layer in the chromium-gold composite electrode located on the side of the chromium layer away from the molybdenum disulfide channel layer.

10. A photoelectric synaptic device, characterized in that, It is prepared by the method of any one of claims 1-9.

Images