Array substrate and display panel

Abstract

The array substrate and the display panel provided by the embodiment of the present application relate to the technical field of display, and the array substrate comprises a time division multiplexing circuit, a data connection trace, a data voltage signal trace and a plurality of pixel circuits. The time division multiplexing circuit comprises a first time division multiplexing unit and a second time division multiplexing unit. The data connection trace comprises a first data connection sub-trace and a second data connection sub-trace. The first data connection sub-trace and the second data connection sub-trace are located in the same row. The first time division multiplexing unit and the second time division multiplexing unit are simultaneously in an open state. The data voltage signal trace comprises a first data voltage sub-trace and a second data voltage sub-trace. The first data voltage sub-trace and the second data voltage sub-trace are electrically connected to the same type of pixel circuit. The present application can make the influence of the scanning signal trace on the first data connection sub-trace and the second data connection sub-trace the same.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display panels.

[0003] However, there are still some problems with the display panel that need to be addressed. Summary of the Invention

[0004] To overcome the technical problems mentioned in the background, this application provides an array substrate, the array substrate comprising: The time-division multiplexing circuit includes a first time-division multiplexing unit and a second time-division multiplexing unit; The data connection trace extends along a first direction and includes a first data connection sub-trace and a second data connection sub-trace spaced apart. The first data connection sub-trace and the second data connection sub-trace are located in the same row. The first data connection sub-trace is connected to the first time-division multiplexing unit, and the second data connection trace is connected to the second time-division multiplexing unit. The first time-division multiplexing unit and the second time-division multiplexing unit are both in the open state. A data voltage signal trace extends along a second direction. The data voltage signal trace includes a first data voltage sub-trace and a second data voltage sub-trace spaced apart. The first data voltage sub-trace is electrically connected to the first data connection sub-trace, and the second data voltage sub-trace is electrically connected to the second data connection sub-trace. The second direction intersects with the first direction. Multiple pixel circuits, wherein the first data voltage sub-line and the second data voltage sub-line are electrically connected to the same type of pixel circuit.

[0005] In some possible implementations, the array substrate further includes: A data voltage transition trace extends along a second direction. The data voltage transition trace includes a first transition sub-trace and a second transition sub-trace spaced apart. One end of the first transition sub-trace is connected to the first time-division multiplexing unit, and the other end is connected to the first data connection sub-trace. One end of the second transition sub-trace is connected to the second time-division multiplexing unit, and the other end is connected to the second data connection sub-trace. The first time-division multiplexing unit and the second time-division multiplexing unit simultaneously provide data voltage signals to the first transition sub-trace and the second transition sub-trace, respectively. Preferably, the array substrate includes a substrate and a first conductive layer and a second conductive layer sequentially stacked in a direction away from the substrate. The data connection traces are located in the first conductive layer, and the data voltage signal traces and data voltage transition traces are both located in the second conductive layer. The first data connection sub-trace is connected to the first data voltage sub-trace through a first via, the first data connection sub-trace is connected to the first transition sub-trace through a second via, the second data connection sub-trace is connected to the second data voltage sub-trace through a third via, and the second data connection sub-trace is connected to the second transition sub-trace through a fourth via. Preferably, the array substrate includes a display area and a non-display area surrounding at least a portion of the display area, the time-division multiplexing circuit is located in the non-display area, the data voltage signal trace is located in the display area, and the data voltage transition trace extends from the non-display area to the display area; Preferably, the second direction is perpendicular to the first direction.

[0006] In some possible implementations, the time-division multiplexing circuit includes a first time-division data voltage control trace. The first time-division multiplexing unit includes a first switching transistor and a first data voltage supply trace. The first data voltage supply trace is connected to a first terminal of the first switching transistor, and the first transition trace is connected to a second terminal of the first switching transistor. The second time-division multiplexing unit includes a second switching transistor and a second data voltage supply trace. The second data voltage supply trace is connected to a first terminal of the second switching transistor, and the second transition trace is connected to a second terminal of the second switching transistor. The first time-division data voltage control trace is connected to the gate of both the first and second switching transistors.

[0007] In some possible implementations, the array substrate includes a first region and a second region that are interconnected, the first region and the second region being arranged along the first direction, and the first time-division multiplexing unit, the first transition sub-trace, the first data connection sub-trace and the first data voltage sub-trace are all located in the first region; Preferably, the second time-division multiplexing unit, the second transition sub-trace, the second data connection sub-trace, and the second data voltage sub-trace are all located in the second region.

[0008] In some possible implementations, the data connection traces further include a third data connection sub-trace and a fourth data connection sub-trace spaced apart, the third data connection sub-trace and the fourth data connection sub-trace being located in the same row, the time-division multiplexing circuit including a third time-division multiplexing unit and a fourth time-division multiplexing unit, the third data connection sub-trace being connected to the third time-division multiplexing unit, the fourth data connection sub-trace being connected to the fourth time-division multiplexing unit, and the third time-division multiplexing unit and the fourth time-division multiplexing unit being simultaneously in an open state; The data voltage signal trace further includes a third data voltage sub-trace and a fourth data voltage sub-trace spaced apart. The third data voltage sub-trace is electrically connected to the third data connection sub-trace, and the fourth data voltage sub-trace is electrically connected to the fourth data connection sub-trace. The third data voltage sub-trace and the fourth data voltage sub-trace are electrically connected to the same type of pixel circuit. The type of pixel circuit connected to the third data voltage sub-trace is different from the type of pixel circuit connected to the first data voltage sub-trace. Preferably, the plurality of pixel circuits includes a first type of pixel circuit, a second type of pixel circuit, and a third type of pixel circuit. The first data voltage sub-line is electrically connected to both the first type of pixel circuit and the second type of pixel circuit, and the third data voltage sub-line is electrically connected to the third type of pixel circuit.

[0009] In some possible implementations, the data voltage transition trace includes a third transition sub-trace and a fourth transition sub-trace. One end of the third transition sub-trace is connected to the third time-division multiplexing unit, and the other end is connected to the third data connection sub-trace. One end of the fourth transition sub-trace is connected to the fourth time-division multiplexing unit, and the other end is connected to the fourth data connection sub-trace. The third time-division multiplexing unit and the fourth time-division multiplexing unit simultaneously provide data voltage signals to the third transition sub-trace and the fourth transition sub-trace, respectively. Preferably, the third data connection sub-trace is connected to the third data voltage sub-trace through a fifth through-hole, the third data connection sub-trace is connected to the third transition sub-trace through a sixth through-hole, the fourth data connection sub-trace is connected to the fourth data voltage sub-trace through a seventh through-hole, and the fourth data connection sub-trace is connected to the fourth transition sub-trace through an eighth through-hole.

[0010] In some possible implementations, the time-division multiplexing circuit includes a second time-division data voltage control trace; the third time-division multiplexing unit includes a third switching transistor, the first terminal of which is connected to both the first data voltage supply trace and the first terminal of the first switching transistor; the second terminal of which is connected to the third transition trace; the fourth time-division multiplexing unit includes a fourth switching transistor, the first terminal of which is connected to both the second data voltage supply trace and the first terminal of the second switching transistor; the second terminal of which is connected to the fourth transition trace; and the second time-division data voltage control trace is connected to both the gate of the third switching transistor and the gate of the fourth switching transistor. Preferably, the array substrate includes a first region and a second region that are interconnected, the first region and the second region are arranged along the first direction, and the third time-division multiplexing unit, the third transition sub-trace, the third data connection sub-trace and the third data voltage sub-trace are all located in the first region; Preferably, the fourth time-division multiplexing unit, the fourth transition sub-trace, the fourth data connection sub-trace, and the fourth data voltage sub-trace are all located in the second region.

[0011] In some possible implementations, the array substrate further includes: Substrate, The first scan signal trace is located on one side of the substrate and extends along the first direction; The second scan signal trace is located on one side of the substrate and extends along the first direction. The distance between the orthographic projection of the first data connection sub-trace on the substrate and the orthographic projection of the first scan signal trace on the substrate is less than the distance between the orthographic projection of the first data connection sub-trace on the substrate and the orthographic projection of the second scan signal trace on the substrate. The distance between the orthographic projection of the third data connection sub-trace on the substrate and the orthographic projection of the second scan signal trace on the substrate is less than the distance between the orthographic projection of the third data connection sub-trace on the substrate and the orthographic projection of the first scan signal trace on the substrate. When the data signal flows through the first data connection sub-trace and the second data connection sub-trace, the scan signal flows through the first scan signal trace, and / or, when the data signal flows through the third data connection sub-trace and the fourth data connection sub-trace, the scan signal flows through the second scan signal trace.

[0012] In some possible implementations, the array substrate further includes a driving trace layer and a chip, with the time-division multiplexing circuit located on the chip or the driving trace layer.

[0013] In some possible implementations, this application also provides a display panel, which includes the array substrate described in this application.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides an array substrate and a display panel. By configuring the first data voltage sub-line and the second data voltage sub-line to be electrically connected to the same type of pixel circuit, and configuring the first time-division multiplexing unit and the second time-division multiplexing unit to be simultaneously in the open state, the influence of the scan signal line on the first data connection sub-line and the second data connection sub-line can be made the same. This can improve the problem of dark lines or bright lines at the first data connection sub-line and the second data connection sub-line, thereby improving the display effect of the display panel corresponding to the array substrate. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A top view of the array substrate provided in the embodiments of this application, including time-division multiplexing circuits, data connection traces, and data voltage signal traces; Figure 2 The array substrate provided in the embodiments of this application also includes a top view of the data voltage transition traces; Figure 3 A cross-sectional schematic diagram of a first data connection sub-trace provided in an embodiment of this application, wherein one end of the first data connection sub-trace is connected to a first data voltage sub-trace through a first through-hole, and the other end is connected to a first transition sub-trace through a second through-hole. Figure 4 A cross-sectional schematic diagram of a second data connection sub-trace provided in an embodiment of this application, wherein one end of the second data connection sub-trace is connected to the second data voltage sub-trace through a third through-hole, and the other end is connected to the second transition sub-trace through a fourth through-hole. Figure 5 A top view of the array substrate provided in the embodiments of this application, including a first region and a second region; Figure 6 A top view schematic diagram showing the first multiplexing unit provided in the embodiments of this application, which includes a first switching transistor, and the second multiplexing unit, which includes a second switching transistor; Figure 7 The array substrate provided for the embodiments of this application also includes a schematic diagram of a third multiplexing unit and a fourth multiplexing unit; Figure 8 A cross-sectional schematic diagram of a third data connection sub-trace provided in an embodiment of this application, wherein one end of the third data connection sub-trace is connected to the third data voltage sub-trace through a fifth through hole, and the other end is connected to the third transition sub-trace through a sixth through hole; Figure 9 A cross-sectional schematic diagram of a fourth data connection sub-trace provided in an embodiment of this application, wherein one end of the fourth data connection sub-trace is connected to the fourth data voltage sub-trace through a seventh through-hole, and the other end is connected to the fourth transition sub-trace through an eighth through-hole. Figure 10 A top view schematic diagram showing the third multiplexing unit, which includes a third switching transistor, and the fourth multiplexing unit, which includes a fourth switching transistor, provided in the embodiments of this application. Figure 11 A top view of the array substrate provided in the embodiments of this application, including a first scan line and a second scan line; Figure 12 A timing diagram of the first scan signal trace, the second scan signal trace, the first time-division data voltage control trace, and the second time-division data voltage control trace provided in the embodiments of this application; Figure 13 This is a three-dimensional structural diagram of the electronic device provided in an embodiment of this application.

[0017] Reference numerals: 01, Display panel; 100, Electronic device; 1, Time-division multiplexing circuit; 11, First time-division multiplexing unit; 111, First switching transistor; 112, First data voltage supply trace; 12, Second time-division multiplexing unit; 121, Second switching transistor; 13, Third time-division multiplexing unit; 131, Third switching transistor; 14, Fourth time-division multiplexing unit; 141, Fourth switching transistor; 2, Data connection trace; 21, First data connection sub-trace; 22, Second data connection sub-trace; 23, Third data connection sub-trace; 24, Fourth data connection sub-trace; 3, Data voltage signal trace; 31, First data voltage Sub-trace; 32, Second data voltage sub-trace; 33, Third data voltage sub-trace; 34, Fourth data voltage sub-trace; 4, Pixel circuit; 41, First type pixel circuit; 42, Second type pixel circuit; 43, Third type pixel circuit; 5, Data voltage transition trace; 51, First transition sub-trace; 52, Second transition sub-trace; 53, Third transition sub-trace; 54, Fourth transition sub-trace; 6, Substrate; 7, First conductive layer; 8, Second conductive layer; 91, First via; 92, Second via; 93, Third via; 94, Fourth via; 95, Fifth via; 96, Sixth via; 97, Seventh via; 98, Eighth via. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0021] Furthermore, when using terms such as "above," "above," "below," "below," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by gaps or other elements. In addition, the terms "first," "second," and "third," etc., are only used for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] The array substrate in the related technology includes a time-division multiplexing circuit, which includes multiple time-division multiplexing units and data connection lines. The data connection lines transmit the data signal located in the middle of the array substrate laterally to the data lines on the left and right sides of the array substrate. In this way, the data lines located on the left and right sides of the array substrate do not need to be transmitted to the bottom bezel of the array substrate, thereby reducing the width of the bottom bezel and making it easier to achieve a narrow bezel.

[0024] However, in related technologies, multiple time-division multiplexing unit arrays are arranged such that two horizontal data connection lines in the same row connect sub-pixels of different colors. That is, the two horizontal data connection lines in the same row will not receive data signals at the same time. When the scan line corresponding to that row transmits a scan signal, since one of the two horizontal data connection lines in the same row receives a data signal while the other does not, the scan line corresponding to that row will have different effects on the data connection lines on the left and right sides of that row, resulting in bright or dark lines in that row, and ultimately affecting the display effect of the display panel corresponding to the array substrate.

[0025] To address the aforementioned technical problems, the following innovative technical solutions are designed. The specific implementation schemes of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below should be considered contributions made to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0026] Please see Figure 1 This embodiment provides an array substrate, which includes a time-division multiplexing circuit 1, data connection traces 2, data voltage signal traces 3, and multiple pixel circuits 4.

[0027] The time-division multiplexing circuit 1 includes a first time-division multiplexing unit 11 and a second time-division multiplexing unit 12.

[0028] The data connection line 2 extends along the first direction X. The data connection line 2 includes a first data connection sub-line 21 and a second data connection sub-line 22 that are spaced apart. The first data connection sub-line 21 and the second data connection sub-line 22 are located in the same row. The first data connection sub-line 21 is connected to the first time-division multiplexing unit 11, and the second data connection sub-line 22 is connected to the second time-division multiplexing unit 12. The first time-division multiplexing unit 11 and the second time-division multiplexing unit 12 are both in the open state.

[0029] The data voltage signal trace 3 extends along the second direction Y. The data voltage signal trace 3 includes a first data voltage sub-trace 31 and a second data voltage sub-trace 32 that are spaced apart. The first data voltage sub-trace 31 is electrically connected to the first data connection sub-trace 21, and the second data voltage sub-trace 32 is electrically connected to the second data connection sub-trace 22. The second direction Y intersects the first direction X.

[0030] The first data voltage sub-line 31 and the second data voltage sub-line 32 are electrically connected to the same type of pixel circuit 4.

[0031] The first direction X includes the row direction of the array substrate, and the second direction Y includes the column direction of the array substrate. The first data connection sub-trace 21 and the second data connection sub-trace 22 are spaced apart, that is, the first data connection sub-trace 21 and the second data connection sub-trace 22 are two independent data connection sub-traces. The first data connection sub-trace 21 and the second data connection sub-trace 22 are arranged in the same row, that is, the extension of the first data connection sub-trace 21 and the extension of the second data connection sub-trace 22 overlap.

[0032] The first data voltage sub-line 31 and the second data voltage sub-line 32 are two independent data voltage sub-lines. The first data voltage sub-line 31 and the second data voltage sub-line 32 are respectively connected to a column of pixel circuits 4, and the pixel circuits 4 are then connected to the corresponding sub-pixels.

[0033] The same type of pixel circuit 4 connects to sub-pixels of the same color. The first data voltage sub-line 31 and the second data voltage sub-line 32 are electrically connected to the same type of pixel circuit 4, that is, the first data voltage sub-line 31 and the second data voltage sub-line 32 connect to sub-pixels of the same color.

[0034] When the first time-division multiplexing unit 11 and the second time-division multiplexing unit 12 are both in the open state, the data signal can flow through the first data connection sub-line 21 and the second data connection sub-line 22 simultaneously.

[0035] When the scan signal traces corresponding to the first data connection sub-trace 21 and the second data connection sub-trace 22 transmit scan signals, since the first data connection sub-trace 21 and the second data connection sub-trace 22 located in the same row can simultaneously receive data signals, the scan signal traces in that row have the same effect on the first data connection sub-trace 21 and the second data connection sub-trace 22. This can improve the problem of dark or bright lines at the first data connection sub-trace 21 and the second data connection sub-trace 22, thereby improving the display effect of the display panel corresponding to the array substrate.

[0036] Based on the above design, this embodiment sets the first data voltage sub-line 31 and the second data voltage sub-line 32 to be electrically connected to the same type of pixel circuit 4, and sets the first time-division multiplexing unit 11 and the second time-division multiplexing unit 12 to be in the open state at the same time. This can make the scanning signal line have the same effect on the first data connection sub-line 21 and the second data connection sub-line 22, thereby improving the problem of dark lines or bright lines at the first data connection sub-line 21 and the second data connection sub-line 22, and thus improving the display effect of the display panel corresponding to the array substrate.

[0037] For some possible implementations, please refer to Figure 2The array substrate also includes a data voltage transition trace 5, which extends along the second direction Y. The data voltage transition trace 5 includes a first transition sub-trace 51 and a second transition sub-trace 52 spaced apart. One end of the first transition sub-trace 51 is connected to the first time-division multiplexing unit 11, and the other end is connected to the first data connection sub-trace 21. One end of the second transition sub-trace 52 is connected to the second time-division multiplexing unit 12, and the other end is connected to the second data connection sub-trace 22. The first time-division multiplexing unit 11 and the second time-division multiplexing unit 12 simultaneously provide data voltage signals to the first transition sub-trace 51 and the second transition sub-trace 52, respectively.

[0038] Optionally, the second direction Y is perpendicular to the first direction X.

[0039] The data signal flowing through the first transition sub-trace 51 can be sequentially transmitted to the first data connection sub-trace 21 and the first data voltage sub-trace 31, and then the first data voltage sub-trace 31 transmits the data signal to the corresponding pixel circuit 4; the data signal flowing through the second transition sub-trace 52 can be sequentially transmitted to the second data connection sub-trace 22 and the second data voltage sub-trace 32, and then the second data voltage sub-trace 32 transmits the data signal to the corresponding pixel circuit 4.

[0040] Optionally, please see Figure 3 and Figure 4 The array substrate includes a substrate 6 and a first conductive layer 7 and a second conductive layer 8 stacked sequentially in a direction away from the substrate 6. Data connection trace 2 is located on the first conductive layer 7, and data voltage signal trace 3 and data voltage transition trace 5 are both located on the second conductive layer 8. The first data connection sub-trace 21 is connected to the first data voltage sub-trace 31 through a first via 91. The first data connection sub-trace 21 is connected to the first transition sub-trace 51 through a second via 92. The second data connection sub-trace 22 is connected to the second data voltage sub-trace 32 through a third via 93. The second data connection sub-trace 22 is connected to the second transition sub-trace 52 through a fourth via 94.

[0041] Please see again Figure 3 One end of the first data connection sub-trace 21 is connected to the first data voltage sub-trace 31 through the first via 91, and the other end is connected to the first transition sub-trace 51 through the second via 92. In this way, the first data connection sub-trace 21 and the first transition sub-trace 51 can be connected through the first data connection sub-trace 21 of different layers, which makes it easier for data signals to be transmitted to the first data voltage sub-trace 31.

[0042] Please see again Figure 4One end of the second data connection sub-trace 22 is connected to the second data voltage sub-trace 32 through the third via 93, and the other end is connected to the second transition sub-trace 52 through the fourth via 94. In this way, the second data connection sub-trace 22 and the second transition sub-trace 52 can be connected through second data connection sub-trace 22 on different layers, which makes it easier for data signals to be transmitted to the first data voltage sub-trace 31.

[0043] For some possible implementations, please refer to Figure 2 and Figure 5 The array substrate includes a first region AA1 and a second region AA2 that are interconnected. The first region AA1 and the second region AA2 are arranged along the first direction X. The first time-division multiplexing unit 11, the first transition sub-line 51, the first data connection sub-line 21 and the first data voltage sub-line 31 are all located in the first region AA1.

[0044] Optionally, the second time-division multiplexing unit 12, the second transition sub-line 52, the second data connection sub-line 22, and the second data voltage sub-line 32 are all located in the second region AA2.

[0045] Optionally, the array substrate includes a display area AA and a non-display area AB surrounding at least a portion of the display area AA. The time-division multiplexing circuit 1 is located in the non-display area AB, the data voltage signal trace 3 is located in the display area AA, and the data voltage transition trace 5 extends from the non-display area AB to the display area AA.

[0046] by Figure 5 Based on the viewing angle, the first region AA1 is located on the left side of the array substrate, the second region AA2 is located on the right side of the array substrate, and the non-display area AB includes the border of the array substrate.

[0047] The first transition sub-trace 51 and the second transition sub-trace 52 are located in the middle of the array substrate. The first data voltage sub-trace 31 is located near the left edge of the array substrate, and the second data voltage sub-trace 32 is located near the right edge of the array substrate.

[0048] The data signal flowing through the first transition sub-trace 51 is transmitted to the first data voltage sub-trace 31 through the first data connection sub-trace 21 extending along the first direction X. In this way, the first data voltage sub-trace 31 does not need to extend to the lower border of the array substrate, thereby reducing the space occupied by the first data voltage sub-trace 31 on the lower border of the array substrate, and thus reducing the width of the lower border of the array substrate.

[0049] The data signal flowing through the second transition sub-trace 52 is transmitted to the second data voltage sub-trace 32 through the second data connection sub-trace 22 extending along the first direction X. In this way, the second data voltage sub-trace 32 does not need to extend to the lower border of the array substrate, thereby reducing the space occupied by the second data voltage sub-trace 32 on the lower border of the array substrate, and thus reducing the width of the lower border of the array substrate.

[0050] Therefore, the above design is more conducive to achieving the goal of narrow bezels on the array substrate.

[0051] For some possible implementations, please refer to Figure 6 The time-division multiplexing circuit 1 includes a first time-division data voltage control line Mux1. The first time-division multiplexing unit 11 includes a first switching transistor 111 and a first data voltage supply line 112. The first data voltage supply line 112 is connected to the first terminal of the first switching transistor 111, and the first transition line 51 is connected to the second terminal of the first switching transistor 111. The second time-division multiplexing unit 12 includes a second switching transistor 121 and a second data voltage supply line. The second data voltage supply line is connected to the first terminal of the second switching transistor 121, and the second transition line 52 is connected to the second terminal of the second switching transistor 121. The first time-division data voltage control line Mux1 is connected to the gate of both the first and second switching transistors.

[0052] The first data voltage supply trace 112 and the second data voltage supply trace can be electrically connected to the chip. The chip can provide data signals to the first data voltage supply trace 112 and the second data voltage supply trace. The first time-division data voltage control trace Mux1 can control whether the first switching transistor 111 and the second switching transistor 121 are turned on simultaneously.

[0053] When the first time-division data voltage control line Mux1 is turned on, for example, when it is at a low level, the data signal flowing through the first data voltage supply line 112 will pass through the first switching transistor 111 in sequence through the first transition sub-line 51, the first data connection sub-line 21 and the first data voltage sub-line 31. The data signal flowing through the first data voltage sub-line 31 is then transmitted to a column of pixel circuits 4 connected to the first data voltage sub-line 31.

[0054] When the first time-division data voltage control line Mux1 is turned on, for example, when it is at a low level, the data signal flowing through the second data voltage supply line will pass through the second switching transistor 121 in sequence through the second transition sub-line 52, the second data connection sub-line 22, and the second data voltage sub-line 32. The data signal flowing through the second data voltage sub-line 32 is then transmitted to a column of pixel circuits 4 connected to the second data voltage sub-line 32.

[0055] Since the gates of the first switching transistor and the second switching transistor are both connected to the first time-division data voltage control trace Mux1, the first switching transistor 111 and the second switching transistor 121 can be turned on simultaneously. This allows the data signal to flow through the first data connection sub-trace 21 and the second data connection sub-trace 22 simultaneously. Consequently, the corresponding scan signal traces can have the same effect on the first data connection sub-trace 21 and the second data connection sub-trace 22, ultimately improving the problem of dark or bright lines appearing at the first data connection sub-trace 21 and the second data connection sub-trace 22.

[0056] For some possible implementations, please refer to Figure 7 The data connection trace 2 also includes a third data connection sub-trace 23 and a fourth data connection sub-trace 24 spaced apart. The third data connection sub-trace 23 and the fourth data connection sub-trace 24 are located in the same row. The time-division multiplexing circuit 1 includes a third time-division multiplexing unit 13 and a fourth time-division multiplexing unit 14. The third data connection sub-trace 23 is connected to the third time-division multiplexing unit 13, and the fourth data connection sub-trace 24 is connected to the fourth time-division multiplexing unit 14. The third time-division multiplexing unit 13 and the fourth time-division multiplexing unit 14 are both in the open state.

[0057] The data voltage signal trace 3 also includes a third data voltage sub-trace 33 and a fourth data voltage sub-trace 34 spaced apart. The third data voltage sub-trace 33 is electrically connected to the third data connection sub-trace 23, and the fourth data voltage sub-trace 34 is electrically connected to the fourth data connection sub-trace 24. The third data voltage sub-trace 33 and the fourth data voltage sub-trace 34 are electrically connected to the same type of pixel circuit 4. The type of pixel circuit 4 connected to the third data voltage sub-trace 33 is different from the type of pixel circuit 4 connected to the first data voltage sub-trace 31.

[0058] The third data connection sub-trace 23 and the fourth data connection sub-trace 24 are spaced apart, meaning that the third data connection sub-trace 23 and the fourth data connection sub-trace 24 are two independent data connection sub-traces; the third data connection sub-trace 23 and the fourth data connection sub-trace 24 are arranged in the same line, meaning that the extension of the third data connection sub-trace 23 and the extension of the fourth data connection sub-trace 24 overlap.

[0059] The third data voltage sub-line 33 and the fourth data voltage sub-line 34 are two independent data voltage sub-lines. The third data voltage sub-line 33 and the fourth data voltage sub-line 34 are respectively connected to a column of pixel circuits 4, and the pixel circuits 4 are then connected to the corresponding sub-pixels.

[0060] The third data voltage sub-line 33 and the fourth data voltage sub-line 34 are electrically connected to the same type of pixel circuit 4, that is, the third data voltage sub-line 33 and the fourth data voltage sub-line 34 are connected to sub-pixels of the same color, and the emission color of the sub-pixels connected by the third data voltage sub-line 33 and the fourth data voltage sub-line 34 is different from the emission color of the sub-pixels connected by the first data voltage sub-line 31 and the second data voltage sub-line 32.

[0061] When the third time-division multiplexing unit 13 and the fourth time-division multiplexing unit 14 are both open, the data signal can flow through the third data connection sub-line 23 and the fourth data connection sub-line 24 simultaneously.

[0062] When the scan signal traces corresponding to the third data connection sub-trace 23 and the fourth data connection sub-trace 24 transmit scan signals, since the third data connection sub-trace 23 and the fourth data connection sub-trace 24 located in the same row can simultaneously receive data signals, the scan signal traces in that row have the same effect on the third data connection sub-trace 23 and the fourth data connection sub-trace 24. This can improve the problem of dark or bright lines appearing at the third data connection sub-trace 23 and the fourth data connection sub-trace 24, thereby improving the display effect of the display panel corresponding to the array substrate.

[0063] Optionally, please see again Figure 7 The multiple pixel circuits 4 include a first type of pixel circuit 41, a second type of pixel circuit 42 and a third type of pixel circuit 43. The first data voltage sub-line 31 is electrically connected to both the first type of pixel circuit 41 and the second type of pixel circuit 42, and the third data voltage sub-line 33 is electrically connected to the third type of pixel circuit 43.

[0064] The first type of pixel circuit 41 is electrically connected to the first sub-pixel, the second type of pixel circuit 42 is electrically connected to the second sub-pixel, and the third type of pixel circuit 43 is electrically connected to the third sub-pixel. The light emission color of the first sub-pixel includes red, the light emission color of the second sub-pixel includes blue, and the light emission color of the third sub-pixel includes green.

[0065] Data signals flowing through the first data connection sub-line 21 are transmitted to the first type of pixel circuit 41 and the second type of pixel circuit 42 via the first data voltage sub-line 31; data signals flowing through the second data connection sub-line 22 are transmitted to the first type of pixel circuit 41 and the second type of pixel circuit 42 via the second data voltage sub-line 32; data signals flowing through the third data connection sub-line 23 are transmitted to the third type of pixel circuit 43 via the third data voltage sub-line 33; and data signals flowing through the fourth data connection sub-line 24 are transmitted to the third type of pixel circuit 43 via the fourth data voltage sub-line 34.

[0066] Data signals can flow simultaneously through the first data connection sub-trace 21 and the second data connection sub-trace 22 to provide data signals for the first sub-pixel and the second sub-pixel. This allows the corresponding scan signal traces to have the same effect on the first data connection sub-trace 21 and the second data connection sub-trace 22, ultimately improving the problem of dark or bright lines appearing at the first data connection sub-trace 21 and the second data connection sub-trace 22.

[0067] The data signal can flow through the third data connection sub-trace 23 and the fourth data connection sub-trace 24 simultaneously to provide data signal to the third sub-pixel. This allows the corresponding scan signal trace to have the same effect on the third data connection sub-trace 23 and the fourth data connection sub-trace 24, ultimately improving the problem of dark or bright lines appearing at the third data connection sub-trace 23 and the fourth data connection sub-trace 24.

[0068] In some possible implementations, please refer again. Figure 7 The data voltage transition trace 5 includes a third transition sub-trace 53 and a fourth transition sub-trace 54. One end of the third transition sub-trace 53 is connected to the third time-division multiplexing unit 13, and the other end is connected to the third data connection sub-trace 23. One end of the fourth transition sub-trace 54 is connected to the fourth time-division multiplexing unit 14, and the other end is connected to the fourth data connection sub-trace 24. The third time-division multiplexing unit 13 and the fourth time-division multiplexing unit 14 simultaneously provide data voltage signals to the third transition sub-trace 53 and the fourth transition sub-trace 54, respectively.

[0069] The data signal flowing through the third transition sub-trace 53 can be sequentially transmitted to the third data connection sub-trace 23 and the third data voltage sub-trace 33, and then the data signal is transmitted to the corresponding third type pixel circuit 43 by the third data voltage sub-trace 33; the data signal flowing through the fourth transition sub-trace 54 can be sequentially transmitted to the fourth data connection sub-trace 24 and the fourth data voltage sub-trace 34, and then the data signal is transmitted to the corresponding fourth type pixel circuit 4 by the fourth data voltage sub-trace 34.

[0070] Optionally, please see Figure 8 and Figure 9 The third data connection sub-trace 23 is connected to the third data voltage sub-trace 33 through the fifth through hole 95. The third data connection sub-trace 23 is connected to the third transition sub-trace 53 through the sixth through hole 96. The fourth data connection sub-trace 24 is connected to the fourth data voltage sub-trace 34 through the seventh through hole 97. The fourth data connection sub-trace 24 is connected to the fourth transition sub-trace 54 through the eighth through hole 98.

[0071] Please see again Figure 8One end of the third data connection sub-trace 23 is connected to the third data voltage sub-trace 33 through the fifth via 95, and the other end is connected to the third transition sub-trace 53 through the sixth via 96. In this way, the third data connection sub-trace 23 and the third transition sub-trace 53 can be connected through the third data connection sub-trace 23 of different layers, which makes it easier for data signals to be transmitted to the third data voltage sub-trace 33.

[0072] Please see again Figure 9 One end of the fourth data connection sub-trace 24 is connected to the fourth data voltage sub-trace 34 through the seventh via 97, and the other end is connected to the fourth transition sub-trace 54 through the eighth via 98. In this way, the fourth data connection sub-trace 24 and the fourth transition sub-trace 54 can be connected through the fourth data connection sub-trace 24 on different layers, which makes it easier for data signals to be transmitted to the fourth data voltage sub-trace 34.

[0073] For some possible implementations, please refer to Figure 10 The time-division multiplexing circuit 1 includes a second time-division data voltage control line Mux2; the third time-division multiplexing unit 13 includes a third switching transistor 131, the first terminal of the third switching transistor 131 is connected to both the first data voltage supply line 112 and the first terminal of the first switching transistor 111, and the second terminal of the third switching transistor 131 is connected to the third transition line 53; the fourth time-division multiplexing unit 14 includes a fourth switching transistor 141, the first terminal of the fourth switching transistor 141 is connected to both the second data voltage supply line and the first terminal of the second switching transistor 121, and the second terminal of the fourth switching transistor 141 is connected to the fourth transition line 54; the second time-division data voltage control line Mux2 is connected to both the gate of the third switching transistor and the gate of the fourth switching transistor.

[0074] The third and fourth data voltage supply traces can be electrically connected to the chip. The chip can provide data signals to the third and fourth data voltage supply traces. The second time-division data voltage control trace Mux2 can control whether the third switching transistor 131 and the fourth switching transistor 141 are turned on simultaneously.

[0075] When the second time-division data voltage control line Mux2 is turned on, for example, when it is at a low level, the data signal flowing through the third data voltage supply line will pass through the third switching transistor 131 in sequence through the third transition sub-line 53, the third data connection sub-line 23 and the third data voltage sub-line 33. The data signal flowing through the third data voltage sub-line 33 is then transmitted to a column of pixel circuits 4 connected to the third data voltage sub-line 33.

[0076] When the second time-division data voltage control line Mux2 is turned on, for example, when it is at a low level, the data signal flowing through the fourth data voltage supply line will pass through the fourth switching transistor 141 in sequence through the fourth transition sub-line 54, the fourth data connection sub-line 24 and the fourth data voltage sub-line 34. The data signal flowing through the fourth data voltage sub-line 34 is then transmitted to a column of pixel circuits 4 connected to the fourth data voltage sub-line 34.

[0077] Since the gates of the third and fourth switching transistors are both connected to the second time-division data voltage control trace Mux2, the third switching transistor 131 and the fourth switching transistor 141 can be turned on simultaneously. This allows the data signal to flow through the third data connection sub-trace 23 and the fourth data connection sub-trace 24 at the same time. Consequently, the corresponding scan signal traces can have the same effect on the third data connection sub-trace 23 and the fourth data connection sub-trace 24, ultimately improving the problem of dark or bright lines appearing at the third data connection sub-trace 23 and the fourth data connection sub-trace 24.

[0078] Optionally, please see again Figure 5 and Figure 10 The third time-division multiplexing unit 13, the third transition sub-line 53, the third data connection sub-line 23, and the third data voltage sub-line 33 are all located in the first region AA1.

[0079] Optionally, the fourth time-division multiplexing unit 14, the fourth transition sub-line 54, the fourth data connection sub-line 24, and the fourth data voltage sub-line 34 are all located in the second region AA2.

[0080] The third transition sub-trace 53 and the fourth transition sub-trace 54 are located in the middle of the array substrate, the third data voltage sub-trace 33 is located near the left edge of the array substrate, and the fourth data voltage sub-trace 34 is located near the right edge of the array substrate.

[0081] The data signal flowing through the third transition sub-trace 53 is transmitted to the third data voltage sub-trace 33 through the third data connection sub-trace 23 extending along the first direction X. In this way, the third data voltage sub-trace 33 does not need to extend to the lower border of the array substrate, thereby reducing the space occupied by the third data voltage sub-trace 33 on the lower border of the array substrate, and thus reducing the width of the lower border of the array substrate.

[0082] The data signal flowing through the fourth transition sub-trace 54 is transmitted to the fourth data voltage sub-trace 34 through the fourth data connection sub-trace 24 extending along the first direction X. In this way, the fourth data voltage sub-trace 34 does not need to extend to the lower border of the array substrate, thereby reducing the space occupied by the fourth data voltage sub-trace 34 on the lower border of the array substrate, and thus reducing the width of the lower border of the array substrate.

[0083] For some possible implementations, please refer to Figure 3 and Figure 11 The array substrate also includes a substrate 6, a first scan signal trace Scan1, and a second scan signal trace Scan2.

[0084] The first scan signal trace Scan1 is located on one side of the substrate 6 and extends along the first direction X.

[0085] The second scan signal trace Scan2 is located on one side of the substrate 6. The second scan signal trace Scan2 extends along the first direction X. The distance D1 between the orthographic projection of the first data connection sub-trace 21 on the substrate 6 and the orthographic projection of the first scan signal trace Scan1 on the substrate 6 is less than the distance D2 between the orthographic projection of the first data connection sub-trace 21 on the substrate 6 and the orthographic projection of the second scan signal trace Scan2 on the substrate 6. The distance D3 between the orthographic projection of the third data connection sub-trace 23 on the substrate 6 and the orthographic projection of the second scan signal trace Scan2 on the substrate 6 is less than the distance D4 between the orthographic projection of the third data connection sub-trace 23 on the substrate 6 and the orthographic projection of the first scan signal trace Scan1 on the substrate 6.

[0086] When the data signal flows through the first data connection sub-line 21 and the second data connection sub-line 22, the scan signal flows through the first scan signal line Scan1, and / or, when the data signal flows through the third data connection sub-line 23 and the fourth data connection sub-line 24, the scan signal flows through the second scan signal line Scan2.

[0087] The first scan signal trace Scan1 and the second scan signal trace Scan2 can be connected to the chip, and the chip can provide scan signals for the first scan signal trace Scan1 and the second scan signal trace Scan2.

[0088] Please see Figure 12 When the first scan signal trace Scan1 receives a scan signal, the second scan signal trace Scan2 does not receive a scan signal, the first time-division data voltage control trace Mux1 receives a conduction signal, and the second time-division data voltage control trace Mux2 does not receive a conduction signal; when the second scan signal trace Scan2 receives a scan signal, the first scan signal trace Scan1 does not receive a scan signal, the second time-division data voltage control trace Mux2 receives a conduction signal, and the first time-division data voltage control trace Mux1 does not receive a conduction signal.

[0089] In related technologies, since the first data connection sub-line 21 and the second data connection sub-line 22 connect different types of pixel circuits 4, data signals will not flow through the first data connection sub-line 21 and the second data connection sub-line 22 simultaneously. Because the first scan signal line Scan1 is relatively close to the first data connection sub-line 21 and the second data connection sub-line 22, when the scan signal flows through the first scan signal line Scan1, bright spots will be generated between the first scan signal line Scan1 and either the first data connection sub-line 21 or the second data connection sub-line 22 that does not receive data signals. For example, if the data signal does not flow through the first data connection sub-line 21, a bright spot will be generated on the left side of the array substrate. Multiple bright spots connected together will produce a bright line.

[0090] In this embodiment, since the first data connection sub-line 21 and the second data connection sub-line 22 connect to the same type of pixel circuit 4, and the data signal can flow through the first data connection sub-line 21 and the second data connection sub-line 22 simultaneously, when the scan signal flows through the first scan signal line Scan1, the data signal simultaneously flows through the first data connection sub-line 21 and the second data connection sub-line 22. Therefore, the first scan signal line Scan1 is less likely to affect the first data connection sub-line 21 and the second data connection sub-line 22. The first scan signal line Scan1 and the first data connection sub-line 21... Bright spots are unlikely to occur between the second data connection sub-trace 22; since the third data connection sub-trace 23 and the fourth data connection sub-trace 24 are relatively far from the first scan signal trace Scan1, even if the data signal does not flow through the third data connection sub-trace 23 and the fourth data connection sub-trace 24, the first scan signal trace Scan1 is unlikely to affect the third data connection sub-trace 23 and the fourth data connection sub-trace 24, and bright spots are unlikely to occur at the third data connection sub-trace 23 and the fourth data connection sub-trace 24, thus bright lines are unlikely to occur on the display panel corresponding to the array substrate.

[0091] In related technologies, since the third data connection sub-line 23 and the fourth data connection sub-line 24 connect different types of pixel circuits 4, data signals will not flow through the third data connection sub-line 23 and the fourth data connection sub-line 24 simultaneously. Because the second scan signal line Scan2 is relatively close to the third data connection sub-line 23 and the fourth data connection sub-line 24, when the scan signal flows through the second scan signal line Scan2, bright spots will be generated between the second scan signal line Scan2 and the third data connection sub-line 23 or the fourth data connection sub-line 24 that does not receive data signals. For example, if the data signal does not flow through the third data connection sub-line 23, a bright spot will be generated on the left side of the array substrate. Multiple bright spots connected together will produce a bright line.

[0092] In this embodiment, since the third data connection sub-line 23 and the fourth data connection sub-line 24 are connected to the same type of pixel circuit 4, and the data signal can flow through both the third data connection sub-line 23 and the fourth data connection sub-line 24 simultaneously, when the scan signal flows through the second scan signal line Scan2, the data signal also flows through both the third data connection sub-line 23 and the fourth data connection sub-line 24. Therefore, the second scan signal line Scan2 is less likely to affect the third data connection sub-line 23 and the fourth data connection sub-line 24. The second scan signal line Scan2 and the third data connection sub-line 23... Bright spots are less likely to occur between the first data connection sub-trace 21 and the second data connection sub-trace 22; since the first data connection sub-trace 21 and the second data connection sub-trace 22 are relatively far from the second scan signal trace Scan2, even if the data signal does not flow through the first data connection sub-trace 21 and the second data connection sub-trace 22, the second scan signal trace Scan2 is less likely to affect the first data connection sub-trace 21 and the second data connection sub-trace 22, and bright spots are less likely to occur at the first data connection sub-trace 21 and the second data connection sub-trace 22, thus making it less likely for bright lines to occur on the display panel corresponding to the array substrate.

[0093] In some possible implementations, the array substrate also includes a driving trace layer and a chip, with the time-division multiplexing circuit 1 located on the chip or the driving trace layer.

[0094] In some embodiments, the time-division multiplexing circuit 1 is disposed within the chip.

[0095] In other embodiments, the time-division multiplexing circuit 1 is disposed within the drive trace layer of the array substrate.

[0096] In this way, the time-division multiplexing circuit 1 can be set in different positions according to actual needs, and all of them can effectively improve the problem of bright lines on the display panel corresponding to the array substrate.

[0097] In some possible implementations, this application also provides a display panel, which includes the array substrate described in this application.

[0098] Since the display panel includes the array substrate described in this application, the display panel is less prone to producing bright lines, thereby improving the display effect of the display panel.

[0099] For some possible implementations, please refer to Figure 13This application also provides an electronic device 100, which includes the display panel 01 described in this application, or a display panel 01 prepared by the method described in this application. The electronic device 100 may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, automotive displays, wearable devices, etc. Because the electronic device 100 includes the display panel 01 described in this application, its display effect is better.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: The time-division multiplexing circuit includes a first time-division multiplexing unit and a second time-division multiplexing unit; The data connection trace extends along a first direction and includes a first data connection sub-trace and a second data connection sub-trace spaced apart. The first data connection sub-trace and the second data connection sub-trace are located in the same row. The first data connection sub-trace is connected to the first time-division multiplexing unit, and the second data connection trace is connected to the second time-division multiplexing unit. The first time-division multiplexing unit and the second time-division multiplexing unit are both in the open state. A data voltage signal trace extends along a second direction. The data voltage signal trace includes a first data voltage sub-trace and a second data voltage sub-trace spaced apart. The first data voltage sub-trace is electrically connected to the first data connection sub-trace, and the second data voltage sub-trace is electrically connected to the second data connection sub-trace. The second direction intersects with the first direction. Multiple pixel circuits, wherein the first data voltage sub-line and the second data voltage sub-line are electrically connected to the same type of pixel circuit.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes: A data voltage transition trace extends along a second direction. The data voltage transition trace includes a first transition sub-trace and a second transition sub-trace spaced apart. One end of the first transition sub-trace is connected to the first time-division multiplexing unit, and the other end is connected to the first data connection sub-trace. One end of the second transition sub-trace is connected to the second time-division multiplexing unit, and the other end is connected to the second data connection sub-trace. The first time-division multiplexing unit and the second time-division multiplexing unit simultaneously provide data voltage signals to the first transition sub-trace and the second transition sub-trace, respectively. Preferably, the array substrate includes a substrate and a first conductive layer and a second conductive layer sequentially stacked in a direction away from the substrate. The data connection traces are located in the first conductive layer, and the data voltage signal traces and data voltage transition traces are both located in the second conductive layer. The first data connection sub-trace is connected to the first data voltage sub-trace through a first via, the first data connection sub-trace is connected to the first transition sub-trace through a second via, the second data connection sub-trace is connected to the second data voltage sub-trace through a third via, and the second data connection sub-trace is connected to the second transition sub-trace through a fourth via. Preferably, the array substrate includes a display area and a non-display area surrounding at least a portion of the display area, the time-division multiplexing circuit is located in the non-display area, the data voltage signal trace is located in the display area, and the data voltage transition trace extends from the non-display area to the display area; Preferably, the second direction is perpendicular to the first direction.

3. The array substrate according to claim 2, characterized in that, The time-division multiplexing circuit includes a first time-division data voltage control trace. The first time-division multiplexing unit includes a first switching transistor and a first data voltage supply trace. The first data voltage supply trace is connected to a first terminal of the first switching transistor, and the first transition trace is connected to a second terminal of the first switching transistor. The second time-division multiplexing unit includes a second switching transistor and a second data voltage supply trace. The second data voltage supply trace is connected to a first terminal of the second switching transistor, and the second transition trace is connected to a second terminal of the second switching transistor. The first time-division data voltage control trace is connected to the gate of both the first switching transistor and the gate of the second switching transistor.

4. The array substrate according to claim 3, characterized in that, The array substrate includes a first region and a second region that are interconnected. The first region and the second region are arranged along the first direction. The first time-division multiplexing unit, the first transition sub-trace, the first data connection sub-trace, and the first data voltage sub-trace are all located in the first region. Preferably, the second time-division multiplexing unit, the second transition sub-trace, the second data connection sub-trace, and the second data voltage sub-trace are all located in the second region.

5. The array substrate according to claim 3, characterized in that, The data connection traces also include a third data connection sub-trace and a fourth data connection sub-trace spaced apart, the third data connection sub-trace and the fourth data connection sub-trace are located in the same row, the time-division multiplexing circuit includes a third time-division multiplexing unit and a fourth time-division multiplexing unit, the third data connection sub-trace is connected to the third time-division multiplexing unit, the fourth data connection sub-trace is connected to the fourth time-division multiplexing unit, and the third time-division multiplexing unit and the fourth time-division multiplexing unit are simultaneously in the open state; The data voltage signal trace further includes a third data voltage sub-trace and a fourth data voltage sub-trace spaced apart. The third data voltage sub-trace is electrically connected to the third data connection sub-trace, and the fourth data voltage sub-trace is electrically connected to the fourth data connection sub-trace. The third data voltage sub-trace and the fourth data voltage sub-trace are electrically connected to the same type of pixel circuit. The type of pixel circuit connected to the third data voltage sub-trace is different from the type of pixel circuit connected to the first data voltage sub-trace. Preferably, the plurality of pixel circuits includes a first type of pixel circuit, a second type of pixel circuit, and a third type of pixel circuit. The first data voltage sub-line is electrically connected to both the first type of pixel circuit and the second type of pixel circuit, and the third data voltage sub-line is electrically connected to the third type of pixel circuit.

6. The array substrate according to claim 5, characterized in that, The data voltage transition trace includes a third transition sub-trace and a fourth transition sub-trace. One end of the third transition sub-trace is connected to the third time-division multiplexing unit, and the other end is connected to the third data connection sub-trace. One end of the fourth transition sub-trace is connected to the fourth time-division multiplexing unit, and the other end is connected to the fourth data connection sub-trace. The third time-division multiplexing unit and the fourth time-division multiplexing unit simultaneously provide data voltage signals to the third transition sub-trace and the fourth transition sub-trace, respectively. Preferably, the third data connection sub-trace is connected to the third data voltage sub-trace through a fifth through-hole, the third data connection sub-trace is connected to the third transition sub-trace through a sixth through-hole, the fourth data connection sub-trace is connected to the fourth data voltage sub-trace through a seventh through-hole, and the fourth data connection sub-trace is connected to the fourth transition sub-trace through an eighth through-hole.

7. The array substrate according to claim 6, characterized in that, The time-division multiplexing circuit includes a second time-division data voltage control trace; the third time-division multiplexing unit includes a third switching transistor, the first terminal of which is connected to both the first data voltage supply trace and the first terminal of the first switching transistor; the second terminal of which is connected to the third transition trace; the fourth time-division multiplexing unit includes a fourth switching transistor, the first terminal of which is connected to both the second data voltage supply trace and the first terminal of the second switching transistor; the second terminal of which is connected to the fourth transition trace; and the second time-division data voltage control trace is connected to both the gate of the third switching transistor and the gate of the fourth switching transistor. Preferably, the array substrate includes a first region and a second region that are interconnected, the first region and the second region are arranged along the first direction, and the third time-division multiplexing unit, the third transition sub-trace, the third data connection sub-trace and the third data voltage sub-trace are all located in the first region; Preferably, the fourth time-division multiplexing unit, the fourth transition sub-trace, the fourth data connection sub-trace, and the fourth data voltage sub-trace are all located in the second region.

8. The array substrate according to any one of claims 5-7, characterized in that, The array substrate further includes: Substrate, The first scan signal trace is located on one side of the substrate and extends along the first direction; The second scan signal trace is located on one side of the substrate and extends along the first direction. The distance between the orthographic projection of the first data connection sub-trace on the substrate and the orthographic projection of the first scan signal trace on the substrate is less than the distance between the orthographic projection of the first data connection sub-trace on the substrate and the orthographic projection of the second scan signal trace on the substrate. The distance between the orthographic projection of the third data connection sub-trace on the substrate and the orthographic projection of the second scan signal trace on the substrate is less than the distance between the orthographic projection of the third data connection sub-trace on the substrate and the orthographic projection of the first scan signal trace on the substrate. When the data signal flows through the first data connection sub-trace and the second data connection sub-trace, the scan signal flows through the first scan signal trace, and / or, when the data signal flows through the third data connection sub-trace and the fourth data connection sub-trace, the scan signal flows through the second scan signal trace.

9. The array substrate according to any one of claims 1-7, characterized in that, The array substrate further includes a driving trace layer and a chip, and the time-division multiplexing circuit is located on the chip or the driving trace layer.

10. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-9.

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