A lateral heterojunction memristor

Abstract

The application discloses a lateral heterojunction memristor, wherein a composite layer is arranged on an insulating substrate, the composite layer comprises a GeO2 material region, a TiO2 material region and an insulating material region, the GeO2 material region, the TiO2 material region and the insulating material region form a heterojunction in the same plane, and the insulating material region separates the GeO2 material region and the TiO2 material region. A metal active electrode is arranged on the GeO2 material region. An inert electrode is arranged on the TiO2 material region. The partition structure of the composite layer of the application can not only realize the resistance state switching of the memristor, but also effectively regulate the carrier transport through the intermediate insulating material region, thereby enhancing the nonlinearity and adjustability of the conductive behavior of the device, which is beneficial to reduce the leakage current in the array application and improve the device selectivity; and the resistance state transformation of the memristor is not dependent on the formation and breakage of the conductive filament, but is based on the capture and release of the carriers of the insulating material region, which can effectively reduce the loss of the material.

Description

Technical Field

[0001] This invention relates to the field of memristors, and more particularly to a lateral heterojunction memristor. Background Technology

[0002] Memristors, as core devices for non-volatile storage and neuromorphic computing, exhibit reversible changes in resistance state under the influence of an applied electrical signal, which are maintained after the signal is removed. This allows for applications such as information storage and simulating synaptic weight updates. Generally, the resistance state switching of a memristor is related to the physicochemical processes within the material, such as the migration and reduction of active ions driven by an electric field, the generation and redistribution of defects in the medium, or the modulation of the interface barrier between the electrodes and functional layers. Existing memristor structures mostly employ a vertical stacking configuration, where one or more insulating or functional thin films are placed between the upper and lower electrodes. An electric field is created along the thickness of the thin film by applying a voltage to drive the resistance state switching. This structure has a relatively mature fabrication process, facilitating device fabrication and array integration through thin film deposition and photolithography. Furthermore, due to the short effective switching distance, resistance switching can typically be achieved at relatively low driving voltages, thus possessing high integration potential and a solid application foundation.

[0003] In high-density integrated applications such as cross-arrays, memristors generally face crosstalk current and leakage current problems, often requiring the introduction of additional gating devices to suppress leakage current in non-gating cells, resulting in complex device structure, increased process cost, increased array power consumption and decreased yield.

[0004] Furthermore, the vertical MIM type memristor has the following shortcomings in practical applications: First, the resistive switching process of the device often depends on the random nucleation and growth of conductive filaments or the local enrichment of defects / ions, resulting in the distribution of forming voltage, switching voltage, conduction current and resistive state between different devices, thus leading to a large degree of dispersion, which in turn affects the consistency and programmability of large-scale arrays; Second, the vertical stacking structure usually needs to obtain a lower operating voltage by thinning the dielectric layer or introducing a stronger electric field, but an excessively thin dielectric layer is prone to increased leakage current, decreased retention characteristics and deterioration of reliability, thus creating a contradiction between low voltage, low power consumption and long-term stability. Summary of the Invention

[0005] This invention provides a lateral heterojunction memristor that can help reduce leakage current and improve device selectivity in array applications.

[0006] This invention provides a lateral heterojunction memristor, comprising an insulating substrate, a composite layer, a metal active electrode, and an inert electrode. The composite layer is disposed on the insulating substrate and includes a GeO2 material region, a TiO2 material region, and an insulating material region. The GeO2 material region, TiO2 material region, and insulating material region form a heterojunction in the same plane, with the insulating material region separating the GeO2 material region and the TiO2 material region. The metal active electrode is disposed on the GeO2 material region. The inert electrode is disposed on the TiO2 material region.

[0007] Furthermore, the thickness of the GeO2 material region is 20nm-10000nm.

[0008] Furthermore, the thickness of the TiO2 material region is 20nm-10000nm.

[0009] Furthermore, the width of the insulating material region is 7nm-150nm.

[0010] Furthermore, the thickness of the insulating material region is 20nm-10000nm.

[0011] Furthermore, the thickness of the insulating material region is greater than or equal to the thickness of the GeO2 material region and the TiO2 material region.

[0012] Furthermore, the thickness of the GeO2 material region and the TiO2 material region is the same, while the thickness of the insulating material region is greater than the thickness of both the GeO2 material region and the TiO2 material region.

[0013] Furthermore, the insulating material region includes a barrier portion and an extension portion. The barrier portion is disposed between the GeO2 material region and the TiO2 material region, and the extension portion is disposed above the barrier portion, the GeO2 material region, and the TiO2 material region.

[0014] Furthermore, the metal active electrode includes an Ag electrode.

[0015] Furthermore, the inert electrode includes a Pt electrode.

[0016] The present invention has the following beneficial effects: (1) The partitioned structure of the composite layer can not only realize the resistance state switching of the memristor, but also effectively regulate the carrier transport through the middle insulating material region, thereby enhancing the nonlinearity and adjustability of the device's conductivity behavior, which is beneficial to reduce leakage current and improve device selectivity in array applications; and makes the resistance state transformation of the memristor no longer dependent on the formation and breakage of conductive filaments, but based on the capture and release of carriers in the insulating material region, which can effectively reduce material loss.

[0017] (2) GeO2 and TiO2 differ in electrical properties, defect behavior and carrier transport mechanism. When combined with an intermediate insulating material, they can form a more obvious barrier modulation effect and conductivity asymmetry in the plane, providing a structural and material basis for realizing the self-rectification characteristics and stable resistance switching of the device.

[0018] (3) The Ag electrode can provide mobile metal ions and participate in local conductivity regulation, while the Pt electrode is used as a stable counter electrode. The above electrode combination helps to enhance the conductivity state modulation capability of the device, improve the switching ratio, reduce power consumption, and further improve the directional selectivity and rectification characteristics of resistive switching behavior. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the elevation structure of the transverse heterojunction memristor in this invention; Figure 2 This is a schematic diagram of the overall structure of the transverse heterojunction memristor in this invention; Figure 3 This is a flowchart illustrating step S2 in the fabrication process of the lateral heterojunction memristor in this invention. Figure 4 This is a flowchart illustrating step S3 in the fabrication process of the lateral heterojunction memristor in this invention. Figure 5 This is a flowchart illustrating step S4 in the fabrication process of the lateral heterojunction memristor in this invention. Figure 6 This is a flowchart illustrating step S5 in the fabrication process of the lateral heterojunction memristor in this invention. Figure 7 This is a current density-source-drain voltage curve of a lateral heterojunction memristor with and without SiO2 material regions in this invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] See Figure 1-2 The present invention provides a lateral heterojunction memristor, comprising an insulating substrate, a composite layer, a metal active electrode, and an inert electrode.

[0022] The core function of the insulating substrate is to act as an electrical insulation support platform, ensuring that current flows only within the functional layer and preventing leakage current from flowing through the substrate. The insulating substrate can be a silicon dioxide (SiO2) substrate.

[0023] The composite layer is disposed on an insulating substrate. The composite layer includes a GeO2 material region, a TiO2 material region, and an insulating material region. The GeO2 material region, TiO2 material region, and insulating material region form a heterojunction in the same plane. The insulating material region separates the GeO2 material region and the TiO2 material region.

[0024] The GeO2 material region, also known as the GeO2 thin film region, plays a crucial role as one of the variable resistance media for ion / defect modulation. It provides a migration and nucleation environment for Ag ions, participating in the formation / breakage of conductive channels or modulating local conductivity. The thickness of the GeO2 material region ranges from 20nm to 10000nm (10μm), such as 20nm, 500nm, 1000nm, 5000nm, and 10000nm.

[0025] The TiO2 material region, also known as the TiO2 thin film region, serves as the other side of the resistive switching functional layer. It provides a relatively stable carrier transport channel and a tunable defect environment, and together with the intermediate SiO2 barrier region, determines the device's conductivity state and switching behavior, thereby enhancing conductivity asymmetry (self-rectification / nonlinearity) and improving switching consistency. The thickness of the TiO2 material region ranges from 20nm to 10000nm (10μm), such as 20nm, 500nm, 1000nm, 5000nm, and 10000nm. The thicknesses of the TiO2 and GeO2 material regions can be the same or different, but the difference should not be too large.

[0026] The core function of the insulating material region is to act as a barrier layer between GeO2 and TiO2, regulating the carrier transport process across the region and providing the structural basis for interface barrier modulation, defect trapping / release, and tunneling transport. The insulating material region can be SiO2, HfO2, or Al2O3. The width of the insulating material region should not be too large, typically ranging from 7nm to 150nm (e.g., 7nm, 50nm, 100nm, 150nm). The thickness of the insulating material region is typically 20nm to 10000nm (10μm) (e.g., 20nm, 500nm, 1000nm, 5000nm, 10000nm).

[0027] The thickness of the insulating material region can be greater than or equal to the thickness of the GeO2 material region and the TiO2 material region. Optionally, the thickness of the insulating material region is greater than the thickness of the GeO2 material region and the TiO2 material region. Specifically, the insulating material region includes a barrier portion and an extension portion, with the barrier portion disposed between the GeO2 material region and the TiO2 material region, and the extension portion disposed above the barrier portion, the GeO2 material region, and the TiO2 material region.

[0028] The metal active electrode is disposed on the GeO2 material region. The core function of the metal active electrode is to provide migratable metal ions. The metal active electrode can be an Ag electrode.

[0029] An inert electrode is placed on the TiO2 material region. The core function of the inert electrode is to not participate in dissolution and migration, serving as a reduction deposition / collection end. The inert electrode can be a Pt electrode or a TiN electrode.

[0030] In the lateral heterojunction memristor of the present invention, due to the differences in band structure, defect state distribution and carrier transport characteristics between GeO2, SiO2 and TiO2, carrier capture / release, barrier modulation and local conductive channel evolution can occur in the middle barrier region and the two side interfaces under the action of an external electric field, thereby realizing reversible resistive switching characteristics; at the same time, combined with the differences in work function and activity of Ag / Pt asymmetric electrodes, the device can be further endowed with certain rectification or self-rectification characteristics.

[0031] This invention provides a method for fabricating the above-mentioned lateral heterojunction memristor, comprising the following steps: Step S1: Clean and dry the insulating substrate.

[0032] In the above steps, the insulating substrate can be ultrasonically cleaned for 10 minutes with alcohol and deionized water respectively.

[0033] Step S2: Spin-coat a layer of photoresist onto the insulating substrate obtained in step S1. After exposure and development, the photoresist on the right half is removed. Then, deposit a TiO2 film. After that, peel off the photoresist, leaving only the TiO2 film on the right side.

[0034] In the above steps, TiO2 thin films can be deposited by adjusting the flow ratio of argon and oxygen using DC magnetron sputtering on a Ti target. Other methods, such as ALD and PLD, can also be used to deposit TiO2 thin films. See the above steps for details. Figure 3 .

[0035] Step S3: Spin-coat a layer of photoresist onto the insulating material obtained in step S2. After exposure and development, the photoresist on the left half is removed. Then, deposit a GeO2 film. After that, strip and remove the photoresist, leaving only the GeO2 film on the left side.

[0036] In the above steps, GeO2 thin films can be deposited by adjusting the flow rate ratio of argon to oxygen using DC magnetron sputtering on a Ge target. Other methods, such as ALD and PLD, can also be used to deposit GeO2 thin films. See the above steps for details. Figure 4 .

[0037] Step S4: Spin-coat a layer of photoresist onto the insulating layer obtained in step S3. After exposure and development, the photoresist at the junction of the TiO2 film and the GeO2 film is removed. Then, the junction of the TiO2 film and the GeO2 film is etched. After that, the photoresist is removed and a mask is attached to deposit insulating material at the junction of the TiO2 film and the GeO2 film.

[0038] In the above steps, SiO2 material can be deposited using an RF magnetron sputtering SiO2 target. Other methods, such as ALD and PLD, can also be used to deposit SiO2 material. Please refer to the above steps. Figure 5 .

[0039] Step S5: Attach a mask to the insulation obtained in step S4, deposit an inert electrode on the TiO2 thin film, and deposit a metal active electrode on the GeO2 thin film.

[0040] In the above steps, Pt and Ag electrodes can be sputtered using DC magnetron sputtering. See the above steps for details. Figure 6 .

[0041] Example 1 (Transverse heterojunction memristor with SiO2 material region) Step S1: Ultrasonically clean the insulating substrate with alcohol and deionized water for 10 minutes each, then dry it. Step S2: A layer of photoresist is spin-coated onto the insulating substrate obtained in step S1. After exposure and development, the photoresist on the right half is removed. Then, a 20nm thick TiO2 film is deposited by DC magnetron sputtering of a Ti target with the flow ratio of argon to oxygen adjusted. After that, the photoresist is removed by peeling, leaving only the TiO2 film on the right side.

[0042] Step S3: Spin-coat a layer of photoresist on the insulating material obtained in step S2. After exposure and development, the photoresist on the left half is removed. Then, deposit a 20nm thick GeO2 film by DC magnetron sputtering of a Ge target and adjusting the flow ratio of argon and oxygen. After that, peel off the photoresist, leaving only the GeO2 film on the left side.

[0043] Step S4: Spin-coat a layer of photoresist onto the insulating substrate obtained in step S3. After exposure and development, the photoresist at the interface between the TiO2 and GeO2 films is removed. Then, etch the interface between the TiO2 and GeO2 films. After removing the photoresist and attaching a mask, deposit a 150nm wide and 30nm thick SiO2 material at the interface between the TiO2 and GeO2 films using an RF magnetron sputtering SiO2 target.

[0044] Step S5: Attach a mask to the insulation obtained in step S4, and deposit a 20 nm thick Pt electrode on the TiO2 thin film by DC magnetron sputtering, and deposit a 20 nm thick Ag electrode on the GeO2 thin film by DC magnetron sputtering.

[0045] Comparative Example 1 (Transverse heterojunction memristor without SiO2 material region) Step S1: Ultrasonically clean the insulating substrate with alcohol and deionized water for 10 minutes each, then dry it. Step S2: A layer of photoresist is spin-coated onto the insulating substrate obtained in step S1. After exposure and development, the photoresist on the right half is removed. Then, a 20nm thick TiO2 film is deposited by DC magnetron sputtering of a Ti target with the flow ratio of argon to oxygen adjusted. After that, the photoresist is removed by peeling, leaving only the TiO2 film on the right side.

[0046] Step S3: Spin-coat a layer of photoresist on the insulating material obtained in step S2. After exposure and development, the photoresist on the left half is removed. Then, deposit a 20nm thick GeO2 film by DC magnetron sputtering of a Ge target and adjusting the flow ratio of argon and oxygen. After that, peel off the photoresist, leaving only the GeO2 film on the left side.

[0047] Step S4: Attach a mask to the insulation obtained in step S4, and deposit a 20 nm thick Pt electrode on the TiO2 thin film by DC magnetron sputtering, and deposit a 20 nm thick Ag electrode on the GeO2 thin film by DC magnetron sputtering.

[0048] Experimental Example 1 The current density-source-drain voltage curves of lateral heterojunction memristors with and without SiO2 material regions are shown in the figure. Figure 7 As shown.

[0049] Depend on Figure 7 It can be seen that the turn-on voltage of the lateral heterojunction memristor with SiO2 material region is negatively offset compared to the lateral heterojunction memristor without SiO2 material region.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A lateral heterojunction memristor, characterized in that, include: Insulating substrate; A composite layer is disposed on the insulating substrate. The composite layer includes a GeO2 material region, a TiO2 material region, and an insulating material region. The GeO2 material region, the TiO2 material region, and the insulating material region form a heterojunction in the same plane. The insulating material region separates the GeO2 material region and the TiO2 material region. A metal active electrode is disposed on the GeO2 material region; An inert electrode is disposed on the TiO2 material region.

2. The lateral heterojunction memristor as described in claim 1, characterized in that, The thickness of the GeO2 material region is 20nm-10000nm.

3. The lateral heterojunction memristor as described in claim 1, characterized in that, The thickness of the TiO2 material region is 20nm-10000nm.

4. The lateral heterojunction memristor as described in claim 1, characterized in that, The width of the insulating material region is 7nm-150nm.

5. The lateral heterojunction memristor as described in claim 1, characterized in that, The thickness of the insulating material region is 20nm-10000nm.

6. The lateral heterojunction memristor as described in claim 1, characterized in that, The thickness of the insulating material region is greater than or equal to the thickness of the GeO2 material region and the TiO2 material region.

7. The lateral heterojunction memristor as described in claim 6, characterized in that, The thickness of the GeO2 material region and the TiO2 material region are the same, and the thickness of the insulating material region is greater than the thickness of the GeO2 material region and the TiO2 material region.

8. The lateral heterojunction memristor as described in claim 7, characterized in that, The insulating material region includes a barrier portion and an extension portion. The barrier portion is disposed between the GeO2 material region and the TiO2 material region, and the extension portion is disposed above the barrier portion, the GeO2 material region, and the TiO2 material region.

9. The lateral heterojunction memristor as described in claim 1, characterized in that, The metal active electrode includes an Ag electrode.

10. The lateral heterojunction memristor as described in claim 1, characterized in that, The inert electrode includes a Pt electrode.

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