A semiconductor structure and a method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2026-07-10
- Publication Date
- 2026-08-07
AI Technical Summary
[0003]为了将RRAM集成进金属层间，多采用加厚RRAM当层金属通孔高度的方法使RRAM层高，这样不仅需要更新逻辑区域的电阻和寄生电容参数，还可能进一步提高金属填充的工艺难度，带来低良率风险
[0015]本申请提供一种半导体结构及其形成方法，通过对顶电极层的选择性刻蚀，可达到金属通孔的同样效果，并通过工艺中沉积量和研磨量的有效控制，达成存储区域与逻辑区域厚度兼容的目标；采用先沉积第一介质层然后刻蚀第一开口后再填充RRAM结构的工艺，并在此基础上增加了介质填充层作为保护，可有效避免传统金属刻蚀时对阻变层侧壁的损伤，并有效增强RRAM结构与其它器件的隔离效果，可以在不增加RRAM金属层总高度的前提下集成RRAM结构，可以不改变原有逻辑工艺的寄生电容和电阻，降低逻辑工艺风险难度。
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Resistive Random Access Memory (RRAM) has attracted widespread attention due to its small size and simple integration process. RRAM devices generally consist of a bottom electrode, a resistive switching layer, and a top electrode, and are typically integrated between multiple metal layers in subsequent processes, with the upper and lower electrodes connected through lower metal layers and upper vias.
[0003] To integrate RRAM into the metal layers, the height of the RRAM layer is often increased by thickening the metal vias in the RRAM layer. This not only requires updating the resistance and parasitic capacitance parameters of the logic region but may also further increase the difficulty of metal filling, leading to a risk of low yield. Furthermore, the current main process involves etching the RRAM before depositing and polishing the metal layer dielectric. This not only easily causes etching damage on the RRAM sidewalls but also easily creates dielectric voids in high aspect ratio cases, resulting in a height difference between the dielectric layer and the logic region. Insufficient polishing can easily lead to metal residue in the logic region. Summary of the Invention
[0004] This application provides a semiconductor structure and its formation method, which can integrate RRAM structure without increasing the total height of RRAM metal layer, and can reduce the parasitic capacitance and resistance of the original logic process without changing it, thereby reducing the risk and difficulty of logic process.
[0005] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, wherein a first metal layer is formed on the substrate surface of both the first region and the second region; forming a first dielectric layer on the substrate, wherein a first opening is formed in the first dielectric layer above the first metal layer in the first region; sequentially forming a bottom electrode layer, a resistive switching layer, and a top electrode layer on the bottom and sidewalls of the first opening until the first opening is filled, wherein the bottom electrode layer, the resistive switching layer, and the top electrode layer constitute a memory structure; etching the memory structure such that the top surface of the memory structure is lower than the surface of the first dielectric layer; forming a dielectric filling layer on the top surface of the memory structure; forming a second opening in the first region that penetrates the dielectric filling layer and exposes the top electrode layer, and simultaneously forming a third opening in the first dielectric layer in the second region; etching a portion of the top electrode layer along the second opening to form a fourth opening, and simultaneously etching the first dielectric layer at the bottom of the third opening to form a fifth opening that exposes the first metal layer in the second region; and forming a second metal layer in the second opening, the third opening, the fourth opening, and the fifth opening.
[0006] In some embodiments of this application, before forming the first dielectric layer on the substrate surface, the method further includes: sequentially forming a barrier layer and a second dielectric layer on the substrate surface, and a conductive layer that penetrates the second dielectric layer and the barrier layer and electrically connects the first metal layer to the first region, wherein the first dielectric layer is located on the surface of the second dielectric layer, the width of the first opening is greater than the width of the conductive layer, and the first opening exposes the conductive layer.
[0007] In some embodiments of this application, the top electrode layer includes a tantalum nitride layer and a titanium nitride layer sequentially located on the surface of the resistive switching layer.
[0008] In some embodiments of this application, the second opening exposes only the titanium nitride layer, and only the titanium nitride layer is etched when a portion of the top electrode layer is etched along the second opening.
[0009] In some embodiments of this application, a method for forming a second opening in the first region that penetrates the dielectric filling layer to expose the top electrode layer, and simultaneously forming a third opening in the first dielectric layer of the second region, includes: forming a patterned mask layer on the surface of the first dielectric layer, the patterned mask layer exposing the dielectric filling layer and a portion of the first dielectric layer in the second region respectively; and etching the dielectric filling layer and the first dielectric layer using the patterned mask layer as a mask to form the second opening and the third opening.
[0010] In some embodiments of this application, a method for etching a portion of the top electrode layer along the second opening to form a fourth opening, and simultaneously etching the first dielectric layer at the bottom of the third opening to form a fifth opening exposing the first metal layer of the second region, includes: forming a patterned photoresist layer on the surface of a patterned mask layer, the patterned photoresist layer defining the location of the fifth opening; performing an acid pickling process using the patterned photoresist layer as a mask, the acid pickling process consuming the patterned photoresist layer and partially etching the top electrode layer to form the fourth opening, and etching the first dielectric layer below the third opening to form the fifth opening; and removing the patterned mask layer.
[0011] Another aspect of this application provides a semiconductor structure, comprising: a substrate including a first region and a second region, wherein a first metal layer is formed on the surface of both the first and second regions; a first dielectric layer located on the substrate, wherein a first opening is formed in the first dielectric layer above the first metal layer in the first region, wherein a bottom electrode layer, a resistive switching layer, and a top electrode layer are sequentially formed on the bottom and sidewalls of the first opening, wherein the bottom electrode layer, the resistive switching layer, and the top electrode layer constitute a memory structure, wherein the top surface of the memory structure is lower than the surface of the first dielectric layer; a dielectric filling layer located on the top surface of the memory structure; a second opening penetrating the dielectric filling layer to expose the top electrode layer; a third opening located in the first dielectric layer of the second region; a fourth opening located below the second opening and extending into the top electrode layer; a fifth opening located in the first dielectric layer below the third opening to expose the first metal layer of the second region; and a second metal layer filling the second opening, the third opening, the fourth opening, and the fifth opening.
[0012] In some embodiments of this application, a barrier layer and a second dielectric layer are sequentially formed on the substrate surface, and a conductive layer of a first metal layer that penetrates the second dielectric layer and the barrier layer and is electrically connected to the first region is formed. The first dielectric layer is located on the surface of the second dielectric layer, and the width of the first opening is greater than the width of the conductive layer. The first opening exposes the conductive layer.
[0013] In some embodiments of this application, the top electrode layer includes a tantalum nitride layer and a titanium nitride layer sequentially located on the surface of the resistive switching layer.
[0014] In some embodiments of this application, the second opening exposes only the titanium nitride layer, and the fourth opening extends only into the titanium nitride layer.
[0015] This application provides a semiconductor structure and its formation method. By selectively etching the top electrode layer, the same effect as a metal via can be achieved. By effectively controlling the deposition and polishing amounts in the process, the goal of thickness compatibility between the storage region and the logic region can be achieved. The process of first depositing a first dielectric layer, then etching the first opening, and then filling the RRAM structure is adopted. On this basis, a dielectric filling layer is added as a protection, which can effectively avoid damage to the sidewalls of the resistive switching layer during traditional metal etching and effectively enhance the isolation effect between the RRAM structure and other devices. The RRAM structure can be integrated without increasing the total height of the RRAM metal layer. The parasitic capacitance and resistance of the original logic process can be maintained, reducing the risk and difficulty of the logic process. Attached Figure Description
[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein: Figure 1 This application provides a schematic diagram of the substrate structure in the method for forming a semiconductor structure according to some embodiments; Figure 2 This is a schematic diagram of the semiconductor structure forming method described in some embodiments of this application, in which a barrier layer, a second dielectric layer, and a conductive layer are formed on the surface of the substrate. Figure 3 This is a schematic diagram of the structure for forming a first dielectric layer and a first opening in a method for forming a semiconductor structure according to some embodiments of this application; Figure 4 This is a schematic diagram of the semiconductor structure forming a bottom electrode layer, a resistive switching layer, and a top electrode layer in a first opening in some embodiments of this application. Figure 5 This is a schematic diagram of the structure after grinding to remove the bottom electrode layer, resistive switching layer and top electrode layer above the surface of the first dielectric layer in the semiconductor structure formation method described in some embodiments of this application; Figure 6 This is a schematic diagram of a semiconductor structure formation method described in some embodiments of this application, in which the memory structure is etched so that its top surface is lower than the surface of the first dielectric layer. Figure 7 This is a schematic diagram of the structure for forming a dielectric filling layer in a method for forming a semiconductor structure according to some embodiments of this application; Figure 8 This is a schematic diagram of the structure of the patterned mask layer formed in the semiconductor structure formation method described in some embodiments of this application; Figure 9 This is a schematic diagram of the structure for forming the second and third openings in the semiconductor structure formation method described in some embodiments of this application; Figure 10 This is a schematic diagram of the structure of the patterned photoresist layer formed in the semiconductor structure formation method described in some embodiments of this application; Figure 11 This is a schematic diagram of the structure formed by performing an acid pickling process to form the fourth and fifth openings in a semiconductor structure formation method described in some embodiments of this application; Figure 12 This is a schematic diagram of the structure after removing the patterned mask layer in the semiconductor structure formation method described in some embodiments of this application; Figure 13 This is a schematic diagram of the structure after the formation of the second metal layer in the semiconductor structure formation method described in some embodiments of this application. Detailed Implementation
[0017] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0018] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.
[0019] Figures 1 to 13 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. The method for forming a semiconductor structure according to some embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0020] refer to Figure 1 As shown, a substrate 100 is provided, the substrate 100 including a first region 101 and a second region 102, and a first metal layer 110 is formed on the surface of the substrate 100 in both the first region 101 and the second region 102.
[0021] RRAM cells are typically integrated between a metal layer and an upper via in the metal interconnect structure of a back-end semiconductor fabrication process. In this application, the substrate 100 includes a semiconductor structure formed by a front-end process and a portion of the metal interconnect structure in the back-end process, wherein the first metal layer 110 is a metal layer in the metal interconnect structure of the back-end process.
[0022] In some embodiments of this application, the first region 101 is a storage region for integrating an RRAM structure; the second region 102 is a logic region for forming logic devices.
[0023] In some embodiments of this application, the material of the first metal layer 110 includes copper.
[0024] refer to Figure 2 As shown, a barrier layer 120 and a second dielectric layer 130, as well as a conductive layer 140 that penetrates the second dielectric layer 130 and the barrier layer 120 and electrically connects to the first metal layer 110 of the first region 101, are sequentially formed on the surface of the substrate 100.
[0025] In some embodiments of this application, the material of the barrier layer 120 includes silicon nitride or nitrogen-doped silicon carbide, etc. In some embodiments of this application, the material of the second dielectric layer 130 includes tetraethyl orthosilicate (TEOS) silicon oxide, etc.
[0026] In some embodiments of this application, the conductive layer 140 can be any suitable conductive material in the semiconductor field, such as copper, tungsten, titanium nitride, or tantalum nitride. Preferably, the conductive layer 140 is made of the same material as the subsequently formed bottom electrode layer, such as titanium nitride or tantalum nitride.
[0027] refer to Figure 3 As shown, a first dielectric layer 150 is formed on the substrate 100, and a first opening 151 is formed in the first dielectric layer 150 above the first metal layer 110 in the first region 101.
[0028] In some embodiments of this application, the first dielectric layer 150 is located on the surface of the second dielectric layer 130, the width of the first opening 151 is greater than the width of the conductive layer 140, and the first opening 151 exposes the conductive layer 140.
[0029] In other embodiments of this application, when no Figure 2 When the steps shown are not performed, i.e. when the barrier layer 120, the second dielectric layer 130, and the conductive layer 140 are not formed, the first dielectric layer 150 is directly located on the surface of the substrate 100, and the first opening 151 directly exposes the first metal layer 110.
[0030] In some embodiments of this application, the material of the first dielectric layer 150 includes a low dielectric constant material or an ultra-low dielectric constant material, such as fluorine-doped silicon oxide, organosilicon glass, aerogel, etc. To ensure sufficient allowance for subsequent polishing processes, the thickness of the first dielectric layer 150 should be approximately 500 to 1000 angstroms greater than that of the logic process.
[0031] refer to Figure 4 and Figure 5 As shown, a bottom electrode layer 161, a resistive switching layer 162, and a top electrode layer 163 are sequentially formed at the bottom and sidewall of the first opening 151 until the first opening 151 is filled. The bottom electrode layer 161, the resistive switching layer 162, and the top electrode layer 163 constitute a memory structure 160 (RRAM structure).
[0032] Specifically, refer to Figure 4 As shown, a bottom electrode layer 161, a resistive switching layer 162, and a top electrode layer 163 are sequentially formed on the bottom and sidewalls of the first opening 151 and on the surface of the first dielectric layer 150 until the first opening 151 is filled; Reference Figure 5As shown, the bottom electrode layer 161, resistive switching layer 162 and top electrode layer 163 above the surface of the first dielectric layer 150 are removed by chemical mechanical polishing.
[0033] In some embodiments of this application, the top electrode layer 163 includes a tantalum nitride layer 163a and a titanium nitride layer 163b sequentially located on the surface of the resistive switching layer 162.
[0034] In some embodiments of this application, the bottom electrode layer 161 includes any one or more inert electrode films such as titanium nitride, tantalum nitride, ruthenium (Ru), or yttrium (Y); the resistive switching layer 162 includes any one or more films such as hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum, and tantalum oxide; the top electrode layer 163 is a composite film of tantalum nitride and titanium nitride, wherein the final deposited layer is titanium nitride. The basic formation process of the RRAM cell is well known to those skilled in the art and will not be described in detail here.
[0035] refer to Figure 6 As shown, the memory structure 160 is etched so that the top surface of the memory structure 160 is lower than the surface of the first dielectric layer 150.
[0036] In some embodiments of this application, the memory structure 160 is selectively etched using a metal etching gas without damaging the first dielectric layer 150.
[0037] refer to Figure 7 As shown, a dielectric filling layer 170 is formed on the top surface of the memory structure 160. The top surface of the dielectric filling layer 170 is flush with the top surface of the first opening 151.
[0038] In some embodiments of this application, the material of the dielectric filling layer 170 includes insulating dielectric materials such as silicon nitride or silicon oxide.
[0039] refer to Figure 8 and Figure 9 As shown, a second opening 152 is formed in the first region 101, penetrating the dielectric filling layer 170 to expose the top electrode layer 163, while a third opening 153 is formed in the first dielectric layer 150 of the second region 102.
[0040] Specifically, refer to Figure 8 As shown, a patterned mask layer 180 is formed on the surface of the first dielectric layer 150, the patterned mask layer 180 exposing the dielectric filling layer 170 and a portion of the first dielectric layer 150 in the second region 102, respectively; Reference Figure 9As shown, the patterned mask layer 180 is used as a mask to etch the dielectric filling layer 170 and the first dielectric layer 150 to form the second opening 152 and the third opening 153. In some embodiments of this application, the materials of the dielectric filling layer 170 and the first dielectric layer 150 are selected such that the etching rate of the dielectric filling layer 170 is less than the etching rate of the first dielectric layer 150. For example, the material of the dielectric filling layer 170 is silicon nitride, and the material of the first dielectric layer 150 is silicon oxide. The etching rate of the dielectric filling layer 170 is less than the etching rate of the first dielectric layer 150, and with a certain amount of over-etching, the depth of the third opening 153 is greater than the depth of the second opening 152. Figure 9 The etching steps shown selectively etch silicon oxide and silicon nitride, but do not etch the top electrode layer 163, and Figure 9 The etching steps shown have a higher etching rate for silicon oxide than for silicon nitride.
[0041] In some embodiments of this application, the second opening 152 exposes only the titanium nitride layer 163b. The width of the second opening 152 is slightly smaller than the width of the titanium nitride layer 163b to avoid short-circuiting the top electrode layer 163 and the bottom electrode layer 161.
[0042] refer to Figures 10 to 12 As shown, a portion of the top electrode layer 163 is etched along the second opening 152 to form a fourth opening 154, while the first dielectric layer 150 at the bottom of the third opening 153 is etched to form a fifth opening 155 that exposes the first metal layer 110 of the second region 102.
[0043] Specifically, refer to Figure 10 As shown, a patterned photoresist layer 181 is formed on the surface of the patterned mask layer 180, and the patterned photoresist layer 181 defines the position of the fifth opening 155; Reference Figure 11 As shown, an acid etching process is performed using the patterned photoresist layer 181 as a mask. This process completely consumes the patterned photoresist layer 181 and partially etches the top electrode layer 163 to form the fourth opening 154, and etches the first dielectric layer 150 below the third opening 153 to form the fifth opening 155. The depth of the third opening 153 is also increased. (Reference) Figure 12 As shown, the patterned mask layer 180 is removed.
[0044] In some embodiments of this application, the materials of the top electrode layer 163 and the first dielectric layer 150 are selected to ensure that the pickling process has high selectivity for a portion of the top electrode layer 163 and the first dielectric layer 150, thereby removing only a portion of the top electrode layer 163 without damaging the resistive switching layer 162, and the corrosion rate of the portion of the top electrode layer 163 is lower than the corrosion rate of the first dielectric layer 150. For example, the top electrode layer 163 includes a tantalum nitride layer 163a and a titanium nitride layer 163b sequentially located on the surface of the resistive switching layer 162, the first dielectric layer 150 is made of silicon oxide, the pickling process has high selectivity for the titanium nitride layer 163b and the first dielectric layer 150, the pickling process does not lose the tantalum nitride layer 163a, and the corrosion rate of the titanium nitride layer 163b is lower than the corrosion rate of the first dielectric layer 150.
[0045] In some embodiments of this application, only the titanium nitride layer 163b is etched when a portion of the top electrode layer 163 is etched along the second opening 152.
[0046] In some embodiments of this application, the titanium nitride layer 163b may be partially or completely etched away, leaving only the tantalum nitride layer 163a.
[0047] refer to Figure 13 As shown, a second metal layer 190 is formed by filling the second opening 152, the third opening 153, the fourth opening 154, and the fifth opening 155.
[0048] In some embodiments of this application, the material of the second metal layer 190 includes conductive materials such as copper or tungsten.
[0049] This application provides a method for forming a semiconductor structure. By selectively etching the top electrode layer, the same effect as a metal via can be achieved. By effectively controlling the deposition and polishing amounts in the process, the goal of thickness compatibility between the storage region and the logic region can be achieved. The method adopts a process of first depositing a first dielectric layer, then etching the first opening, and then filling the RRAM structure. On this basis, a dielectric filling layer is added as a protection, which can effectively avoid damage to the sidewalls of the resistive switching layer during traditional metal etching and effectively enhance the isolation effect between the RRAM structure and other devices. The RRAM structure can be integrated without increasing the total height of the RRAM metal layer. The parasitic capacitance and resistance of the original logic process can be maintained, reducing the risk and difficulty of the logic process.
[0050] Embodiments of this application also provide a semiconductor structure, referencing Figure 13As shown, the system includes: a substrate 100, which includes a first region 101 and a second region 102, both of which have a first metal layer 110 formed on their surfaces; and a first dielectric layer 150 located on the substrate 100, wherein a first opening 151 is formed in the first dielectric layer 150 above the first metal layer 110 in the first region 101, and a bottom electrode layer 161, a resistive switching layer 162, and a top electrode layer 163 are sequentially formed on the bottom and sidewalls of the first opening 151, which together constitute a memory structure 160, wherein the top surface of the memory structure 160 is lower than... The first dielectric layer 150 has a surface; a dielectric filling layer 170 is located on the top surface of the memory structure 160; a second opening 152 penetrates the dielectric filling layer 170 to expose the top electrode layer 163; a third opening 153 is located in the first dielectric layer 150 of the second region 102; a fourth opening 154 is located below the second opening 152 and extends into the top electrode layer 163; a fifth opening 155 is located in the first dielectric layer 150 below the third opening 153 to expose the first metal layer 110 of the second region 102; and a second metal layer 190 fills the second opening 152, the third opening 153, the fourth opening 154, and the fifth opening 155.
[0051] In some embodiments of this application, the first region 101 is a storage region for integrating an RRAM structure; the second region 102 is a logic region for forming logic devices.
[0052] In some embodiments of this application, the material of the first metal layer 110 includes copper.
[0053] In some embodiments of this application, a barrier layer 120 and a second dielectric layer 130 are sequentially formed on the surface of the substrate 100, and a conductive layer 140 is formed through the second dielectric layer 130 and the barrier layer 120 to electrically connect the first metal layer 110 of the first region 101. The first dielectric layer 150 is located on the surface of the second dielectric layer 130, and the width of the first opening 151 is greater than the width of the conductive layer 140, and the first opening 151 exposes the conductive layer 140.
[0054] In some embodiments of this application, the material of the barrier layer 120 includes silicon nitride or nitrogen-doped silicon carbide, etc. In some embodiments of this application, the material of the second dielectric layer 130 includes tetraethyl orthosilicate (TEOS) silicon oxide, etc.
[0055] In some embodiments of this application, the conductive layer 140 can be any suitable conductive material in the semiconductor field, such as copper, tungsten, titanium nitride, or tantalum nitride. Preferably, the conductive layer 140 is made of the same material as the subsequently formed bottom electrode layer, such as titanium nitride or tantalum nitride.
[0056] In other embodiments of this application, when the barrier layer 120, the second dielectric layer 130, and the conductive layer 140 are not formed, the first dielectric layer 150 is directly located on the surface of the substrate 100, and the first opening 151 directly exposes the first metal layer 110.
[0057] In some embodiments of this application, the material of the first dielectric layer 150 includes a low dielectric constant material or an ultra-low dielectric constant material, such as fluorine-doped silicon oxide, organosilicon glass, aerogel, etc. To ensure sufficient allowance for subsequent polishing processes, the thickness of the first dielectric layer 150 should be approximately 500 to 1000 angstroms greater than that of the logic process.
[0058] In some embodiments of this application, the top electrode layer 163 may consist only of a tantalum nitride layer 163a located on the surface of the resistive switching layer 162, or it may further include a titanium nitride layer 163b located on the surface of the tantalum nitride layer 163a.
[0059] In some embodiments of this application, the bottom electrode layer 161 includes any one or more inert electrode films such as titanium nitride, tantalum nitride, ruthenium (Ru), or yttrium (Y); the resistive switching layer 162 includes any one or more films such as hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum, and tantalum oxide; the top electrode layer 163 is a composite film of tantalum nitride and titanium nitride, wherein the final deposited layer is titanium nitride. The basic formation process of the RRAM cell is well known to those skilled in the art and will not be described in detail here.
[0060] In some embodiments of this application, the material of the dielectric filling layer 170 includes insulating dielectric materials such as silicon nitride or silicon oxide.
[0061] In some embodiments of this application, the second opening 152 exposes only the titanium nitride layer 163b. The width of the second opening 152 is slightly smaller than the width of the titanium nitride layer 163b to avoid short-circuiting the top electrode layer 163 and the bottom electrode layer 161.
[0062] In some embodiments of this application, the fourth opening 154 extends only into the titanium nitride layer 163b.
[0063] In some embodiments of this application, the material of the second metal layer 190 includes conductive materials such as copper or tungsten.
[0064] This application provides a semiconductor structure and its formation method. By selectively etching the top electrode layer, the same effect as a metal via can be achieved. By effectively controlling the deposition and polishing amounts in the process, the goal of thickness compatibility between the storage region and the logic region can be achieved. The process of first depositing a first dielectric layer, then etching the first opening, and then filling the RRAM structure is adopted. On this basis, a dielectric filling layer is added as a protection, which can effectively avoid damage to the sidewalls of the resistive switching layer during traditional metal etching and effectively enhance the isolation effect between the RRAM structure and other devices. The RRAM structure can be integrated without increasing the total height of the RRAM metal layer. The parasitic capacitance and resistance of the original logic process can be maintained, reducing the risk and difficulty of the logic process.
[0065] In summary, after reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that the invention is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0066] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0067] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "containing," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0068] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0069] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, and a first metal layer is formed on the substrate surface of both the first region and the second region; A first dielectric layer is formed on the substrate, and a first opening is formed in the first dielectric layer above a first metal layer located in the first region. A bottom electrode layer, a resistive switching layer, and a top electrode layer are sequentially formed at the bottom and sidewalls of the first opening until the first opening is filled, wherein the bottom electrode layer, the resistive switching layer, and the top electrode layer constitute a memory structure. The memory structure is etched so that the top surface of the memory structure is lower than the surface of the first dielectric layer. A dielectric filling layer is formed on the top surface of the memory structure; A second opening is formed in the first region, penetrating the dielectric filling layer to expose the top electrode layer, while a third opening is formed in the first dielectric layer in the second region; A fourth opening is formed by etching a portion of the top electrode layer along the second opening, and a fifth opening is formed by etching the first dielectric layer at the bottom of the third opening to expose the first metal layer of the second region. A second metal layer is formed in the second opening, the third opening, the fourth opening, and the fifth opening.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first dielectric layer on the substrate surface, the method further includes: sequentially forming a barrier layer and a second dielectric layer on the substrate surface, and a conductive layer that penetrates the second dielectric layer and the barrier layer and electrically connects the first metal layer to the first region, wherein the first dielectric layer is located on the surface of the second dielectric layer, the width of the first opening is greater than the width of the conductive layer, and the first opening exposes the conductive layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top electrode layer includes a tantalum nitride layer and a titanium nitride layer sequentially located on the surface of the resistive switching layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The second opening exposes only the titanium nitride layer, and when etching a portion of the top electrode layer along the second opening, only the titanium nitride layer is etched.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a second opening in the first region that penetrates the dielectric filling layer to expose the top electrode layer, and simultaneously forming a third opening in the first dielectric layer of the second region, includes: forming a patterned mask layer on the surface of the first dielectric layer, the patterned mask layer exposing the dielectric filling layer and a portion of the first dielectric layer in the second region respectively; and etching the dielectric filling layer and the first dielectric layer using the patterned mask layer as a mask to form the second opening and the third opening.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, A method for etching a portion of the top electrode layer along the second opening to form a fourth opening, and simultaneously etching the first dielectric layer at the bottom of the third opening to form a fifth opening exposing the first metal layer of the second region, includes: forming a patterned photoresist layer on the surface of a patterned mask layer, the patterned photoresist layer defining the location of the fifth opening; performing an acid pickling process using the patterned photoresist layer as a mask, the acid pickling process consuming the patterned photoresist layer and partially etching the top electrode layer to form the fourth opening, and etching the first dielectric layer below the third opening to form the fifth opening; and removing the patterned mask layer.
7. A semiconductor structure, characterized in that, include: The substrate includes a first region and a second region, and a first metal layer is formed on the surface of both the first region and the second region. A first dielectric layer is located on the substrate. A first opening is formed in the first dielectric layer above a first metal layer in the first region. A bottom electrode layer, a resistive switching layer, and a top electrode layer are formed sequentially on the bottom and sidewalls of the first opening. The bottom electrode layer, the resistive switching layer, and the top electrode layer constitute a memory structure. The top surface of the memory structure is lower than the surface of the first dielectric layer. A dielectric filling layer is located on the top surface of the memory structure; The second opening penetrates the dielectric filling layer to expose the top electrode layer; The third opening is located in the first dielectric layer of the second region; The fourth opening is located below the second opening and extends into the top electrode layer; The fifth opening exposes the first metal layer of the second region within the first dielectric layer below the third opening; The second metal layer fills the second opening, the third opening, the fourth opening, and the fifth opening.
8. The semiconductor structure as described in claim 7, characterized in that, The substrate surface is further provided with a barrier layer and a second dielectric layer, and a conductive layer that penetrates the second dielectric layer and the barrier layer and is electrically connected to the first region. The first dielectric layer is located on the surface of the second dielectric layer. The width of the first opening is greater than the width of the conductive layer, and the first opening exposes the conductive layer.
9. The semiconductor structure as described in claim 7, characterized in that, The top electrode layer includes a tantalum nitride layer and a titanium nitride layer sequentially located on the surface of the resistive switching layer.
10. The semiconductor structure as described in claim 9, characterized in that, The second opening exposes only the titanium nitride layer, and the fourth opening extends only into the titanium nitride layer.