Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a semiconductor material layer; the semiconductor material layer comprises a doped region; forming a passivation layer on the semiconductor material layer; the passivation layer has a groove, and the groove exposes a top surface of the doped region; filling a metal material in the groove to form a metal layer; the melting point of the passivation layer is greater than that of the metal layer; and the metal layer is subjected to a thermal annealing treatment to form an ohmic contact between the metal layer and the doped region. The preparation method of the semiconductor structure provided by the application can ensure the consistency and stability of the pattern and thickness of the metal layer before and after thermal annealing, thereby improving the reliability of subsequent processes and reducing production costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the field of integrated circuit manufacturing, metallization technology plays a crucial role as a core process for achieving electrical connections between electronic components such as transistors, resistors, and capacitors, as well as signal transmission with external circuits. However, in the process of forming a stable ohmic contact between metal and semiconductor, high-temperature heat treatment of the metal is usually required to obtain a low contact resistance. This process can easily cause deformation of low-melting-point metals during annealing. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure and its preparation method to address the deformation problem of low-melting-point metals during annealing.

[0004] A method for fabricating a semiconductor structure includes: providing a semiconductor material layer; the semiconductor material layer including a doped region; forming a passivation layer on the semiconductor material layer; the passivation layer having trenches exposing the top surface of the doped region; filling the trenches with a metal material to form a metal layer; the melting point of the passivation layer being greater than the melting point of the metal layer; and performing a thermal annealing treatment on the metal layer to form an ohmic contact between the metal layer and the doped region.

[0005] In one embodiment, the passivation layer is a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer; the metal layer is a gold-tin alloy layer.

[0006] In one embodiment, the passivation layer is a silicon nitride layer; the gold-tin alloy layer has a gold mass fraction of 60%-80% and a tin mass fraction of 20%-40%.

[0007] In one embodiment, the ratio of the thickness of the passivation layer to the thickness of the metal layer is 1-1.2.

[0008] In one embodiment, the thickness of the metal layer is 1 μm-5 μm.

[0009] In one embodiment, forming the passivation layer on the semiconductor material layer includes: sequentially forming a passivation material layer and a patterned first photoresist layer on the semiconductor material layer; using the patterned first photoresist layer as a mask and the semiconductor material layer as an etch stop layer, etching the passivation material layer to form a passivation layer with trenches.

[0010] In one embodiment, the semiconductor material layer is a silicon substrate, and the passivation layer is a silicon nitride layer; when etching the passivation material layer, the etching gas is a fluorine-based gas.

[0011] In one embodiment, the metal layer is subjected to thermal annealing, which includes rapid thermal annealing of the metal layer in a nitrogen, argon atmosphere or a vacuum environment.

[0012] In one embodiment, the rapid thermal annealing is performed at an annealing temperature of 320°C-480°C, an annealing time of 15s-60s, and a heating rate of 50°C / s-150°C / s.

[0013] A semiconductor structure is prepared using the semiconductor structure preparation method described in any of the above embodiments.

[0014] The semiconductor structure fabrication method provided in this application first forms a passivation layer with trenches on a semiconductor material layer, and then fills the trenches with metal material to form a metal layer, wherein the melting point of the passivation layer is greater than that of the metal layer; thus, when the metal layer is subsequently subjected to thermal annealing to obtain a lower contact resistance, the passivation layer can act as a limiting structure to confine the metal layer inside the trenches, thereby limiting the deformation of the metal layer during thermal annealing, and ensuring a high degree of consistency and stability between the metal layer pattern and the design drawing after subsequent actual processing; in addition, by limiting the deformation of the metal layer during thermal annealing, the consistency of its thickness before and after thermal annealing can be ensured, thereby avoiding increased production costs due to process compensation.

[0015] In summary, the semiconductor structure fabrication method provided in this application can ensure the consistency and stability of the pattern and thickness of the metal layer before and after thermal annealing, thereby improving the reliability of subsequent processes and reducing production costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figures 1 to 7 A schematic diagram of the cross-sectional structure of a semiconductor structure during the fabrication process, provided for related technologies;

[0018] Figure 8 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0019] Figures 9 to 16This is a cross-sectional structural diagram of the semiconductor structure provided in the embodiments of this application during the fabrication process. Detailed Implementation

[0020] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0022] In this invention, numerical ranges are involved. Unless otherwise specified, the numerical ranges are considered continuous and include the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe features or characteristics, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included.

[0023] Figures 1 to 7 A cross-sectional structural diagram of a semiconductor structure during its fabrication process, provided for related technologies.

[0024] Please refer to Figures 1 to 7To achieve stable ohmic contact between the metal and semiconductor, the metallization process specifically includes the following steps: First, a semiconductor material layer 100 is provided, including doped regions 110; then, photoresist (PR) is coated on the semiconductor material layer 100, and photolithography processes such as exposure and development are performed to form a first patterned photoresist 111, which exposes the top surface of the doped regions 110; next, a metal material 202 (e.g., a gold-tin (AuSn) alloy) is deposited on the semiconductor material layer 100, covering the top surface of the doped regions 110 and the top surface of the first patterned photoresist 111; then, the first patterned photoresist 111 and the metal material 202 on the first patterned photoresist 111 are stripped off, and the remaining metal material 202 covering the top surface of the doped regions 110 forms a metal layer 220; then, the metal layer 220 is thermally annealed. Annealing (TA) is performed to form an ohmic contact between the metal layer 220 and the semiconductor material layer 100. Next, an insulating material 113 is deposited on the metal layer 220, covering the surface of the semiconductor material layer 100 not covered by the metal layer 220 and completely covering the metal layer 220. Then, photoresist is coated on the surface of the insulating material 113, and photolithography processes such as exposure and development are performed to form a second patterned photoresist 112. Finally, using the second patterned photoresist 112 as a mask, the insulating material 113 is etched to remove the insulating material 113 covering the metal layer 220 and expose the top surface of the metal layer 220. The remaining insulating material 113 forms an insulating layer 114 for achieving lateral electrical isolation of the metal layer 220.

[0025] It should be noted that the above process describes the metallization process using a gold-tin alloy (e.g., 202) as an example. However, compared to the high melting point of gold (Au), the gold-tin alloy begins to exhibit fluidity around 280°C and gradually forms ohmic contacts with other semiconductor materials. The quality of the ohmic contact is optimal at 500°C, with the contact resistance reaching its lowest value. Typically, the gold-tin alloy layer is annealed at 420°C to achieve a lower contact resistance. However, since the gold-tin alloy begins to exhibit fluidity around 280°C, this annealing temperature causes deformation in the pattern of the gold-tin alloy after heat annealing compared to before heat annealing (see details...). Figure 3 and Figure 4 Specifically, the neat metal lines of the gold-tin alloy become jagged, and the film thickness of the gold-tin alloy also decreases significantly. Furthermore, to obtain even lower contact resistance, an annealing temperature above 450°C is required for the gold-tin alloy, which further exacerbates the pattern deformation.

[0026] Based on this, embodiments of this application provide a method for fabricating a semiconductor structure. Figure 8 A schematic flowchart of a method for fabricating a semiconductor structure provided in this application embodiment is shown in the figure. The method for fabricating a semiconductor structure includes:

[0027] Step S101: Provide a semiconductor material layer; the semiconductor material layer includes doped regions;

[0028] Step S102: A passivation layer is formed on the semiconductor material layer; the passivation layer has trenches, and the trenches expose the top surface of the doped region;

[0029] Step S103: Fill the trench with metal material to form a metal layer; the melting point of the passivation layer is greater than the melting point of the metal layer;

[0030] Step S104: Perform thermal annealing on the metal layer to form an ohmic contact between the metal layer and the doped region.

[0031] The semiconductor structure fabrication method provided in this application first forms a passivation layer with trenches on a semiconductor material layer, and then fills the trenches with metal material to form a metal layer, wherein the melting point of the passivation layer is greater than that of the metal layer; thus, when the metal layer is subsequently subjected to thermal annealing to obtain a lower contact resistance, the passivation layer can act as a limiting structure to confine the metal layer inside the trenches, thereby limiting the deformation of the metal layer during thermal annealing, and ensuring a high degree of consistency and stability between the metal layer pattern and the design drawing after subsequent actual processing; in addition, by limiting the deformation of the metal layer during thermal annealing, the consistency of its thickness before and after thermal annealing can be ensured, thereby avoiding increased production costs due to process compensation.

[0032] In summary, the semiconductor structure fabrication method provided in this application can ensure the consistency and stability of the pattern and thickness of the metal layer before and after thermal annealing, thereby improving the reliability of subsequent processes and reducing production costs.

[0033] It should also be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0034] Figures 9 to 16 This is a cross-sectional structural diagram illustrating the semiconductor structure during fabrication as provided in the embodiments of this application. Below, in conjunction with... Figures 9 to 16 The preparation method of the semiconductor structure provided in the embodiments of this application and its beneficial effects are further described in detail.

[0035] First, please refer to Figure 9 Step S101 is executed to provide a semiconductor material layer 100; the semiconductor material layer 100 includes a doped region 110.

[0036] In some embodiments, the semiconductor material layer 100 may specifically be a semiconductor substrate, such as a silicon (Si) substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, or other suitable III-V group semiconductor substrates. In this application, the semiconductor material layer 100 is a silicon substrate.

[0037] In some specific embodiments, a doped region 110 is formed on the semiconductor material layer 100. The doped region 110 can be formed by doping processes such as ion implantation and thermal diffusion; specifically, by implanting dopants such as boron (B), phosphorus (P), and arsenic (As) into the semiconductor material layer 100, the conductivity of the material can be controlled, thereby forming a doped region 110 with low contact resistance. This doped region 110 is used to form an ohmic contact with the metal layer subsequently located on the top surface of the doped region 110. It should be noted that this application does not particularly limit the specific structure and morphology of the semiconductor material layer 100, which is not limited to a semiconductor substrate, but can also be a semiconductor thin film, semiconductor epitaxial layer, or other semiconductor device formed on a semiconductor substrate that needs to form an electrical contact with a metal layer. This application does not specifically limit this.

[0038] Then, please refer to Figures 10 to 12 In step S102, a passivation layer 210 is formed on the semiconductor material layer 100; the passivation layer 210 has trenches T, and the trenches T expose the top surface of the doped region 110.

[0039] In some embodiments, the specific steps of forming a passivation layer 210 on the semiconductor material layer 100 may include: sequentially forming a passivation material layer 201 and a patterned first photoresist layer 310 on the semiconductor material layer 100; using the patterned first photoresist layer 310 as a mask and the semiconductor material layer 100 as an etch stop layer, etching the passivation material layer 201 to form a passivation layer 210 with trenches T.

[0040] In some embodiments, please refer to Figure 10The passivation material layer 201 can be formed by depositing passivation materials such as silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiON) on the semiconductor material layer 100 through deposition processes such as physical vapor deposition (PVD), plasma enhanced physical vapor deposition (PEPVD), and chemical vapor deposition (CVD). Correspondingly, the passivation layer 210 formed after etching the passivation material layer 201 can be a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. In this application, the passivation layer 210 is a silicon nitride layer.

[0041] It is understandable that this application selects a silicon nitride layer as the passivation layer 210 because silicon nitride has high density and hardness, and can provide stable mechanical support at a relatively thin thickness. This ensures that the passivation layer 210 will not affect the stability and consistency of the metal layer's pattern and thickness due to deformation during subsequent heat treatment processes, thereby providing excellent lateral isolation and structural support for the subsequently formed metal layer and preventing electrical short circuits between adjacent metal lines.

[0042] In some embodiments, please refer to Figure 11 The patterned first photoresist layer 310 can be formed by coating photoresist on the passivation material layer 201 and performing photolithography processes such as exposure and development.

[0043] In some embodiments, please refer to Figure 12 The passivation material layer 201 can be etched using dry etching methods, such as plasma etching. In some specific embodiments, when etching the passivation material layer 201, an etching gas with a high etching selectivity relative to the semiconductor material layer 100 can be selected. Specifically, when the passivation material layer 201 is made of silicon nitride and the semiconductor material layer 100 is a silicon substrate, a fluorine-based gas can be selected as the etching gas; fluorine-based gases include, but are not limited to, carbon tetrafluoride (CHF4), trifluoromethane (CHF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), or any combination thereof. By reasonably controlling process parameters such as etching gas flow rate, RF power, cavity pressure, and substrate temperature, selective etching of the passivation material layer 201 can be achieved with a high etching selectivity, while effectively protecting the underlying semiconductor material layer 100 from etching damage.

[0044] In this way, the semiconductor material layer 100 can serve as an etch stop layer for the etch of the passivation material layer 201, ensuring that the etching process is essentially terminated when it reaches the surface of the semiconductor material layer 100, thereby improving the accuracy and repeatability of the etching process.

[0045] In some embodiments, after etching the passivation material layer 201, a trench T is formed on the passivation material layer 201, penetrating its top and bottom surfaces. Here, the trench T serves as a reserved window for subsequent deposition of metal material to form a metal layer. The trench T exposes the top surface of the doped region 110 in the semiconductor material layer 100, so that the doped region 110 and the metal layer form an ohmic contact.

[0046] In some embodiments, please refer to Figure 12 After forming the trench T, the semiconductor structure fabrication method also includes: removing the patterned first photoresist layer 310 through wet stripping, plasma ashing (such as oxygen plasma), reactive ion etching ashing, and other dry ashing processes. Specifically, wet stripping can be achieved by immersing in photoresist stripping solution or by ultrasonic-assisted stripping, so as to quickly remove the patterned first photoresist layer 310 without damaging the underlying material layer; dry ashing can be achieved by chemically reacting plasma with the photoresist to decompose the patterned first photoresist layer 310 into volatile substances, thereby achieving residue-free removal.

[0047] Next, please refer to Figures 13 to 15 In step S103, metal material 202 is filled into the trench T to form a metal layer 220; the melting point of the passivation layer 210 is greater than the melting point of the metal layer 220.

[0048] In some embodiments, please refer to Figure 13 Before filling the trench T with metal material 202, the method for fabricating the semiconductor structure further includes: forming a patterned second photoresist layer 320 on the passivation layer 210; specifically, the patterned second photoresist layer 320 can be formed by coating photoresist on the passivation layer 210 and performing photolithography processes such as exposure and development.

[0049] In some embodiments, please refer to Figure 14 The trench T is filled with metal material 202, which can be achieved through processes such as physical vapor deposition, plasma-enhanced physical vapor deposition, and sputtering.

[0050] In some embodiments, please refer to Figure 15 After filling the trench T with metal material 202, the method for fabricating the semiconductor structure may further include: removing the patterned second photoresist layer 320 located on the passivation layer 210 and the excess metal material 202 located on the patterned second photoresist layer 320; the remaining metal material 202 located in the trench T constitutes the metal layer 220. The metal layer 220 may also be referred to as a "metal electrode".

[0051] In some specific embodiments, wet etching can be used to remove the patterned second photoresist layer 320. Once the patterned second photoresist layer 320 is removed, the metal material 202 located on the patterned second photoresist layer 320 will also be removed along with the removal of the patterned second photoresist layer 320.

[0052] In some embodiments, before removing the patterned second photoresist layer 320, the method for fabricating the semiconductor structure further includes: coating a protective film (such as a photoresist or an organic polymer) onto the metal material 202 located in the trench T. This protective film can prevent the metal material 202 from being corroded or dissolved by a chemical solution.

[0053] In some embodiments, the metal layer 220 can be a low-melting-point metal, and the material of the metal layer 220 can be a pure metal such as tin (Sn), bismuth (Bi), indium (In), gallium (Ga), or an alloy such as gold-tin alloy, gold-indium (AuIn) alloy, or tin-bismuth (SnBi) alloy.

[0054] In some specific embodiments, the metal layer 220 can be a gold-tin alloy layer; wherein the mass fraction of gold in the gold-tin alloy layer can be 60%-80%, and the mass fraction of tin can be 20%-40%. In this application, the metal layer 220 is Au80Sn20. Au80Sn20 refers to a gold-tin alloy layer with a mass fraction of 80% gold and 20% tin, which is the standard and most mainstream AuSn solder in optoelectronics and semiconductor packaging. For example, in the fabrication process of photosensitive MEMS devices, Au80Sn20 metal material is usually selected as the binding material for realizing ohmic contacts and subsequent chip packaging in the device.

[0055] Understandably, gold-tin alloys, due to their high conductivity, good wettability, oxidation resistance, and fatigue resistance, perform exceptionally well in specific applications such as laser diodes (LDs) and hermetic packaging, significantly improving the performance and reliability of semiconductor structures.

[0056] In some embodiments, the melting point of the passivation layer 210 is greater than the melting point of the metal layer 220, and the melting point of the passivation layer 210 is greater than the annealing temperature set during subsequent thermal annealing.

[0057] Understandably, because the passivation layer 210 has a high melting point, it will not melt or deform during subsequent thermal annealing. This effectively fixes and constrains the position of the metal layer 220, preventing unnecessary deformation and thus effectively protecting the pattern and thickness of the metal layer 220 from high-temperature melting and deformation. This further improves the integrity and stability of the metal layer 220 during thermal annealing. Furthermore, the melting point of the passivation layer 210 is higher than the annealing temperature, which significantly reduces the risk of defects and damage to the passivation layer 210 during heat treatment, further enhancing the overall mechanical strength of the semiconductor structure.

[0058] In some embodiments, the thickness of the metal layer 220 is less than or equal to the thickness of the passivation layer 210. Specifically, the ratio of the thickness of the passivation layer 210 to the thickness of the metal layer 220 can be 1-1.2; for example, the ratio of the thickness of the passivation layer 210 to the thickness of the metal layer 220 can be 1, 1.05, 1.1, 1.15, or 1.2, etc.

[0059] It is understandable that by limiting the thickness of the metal layer 220 to be less than or equal to the thickness of the passivation layer 210, it can be ensured that the passivation layer 210 can effectively constrain the lateral flow and morphological deformation of the metal layer 220 during subsequent heat treatment, and maintain the stability and consistency of the pattern and thickness of the metal layer 220.

[0060] Furthermore, by limiting the thickness ratio of the passivation layer 210 to the metal layer 220 to 1-1.2, it can be ensured that the metal layer 220 is adequately protected during subsequent heat treatment. If the ratio of the passivation layer 210 to the metal layer 220 is too large, it may affect the integration density of the final semiconductor structure; conversely, if the ratio is too small, the metal layer 220 will be too thick, exceeding the protection range of the passivation layer 210, thus preventing the passivation layer 210 from effectively constraining the lateral flow and morphological deformation of the metal layer 220 during subsequent heat treatment. Therefore, a thickness ratio of 1-1.2 for the passivation layer 210 to the metal layer 220 can minimize the height of the semiconductor structure, optimize the overall layout of the semiconductor structure, reduce additional space occupation, and thus improve the overall integration density, while ensuring the stability and consistency of the metal layer 220 pattern and thickness.

[0061] In summary, the thickness of the metal layer 220 is less than or equal to the thickness of the passivation layer 210, and the thickness ratio of the passivation layer 210 to the metal layer 220 is 1-1.2. This not only effectively maintains the stability and consistency of the pattern and thickness of the metal layer 220, but also optimizes the integration density of the semiconductor structure.

[0062] In some specific embodiments, the thickness of the metal layer 220 can be 1μm-5μm; for example, the thickness of the metal layer 220 can be 1μm, 2μm, 3μm, 4μm, 5μm, etc. In the embodiments of this application, the thickness of the metal layer 220 is 3μm.

[0063] It should be noted that by depositing metal material 202 in the trench T after the passivation layer 210 is prepared, the metal layer 220 can not only limit the deformation of the metal layer 220 in the subsequent hot annealing process, thereby ensuring the high consistency and stability of the metal layer 220 pattern with the design drawing in the subsequent actual process, but also prevent the high temperature environment during the preparation of the passivation layer 210 from causing damage or deformation to the metal layer 220.

[0064] Finally, please refer to Figure 16 Step S104 is executed to perform thermal annealing on the metal layer 220 so that the metal layer 220 and the doped region 110 form an ohmic contact.

[0065] In some embodiments, the metal layer 220 is subjected to thermal annealing, specifically rapid thermal annealing (RTA) can be used to process the metal layer 220 so that the metal layer 220 forms an ohmic contact with the doped region 110.

[0066] Understandably, rapid thermal annealing can reach the required annealing temperature in a shorter time, effectively reducing thermal stress caused by prolonged high-temperature processing. Furthermore, rapid thermal annealing can significantly shorten annealing time and improve process efficiency, thereby simplifying the overall semiconductor structure manufacturing process and reducing production costs.

[0067] It is also understandable that rapid thermal annealing enables the formation of a high-quality ohmic contact between the metal layer 220 and the doped region 110. This is because rapid thermal annealing promotes atomic diffusion and recombination at the interface at high temperatures, resulting in a tight physical bond. This helps reduce the contact resistance between the metal layer 220 and the doped region 110. The formation of a low-resistance ohmic contact ensures efficient carrier transport between the metal layer 220 and the doped region 110, thereby improving the operating efficiency of the semiconductor structure.

[0068] In some embodiments, the metal layer 220 is subjected to thermal annealing, which includes rapid thermal annealing of the metal layer 220 in a nitrogen, argon atmosphere or a vacuum environment.

[0069] Understandably, different annealing atmospheres significantly affect the annealing effect and performance of the metal layer 220. For example, nitrogen atmosphere has good oxidation resistance, which can effectively prevent the surface oxidation of the metal layer 220 during annealing, avoid the formation of an oxide layer that would increase the contact resistance between the metal layer 220 and the doped region 110, and ensure the stability of the ohmic contact. Argon, as an inert gas, has more stable chemical properties, which not only plays an anti-oxidation protection role, but also reduces the adsorption of impurities on the surface of the metal layer 220 and improves the crystal quality of the metal layer 220. It is especially suitable for the annealing treatment of precious metal alloys such as gold-tin alloys and gold-indium alloys. A vacuum environment can completely avoid the interference of gas molecules on the annealing process, prevent impurities in the atmosphere from reacting chemically with the metal layer 220, and at the same time facilitate the diffusion and elimination of defects in the metal layer 220, further reducing the contact resistance.

[0070] In some embodiments, the annealing temperature of rapid thermal annealing can be 320℃-480℃, the annealing time can be 15s-60s, and the heating rate can be 50℃ / s-150℃ / s.

[0071] In some specific embodiments, the annealing temperature of rapid thermal annealing can be 320℃, 350℃, 380℃, 420℃, 450℃, 480℃, etc.; the annealing time can be 15s, 20s, 30s, 40s, 50s, 60s, etc.; and the heating rate can be 50℃ / s, 70℃ / s, 90℃ / s, 110℃ / s, 130℃ / s, 150℃ / s, etc.

[0072] It is understandable that the annealing temperature and annealing time can be adjusted according to the material adaptability of the metal layer 220. In this embodiment, the annealing temperature for rapid thermal annealing is limited to the range of 320℃-480℃. On the one hand, this avoids damage and deformation of the passivation layer 210 due to excessively high annealing temperatures, affecting the stability and consistency of the pattern and thickness of the metal layer 220. On the other hand, it avoids excessively low annealing temperatures, which would fail to fully activate the interfacial reaction between the metal layer 220 and the doped region 110, making it difficult to form a low-resistance ohmic contact. In this embodiment, the annealing time for rapid thermal annealing is limited to the range of 15s-60s. On the one hand, this avoids excessive grain growth and uneven grain size in the metal layer 220 due to excessively long annealing times, leading to increased contact resistance. On the other hand, it avoids insufficient annealing times, resulting in incomplete interfacial reaction between the metal layer 220 and the doped region 110, incomplete defect elimination, and failure to achieve the desired annealing effect.

[0073] It is also understood that the heating rate in this embodiment is limited to the range of 50℃ / s-150℃ / s. On the one hand, this avoids the problem of excessively rapid heating causing large thermal stress inside the metal layer 220, leading to cracking, detachment, or interface peeling between the metal layer 220 and the semiconductor material layer 100, which would increase contact resistance and even cause device failure. On the other hand, it avoids the problem of excessively slow heating causing accelerated oxidation on the surface of the metal layer 220 and failing to achieve the advantage of rapid thermal annealing in quickly eliminating defects in the metal layer 220, thus affecting the stability of contact resistance. Therefore, by reasonably controlling the heating rate, thermal stress can be reduced, ensuring that the metal layer 220 after rapid thermal annealing has low contact resistance.

[0074] In summary, the embodiments of this application provide an optimized ohmic contact process for low-melting-point alloys such as AuSn alloys. By confining the AuSn alloy within the pattern encapsulated by the passivation layer, deformation of the metal layer can be avoided, ensuring the consistency and stability of the metal layer pattern and the design pattern before and after rapid thermal annealing, maintaining the consistency of the film thickness before and after rapid thermal annealing and before and after metal material peeling, thereby ensuring the reliability of subsequent processes.

[0075] Furthermore, since the thickness of the metal layer remains unchanged, increased production costs due to process compensation can be avoided, effectively reducing production costs. For example, if the original technical solution planned to deposit a 1µm thick metal layer using the metallization process of related technologies, the thickness of the metal layer after thermal annealing deformation would become 0.7µm-0.8µm; however, using the semiconductor structure fabrication method provided in this application, the metal layer can be directly deposited at 0.7µm, saving approximately 30% of the cost.

[0076] Based on this, the present application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method in any of the above embodiments.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: A semiconductor material layer is provided; the semiconductor material layer includes doped regions; A passivation layer is formed on the semiconductor material layer; the passivation layer has trenches that expose the top surface of the doped region; The trench is filled with a metallic material to form a metal layer; the melting point of the passivation layer is greater than the melting point of the metal layer. The metal layer is subjected to thermal annealing to form an ohmic contact between the metal layer and the doped region.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The passivation layer is a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer; the metal layer is a gold-tin alloy layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The passivation layer is a silicon nitride layer; the gold-tin alloy layer has a gold mass fraction of 60%-80% and a tin mass fraction of 20%-40%.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The ratio of the thickness of the passivation layer to the thickness of the metal layer is 1-1.

2.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the metal layer is 1μm-5μm.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the passivation layer on the semiconductor material layer includes: A passivation material layer and a patterned first photoresist layer are sequentially formed on the semiconductor material layer; Using the patterned first photoresist layer as a mask and the semiconductor material layer as an etch stop layer, the passivation material layer is etched to form a passivation layer with trenches.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The semiconductor material layer is a silicon substrate, and the passivation layer is a silicon nitride layer; When etching the passivation material layer, the etching gas is a fluorine-based gas.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The metal layer is subjected to thermal annealing treatment, including rapid thermal annealing of the metal layer in a nitrogen, argon atmosphere or vacuum environment.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The rapid thermal annealing process involves an annealing temperature of 320℃-480℃, an annealing time of 15s-60s, and a heating rate of 50℃ / s-150℃ / s.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method according to any one of claims 1-9.

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