Dry etching method of a silicon dioxide dielectric film layer and semiconductor device

Abstract

The application provides a dry etching method for a silicon dioxide medium film layer, and the etching method comprises the following steps: providing a wafer with a mask, placing the wafer on an electrostatic chuck in a chamber; etching: introducing CF4, CHF3 and Ar into the chamber, the ratio of CF4, CHF3 and Ar is 1: (1.5-2.5): (5-8), the etching pressure in the chamber is 120 mtorr-180 mtorr, the radio frequency power is 600W-1000W, and the wafer is subjected to plasma etching. Through the synergistic control of the components and ratio of etching gas, the etching pressure and the radio frequency power in the etching process, the etching angle is controlled by avoiding the feature size deviation caused by shrinkage and affecting the balance between chemical etching and physical bombardment in the etching process, so that the etching deviation is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a dry etching method for silicon dioxide dielectric films and semiconductor devices. Background Technology

[0002] In the fabrication of silicon carbide (SiC) semiconductor power devices, dielectric masks are used to shield specific areas on the wafer, ensuring that processes such as etching or implantation only affect the selected areas and avoid impacting other parts. Furthermore, dielectric masks in SiC devices also protect the surface, preventing the formation of an inversion layer caused by charge movement in the oxide layer during passivation, ensuring the long-term stability and reliability of the device. Ideal feature dimensions have a significant impact on subsequent processes. Feature dimensions directly determine device performance parameters such as threshold voltage, on-resistance, and breakdown voltage. Therefore, controlling feature dimensions (CD) through dry etching is a crucial process in the fabrication of SiC power devices.

[0003] Capacitively Coupled Plasma (CCP) etching, due to its capacitive coupling characteristics, can provide higher ion energy, which is beneficial for the selective etching of dielectric materials. While the plasma density of CCP is relatively low, its high ion energy is advantageous for etching dielectric materials. Furthermore, the stronger physical etching component of CCP helps maintain etching perpendicularity, which is crucial for critical dimensional control in dielectric etching. Increasing the sidewall angle means reducing lateral etching during the process, which helps maintain smaller etching deviations. However, excessively large sidewall angles can lead to overly narrow bottoms for etched trenches or holes, affecting subsequent processes. Conversely, decreasing the sidewall angle increases lateral etching, potentially leading to larger feature sizes or even pattern collapse.

[0004] CN118280819A discloses an etching method and etching system, providing a structure to be etched, with a patterned mask layer covering the structure. Using the mask layer as a shield, an oxidizing gas is used to modify the exposed surface of the structure to be etched, forming a modified layer. Then, using the mask layer as a shield, an etching gas is used to remove the modified layer, forming trenches. In this way, by first forming the modified layer and then removing it to form trenches, almost no etching is performed on the unmodified structure to be etched, allowing etching to stop at an appropriate location and achieving precise control over the etching amount. Furthermore, since the trenches are formed by etching the modified layer, the unmodified structure to be etched is not over-etched, thus avoiding the formation of microtrenches, thereby reducing electrical damage and improving device performance.

[0005] In the prior art, the etching deviation of the silicon dioxide dielectric film layer in SiC devices is relatively large. Therefore, it is of great significance to provide an efficient and simple etching method for the silicon dioxide dielectric film layer. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a dry etching method for silicon dioxide dielectric films. This invention optimizes the etching process to solve the problem of large etching deviations in silicon dioxide dielectric films of SiC devices.

[0007] To achieve this objective, the present invention adopts the following technical solution: On one hand, the present invention provides a dry etching method for silicon dioxide dielectric films, the etching method comprising: providing a wafer with a mask, placing the wafer on an electrostatic chuck in a chamber; introducing CF4, CHF3, and Ar into the chamber, wherein the ratio of CF4, CHF3, and Ar is 1:(1.5-2.5):(5-8), and performing plasma etching on the wafer.

[0008] Preferably, the mask material is photoresist.

[0009] In the etching process provided by this invention, a mask is disposed on the silicon dioxide dielectric film layer of the wafer to be etched. The etching gas used is CF4, CHF3, and Ar, a combination that offers high selectivity for SiO2 etching. CF4 serves as the main etching gas, while CHF3 acts as a protective gas. During etching, CF4 decomposes to release fluorine radicals that react with silicon dioxide; a higher CF4 content results in a faster etching reaction rate. CHF3, after dissociation, forms a thick polymer layer on its surface, hindering the etching reaction. Therefore, a higher CHF3 proportion results in a more inclined etching angle. Ar enhances etching anisotropy through physical bombardment after dissociation. By optimizing the proportions of each component in the etching gas, the chemical etching and physical bombardment processes are controlled, thereby controlling the etching angle and reducing etching deviation.

[0010] Preferably, in the etching gas, the flow rate of CF4 is 15 sccm-25 sccm, the flow rate of CHF3 is 23 sccm-63 sccm, and the flow rate of Ar is 75 sccm-200 sccm.

[0011] Preferably, when plasma etching is performed on the wafer, the etching pressure in the chamber is 120 mtorr-180 mtorr.

[0012] Etching pressure directly affects the ratio of ions to free radicals during the etching process. Low pressure leads to physical etching dominance but poor etching uniformity; high pressure leads to chemical etching dominance. Optimizing the chamber pressure controls the balance between physical bombardment and chemical etching, thereby reducing etching deviation.

[0013] Preferably, the time for plasma etching of the wafer is 280s-340s.

[0014] Preferably, the radio frequency power for plasma etching of the wafer is 600W-1000W.

[0015] Radio frequency (RF) power directly affects plasma density and ion energy; increasing RF power can directly enhance physical bombardment. However, this can lead to excessively high plasma temperatures on the wafer surface, causing feature size shifts due to resist shrinkage during the process, resulting in uncontrollable etching deviations. By optimizing RF power, feature size shifts can be avoided, and physical bombardment can be controlled, reducing etching deviations.

[0016] Preferably, the temperature of the electrostatic chuck in the pretreatment is 10-20℃.

[0017] Preferably, the chamber is the chamber of a capacitively coupled plasma etching device.

[0018] In this invention, the etching of SiO2 dielectric film requires higher selectivity for the dielectric material and higher energy ions. The capacitively coupled plasma etching method used in this invention is more suitable for etching SiO2 dielectric film and maintaining the verticality of the etching.

[0019] Preferably, the etching method includes: A wafer with a photoresist mask is provided; the wafer is placed on an electrostatic chuck that has been kept at a constant temperature of 10-20°C in the chamber of a capacitive plasma etching apparatus. CF4, CHF3, and Ar are introduced into the chamber in a ratio of 1:(1.5-2.5):(5-8). The flow rate of CF4 is 15-25 sccm, the flow rate of CHF3 is 23-63 sccm, and the flow rate of Ar is 75-200 sccm. The etching pressure in the chamber is 120-180 mtorr. Plasma etching is performed on the wafer for a time of 280-340 s and a radio frequency power of 600-1000 W.

[0020] This invention reduces etching deviation by synergistically controlling the composition and proportion of etching gas, etching pressure, and radio frequency power during the etching process. This avoids feature size shifts caused by shrinkage and affects the balance between chemical etching and physical bombardment during the etching process, thereby controlling the etching angle.

[0021] In a second aspect, the present invention provides a semiconductor device, which is obtained by etching using the etching method described in the first aspect.

[0022] Compared with the prior art, the present invention has the following beneficial effects: This invention involves etching a wafer with a mask, using CF4, CHF3, and Ar etching gases, depending on the materials of the dielectric film and the mask. By avoiding feature size shifts caused by resin shrinkage and controlling the etching angle to balance the chemical etching and physical bombardment processes, etching deviations are reduced. Attached Figure Description

[0023] Figure 1 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 1.

[0024] Figure 2 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 2.

[0025] Figure 3 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 3.

[0026] Figure 4 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 4.

[0027] Figure 5 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 5.

[0028] Figure 6 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 6.

[0029] Figure 7 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 7.

[0030] Figure 8 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 8.

[0031] Figure 9 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Example 9.

[0032] Figure 10 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Comparative Example 1.

[0033] Figure 11 This is a scanning electron microscope (SEM) image of the trenches obtained by etching in Comparative Example 2.

[0034] Figure 12 This is a scanning electron microscope (SEM) image of the trench obtained by etching in Comparative Example 3. Detailed Implementation

[0035] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms “comprising” and “having” and any variations thereof in this invention are intended to cover non-exclusive inclusion.

[0037] In the description of this invention, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this invention, "a plurality of" means two or more, unless otherwise explicitly defined.

[0038] For example, it can include, but is not limited to, the listed values; other unlisted values ​​within the range are also applicable.

[0039] In one specific embodiment, the present invention provides a dry etching method for a silicon dioxide dielectric film, the etching method comprising: providing a wafer with a mask, placing the wafer on an electrostatic chuck in a cavity; introducing CF4, CHF3, and Ar into the cavity, wherein the ratio of CF4, CHF3, and Ar is 1:(1.5-2.5):(5-8), and performing plasma etching on the wafer. The mask is made of photoresist.

[0040] In the etching process provided by this invention, a mask is disposed on the silicon dioxide dielectric film layer of the wafer to be etched. The etching gas used is CF4, CHF3, and Ar, a combination that offers high selectivity for silicon dioxide etching. CF4 serves as the main etching gas, while CHF3 acts as a protective gas. During etching, CF4 decomposes to release fluorine radicals that react with silicon dioxide; a higher CF4 content results in a faster etching reaction rate. CHF3, after dissociation, forms a thick polymer layer on the surface, hindering the etching reaction. Therefore, a higher CHF3 proportion results in a more inclined etching angle. Ar enhances etching anisotropy through physical bombardment after dissociation. By optimizing the proportions of each component in the etching gas, the chemical etching and physical bombardment processes are controlled, thereby controlling the etching angle and reducing etching deviation.

[0041] In some implementations, the flow rate of CF4 in the etching gas is 15 sccm-25 sccm, the flow rate of CHF3 is 23 sccm-63 sccm, and the flow rate of Ar is 75 sccm-200 sccm.

[0042] The flow rate of the etching gas directly affects the etching reaction rate. In addition, the flow rate of the etching gas affects the formation and concentration of etching byproducts such as silicon tetrafluoride, which in turn affects the etching reaction rate.

[0043] In some embodiments, the etching pressure during plasma etching of the wafer is 120 mtorr-180 mtorr. For example, it can be 120 mtorr, 130 mtorr, 140 mtorr, 150 mtorr, 160 mtorr, 170 mtorr, or 180 mtorr, including but not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0044] Etching pressure directly affects the ratio of ions to free radicals during the etching process. Lower pressure results in physical etching being dominant but with poor etching uniformity, while higher pressure results in chemical etching being dominant. Optimizing the chamber pressure controls the balance between physical bombardment and chemical etching, thereby reducing etching deviation.

[0045] In some implementations, the time for plasma etching of the wafer is 280s-340s. For example, it can be 280s, 290s, 300s, 310s, 320s, 330s, 340s, and other values ​​not listed, including but not limited to the values ​​listed. Other unlisted values ​​within the range are also applicable.

[0046] In some implementations, the radio frequency power for plasma etching of the wafer is 600W-1000W. For example, it can be 600W, 700W, 800W, 900W, 1000W, including but not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0047] Radio frequency (RF) power directly affects plasma density and ion energy; increasing RF power can directly enhance physical bombardment. However, this can lead to excessively high wafer surface temperatures, causing feature size shifts due to resin shrinkage and resulting in excessive etching deviations. Optimizing RF power can avoid feature size shifts, control physical bombardment, and reduce etching deviations.

[0048] In some embodiments, the temperature of the electrostatic chuck during pretreatment is 10-20°C. For example, it can be 10°C, 11°C, 12°C, 13°C, 14°C, 15°C, 16°C, 17°C, 18°C, 19°C, or 20°C, including but not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0049] In some implementations, the chamber is the chamber of a capacitively coupled plasma etching apparatus.

[0050] In this invention, the etching of silicon dioxide dielectric films requires higher selectivity for the dielectric material and higher energy ions. The capacitively coupled plasma etching method used in this invention is more suitable for etching silicon dioxide dielectric films and maintaining the verticality of the etching.

[0051] In some embodiments, the etching method includes: A wafer with a photoresist mask is provided, and the wafer is placed on an electrostatic chuck set at a constant temperature of 10-20°C in the chamber of a capacitive plasma etching equipment. Etching gases CF4, CHF3, and Ar are introduced into the chamber, with the ratio of CF4, CHF3, and Ar being 1:(1.5-2.5):(5-8). The flow rate of CF4 is 15-25 sccm, the flow rate of CHF3 is 23-63 sccm, and the flow rate of Ar is 75-200 sccm. The pressure inside the chamber is 120-180 mtorr. Plasma etching is performed on the wafer for 280-340 s, and the radio frequency power of the plasma etching is 600-1000 W.

[0052] This invention reduces etching deviation by synergistically controlling the composition and proportion of etching gas, etching pressure, and radio frequency power during the etching process. This avoids feature size shifts caused by shrinkage and affects the balance between chemical etching and physical bombardment during the etching process, thereby controlling the etching angle.

[0053] In another specific embodiment, the present invention provides a semiconductor device, which is obtained by etching using the etching method described in the first aspect.

[0054] Example 1 This embodiment provides a dry etching method for silicon dioxide dielectric films, the etching method including: (1) Provide a wafer with a photoresist mask material and place the wafer on an electrostatic chuck set at 15°C in the chamber of a capacitor plasma etching equipment; (2) Etching gases CF4, CHF3 and Ar are introduced into the chamber. The ratio of CF4, CHF3 and Ar is 1:2:6. The flow rate of CF4 is 20 sccm, the flow rate of CHF3 is 40 sccm and the flow rate of Ar is 120 sccm. The pressure in the chamber is maintained at 150 mtorr. The wafer is subjected to plasma etching for 300 s. The radio frequency power of the plasma etching is 800 W.

[0055] Example 2 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for the radio frequency power of 600W in the plasma etching step (2), the etching method is the same as that in Embodiment 1.

[0056] Example 3 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for the radio frequency power of 1000W in the plasma etching step (2), the etching method is the same as that in Embodiment 1.

[0057] Example 4 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for step (2), in which the ratio of CF4, CHF3 and Ar is 1:1.6:7.6, the flow rate of CF4 is 18 sccm, the flow rate of CHF3 is 29 sccm and the flow rate of Ar is 137 sccm, the rest of the etching method is the same as in embodiment 1.

[0058] Example 5 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for step (2), in which the ratio of CF4, CHF3 and Ar is 1:2.4:5.5, the flow rate of CF4 is 22 sccm, the flow rate of CHF3 is 53 sccm and the flow rate of Ar is 121 sccm, the rest of the etching method is the same as in embodiment 1.

[0059] Example 6 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for step (2), in which the pressure inside the chamber is maintained at 120 mtorr, the etching method is the same as in embodiment 1.

[0060] Example 7 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for step (2), in which the pressure inside the chamber is maintained at 180 mtorr, the etching method is the same as in embodiment 1.

[0061] Example 8 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for the plasma etching time of 280s in step (3), the etching method is the same as that in embodiment 1.

[0062] Example 9 This embodiment provides a dry etching method for silicon dioxide dielectric films. Except for the plasma etching time of 340s in step (3), the etching method is the same as that in embodiment 1.

[0063] Comparative Example 1 In this comparative example, the dry etching method for the silicon dioxide dielectric film is the same as that in Comparative Example 1, except that the radio frequency power of the plasma etching in step (3) is 1200W.

[0064] Comparative Example 2 In this comparative example, the dry etching method for the silicon dioxide dielectric film is the same as that in Comparative Example 1, except that the radio frequency power of plasma etching in step (3) is 400W.

[0065] Comparative Example 3 In this comparative example, the dry etching method for the silicon dioxide dielectric film is the same as in Example 1, except that in step (3), the ratio of CF4, CHF3 and Ar is 1:3:10, the flow rate of CF4 is 30 sccm, the flow rate of CHF3 is 90 sccm and the flow rate of Ar is 300 sccm.

[0066] The morphology of the wafers etched in Examples 1-9 and Comparative Examples 1-3 was measured using scanning electron microscopy (SEM), and the morphology images are shown below. Figure 1-12 As shown in Table 1, the feature size and sidewall tilt angle after etching are shown in Table 1. Wherein, CD deviation = bottom CD after etching - ADI, CD deviation represents the magnitude of the feature size CD offset after etching, and ADI is the mask size before etching after photolithography and development.

[0067] Table 1 Example 1 1390 1310 1420 88.1 88.4 30 Example 2 1380 1300 1470 86.3 87.0 90 Example 3 1390 1300 1440 87.3 87.2 50 Example 4 1390 1320 1420 87.4 88.0 30 Example 5 1390 1310 1470 87.3 86.6 80 Example 6 1390 1310 1500 86.4 86.5 110 Example 7 1390 1310 1430 87.5 87.8 40 Example 8 1380 1300 1500 87.2 87.3 120 Example 9 1390 1310 1440 87.2 87.6 50 Comparative Example 1 1390 1230 1340 88.3 88.5 -50 Comparative Example 2 1380 1310 1530 86.5 86.7 150 Comparative Example 3 1390 1330 1650 84.3 84.8 260

[0068] According to the test results in Table 1, this invention reduces etching deviation by coordinating the composition and ratio of etching gas, etching pressure and radio frequency power during the etching process. This avoids feature size shifts caused by shrinkage and affects the balance between chemical etching and physical bombardment during the etching process, thereby controlling the etching angle.

[0069] As can be seen from Examples 1-3 and Comparative Examples 4-5, the radio frequency power significantly affects the bottom CD of the photoresist mask. For example, in Comparative Example 1, if the radio frequency power is too high, both the top CD and the bottom CD after etching are significantly smaller than ADI, the CD deviation becomes negative, the bottom CD of the photoresist mask is significantly reduced, the sidewall angle becomes steeper, the etching is over-etched, and the photoresist shrinks. In Comparative Example 2, if the radio frequency power is too low, the bottom CD after etching is significantly increased, the sidewall angle becomes more inclined, the CD deviation increases, and the etching is insufficient.

[0070] As shown in Examples 1, 4, and 5 and Comparative Example 3, the CHF3 gas ratio affects the bottom CD of the photomask and the tilt angle after etching. When the ratio of CHF3 to Ar is 1:(1.5-2.5):(5-8), the CD offset is relatively small. In Comparative Example 3, the CHF3 gas ratio is too small, resulting in a significant increase in the bottom CD after etching and an increased CD deviation.

[0071] As can be seen from Examples 1 and 6-9, the chamber pressure and etching time affect the magnitude of CD deviation, but within the range of radio frequency power and etching gas composition in this invention, the CD deviation remains within a small range.

[0072] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A dry etching method for a silicon dioxide dielectric film, characterized in that, The etching method includes: A wafer with a mask is provided, and the wafer is placed on an electrostatic chuck in a chamber; CF4, CHF3, and Ar are introduced into the chamber in a ratio of 1:(1.5-2.5):(5-8) to perform plasma etching on the wafer.

2. The etching method as described in claim 1, characterized in that, The mask is made of photoresist.

3. The etching method as described in claim 1, characterized in that, In the etching gas, the flow rate of CF4 is 15 sccm-25 sccm, the flow rate of CHF3 is 23 sccm-63 sccm, and the flow rate of Ar is 75 sccm-200 sccm.

4. The etching method as described in claim 1, characterized in that, When plasma etching is performed on the wafer, the etching pressure in the chamber is 120 mtorr-180 mtorr.

5. The etching method as described in claim 1, characterized in that, The time for plasma etching of the wafer is 280s-340s.

6. The etching method as described in claim 1, characterized in that, The radio frequency power for plasma etching of the wafer is 600W-1000W.

7. The etching method as described in claim 1, characterized in that, The temperature of the electrostatic chuck in the pretreatment is 10-20℃.

8. The etching method as described in claim 1, characterized in that, The chamber is the chamber of a capacitively coupled plasma etching device.

9. The etching method as described in claim 1, characterized in that, The etching method includes: A wafer with a photoresist mask is provided, and the wafer is placed on an electrostatic chuck at 10-20°C in the chamber of a capacitive plasma etching apparatus. CF4, CHF3, and Ar are introduced into the chamber in a ratio of 1:(1.5-2.5):(5-8). The flow rate of CF4 is 15-25 sccm, the flow rate of CHF3 is 23-63 sccm, and the flow rate of Ar is 75-200 sccm. The etching pressure in the chamber is 120-180 mtorr. Plasma etching is performed on the wafer for a time of 280-340 s and a radio frequency power of 600-1000 W.

10. A semiconductor device, characterized in that, The wafer with the mask is obtained by etching using the etching method described in any one of claims 1 to 9.

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