Test structure and test method

Abstract

The application provides a test structure and a test method. The test structure comprises at least two stacked substrates, different substrates have the same type, and first, second, third and fourth interconnection structures insulated from each other are formed in the substrates. When the contact resistance of a to-be-tested conductive structure is tested, a current loop is formed between the first and second interconnection structures through a first auxiliary interconnection structure, the to-be-tested conductive structure, a first conductive switch layer and a first conductive trace layer and / or a second conductive trace layer, and a voltage test loop is formed between the third and fourth interconnection structures through a second auxiliary interconnection structure, the to-be-tested conductive structure, a second conductive switch layer and a third conductive trace layer and / or a fourth conductive trace layer. The technical scheme of the application improves the test accuracy of the contact resistance of the to-be-tested conductive structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a test structure and test method. Background Technology

[0002] In a typical three-dimensional stacked structure, all wafers are of the same type. When performing WAT (Wafer Acceptance Test) on the three-dimensional stacked structure using the Kelvin four-terminal method, the interconnect structure corresponding to one current application terminal and one voltage test terminal of the test structure within each wafer is electrically connected. This results in a first current loop and a voltage test loop being formed between the two current application terminals and the two voltage test terminals of the test structure, respectively, through the interconnect structure within the wafer, the conductive structure under test (such as the conductive structure of the via through the substrate in the wafer), and the redistribution layer between two adjacent wafers. Furthermore, a second current loop is also formed between one current application terminal and one voltage test terminal through the interconnect structure within two adjacent wafers and the redistribution layer between two adjacent wafers. The first current loop and the second current loop are connected in parallel, which introduces test noise (i.e., a portion of the applied current is diverted by the noise resistor), leading to inaccurate test results for the contact resistance of the conductive structure under test. Summary of the Invention

[0003] The purpose of this invention is to provide a test structure and test method that improves the accuracy of testing the contact resistance of the conductive structure under test.

[0004] To achieve the above objectives, the present invention provides a test structure, comprising:

[0005] At least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure and a fourth interconnect structure that are phase-insulated are formed in the substrates;

[0006] A first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrate or between two adjacent substrates;

[0007] A redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates. The redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively.

[0008] The conductive structure to be tested is formed in the substrate or between two adjacent substrates;

[0009] A first conductive switch layer and a second conductive switch layer are formed in one or both of the substrates, between two adjacent substrates, and on one side of the at least two stacked substrates, such that when testing the contact resistance of the conductive structure under test, a current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer, and a voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer.

[0010] Optionally, the first interconnect structures, the second interconnect structures, the third interconnect structures, and the fourth interconnect structures in different substrates are electrically connected to each other.

[0011] Optionally, when the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed in the substrate, the first auxiliary interconnect structure in different substrates is the same and the second auxiliary interconnect structure in different substrates is the same; when the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed between two adjacent substrates, the first auxiliary interconnect structure and the second auxiliary interconnect structure between any two adjacent substrates are the same as the first auxiliary interconnect structure and the second auxiliary interconnect structure between any other two adjacent substrates.

[0012] Optionally, the test structure further includes:

[0013] A hybrid bonding layer includes two bonded first dielectric layers and a conductive bonding structure penetrating the two first dielectric layers;

[0014] Wherein, when a redistribution layer is formed between two adjacent substrates, the hybrid bonding layer is formed between the redistribution layer and one of the two adjacent substrates, and the first interconnection structure, the second interconnection structure, the third interconnection structure and the fourth interconnection structure in one of the two adjacent substrates are electrically connected to the first conductive trace layer, the second conductive trace layer, the third conductive trace layer and the fourth conductive trace layer in the redistribution layer through the conductive bonding structure;

[0015] When two redistribution layers are formed between two adjacent substrates, the hybrid bonding layer is formed between the two redistribution layers between the two adjacent substrates, and the first conductive routing layer, the second conductive routing layer, the third conductive routing layer, and the fourth conductive routing layer in the two redistribution layers are electrically connected through the conductive bonding structure respectively;

[0016] When the redistribution layer is formed on one side of the at least two stacked substrates, the hybrid bonding layer is formed between two adjacent substrates, and the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure in the two adjacent substrates are electrically connected through the conductive bonding structure.

[0017] Optionally, the substrate includes a substrate and an interlayer dielectric layer formed on the substrate, wherein the first interconnect structure, the second interconnect structure, the third interconnect structure and the fourth interconnect structure are formed in the interlayer dielectric layer.

[0018] Optionally, a through-hole conductive structure is further formed in the substrate, and when the substrate is closer to the redistribution layer than the interlayer dielectric layer, the first interconnect structure, the second interconnect structure, the third interconnect structure and the fourth interconnect structure are electrically connected to the first conductive trace layer, the second conductive trace layer, the third conductive trace layer and the fourth conductive trace layer respectively through the through-hole conductive structure.

[0019] Optionally, the first conductive trace layer, the second conductive trace layer, the third conductive trace layer, and the fourth conductive trace layer each include a second metal layer, or include at least one second metal layer and at least one second conductive plug electrically connected to the second metal layer.

[0020] Optionally, the conductive structure under test includes a conductive bonding structure penetrating the two first dielectric layers; when the first conductive switching layer and the second conductive switching layer are formed between two adjacent substrates, and a redistribution layer is formed between the two adjacent substrates,

[0021] In the current loop, the first interconnect structure in one of two adjacent substrates is electrically connected to the conductive bonding structure under test via a first auxiliary interconnect, a first bonding structure switch, and a first interconnect switch in sequence. The conductive bonding structure under test is electrically connected to the second conductive trace layer via a second auxiliary interconnect, a second bonding structure switch, and a second interconnect switch in sequence. In the voltage test loop, the third interconnect structure in one of two adjacent substrates is electrically connected to the conductive bonding structure under test via a third auxiliary interconnect. The conductive bonding structure under test is electrically connected to the fourth conductive trace layer via a third interconnect switch. The first auxiliary interconnect structure includes a first auxiliary interconnect and a second auxiliary interconnect, the second auxiliary interconnect structure includes the third auxiliary interconnect, the first conductive switch layer includes a first bonding structure switch, a first interconnect switch, a second bonding structure switch, and a second interconnect switch, and the second conductive switch layer includes the third interconnect switch.

[0022] Alternatively, in the current loop, the first conductive trace layer and the conductive bonding structure under test are sequentially connected via a first interconnect switch, a first bonding structure switch, and a first auxiliary interconnect, and the conductive bonding structure under test is connected to the second conductive trace layer via a second interconnect switch; in the voltage test loop, the third conductive trace layer and the conductive bonding structure under test are connected via a third interconnect switch, and the conductive bonding structure under test and the fourth conductive trace layer are connected via a second auxiliary interconnect, a second bonding structure switch, and a fourth interconnect switch; the first auxiliary interconnect structure includes the first auxiliary interconnect, the second auxiliary interconnect structure includes the second auxiliary interconnect, the first conductive switch layer includes the first bonding structure switch, the first interconnect switch, and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch, the second bonding structure switch, and the fourth interconnect switch;

[0023] When the first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates, and two redistribution layers are formed between the two adjacent substrates, in the current loop, the first conductive trace layer in the upper redistribution layer of the two redistribution layers is electrically connected to the conductive bonding structure under test in sequence through a first auxiliary interconnect, a first bonding structure switch, and a first interconnect switch. The conductive bonding structure under test is electrically connected to the second conductive trace layer in the lower redistribution layer of the two redistribution layers in sequence through a second auxiliary interconnect, a second bonding structure switch, and a second interconnect switch. In the voltage test loop, the two redistribution layers... The third conductive trace layer in the upper redistribution layer of the line layer is electrically connected to the conductive bonding structure under test via a third auxiliary interconnect. The conductive bonding structure under test is electrically connected to the fourth conductive trace layer in the lower redistribution layer of the two redistribution layers via a third interconnect switch. The first auxiliary interconnect structure includes a first auxiliary interconnect and a second auxiliary interconnect, the second auxiliary interconnect structure includes the third auxiliary interconnect, the first conductive switch layer includes a first bonding structure switch, a first interconnect switch, a second bonding structure switch, and a second interconnect switch, and the second conductive switch layer includes the third interconnect switch.

[0024] The conductive bonding structure, the conductive bonding structure under test, the first bonding structure switch, and the second bonding structure switch are located on the same layer, and each includes two bonded first metal layers and a first conductive plug on the side of each first metal layer away from the bonding interface.

[0025] Optionally, the conductive structure under test includes a via conductive structure penetrating the substrate; when the first conductive switch layer and the second conductive switch layer are formed in the substrate and between two adjacent substrates, and one or two redistribution layers are formed between the two adjacent substrates; or when the first conductive switch layer and the second conductive switch layer are formed in the substrate and on one side of the at least two stacked substrates, and the redistribution layer is formed on one side of the at least two stacked substrates, in the current loop, the first interconnect structure in the substrate where the via conductive structure under test is located is electrically connected to the via conductive structure under test in sequence through a first auxiliary interconnect, a first via conductive structure switch, and a first interconnect switch; the via conductive structure under test is connected to the second conductive structure in the redistribution layer near the substrate where the via conductive structure under test is located. The layers are sequentially connected via a second auxiliary interconnect, a second via conductive structure switch, and a second interconnect switch. In the voltage test circuit, the third interconnect structure in the substrate where the via conductive structure under test is located is electrically connected to the via conductive structure under test via a third auxiliary interconnect. The via conductive structure under test is electrically connected to the fourth conductive trace layer in the redistribution layer near the substrate where the via conductive structure under test is located via a third interconnect switch. The first auxiliary interconnect structure includes a first auxiliary interconnect and a second auxiliary interconnect. The second auxiliary interconnect structure includes the third auxiliary interconnect. The first conductive switch layer includes a first via conductive structure switch, a first interconnect switch, a second via conductive structure switch, and a second interconnect switch. The second conductive switch layer includes the third interconnect switch.

[0026] When the first conductive switch layer and the second conductive switch layer are formed in the substrate and between two adjacent substrates, and one or two redistribution layers are formed between two adjacent substrates, in the current loop, the first conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test is electrically connected to the conductive structure of the via under test in sequence through a first interconnect switch, a first via conductive structure switch, and a first auxiliary interconnect. The conductive structure of the via under test is electrically connected to the second conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test through a second interconnect switch. In the voltage test loop, the first conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test is electrically connected to the conductive structure of the via under test in sequence through a first interconnect switch, a first via conductive structure switch, and a first auxiliary interconnect. The third conductive trace layer in the redistribution layer is electrically connected to the via conductive structure under test via a third interconnect switch. The via conductive structure under test is electrically connected to the fourth conductive trace layer in the redistribution layer near the substrate where the via conductive structure under test is located via a second auxiliary interconnect, a second via conductive structure switch, and a fourth interconnect switch. The first auxiliary interconnect structure includes the first auxiliary interconnect, the second auxiliary interconnect structure includes the second auxiliary interconnect, the first conductive switch layer includes the first via conductive structure switch, the first interconnect switch, and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch, the second via conductive structure switch, and the fourth interconnect switch.

[0027] In the substrate where the conductive structure under test is located, the conductive structure under test, the first conductive structure switch, and the second conductive structure switch are located on the same layer.

[0028] Optionally, the conductive structure under test includes a second conductive plug; the conductive structure under test, the first conductive switch layer, and the second conductive switch layer are formed between two adjacent substrates; one or two redistribution layers are formed between the two adjacent substrates, wherein when the second metal layer of the first conductive trace layer, the second conductive trace layer, the third conductive trace layer, and the fourth conductive trace layer in one of the redistribution layers is electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure in one of the substrates respectively via the second conductive plug,

[0029] In the current loop, the first interconnect structure in one of the substrates is electrically connected to the second conductive plug under test via a first auxiliary interconnect line, a first plug switch, and a first interconnect line switch in sequence. The second conductive plug under test is electrically connected to the second conductive trace layer in one of the redistribution layers via a second auxiliary interconnect line, a second plug switch, and a second interconnect line switch in sequence. In the voltage test loop, the third interconnect structure in one of the substrates is electrically connected to the second conductive plug under test via a third auxiliary interconnect line. The second conductive plug under test is electrically connected to the fourth conductive trace layer in one of the redistribution layers via a third interconnect line switch. The first auxiliary interconnect structure includes a first auxiliary interconnect line and a second auxiliary interconnect line. The second auxiliary interconnect structure includes the third auxiliary interconnect line. The first conductive switch layer includes a first plug switch, a first interconnect line switch, a second plug switch, and a second interconnect line switch. The second conductive switch layer includes the third interconnect line switch.

[0030] Alternatively, in the current loop, the first conductive trace layer in one of the redistribution layers is electrically connected to the second conductive plug under test via a first interconnect switch, a first plug switch, and a first auxiliary interconnect in sequence; the second conductive plug under test is electrically connected to the second conductive trace layer in one of the redistribution layers via a second interconnect switch. In the voltage test loop, the third conductive trace layer in one of the redistribution layers is electrically connected to the second conductive plug under test via a third interconnect switch; the second conductive plug under test is electrically connected to the fourth conductive trace layer in one of the redistribution layers via a second auxiliary interconnect, a second plug switch, and a fourth interconnect switch. The first auxiliary interconnect structure includes the first auxiliary interconnect, the second auxiliary interconnect structure includes the second auxiliary interconnect, the first conductive switch layer includes the first plug switch, the first interconnect switch, and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch, the second plug switch, and the fourth interconnect switch.

[0031] Two redistribution layers are formed between two adjacent substrates. When each of the first, second, third, and fourth conductive layers in one of the redistribution layers includes at least two second metal layers and a second conductive plug located between adjacent second metal layers, in the current loop, the second metal layer at one end of the second conductive plug in the first conductive layer of one of the redistribution layers is electrically connected to the second conductive plug under test via a first auxiliary interconnect, a first plug switch, and a first interconnect switch. The second conductive plug under test is connected to the second metal layer at the other end of the second conductive plug in the second conductive layer of one of the redistribution layers via a second auxiliary interconnect, a second plug switch, and a second interconnect. The circuit includes a line switch for electrical connection; in the voltage test circuit, the second metal layer at one end of the second conductive plug in the third conductive trace layer of one of the redistribution layers is electrically connected to the second conductive plug under test via a third auxiliary interconnect line, and the second conductive plug under test is electrically connected to the second metal layer at the other end of the second conductive plug in the fourth conductive trace layer of one of the redistribution layers via a third interconnect line switch; the first auxiliary interconnect structure includes the first auxiliary interconnect line and the second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes the first plug switch, the first interconnect line switch, the second plug switch and the second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch;

[0032] The second conductive plug to be tested, the second conductive plug, the first plug switch, and the second plug switch are located on the same layer.

[0033] Optionally, the first conductive switch layer and the second conductive switch layer are formed in any of the substrates, between any two adjacent substrates, and on one or two sides of the at least two stacked substrates.

[0034] The present invention also provides a testing method, comprising:

[0035] Provide a test structure, the test structure including:

[0036] At least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure and a fourth interconnect structure that are phase-insulated are formed in the substrates;

[0037] A first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrate or between two adjacent substrates;

[0038] A redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates. The redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively.

[0039] The conductive structure to be tested is formed in the substrate or between two adjacent substrates;

[0040] The first conductive switch layer and the second conductive switch layer are formed in the substrate, between two adjacent substrates, and on one or both of the at least two stacked substrates;

[0041] A current is applied between the first interconnect structure and the second interconnect structure, and the voltage between the third interconnect structure and the fourth interconnect structure is tested. A current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer. A voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer, in order to obtain the contact resistance of the conductive structure under test.

[0042] Optionally, the first conductive switch layer and the second conductive switch layer are formed in one or two of the following: in any of the substrates, between any two adjacent substrates, and on one side of the at least two stacked substrates, to obtain the contact resistance of the conductive structure under test in any of the substrates or between any two adjacent substrates.

[0043] Compared with the prior art, the test structure and test method of the present invention enable the first interconnect structure and the second interconnect structure to form a current loop through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer when testing the contact resistance of the conductive structure under test. Furthermore, the third interconnect structure and the fourth interconnect structure form a voltage test loop through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer. That is, only one current loop and one voltage test loop are formed in the test structure, avoiding the introduction of test noise and thus preventing any impact on the test results of the contact resistance of the conductive structure under test, thereby improving the accuracy of the contact resistance test. Attached Figure Description

[0044] Figures 1-13 This is a three-dimensional schematic diagram of the test structure according to a specific embodiment of the present invention;

[0045] Figures 14-16 This is a cross-sectional schematic diagram of the test structure according to a specific embodiment of the present invention;

[0046] Figure 17 This is a circuit diagram of the test structure according to a specific embodiment of the present invention;

[0047] Figure 18 This is a flowchart of a testing method according to an embodiment of the present invention.

[0048] Among them, the appendix Figures 1-18 The annotations in the attached figures are explained as follows:

[0049] 10-Substrate; 101-Substrate; 102-Interlayer dielectric layer; 21-First interconnect structure; 22-Second interconnect structure; 23-Third interconnect structure; 24-Fourth interconnect structure; 25-Through-hole conductive structure; 26-Through-hole conductive structure under test; M3-Third metal layer; V3-Third conductive plug; 31-First auxiliary interconnect; 32-Second auxiliary interconnect; 33-Third auxiliary interconnect; 40-Rewiring layer; 41-First conductive trace layer; 42-Second conductive trace layer; 43-Third conductive trace layer; 44-Fourth conductive trace layer; 45-Second conductive plug under test; M 2-Second metal layer; V2-Second conductive plug; 46-Second dielectric layer; 51-First bonding structure switch; 52-Second bonding structure switch; 53-First through-hole conductive structure switch; 54-Second through-hole conductive structure switch; 55-First plug switch; 56-Second plug switch; 57-First interconnect switch; 58-Second interconnect switch; 59-Third interconnect switch; 510-Fourth interconnect switch; 60-Hybrid bonding layer; 61-Conductive bonding structure; 62-Conductive bonding structure under test; M1-First metal layer; V1-First conductive plug; 63-First dielectric layer. Detailed Implementation

[0050] To make the objectives, advantages, and features of this invention clearer, the test structure and test method proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the objectives of the embodiments of this invention.

[0051] An embodiment of the present invention provides a test structure, comprising: at least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure are formed in the substrates; a first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrates or between two adjacent substrates; a redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates, the redistribution layer comprising a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer respectively electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure; and a conductive structure to be tested, formed in the substrates or Between two adjacent substrates; a first conductive switch layer and a second conductive switch layer are formed in one or two of the substrates, between two adjacent substrates, and on one side of the at least two stacked substrates, such that when testing the contact resistance of the conductive structure under test, a current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer, and a voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer.

[0052] See below. Figures 1-17 The test structure provided in this embodiment will be described in more detail; wherein, Figure 14 , Figure 15 and Figure 16 The figures shown are respectively Figure 1 , Figure 2 and Figure 3 The test structure shown is a longitudinal cross-sectional view along the plane containing the through-hole conductive structure 26 and the through-hole conductive structure 25. Figures 1-13 The substrate 101 and interlayer dielectric layer 102 in the substrate 10, the second dielectric layer 46 in the redistribution layer 40 and the first dielectric layer 63 in the hybrid bonding layer 60 are not shown in the diagram. Figures 1-13 I in 11 and I 12 These are the current application terminals, V 11 and V 12 These are the voltage test terminals.

[0053] The substrate 10 is a wafer or a chip.

[0054] In at least two stacked substrates 10, the different substrates 10 are of the same type, and a first interconnect structure 21, a second interconnect structure 22, a third interconnect structure 23 and a fourth interconnect structure 24 that are phase-insulated are formed in the substrates 10.

[0055] The same type of different substrates 10 means that different substrates 10 have the same structural composition and the same structure in different substrates 10 is set in the same position in the corresponding substrate 10.

[0056] In one embodiment, the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23 and the fourth interconnect structure 24 each include at least two third metal layers M3 and a third conductive plug V3 electrically connected between two adjacent third metal layers M3.

[0057] In one embodiment, the substrate 10 includes a substrate 101 and an interlayer dielectric layer 102 formed on the substrate 101. The first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 are formed in the interlayer dielectric layer 102, and are insulated from each other by the interlayer dielectric layer 102. The side of the interlayer dielectric layer 102 away from the substrate 101 is the front side of the substrate 10, and the side of the substrate 101 away from the interlayer dielectric layer 102 is the back side of the substrate 10.

[0058] In the at least two stacked substrates 10, as Figure 14 As shown, in one of the two adjacent substrates 10, the substrate 101 is closer to the bonding interface than the interlayer dielectric layer 102, and in the other substrate 10, the interlayer dielectric layer 102 is closer to the bonding interface than the substrate 101 (i.e., the back side of one of the two adjacent substrates 10 is bonded to the front side of the other substrate 10); or, as Figure 15 As shown, in two adjacent substrates 10, the substrate 101 is closer to the bonding interface than the interlayer dielectric layer 102 (i.e., the back sides of two adjacent substrates 10 are bonded to each other); or, as Figure 16 As shown, the interlayer dielectric layer 102 in two adjacent substrates 10 is closer to the bonding interface than the substrate 101 (i.e., the front sides of two adjacent substrates 10 are bonded to each other).

[0059] exist Figure 1 , Figure 4 , Figure 7 , Figure 10 , Figure 11 and Figure 12In the illustrated embodiment, in two adjacent substrates 10, the back side of the upper substrate 10 is bonded to the front side of the lower substrate 10; Figure 2 , Figure 5 and Figure 8 In the illustrated embodiment, in two adjacent substrates 10, the back surface of the upper substrate 10 is bonded to the back surface of the lower substrate 10; Figure 3 , Figure 6 and Figure 9 In the embodiment shown, in two adjacent substrates 10, the front side of the upper substrate 10 is bonded to the front side of the lower substrate 10.

[0060] The first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 in different substrates 10 are electrically connected to each other.

[0061] The first auxiliary interconnect structure and the second auxiliary interconnect structure are formed in the substrate 10 or between two adjacent substrates 10.

[0062] In one embodiment, when the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed in the substrate 10, the first auxiliary interconnect structure in different substrates 10 is the same and the second auxiliary interconnect structure in different substrates 10 is the same (i.e., the structural composition and the placement position of the structure in the substrate 10 are the same); when the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed between two adjacent substrates 10, the first auxiliary interconnect structure and the second auxiliary interconnect structure between any two adjacent substrates 10 are the same as the first auxiliary interconnect structure and the second auxiliary interconnect structure between any other two adjacent substrates 10 (i.e., the structural composition and the placement position of the structure between the two adjacent substrates 10 are the same).

[0063] Rewiring layer 40 is formed between two adjacent substrates 10 (e.g.) Figure 1 , Figure 2 , Figures 4-12 (as shown) or one side of the at least two stacked bases 10 (as shown) Figure 3 As shown, the redistribution layer 40 includes a first conductive routing layer 41, a second conductive routing layer 42, a third conductive routing layer 43, and a fourth conductive routing layer 44, which are electrically connected to the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24, respectively.

[0064] In one embodiment, the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43 and the fourth conductive trace layer 44 each include a second metal layer M2, or include at least one second metal layer M2 and at least one second conductive plug V2 electrically connected to the second metal layer M2.

[0065] In one embodiment, the redistribution layer 40 further includes a second dielectric layer 46, wherein the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43 and the fourth conductive trace layer 44 are formed in the second dielectric layer 46 at intervals.

[0066] In one embodiment, the test structure further includes:

[0067] The hybrid bonding layer 60 includes two bonded first dielectric layers 63 and the conductive bonding structure 61 penetrating the two first dielectric layers 63;

[0068] Wherein, a redistribution layer 40 is formed between two adjacent substrates 10, such as Figure 1 , Figure 4 , Figure 6 , Figure 9 , Figure 10 and Figure 11 As shown, the hybrid bonding layer 60 is formed between the redistribution layer 40 and one of the two adjacent substrates 10. The first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 in one of the two adjacent substrates 10 are electrically connected to the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 in the redistribution layer 40 through the conductive bonding structure 61.

[0069] When two redistribution layers 40 are formed between two adjacent substrates 10, such as Figure 2 , Figure 5 , Figure 7 , Figure 8 and Figure 12 As shown, the hybrid bonding layer 60 is formed between two redistribution layers 40 between two adjacent substrates 10. The first conductive routing layer 41, the second conductive routing layer 42, the third conductive routing layer 43, and the fourth conductive routing layer 44 in the two redistribution layers 40 are electrically connected through the conductive bonding structure 61.

[0070] When the redistribution layer 40 is formed on one side of the at least two stacked substrates 10, as Figure 3As shown, the hybrid bonding layer 60 is formed between two adjacent substrates 10, and the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23 and the fourth interconnect structure 24 in the two adjacent substrates 10 are electrically connected through the conductive bonding structure 61.

[0071] In one embodiment, the conductive bonding structure 61 includes two bonded first metal layers M1 and a first conductive plug V1 on the side of each first metal layer M1 away from the bonding interface, that is, each first dielectric layer 63 has a first metal layer M1 and a first conductive plug V1 formed therein.

[0072] In one embodiment, a through-hole conductive structure 25 penetrating the substrate 101 is further formed in the substrate 10, the substrate 10 (e.g., Figure 1 , Figure 3 , Figure 4 , Figure 7 , Figure 10 , Figure 11 , Figure 12 The upper substrate 10 in the middle, such as Figure 2 , Figure 5 , Figure 8 When the substrate 101 in the upper and lower substrates 10) is closer to the redistribution layer 40 than the interlayer dielectric layer 102, the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 in this substrate 10 are electrically connected to the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 in this redistribution layer 40 through the via conductive structure 25. The third metal layer M3 in the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 are electrically connected to the second metal layer M2 in the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 through the via conductive structure 25. In one embodiment, the via conductive structure 25 further extends into the interlayer dielectric layer 102 and / or the second dielectric layer 46.

[0073] In one embodiment, the substrate 10 (such as...) Figure 6 The upper substrate 10 in the middle, such as Figure 7 , Figure 9 , Figure 12When the interlayer dielectric layer 102 in the lower substrate 10) is closer to the redistribution layer 40 than the substrate 101, the third metal layer M3 in the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23 and the fourth interconnect structure 24 in this substrate 10 are respectively electrically connected to the second metal layer M2 in the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43 and the fourth conductive trace layer 44 in this redistribution layer 40 through the second conductive plug V2.

[0074] The conductive structure to be tested is formed in the substrate 10 or between two adjacent substrates 10.

[0075] The conductive structure to be tested may include a via conductive structure 26 penetrating the substrate 101, a conductive bonding structure 62 penetrating the two first dielectric layers 63, or a second conductive plug 45 to be tested.

[0076] The first conductive switch layer and the second conductive switch layer are formed in the substrate 10, between two adjacent substrates 10, and on one or two of the at least two stacked substrates 10, such that when testing the contact resistance of the conductive structure under test, the first interconnect structure 21 and the second interconnect structure 22 form a current loop through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer 41 and / or the second conductive trace layer 42, and the third interconnect structure 23 and the fourth interconnect structure 24 form a voltage test loop through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer 43 and / or the fourth conductive trace layer 44.

[0077] exist Figures 1-13 In the illustrated embodiment, by applying current to the first interconnect structure 21 (i.e., current application terminal I) 11 ) and the second interconnection structure 22 (i.e., current application terminal I) 12 A current is applied between the three interconnects, and the third interconnect structure 23 (i.e., the voltage test terminal V) is tested. 11 ) and the fourth interconnect structure 24 (i.e., voltage test terminal V) 12 The voltage between the first interconnect structure 21 and the second interconnect structure 22 is measured, and a current loop is formed between the third interconnect structure 23 and the fourth interconnect structure 24 along the direction indicated by the dashed arrow, so that the contact resistance of the conductive structure under test can be obtained. It should be noted that... Figures 1-13 Current application terminal I in 11 and current application terminal I 12The positions can be interchanged, and at the same time, the voltage test terminal V... 11 and voltage test terminal V 12 The positions can be interchanged; the directions of the current loop and voltage test loop are the same as... Figures 1-13 The solid and dashed arrows shown in the diagram point in opposite directions.

[0078] like Figure 17 The image shown is a pair Figures 1-13 The circuit diagram shown is used to test the contact resistance R of the conductive structure under test in the test structure. Figure 17 It can be seen that when testing the contact resistance R of the conductive structure under test, only one current loop (in the direction indicated by the solid arrow) and one voltage test loop (in the direction indicated by the dashed arrow) are formed in the test structure, and no test noise is introduced, so that the test noise can be avoided from affecting the test result of the contact resistance R of the conductive structure under test.

[0079] like Figure 1 and Figure 2 As shown, the conductive structure under test includes a via conductive structure 26 penetrating the substrate 101. The first conductive switch layer and the second conductive switch layer are formed in the substrate 10 and between two adjacent substrates 10, and a redistribution layer 40 (e.g., ...) is formed between two adjacent substrates 10. Figure 1 (as shown) or two layers of the redistribution layer 40 (as shown) Figure 2As shown), in the current loop, the first interconnect structure 21 in the substrate 10 where the via conductive structure 26 is located is electrically connected to the via conductive structure 26 in sequence via a first auxiliary interconnect 31, a first via conductive structure switch 53, and a first interconnect switch 57. The via conductive structure 26 is electrically connected to the second conductive trace layer 42 in the redistribution layer 40 near the substrate 10 where the via conductive structure 26 is located via a second auxiliary interconnect 32, a second via conductive structure switch 54, and a second interconnect switch 58 in sequence. In the voltage test loop, the third interconnect structure 23 in the substrate 10 where the via conductive structure 26 is located is connected to the... The conductive structures 26 under test are electrically connected to each other via a third auxiliary interconnect 33. The conductive structure 26 under test is electrically connected to the fourth conductive trace layer 44 in the redistribution layer 40 of the substrate 10 near the conductive structure 26 under test via a third interconnect switch 59. The first auxiliary interconnect structure includes the first auxiliary interconnect 31 and the second auxiliary interconnect 32. The second auxiliary interconnect structure includes the third auxiliary interconnect 33. The first conductive switch layer includes the first via conductive structure switch 53, the first interconnect switch 57, the second via conductive structure switch 54 and the second interconnect switch 58. The second conductive switch layer includes the third interconnect switch 59.

[0080] like Figure 3As shown, the conductive structure under test includes a via conductive structure 26 penetrating the substrate 101. The first conductive switch layer and the second conductive switch layer are formed in the substrate 10 and on one side of the at least two stacked substrates 10. When the redistribution layer 40 is formed on one side of the at least two stacked substrates 10, in the current loop, the first interconnect structure 21 in the substrate 10 where the via conductive structure 26 is located (e.g., the third metal layer M closest to the via conductive structure 26 in the first interconnect structure 21)... 3) The via conductive structure 26 under test is electrically connected to the via conductive structure 26 in sequence via a first auxiliary interconnect 31, a first via conductive structure switch 53, and a first interconnect switch 57. The via conductive structure 26 under test is connected to the second conductive routing layer 42 in the redistribution layer 40 of the substrate 10 near the via conductive structure 26 under test (e.g., the second metal layer M2 in the second conductive routing layer 42 closest to the via conductive structure 26 under test) in sequence via a second auxiliary interconnect 32, a second via conductive structure switch 54, and a second interconnect switch 57. 58 Electrical connection; In the voltage test circuit, the third interconnect structure 23 (e.g., the third metal layer M3 closest to the via conductive structure 26 in the substrate 10 where the via conductive structure 26 is located) is electrically connected to the via conductive structure 26 through a third auxiliary interconnect line 33. The via conductive structure 26 is electrically connected to the fourth conductive routing layer 44 (e.g., the second metal layer M2 closest to the via conductive structure 26 in the fourth conductive routing layer 44) in the redistribution layer 40 near the substrate 10 where the via conductive structure 26 is located through a third interconnect switch 59. The first auxiliary interconnect structure includes the first auxiliary interconnect line 31 and the second auxiliary interconnect line 32. The second auxiliary interconnect structure includes the third auxiliary interconnect line 33. The first conductive switch layer includes the first via conductive structure switch 53, the first interconnect switch 57, the second via conductive structure switch 54 and the second interconnect switch 58. The second conductive switch layer includes the third interconnect switch 59.

[0081] like Figure 10 As shown, the conductive structure under test includes a via conductive structure 26 penetrating the substrate 101. The first conductive switch layer and the second conductive switch layer are formed in the substrate 10 and between two adjacent substrates 10. One or two redistribution layers 40 are formed between two adjacent substrates 10 (e.g., ...). Figure 10When the via conductive structure 26 is located (as shown), in the current loop, the first conductive trace layer 41 (e.g., the second metal layer M2 closest to the via conductive structure 26 in the redistribution layer 40 of the substrate 10) near the via conductive structure 26 under test is electrically connected to the via conductive structure 26 under test in sequence through a first interconnect switch 57, a first via conductive structure switch 53, and a first auxiliary interconnect 31. The via conductive structure 26 under test is electrically connected to the second conductive trace layer 42 (e.g., the second metal layer M2 closest to the via conductive structure 26 in the redistribution layer 40 of the substrate 10) near the via conductive structure 26 under test through a second interconnect switch 58. In the voltage test loop, the third conductive trace layer 43 (e.g., the second metal layer M2 closest to the via conductive structure 26 in the redistribution layer 40 of the substrate 10) near the via conductive structure 26 under test is electrically connected to the via conductive structure 26 under test through a second interconnect switch 58. The second metal layer M2 near the conductive structure 26 under test is electrically connected to the conductive structure 26 under test via a third interconnect switch 59. The conductive structure 26 under test is electrically connected to the fourth conductive routing layer 44 in the redistribution layer 40 of the substrate 10 where the conductive structure 26 under test is located (e.g., the second metal layer M2 closest to the conductive structure 26 under test in the fourth conductive routing layer 44) via a second auxiliary interconnect 32, a second via conductive structure switch 54, and a fourth interconnect switch 510. The first auxiliary interconnect structure includes the first auxiliary interconnect 31, the second auxiliary interconnect structure includes the second auxiliary interconnect 32, the first conductive switch layer includes the first via conductive structure switch 53, the first interconnect switch 57, and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59, the second via conductive structure switch 54, and the fourth interconnect switch 510.

[0082] In the substrate 10 where the via conductive structure 26 to be tested is located, the via conductive structure 25, the via conductive structure 26 to be tested, the first via conductive structure switch 53, and the second via conductive structure switch 54 are located on the same layer; the first auxiliary interconnect 31, the second auxiliary interconnect 32, and the third auxiliary interconnect 33 are located on the same layer as the third metal layer M3 in the substrate 10 where the via conductive structure 26 to be tested is located, which is closest to the via conductive structure 26 to be tested; the first interconnect switch 57, the second interconnect switch 58, the third interconnect switch 59, and the fourth interconnect switch 510 are located on the same layer as the second metal layer M2 in the redistribution layer 40 near the via conductive structure 26 to be tested.

[0083] like Figure 4 and Figure 6As shown, the conductive structure under test includes a conductive bonding structure 62 penetrating the two first dielectric layers 63. The first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10, and a redistribution layer 40 is formed between the two adjacent substrates 10. In the current loop, the first interconnection structure 21 (e.g., the third metal layer M3 closest to the conductive bonding structure 62 in the first interconnection structure 21) in one of the two adjacent substrates 10 (i.e., the substrate 10 further away from the redistribution layer 40) is electrically connected to the conductive bonding structure 62 under test via a first auxiliary interconnection 31, a first bonding structure switch 51, and a first interconnection switch 57 in sequence. The conductive bonding structure 62 under test is connected to the second conductive routing layer 42 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the second conductive routing layer 42) via a second auxiliary interconnection 32, a second bonding structure switch 52, and a second... Interconnect switch 58 is electrically connected; in the voltage test circuit, the third interconnect structure 23 (e.g., the third metal layer M3 closest to the conductive bonding structure 62 under test in the third interconnect structure 23) of one of the two adjacent substrates 10 is electrically connected to the conductive bonding structure 62 under test through a third auxiliary interconnect 33, and the conductive bonding structure 62 under test is electrically connected to the fourth conductive trace layer 44 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the fourth conductive trace layer 44) through a third interconnect switch 59; the first auxiliary interconnect structure includes the first auxiliary interconnect 31 and the second auxiliary interconnect 32, the second auxiliary interconnect structure includes the third auxiliary interconnect 33, the first conductive switch layer includes the first bonding structure switch 51, the first interconnect switch 57, the second bonding structure switch 52 and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59.

[0084] like Figure 5As shown, the conductive structure under test includes a conductive bonding structure 62 penetrating the two first dielectric layers 63. The first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10. When two redistribution layers 40 are formed between the two adjacent substrates 10, in the current loop, the first conductive trace layer 41 in the upper redistribution layer 40 of the two redistribution layers 40 (for example, the second metal layer in the first conductive trace layer 41 closest to the conductive bonding structure 62 under test) M2) is electrically connected to the conductive bonding structure 62 under test via a first auxiliary interconnect 31, a first bonding structure switch 51, and a first interconnect switch 57 in sequence. The conductive bonding structure 62 under test is electrically connected to the second conductive routing layer 42 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test) in the lower redistribution layer 40 of the two redistribution layers 40 via a second auxiliary interconnect 32, a second bonding structure switch 52, and a second interconnect switch 58 in sequence. In the voltage test circuit, the third conductive trace layer 43 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the upper layer of the two redistribution layers 40) is electrically connected to the conductive bonding structure 62 under test via a third auxiliary interconnect 33. The conductive bonding structure 62 under test is electrically connected to the fourth conductive trace layer 44 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the lower layer of the two redistribution layers 40) via a third interconnect switch 59. The first auxiliary interconnect structure includes the first auxiliary interconnect 31 and the second auxiliary interconnect 32, the second auxiliary interconnect structure includes the third auxiliary interconnect 33, the first conductive switch layer includes the first bonding structure switch 51, the first interconnect switch 57, the second bonding structure switch 52 and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59.

[0085] like Figure 11As shown, the conductive structure under test includes a conductive bonding structure 62 penetrating the two first dielectric layers 63. The first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10, and a redistribution layer 40 is formed between the two adjacent substrates 10. In the current loop, the first conductive routing layer 41 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 in the first conductive routing layer 41) is electrically connected to the conductive bonding structure 62 under test via a first interconnect switch 57, a first bonding structure switch 51, and a first auxiliary interconnect 31 in sequence. The conductive bonding structure 62 under test is electrically connected to the second conductive routing layer 42 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 in the second conductive routing layer 42) via a second interconnect switch 58. In the voltage test loop, the third conductive routing layer 4... 3 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the third conductive trace layer 43) is electrically connected to the conductive bonding structure 62 under test via a third interconnect switch 59. The conductive bonding structure 62 under test is electrically connected to the fourth conductive trace layer 44 (e.g., the second metal layer M2 closest to the conductive bonding structure 62 under test in the fourth conductive trace layer 44) via a second auxiliary interconnect 32, a second bonding structure switch 52, and a fourth interconnect switch 510. The first auxiliary interconnect structure includes the first auxiliary interconnect 31, the second auxiliary interconnect structure includes the second auxiliary interconnect 32, the first conductive switch layer includes the first bonding structure switch 51, the first interconnect switch 57, and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59, the second bonding structure switch, and the fourth interconnect switch 510.

[0086] The conductive bonding structure 61, the conductive bonding structure under test 62, the first bonding structure switch 51, and the second bonding structure switch 52 are located on the same layer; Figure 4 , Figure 6 and Figure 11 In the illustrated embodiment, the first auxiliary interconnect 31, the second auxiliary interconnect 32, and the third auxiliary interconnect 33 are located in the same layer as the third metal layer M3 of one of the two adjacent substrates 10 that is closest to the conductive bonding structure 62 under test; Figure 5 In the illustrated embodiment, the first auxiliary interconnect 31, the second auxiliary interconnect 32, and the third auxiliary interconnect 33 are located on the same layer as the second metal layer M2 of the upper redistribution layer 40, which is closest to the conductive bonding structure 62 under test. Figure 4 , Figure 6 , Figure 11 In the illustrated embodiment, the first interconnect switch 57, the second interconnect switch 58, the third interconnect switch 59, and the fourth interconnect switch 510 are located on the same layer as the second metal layer M2 in the redistribution layer 40 that is closest to the conductive bonding structure 62 under test; Figure 5 In the embodiment shown, the first interconnect switch 57, the second interconnect switch 58, and the third interconnect switch 59 are located on the same layer as the second metal layer M2, which is closest to the conductive bonding structure 62 under test, in the lower layer of the two redistribution layers 40.

[0087] like Figure 7 and Figure 9 As shown, the conductive structure under test includes a second conductive plug 45, which is formed between two adjacent substrates 10; the first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10, and a redistribution layer 40 is formed between two adjacent substrates (e.g., Figure 9 (as shown) or two layers of the redistribution layer 40 (as shown) Figure 7As shown), when the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 in one of the redistribution layers 40 are electrically connected to the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 in one of the substrates 10 respectively via the second conductive plug V2, in the current loop, the first interconnect structure 21 in one of the substrates 10 (e.g., the third metal layer M3 closest to the second conductive plug 45 under test in the first interconnect structure 21) and the second conductive plug 45 under test are sequentially connected via the first auxiliary interconnect line 31, the first plug switch 55, and the first interconnect line switch 57, and the second conductive plug 45 under test is sequentially connected to the second conductive trace layer 42 in one of the redistribution layers 40 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the second conductive trace layer 42) via the second auxiliary interconnect line 31, the first plug switch 55, and the first interconnect line switch 57, respectively. The connection 32, the second plug switch 56, and the second interconnect switch 58 are electrically connected; in the voltage test circuit, the third interconnect structure 23 in one of the substrates 10 (e.g., the third metal layer M3 closest to the second conductive plug 45 under test in the third interconnect structure 23) is electrically connected to the second conductive plug 45 under test through a third auxiliary interconnect line 33, and the second conductive plug 45 under test is electrically connected to the fourth conductive routing layer 44 in one of the redistribution layers 40 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the fourth conductive routing layer 44) through a third interconnect switch 59; the first auxiliary interconnect structure includes the first auxiliary interconnect line 31 and the second auxiliary interconnect line 32, the second auxiliary interconnect structure includes the third auxiliary interconnect line 33, the first conductive switch layer includes the first plug switch 55, the first interconnect switch 57, the second plug switch 56, and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59.

[0088] like Figure 8As shown, the conductive structure under test includes a second conductive plug 45. The first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10. Two redistribution layers 40 are formed between the two adjacent substrates 10. When the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 in one redistribution layer 40 each include at least two second metal layers M2 and a second conductive plug V2 located between adjacent second metal layers M2, the electrical... In the current loop, the second conductive plug V2 closest to the bonding interface in the first conductive trace layer 41 of one of the redistribution layers 40, and the second metal layer M2 at the end away from the bonding interface, are electrically connected to the second conductive plug 45 under test via a first auxiliary interconnect 31, a first plug switch 55, and a first interconnect switch 57. The second conductive plug 45 under test is connected to the second conductive plug V2 closest to the bonding interface in the second conductive trace layer 42 of one of the redistribution layers 40, at the other end of the metal layer M2 closest to the bonding interface. The second metal layers M2 are electrically connected via a second auxiliary interconnect 32, a second plug switch 56, and a second interconnect switch 58. In the voltage test circuit, the second metal layer M2 of the second conductive plug V2 closest to the bonding interface in the third conductive trace layer 43 of one of the redistribution layers 40, away from the bonding interface, is electrically connected to the second conductive plug 45 under test via a third auxiliary interconnect 33. The second conductive plug 45 under test is electrically connected to the second metal layer M2 of the second conductive plug V2 closest to the bonding interface in the fourth conductive trace layer 44 of one of the redistribution layers 40, near the bonding interface, via a third interconnect switch 59. The first auxiliary interconnect structure includes the first auxiliary interconnect 31 and the second auxiliary interconnect 32, the second auxiliary interconnect structure includes the third auxiliary interconnect 33, the first conductive switch layer includes the first plug switch 55, the first interconnect switch 57, the second plug switch 56, and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59.

[0089] like Figure 12 As shown, the conductive structure under test includes a second conductive plug 45, the first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates 10, and one or two redistribution layers 40 are formed between the two adjacent substrates 10 (e.g., ...). Figure 12As shown), when the first conductive trace layer 41, the second conductive trace layer 42, the third conductive trace layer 43, and the fourth conductive trace layer 44 in one of the redistribution layers 40 are electrically connected to the first interconnect structure 21, the second interconnect structure 22, the third interconnect structure 23, and the fourth interconnect structure 24 in one of the substrates 10 respectively via the second conductive plug V2, in the current loop, the first conductive trace layer 41 in one of the redistribution layers 40 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the first conductive trace layer 41) and the second conductive plug 45 under test are electrically connected in sequence via the first interconnect switch 57, the first plug switch 55, and the first auxiliary interconnect 31. The second conductive plug 45 under test and the second conductive trace layer 42 in one of the redistribution layers 40 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the second conductive trace layer 42) are connected via the second interconnect switch. 58 Electrical connection; In the voltage test circuit, the third conductive trace layer 43 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the third conductive trace layer 43) in one of the redistribution layers 40 is electrically connected to the second conductive plug 45 under test through a third interconnect switch 59, and the second conductive plug 45 under test is electrically connected to the fourth conductive trace layer 44 (e.g., the second metal layer M2 closest to the second conductive plug 45 under test in the fourth conductive trace layer 44) in one of the redistribution layers 40 through a second auxiliary interconnect 32, a second plug switch 56, and a fourth interconnect switch 510; The first auxiliary interconnect structure includes the first auxiliary interconnect 31, the second auxiliary interconnect structure includes the second auxiliary interconnect 32, the first conductive switch layer includes the first plug switch 55, the first interconnect switch 57, and the second interconnect switch 58, and the second conductive switch layer includes the third interconnect switch 59, the second plug switch 56, and the fourth interconnect switch 510.

[0090] Among them, the second conductive plug 45 to be tested, the second conductive plug V2, the first plug switch 55, and the second plug switch 56 are located on the same layer; in Figure 7 , Figure 9 and Figure 12 In the illustrated embodiment, the first auxiliary interconnect 31, the second auxiliary interconnect 32, and the third auxiliary interconnect 33 are located on the same layer as the third metal layer M3 closest to the second conductive plug 45 under test; Figure 8In the illustrated embodiment, the first auxiliary interconnect 31, the second auxiliary interconnect 32, and the third auxiliary interconnect 33 are located on the same layer as the second metal layer M2 at the end of the second conductive plug V2 closest to the bonding interface that is furthest from the bonding interface; Figure 7 , Figure 9 and Figure 12 In the illustrated embodiment, the first interconnect switch 57, the second interconnect switch 58, the third interconnect switch 59, and the fourth interconnect switch 510 are located on the same layer as the second metal layer M2 closest to the second conductive plug 45 under test; Figure 8 In the embodiment shown, the first interconnect switch 57, the second interconnect switch 58, and the third interconnect switch 59 are located on the same layer as the second metal layer M2 at the end of the second conductive plug V2 closest to the bonding interface.

[0091] In one embodiment, the first conductive switch layer and the second conductive switch layer are formed in any of the substrates 10, between any two adjacent substrates 10, and on one or two sides of the at least two stacked substrates 10, so that the contact resistance of the conductive structure under test in any of the substrates 10 or between any two adjacent substrates 10 can be tested; when it is necessary to monitor the contact resistance of any one or more of the conductive structures under test, it can be achieved by setting the first conductive switch layer and the second conductive switch layer in the substrate 10 where the conductive structure under test whose contact resistance needs to be monitored is located and / or on the front or back of the substrate 10.

[0092] by Figure 13 Taking the test structure shown as an example, from the first substrate 10 to the nth (n is greater than or equal to 5) substrate 10 from top to bottom, only the third substrate 10 and the space between the third and fourth substrates 10 have the first conductive switch layer and the second conductive switch layer formed. The first conductive switch layer includes the first through-hole conductive structure switch 53, the first interconnect switch 57, the second through-hole conductive structure switch 54, and the second interconnect switch 58. The second conductive switch layer includes the third interconnect switch 59. The other substrates 10 do not have the first conductive switch layer and the second conductive switch layer formed between them and other adjacent substrates 10. This allows the contact resistance of the through-hole conductive structure 26 under test in the third substrate 10 to be tested to be tested, and the other substrates 10 do not affect the test result of the contact resistance of the through-hole conductive structure 26 under test in the third substrate 10.

[0093] When the first conductive switch layer and the second conductive switch layer are formed between any two adjacent substrates 10 or on one side of the at least two stacked substrates 10, the test of the conductive structure to be monitored for contact resistance can be achieved simply by adjusting the wiring design between any two adjacent substrates 10 or on one side of the at least two stacked substrates 10, without modifying the structural design of the substrate 10 itself, thus avoiding affecting the structure of the substrate 10 itself; when the first conductive switch layer and the second conductive switch layer are formed in any of the substrates 10, such as Figure 1 , Figure 2 , Figure 3 , Figure 10 and Figure 13 As shown, only the first through-hole conductive structure switch 53 and the second through-hole conductive structure switch 54, which are located on the same layer as the through-hole conductive structure 26 to be tested, need to be added to the substrate 10, which has a very small impact on the structure of the substrate 10 itself.

[0094] One embodiment of the present invention provides a testing method, see below. Figure 18 , Figure 18 This is a flowchart of a testing method according to an embodiment of the present invention, the testing method comprising:

[0095] Step S1: Provide a test structure, the test structure including:

[0096] At least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure and a fourth interconnect structure that are phase-insulated are formed in the substrates;

[0097] A first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrate or between two adjacent substrates;

[0098] A redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates. The redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively.

[0099] The conductive structure to be tested is formed in the substrate or between two adjacent substrates;

[0100] The first conductive switch layer and the second conductive switch layer are formed in the substrate, between two adjacent substrates, and on one or both of the at least two stacked substrates.

[0101] The test structure in step S1 is described in the above-described embodiment of the test structure, and will not be repeated here.

[0102] Step S2: Apply current between the first interconnect structure and the second interconnect structure, and test the voltage between the third interconnect structure and the fourth interconnect structure. A current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer. A voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer, in order to obtain the contact resistance of the conductive structure under test.

[0103] In one embodiment, the first interconnect structure is connected to the current and the second interconnect structure is grounded. The voltage between the third interconnect structure and the fourth interconnect structure is tested, and the voltage is divided by the current to obtain the contact resistance of the conductive structure under test.

[0104] In one embodiment, the first conductive switch layer and the second conductive switch layer are formed in one or two of the following: in any of the substrates, between any two adjacent substrates, and on one side of the at least two stacked substrates, to obtain the contact resistance of the conductive structure under test in any of the substrates or between any two adjacent substrates.

[0105] As can be seen from the above, the test structure and test method provided by the present invention include: at least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure are formed in the substrates; a first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrates or between two adjacent substrates; a redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates, wherein the redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively; a conductive structure under test is formed in the substrates or between two adjacent substrates; a first conductive switch layer and a second conductive switch layer are formed in the substrates, between two adjacent substrates, and on one side of the at least two stacked substrates. One or two of these conditions are chosen so that, when testing the contact resistance of the conductive structure under test, a current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer; and a voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer. That is, only one current loop and one voltage test loop are formed in the test structure. No current loop can be formed between the first interconnect structure and the third interconnect structure, or between the second interconnect structure and the fourth interconnect structure, thus avoiding the introduction of test noise and preventing any impact on the test results of the contact resistance of the conductive structure under test, thereby improving the accuracy of the test results.

[0106] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A test structure, characterized in that, include: At least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure and a fourth interconnect structure that are phase-insulated are formed in the substrates; A first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrate or between two adjacent substrates; A redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates. The redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively. The conductive structure to be tested is formed in the substrate or between two adjacent substrates; The first conductive switch layer and the second conductive switch layer are formed in one or two of the following locations, including in any one of the substrates, between any two adjacent substrates, and on one side of the at least two stacked substrates, such that when testing the contact resistance of the conductive structure under test in any one of the substrates or between any two adjacent substrates, a current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer, and a voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer.

2. The test structure as described in claim 1, characterized in that, The first interconnect structures, the second interconnect structures, the third interconnect structures, and the fourth interconnect structures in different substrates are electrically connected to each other.

3. The test structure as described in claim 2, characterized in that, When the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed in the substrate, the first auxiliary interconnect structure in different substrates is the same and the second auxiliary interconnect structure in different substrates is the same; when the first auxiliary interconnect structure and the second auxiliary interconnect structure are formed between two adjacent substrates, the first auxiliary interconnect structure and the second auxiliary interconnect structure between any two adjacent substrates are the same as the first auxiliary interconnect structure and the second auxiliary interconnect structure between any other two adjacent substrates.

4. The test structure as described in claim 2, characterized in that, The test structure also includes: A hybrid bonding layer includes two bonded first dielectric layers and a conductive bonding structure penetrating the two first dielectric layers; Wherein, when a redistribution layer is formed between two adjacent substrates, the hybrid bonding layer is formed between the redistribution layer and one of the two adjacent substrates, and the first interconnection structure, the second interconnection structure, the third interconnection structure and the fourth interconnection structure in one of the two adjacent substrates are electrically connected to the first conductive trace layer, the second conductive trace layer, the third conductive trace layer and the fourth conductive trace layer in the redistribution layer through the conductive bonding structure; When two redistribution layers are formed between two adjacent substrates, the hybrid bonding layer is formed between the two redistribution layers between the two adjacent substrates, and the first conductive routing layer, the second conductive routing layer, the third conductive routing layer, and the fourth conductive routing layer in the two redistribution layers are electrically connected through the conductive bonding structure respectively; When the redistribution layer is formed on one side of the at least two stacked substrates, the hybrid bonding layer is formed between two adjacent substrates, and the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure in the two adjacent substrates are electrically connected through the conductive bonding structure.

5. The test structure as described in claim 2, characterized in that, The substrate includes a substrate and an interlayer dielectric layer formed on the substrate, wherein the first interconnect structure, the second interconnect structure, the third interconnect structure and the fourth interconnect structure are formed in the interlayer dielectric layer.

6. The test structure as described in claim 5, characterized in that, The substrate also has a through-hole conductive structure that penetrates the substrate. When the substrate is closer to the redistribution layer than the interlayer dielectric layer, the first interconnect structure, the second interconnect structure, the third interconnect structure and the fourth interconnect structure are electrically connected to the first conductive trace layer, the second conductive trace layer, the third conductive trace layer and the fourth conductive trace layer respectively through the through-hole conductive structure.

7. The test structure as described in claim 2, characterized in that, The first conductive trace layer, the second conductive trace layer, the third conductive trace layer, and the fourth conductive trace layer each include a second metal layer, or include at least one second metal layer and at least one second conductive plug electrically connected to the second metal layer.

8. The test structure as described in claim 4, characterized in that, The conductive structure under test includes a conductive bonding structure penetrating the two first dielectric layers; when the first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates, and a redistribution layer is formed between the two adjacent substrates, In the current loop, the first interconnect structure in one of two adjacent substrates is electrically connected to the conductive bonding structure under test via a first auxiliary interconnect, a first bonding structure switch, and a first interconnect switch in sequence; the conductive bonding structure under test is electrically connected to the second conductive trace layer via a second auxiliary interconnect, a second bonding structure switch, and a second interconnect switch in sequence. In the voltage test loop, the third interconnect structure in one of two adjacent substrates is electrically connected to the conductive bonding structure under test via a third auxiliary interconnect; the conductive bonding structure under test is electrically connected to the fourth conductive trace layer via a third interconnect switch. The first auxiliary interconnect structure includes a first auxiliary interconnect line and a second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes a first bonding structure switch, a first interconnect line switch, a second bonding structure switch and a second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch; Alternatively, in the current loop, the first conductive trace layer and the conductive bonding structure under test are sequentially connected via a first interconnect switch, a first bonding structure switch, and a first auxiliary interconnect, and the conductive bonding structure under test is connected to the second conductive trace layer via a second interconnect switch; in the voltage test loop, the third conductive trace layer and the conductive bonding structure under test are connected via a third interconnect switch, and the conductive bonding structure under test and the fourth conductive trace layer are connected via a second auxiliary interconnect, a second bonding structure switch, and a fourth interconnect switch; the first auxiliary interconnect structure includes the first auxiliary interconnect, the second auxiliary interconnect structure includes the second auxiliary interconnect, the first conductive switch layer includes the first bonding structure switch, the first interconnect switch, and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch, the second bonding structure switch, and the fourth interconnect switch; When the first conductive switch layer and the second conductive switch layer are formed between two adjacent substrates, and two redistribution layers are formed between the two adjacent substrates, in the current loop, the first conductive trace layer in the upper redistribution layer of the two redistribution layers is electrically connected to the conductive bonding structure under test via a first auxiliary interconnect, a first bonding structure switch, and a first interconnect switch in sequence. The conductive bonding structure under test is electrically connected to the second conductive trace layer in the lower redistribution layer of the two redistribution layers via a second auxiliary interconnect, a second bonding structure switch, and a second interconnect switch in sequence. In the voltage test loop, the third conductive trace layer in the upper redistribution layer of the two redistribution layers is electrically connected to the conductive bonding structure under test via a third auxiliary interconnect. The conductive bonding structure under test is electrically connected to the fourth conductive trace layer in the lower redistribution layer of the two redistribution layers via a third interconnect switch. The first auxiliary interconnect structure includes a first auxiliary interconnect line and a second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes a first bonding structure switch, a first interconnect line switch, a second bonding structure switch and a second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch; The conductive bonding structure, the conductive bonding structure under test, the first bonding structure switch, and the second bonding structure switch are located on the same layer, and each includes two bonded first metal layers and a first conductive plug on the side of each first metal layer away from the bonding interface.

9. The test structure as described in claim 6, characterized in that, The conductive structure under test includes a via conductive structure penetrating the substrate; when the first conductive switch layer and the second conductive switch layer are formed in the substrate and between two adjacent substrates, and one or two redistribution layers are formed between the two adjacent substrates; or when the first conductive switch layer and the second conductive switch layer are formed in the substrate and on one side of the at least two stacked substrates, and the redistribution layer is formed on one side of the at least two stacked substrates, in the current loop, the first interconnect structure in the substrate where the via conductive structure under test is located and the via conductive structure under test are connected sequentially through a first auxiliary interconnect line and a first via. The conductive structure switch and the first interconnect switch are electrically connected. The conductive structure under test is connected to the second conductive trace layer in the redistribution layer of the substrate near the conductive structure under test via a second auxiliary interconnect, a second via conductive structure switch, and a second interconnect switch in sequence. In the voltage test circuit, the third interconnect structure in the substrate where the conductive structure under test is located is connected to the conductive structure under test via a third auxiliary interconnect. The conductive structure under test is connected to the fourth conductive trace layer in the redistribution layer of the substrate near the conductive structure under test via a third interconnect switch. The first auxiliary interconnect structure includes the first auxiliary interconnect line and the second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes the first through-hole conductive structure switch, the first interconnect line switch, the second through-hole conductive structure switch and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch; When the first conductive switch layer and the second conductive switch layer are formed in the substrate and between two adjacent substrates, and one or two redistribution layers are formed between two adjacent substrates, in the current loop, the first conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test is electrically connected to the conductive structure of the via under test in sequence through a first interconnect switch, a first via conductive structure switch, and a first auxiliary interconnect. The conductive structure of the via under test is electrically connected to the second conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test through a second interconnect switch. In the voltage test loop, the third conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test is electrically connected to the conductive structure of the via under test through a third interconnect switch. The conductive structure of the via under test is electrically connected to the fourth conductive trace layer in the redistribution layer of the substrate near the conductive structure of the via under test through a second auxiliary interconnect, a second via conductive structure switch, and a fourth interconnect switch. The first auxiliary interconnect structure includes the first auxiliary interconnect line, the second auxiliary interconnect structure includes the second auxiliary interconnect line, the first conductive switch layer includes the first through-hole conductive structure switch, the first interconnect line switch and the second interconnect switch, and the second conductive switch layer includes the third interconnect switch, the second through-hole conductive structure switch and the fourth interconnect switch; In the substrate where the conductive structure under test is located, the conductive structure under test, the first conductive structure switch, and the second conductive structure switch are located on the same layer.

10. The test structure as described in claim 7, characterized in that, The conductive structure under test includes a second conductive plug; the conductive structure under test, the first conductive switch layer, and the second conductive switch layer are formed between two adjacent substrates; one or two redistribution layers are formed between the two adjacent substrates, wherein the second metal layer of the first conductive trace layer, the second conductive trace layer, the third conductive trace layer, and the fourth conductive trace layer in one of the redistribution layers is electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure in one of the substrates respectively via the second conductive plug. In the current loop, the first interconnect structure in one of the substrates is electrically connected to the second conductive plug under test via a first auxiliary interconnect line, a first plug switch, and a first interconnect line switch in sequence; the second conductive plug under test is electrically connected to the second conductive trace layer in one of the redistribution layers via a second auxiliary interconnect line, a second plug switch, and a second interconnect line switch in sequence; in the voltage test loop, the third interconnect structure in one of the substrates is electrically connected to the second conductive plug under test via a third auxiliary interconnect line; the second conductive plug under test is electrically connected to the fourth conductive trace layer in one of the redistribution layers via a third interconnect line switch. The first auxiliary interconnect structure includes a first auxiliary interconnect line and a second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes a first plug switch, a first interconnect line switch, a second plug switch and a second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch; Alternatively, in the current loop, the first conductive trace layer in one of the redistribution layers is electrically connected to the second conductive plug under test via a first interconnect switch, a first plug switch, and a first auxiliary interconnect in sequence, and the second conductive plug under test is electrically connected to the second conductive trace layer in one of the redistribution layers via a second interconnect switch; in the voltage test loop, the third conductive trace layer in one of the redistribution layers is electrically connected to the second conductive plug under test via a third interconnect switch, and the second conductive plug under test is electrically connected to the fourth conductive trace layer in one of the redistribution layers via a second auxiliary interconnect, a second plug switch, and a fourth interconnect switch; The first auxiliary interconnect structure includes the first auxiliary interconnect line, the second auxiliary interconnect structure includes the second auxiliary interconnect line, the first conductive switch layer includes the first plug switch, the first interconnect line switch and the second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch, the second plug switch and the fourth interconnect line switch; Two redistribution layers are formed between two adjacent substrates. When the first conductive trace layer, the second conductive trace layer, the third conductive trace layer, and the fourth conductive trace layer in one of the redistribution layers each include at least two second metal layers and a second conductive plug located between adjacent second metal layers, in the current loop, the second metal layer at one end of the second conductive plug in the first conductive trace layer of one of the redistribution layers is electrically connected to the second conductive plug under test in sequence through a first auxiliary interconnect, a first plug switch, and a first interconnect switch. The second conductive plug under test is electrically connected to the second metal layer at the other end of the second conductive plug in the second conductive trace layer of one of the redistribution layers through a second auxiliary interconnect, a second plug switch, and a second interconnect switch. In the voltage test circuit, the second metal layer at one end of the second conductive plug in the third conductive trace layer of one of the redistribution layers is electrically connected to the second conductive plug under test through a third auxiliary interconnect line, and the second conductive plug under test is electrically connected to the second metal layer at the other end of the second conductive plug in the fourth conductive trace layer of one of the redistribution layers through a third interconnect line. The first auxiliary interconnect structure includes a first auxiliary interconnect line and a second auxiliary interconnect line, the second auxiliary interconnect structure includes the third auxiliary interconnect line, the first conductive switch layer includes a first plug switch, a first interconnect line switch, a second plug switch and a second interconnect line switch, and the second conductive switch layer includes the third interconnect line switch; The second conductive plug to be tested, the second conductive plug, the first plug switch, and the second plug switch are located on the same layer.

11. A testing method, characterized in that, include: Provide a test structure, the test structure including: At least two stacked substrates of the same type, wherein a first interconnect structure, a second interconnect structure, a third interconnect structure and a fourth interconnect structure that are phase-insulated are formed in the substrates; A first auxiliary interconnect structure and a second auxiliary interconnect structure are formed in the substrate or between two adjacent substrates; A redistribution layer is formed between two adjacent substrates or on one side of the at least two stacked substrates. The redistribution layer includes a first conductive trace layer, a second conductive trace layer, a third conductive trace layer, and a fourth conductive trace layer that are electrically connected to the first interconnect structure, the second interconnect structure, the third interconnect structure, and the fourth interconnect structure, respectively. The conductive structure to be tested is formed in the substrate or between two adjacent substrates; The first conductive switch layer and the second conductive switch layer are formed in one or two of the following locations, including in any one of the substrates, between any two adjacent substrates, and on one side of the at least two stacked substrates; A current is applied between the first interconnect structure and the second interconnect structure, and the voltage between the third interconnect structure and the fourth interconnect structure is tested. A current loop is formed between the first interconnect structure and the second interconnect structure through the first auxiliary interconnect structure, the conductive structure under test, the first conductive switch layer, and the first conductive trace layer and / or the second conductive trace layer. A voltage test loop is formed between the third interconnect structure and the fourth interconnect structure through the second auxiliary interconnect structure, the conductive structure under test, the second conductive switch layer, and the third conductive trace layer and / or the fourth conductive trace layer, in order to obtain the contact resistance of the conductive structure under test in any one of the substrates or between any two adjacent substrates.

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