Wafer stack structure and fabrication method

Abstract

The application discloses a wafer stacking structure and a manufacturing method, and belongs to the field of integrated circuit manufacturing.The wafer stacking structure comprises the following steps: step one, preparing a wafer with grooves on the surface;step two, setting an adhesive on the grooves;step three, attaching a silicon chip on the grooves;step four, filling plastic encapsulation resin above the wafer and around the silicon chip to form a plastic encapsulation layer; and step five, grinding the back surface of the silicon chip.The wafer is patterned by dry etching to form a wafer with several deep groove structures, and the wafer has increased bonding force between product materials due to the groove design on the wafer, so that the warping problem of conventional wafers in the manufacturing process can be solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically referring to a wafer stacking structure and its fabrication method. Background Technology

[0002] In the fields of integrated circuit manufacturing and semiconductor packaging, wafers, as the core carriers, undergo multiple processing steps, including thin film deposition, etching, and bonding. Subsequent molding processes are then used to protect and integrate the devices. However, due to the significant mismatch in the coefficients of thermal expansion (CTE) between the wafer, the process dielectric layer, and the molding material, conventional wafer products are prone to significant warpage under the combined effects of process thermal stress and material shrinkage stress. This warpage not only leads to a decrease in the process accuracy of subsequent processes (such as precision bonding and thinning), increasing the risk of yield loss, but also poses a significant technical challenge to warpage control, becoming one of the key bottlenecks restricting the mass production stability of highly integrated wafer products. Summary of the Invention

[0003] In response to the above situation and to overcome the shortcomings of the prior art, the present invention provides a wafer stacking structure and manufacturing method, which effectively solves the problem that conventional wafers on the market often have large warpages after multiple processes and molding due to the mismatch of the coefficients of thermal expansion (CTE) between different materials, which poses a great challenge to product warpage management.

[0004] The technical solution adopted by the present invention is as follows: The present invention proposes a wafer stacking structure and a fabrication method, including step one: preparing a wafer with trenches on its surface;

[0005] Step 2: An adhesive is applied to the trench;

[0006] Step 3: A silicon chip is mounted on the trench;

[0007] Step 4: Fill the wafer with molding resin and around the silicon chip to form a molding layer;

[0008] Step 5: Polish the back of the silicon chip.

[0009] Preferably, the depth of the trench is in the range of 50-100 micrometers.

[0010] Preferably, the wafer is provided with a plurality of units, the units having a size of 15mm x 15mm-26mm x 33mm, and each unit containing a plurality of trenches having a size of 2mm x 2mm-5mm x 5mm.

[0011] Preferably, each of the trenches is fitted with several silicon chips, the silicon chips being 0.5mm x 0.5mm to 1mm x 1mm in size, and the spacing between each silicon chip being 20mm to 50mm.

[0012] Preferably, the wafer is mounted with a plurality of silicon chips.

[0013] Preferably, the adhesive is injected into the groove through an injection head, and the method of applying the adhesive includes coating, spraying, and dotting.

[0014] Preferably, in step three, the silicon chip is picked up by a suction nozzle and placed on the trench.

[0015] Preferably, in step five, the molding compound is thinned using a grinding wheel to expose the back side of the silicon chip.

[0016] Furthermore, the wafer surface is provided with trenches, and a silicon chip is attached to the trenches by an adhesive, with a molding compound layer between the wafer and the silicon chip.

[0017] The beneficial effects achieved by using the above-mentioned structure of the present invention are as follows: The present invention proposes a wafer stacking structure and a fabrication method. This method uses dry etching to pattern the wafer to form a waffle structure. The waffle structure includes several trench structures. The trench structure reduces the thickness of the wafer body, effectively improving the heat dissipation performance in 3D chip stacking scenarios. At the same time, the trench structure increases the contact area between different materials, thereby enhancing the bonding force between different materials. This can significantly suppress the warping problem generated by conventional wafers in the process, thereby improving the mechanical reliability of the product. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of step one of the wafer stacking structure and fabrication method proposed in this invention;

[0019] Figure 2 This is a schematic diagram of step one of the wafer stacking structure and fabrication method proposed in this invention;

[0020] Figure 3 This is a schematic diagram of step two of the wafer stacking structure and fabrication method proposed in this invention;

[0021] Figure 4 This is a schematic diagram of step two of the wafer stacking structure and fabrication method proposed in this invention;

[0022] Figure 5 This is a schematic diagram of step three of the wafer stacking structure and fabrication method proposed in this invention;

[0023] Figure 6This is a schematic diagram of step three of the wafer stacking structure and fabrication method proposed in this invention;

[0024] Figure 7 This is a schematic diagram of step four of the wafer stacking structure and fabrication method proposed in this invention;

[0025] Figure 8 This is a schematic diagram of step four of the wafer stacking structure and fabrication method proposed in this invention;

[0026] Figure 9 This is a schematic diagram of step five of the wafer stacking structure and fabrication method proposed in this invention;

[0027] Figure 10 This is a schematic diagram of step five of the wafer stacking structure and fabrication method proposed in this invention;

[0028] Figure 11 This is a schematic diagram of the prior art regarding the wafer stacking structure and fabrication method proposed in this invention;

[0029] Figure 12 This is a schematic diagram of a wafer stacking structure and fabrication method proposed in this invention;

[0030] Figure 13 This is a schematic diagram of a wafer stacking structure and fabrication method proposed in this invention.

[0031] Figure 14 This is a unit schematic diagram of a wafer stacking structure and fabrication method proposed in this invention;

[0032] Figure 15 This is a schematic diagram of the trench in a wafer stacking structure and fabrication method proposed in this invention.

[0033] Among them, 1. wafer; 2. trench; 3. adhesive; 4. silicon chip; 5. molding compound; 6. cell; 7. injection head; 8. nozzle; 9. grinding wheel; 10. conventional wafer.

[0034] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0035] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0036] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0037] like Figures 1-15 As shown, this invention proposes a wafer stacking structure and its fabrication method, such as... Figures 1-2 As shown, the process includes step one: patterning the wafer by dry etching, the wafer structure having a diameter of 300 mm, forming a waffle-shaped wafer 1 with a trench 2 structure.

[0038] It should be noted that, as Figures 13-14 As shown, wafer 1 includes multiple units 6, where each unit 6 represents the area of ​​a single exposure. Each unit 6 has dimensions ranging from 15mm x 15mm to 26mm x 33mm, preferably 19.8mm x 19.8mm. Each unit 6 contains several trenches 2. The trenches 2 have a square cross-sectional shape, with dimensions ranging from 2mm x 2mm to 5mm x 5mm, preferably 3mm x 3mm. The depth of the trenches 2 ranges from 50 to 100 micrometers, preferably 70 micrometers. These trenches 2 can effectively balance the thermal stress distribution of wafer 1 in subsequent processes by reducing the local thickness of the wafer 1 body, avoiding stress concentration caused by differences in thermal expansion coefficients, and solving the warpage problem caused by mismatched thermal expansion coefficients in conventional wafer 1 processes. Meanwhile, the sidewalls of trench 2 are roughened to create a concave-convex structure, which increases the contact area between trench 2 and adhesive 3 and molding layer 5, significantly improving the interfacial bonding between product materials. This fundamentally solves the warping and deformation problem that is prone to occur in conventional flat wafers 1 during mounting and molding processes, ensuring the flatness and stability of the overall wafer structure and laying the foundation for subsequent high-precision mounting processes.

[0039] like Figures 3-4As shown, step two: Adhesive 3 is applied above the trench 2 area within wafer 1 via injection head 7. The adhesive 3 can be applied using any of the following methods: coating, spraying, or dot coating. During operation, ensure that adhesive 3 evenly covers the pre-set mounting area of ​​trench 2, without any defects such as missed areas or accumulation. The uniform coverage of adhesive 3 ensures a continuous and defect-free bonding interface in the trench 2 area. On one hand, it provides stable support and a bonding foundation for the silicon chip 4, preventing misalignment or loosening after mounting. On the other hand, it fills minor imperfections on the surface of trench 2, reducing interface gaps and improving the sealing performance of subsequent molding processes. Simultaneously, it enhances the stress transmission between the silicon chip 4 and wafer 1, reducing the risk of interface peeling due to temperature differences during the manufacturing process. Different adhesive 3 application methods can be adapted to different production scenarios, all ensuring the uniformity of adhesive 3 application and guaranteeing product quality during mass production.

[0040] like Figures 5-6 As shown, step three involves using the suction nozzle 8 to pick up the silicon chip 4 and precisely mount it onto the corresponding position above the trench 2 coated with adhesive 3. This enables the non-destructive and precise transfer of the silicon chip 4, avoiding surface damage or functional failure and ensuring the compatibility between the silicon chip 4 and the trench 2 structure. Multiple silicon chips 4 are mounted within each trench 2 area, ensuring even weight distribution across the trench support area and further improving the overall stress balance of the wafer 1. Simultaneously, precise mounting and positioning ensure that the encapsulating resin can evenly fill the gaps around the silicon chip 4, preventing insufficient or excessive resin filling due to silicon chip 4 misalignment, thus ensuring product structural consistency and stability.

[0041] It should be noted that, as Figure 15 As shown, the dimensions of silicon chips 4 range from 0.5mm x 0.5mm to 1mm x 1mm, preferably 1mm x 1mm or 1mm x 0.5mm, and the spacing between adjacent silicon chips 4 is 20mm-50mm. Multiple silicon chips 4 are mounted on the entire wafer 1. The distribution of silicon chips 4 makes full use of the space in the trench 2 area, achieving high integration and increasing the chip load per unit area of ​​wafer 1. At the same time, the reasonable size matching of silicon chips 4 and the spacing setting of trench 2 can not only avoid signal interference between adjacent silicon chips 4, but also reserve sufficient channels for the subsequent flow and filling of molding resin, ensuring the molding quality of molding layer 5 and improving the electrical performance and structural reliability of the product.

[0042] like Figures 7-8As shown, step four involves using a molding process to fill the space above wafer 1 and the surrounding area of ​​silicon chip 4 with molding resin, forming an encapsulating layer 5. This layer protects wafer 1 and silicon chip 4, isolating them from external moisture, dust, and other impurities, preventing silicon chip 4 from failing due to environmental corrosion. It also buffers external mechanical impacts and vibrations, protecting the silicon chip 4 from damage to its bonding interface. Furthermore, the molding layer 5 provides insulation, preventing short circuits between adjacent silicon chips 4, improving the product's electrical safety and environmental adaptability, and extending its lifespan.

[0043] like Figures 9-10 As shown, step five involves the grinding wheel 9 grinding and thinning the back of the molding compound 5 and the silicon chip 4. This precise control of the grinding thickness corrects the flatness of the molding compound 5 surface and ensures the flatness of the wafer stacking structure after grinding. Besides directly improving the product's heat dissipation performance, it also reduces the overall product thickness, enabling a thinner and lighter design that meets the application requirements of miniaturized, high-density packaging. Simultaneously, it ensures that the product's appearance and dimensional accuracy meet the requirements of subsequent cutting and packaging processes. Furthermore, the grinding wheel 9 exposes the back of the silicon chip 4, allowing heat to be directly conducted to the outside environment or a heat dissipation structure. Compared to indirect heat dissipation through the molding compound 5, this significantly improves heat dissipation efficiency, effectively reducing the operating temperature of the silicon chip 4 and preventing performance degradation or shortened lifespan due to high temperatures, thus ensuring stable operation of the product under high-power conditions.

[0044] This invention provides a wafer stacking structure, such as Figure 11 As shown, compared to existing technologies, conventional wafers 10, after undergoing multiple processes and molding, suffer from severe warping due to the mismatch in the coefficients of thermal expansion (CTE) between different materials.

[0045] like Figure 12 As shown, this invention provides physical positioning constraints for the silicon chip 4 by setting trenches 2 on the surface of wafer 1, preventing horizontal displacement. The silicon chip 4 is attached to the trenches 2 by adhesive 3, which securely connects the silicon chip 4 to the wafer 1 in the vertical direction. A molding compound 5 is provided between the wafer 1 and the silicon chip 4, filling all gaps to form an integrated protective and support structure. This provides a reliable foundation for subsequent multi-layer stacking, increases the bonding force between product materials, and balances the distribution of thermal stress, thus fundamentally solving the warpage problem caused by wafers during the manufacturing process. Simultaneously, this structural design significantly improves the mechanical strength and environmental adaptability of the stacking structure, preventing the silicon chip 4 from shifting or falling off during handling, stacking, or use. The molding compound 5 effectively isolates moisture, impurities, and external mechanical impacts, improving the lifespan and reliability of the silicon chip 4. The regular structural layout ensures the accuracy of subsequent stacking interconnects, adapting to the needs of high-density, multi-level wafer stacking, and providing reliable structural support for the integrated development of high-end semiconductor devices.

[0046] The above is the overall workflow of this invention. Simply repeat this process the next time you use it.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0048] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0049] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for fabricating a wafer stacked structure, characterized in that: The wafer stacking fabrication method includes the following steps: Step 1: Prepare a wafer (1) with grooves (2) on its surface; Step 2: An adhesive (3) is provided on the groove (2); Step 3: A silicon chip (4) is attached to the trench (2); Step 4: Fill the wafer (1) and the silicon chip (4) with molding resin to form a molding layer (5); Step 5: Polish the back side of the silicon chip (4).

2. The method for fabricating a wafer stacking structure according to claim 1, characterized in that: The depth of the trench (2) ranges from 50 to 100 micrometers.

3. The method for fabricating a wafer stacking structure according to claim 2, characterized in that: The wafer (1) is provided with a plurality of units (6), the unit (6) having a size of 15mm x 15mm - 26mm x 33mm, and each unit (6) containing a plurality of trenches (2) having a size of 2mm x 2mm - 5mm x 5mm.

4. The method for fabricating a wafer stacking structure according to claim 2, characterized in that: Several silicon chips (4) are mounted on each of the trenches (2), the silicon chips (4) are 0.5mm x 0.5mm to 1mm x 1mm in size, and the spacing between each silicon chip (4) is 20mm to 50mm.

5. The method for fabricating a wafer stacking structure according to claim 3, characterized in that: Multiple silicon chips (4) are mounted on the wafer (1).

6. The method for fabricating a wafer stacking structure according to claim 1, characterized in that: The adhesive (3) is injected into the groove (2) through the injection head (7), and the adhesive (3) is applied by coating, spraying and dotting.

7. The method for fabricating a wafer stacking structure according to claim 1, characterized in that: In step three, the silicon chip (4) is picked up by the nozzle (8) and placed on the trench (2).

8. The method for fabricating a wafer stacking structure according to claim 1, characterized in that: In step five, the molding layer (5) is thinned by a grinding wheel (9) to expose the back side of the silicon chip (4).

9. The wafer stacked structure prepared by any one of the fabrication methods according to claims 1-8, characterized in that: The wafer (1) has a trench (2) on its surface, and a silicon chip (4) is attached to the trench (2) by an adhesive (3). A molding compound (5) is provided between the wafer (1) and the silicon chip (4).

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