Method of forming a stacked aip structure and semiconductor device

Abstract

Methods of forming a stacked AIP structure and semiconductor devices are disclosed. The semiconductor device has an antenna substrate, an electrical component disposed over the antenna substrate, and a semiconductor assembly disposed over the electrical component. The electrical component has a first active surface and a second active surface opposite the first active surface, with a conductive via extending between the first active surface and the second active surface. An encapsulant is deposited over and around the antenna substrate and the electrical component. The encapsulant can be deposited over the semiconductor assembly. Portions of the encapsulant are removed to expose the semiconductor assembly. A mask is disposed over the semiconductor assembly. A shielding layer is disposed over and around the antenna substrate, the electrical component, and the semiconductor assembly. The mask blocks the shielding layer from covering portions of the semiconductor assembly. The mask is removed, and an electrical connector is disposed over the semiconductor assembly previously protected by the mask.

Description

Technical Field

[0001] This invention generally relates to semiconductor devices, and more particularly to methods and semiconductor devices for forming a stacked antenna-level package (AiP) structure from discrete components having bonding materials. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communications, often include one or more integrated passive devices (IPDs) to perform necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a system-in-package (SiP) module for higher density and expanded electrical functionality in a small space. Within the SiP module, semiconductor dies and IPDs are deployed across a first surface of the substrate for structural support and electrical interconnection. An encapsulation is deposited on the semiconductor dies, IPDs, and substrate.

[0004] Antennas can be deployed on the second surface of the substrate to provide wireless communication for the SiP module. With the addition of antennas, the SiP constitutes an AiP. With the semiconductor die and IPD extending horizontally across the surface of the substrate, no single device can become excessively large. Otherwise, the semiconductor package might exceed size requirements. Therefore, the current AiP module limits the size of any single semiconductor device. Attached Figure Description

[0005] Figures 1a to 1e The illustration shows various semiconductor wafers, each having multiple semiconductor dies separated by saw tracks; Figures 2a to 2o The illustration shows the process of forming an AiP module with stacked dual-sided electrical components and semiconductor assemblies on top of the antenna intermediate portion; Figures 3a to 3c The diagram illustrates the formation Figures 2a to 2o The processing of semiconductor components used; Figures 4a to 4b The diagram illustrates the alternative semiconductor components; Figures 5a to 5h The illustration shows another process of forming an AiP module with stacked dual-sided electrical components and semiconductor assemblies on top of the antenna interposer; and Figure 6The illustration shows a PCB with different types of packages deployed on the surface of a printed circuit board (PCB). Detailed Implementation

[0006] The invention is described in one or more embodiments in the following description with reference to the figures, in which the same reference numerals denote the same or similar elements. While the invention has been described in view of the best mode for achieving the objectives of the invention, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, as well as their equivalents as supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0007] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage-current relationship necessary for the circuit to function.

[0008] Back-end manufacturing refers to the process of dicing or isomerizing a finished wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To isomerize a semiconductor die, the wafer is etched and damaged along non-functional areas known as scribes. Laser cutting tools or saw blades are used to isomerize the wafer. After isomerization, the individual semiconductor dies are deployed onto a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, pillar bumps, conductive paste, or wiring. Encapsulation or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the functionality of the semiconductor device available to other system components.

[0009] Figure 1aA semiconductor wafer 100a is shown having a substrate material 102 for structural support, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials. Multiple semiconductor dies or components 104a are formed on the wafer 100a, separated by non-active inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100a into individual semiconductor dies 104a. In one embodiment, the semiconductor wafer 100a has a width or diameter of 100-450 millimeters (mm). The semiconductor dies 104a can handle RF signals transmitted and received via an antenna.

[0010] Figure 1b A cross-sectional view of a portion of semiconductor wafer 100a is shown. In one embodiment, each semiconductor die 104a is a dual-sided device having an active surface 108 and an active surface 110, both of which contain active devices, passive devices, conductive layers, and dielectric layers of analog or digital circuitry implemented within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surfaces 110 and 108 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. Semiconductor die 104a may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors. In one embodiment, semiconductor die 104a is an RFIC, monolithic microwave integrated circuit (MMIC), or system-on-a-chip (SoC) type die.

[0011] Multiple vias are formed between the active surface 110 and the active surface 108 using an etching process or by direct laser ablation (LDA) through a substrate material 102. The vias are filled with a conductive material, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material, to form conductive vias 111 extending between the active surface 110 and the active surface 108.

[0012] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. Similarly, a conductive layer 113 is formed on the active surface 108 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. Conductive layers 112 and 113 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layers 112 and 113 function as contact pads for circuitry electrically connected to the active surfaces 110 and 108, respectively.

[0013] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monomerize a semiconductor wafer 100a into individual semiconductor dies 104a through a saw path 106. The individual semiconductor dies 104a can be inspected and electrically tested for identification of known good dies or cells (KGD / KGU) after monomerization.

[0014] Other types of semiconductor dies can be manufactured using a wafer 100b similar to semiconductor wafer 100a. For example, Figure 1d Semiconductor dies 104b are shown below, each having an active surface 110 and a back or passive surface 109 containing analog or digital circuitry implemented within the die and electrically interconnected with active devices, passive devices, conductive layers, and dielectric layers according to the die's electrical design and function. Components with similar functions are assigned the same reference numerals. The circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as DSPs, ASICs, memory, or other signal processing circuitry. Semiconductor dies 104b may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0015] exist Figure 1e In this process, a saw blade or laser cutting tool 118 is used to monomerize a semiconductor wafer 100b into individual semiconductor dies 104b through a saw path 106. The individual semiconductor dies 104b can be inspected and electrically tested for identification of KGD / KGU after monomerization.

[0016] Figures 2a to 2o The illustration shows the process of forming an AiP module with stacked dual-sided electrical components and semiconductor assemblies on top of the antenna intermediate portion. Figure 2a A cross-sectional view of an antenna substrate 120 including a core material 124 for structural support is shown. The core material 124 may be, for example, silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials. Alternatively, the core material 124 may be a multilayer flexible laminate, ceramic, CCL, glass, or epoxy molding compound. The core material 124 may comprise one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), alumina (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The antenna substrate 120 has a main surface 126 and a main surface 128 opposite to surface 126.

[0017] A conductive layer 122 is formed on and through the antenna substrate 120 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 extends vertically and horizontally through the antenna substrate 120 to provide electrical interconnections. The conductive layer 122 is also formed on surface 128 and functions as an antenna 130 to transmit and receive RF signals. Portions of the conductive layer 122 may be electrically shared or electrically isolated depending on the design and function of the electrical components attached to it.

[0018] Figure 2b This is a top view of one embodiment of the antenna 130 on surface 128. The conductive layer 130 includes an array of islands 134 of conductive material suitable for providing RF signal transmission and reception, i.e., RF antennas. In particular, the antenna islands 134 of the conductive layer 122 are exposed from surface 128 to improve RF transmission and reception performance and quality.

[0019] Figure 2c A cross-sectional view of an interconnect substrate or interposer 140 comprising one or more conductive layers 142 and one or more insulating layers 144 is shown. The conductive layer 142 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 142 may be formed using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 142 provides horizontal electrical interconnects across the substrate and vertical electrical interconnects between the top surface 146 and the bottom surface 148 of the substrate 140. Depending on the design and function of the semiconductor dies 104a and 104b and other electrical components, portions of the conductive layer 142 may be electrically shared or electrically isolated. The insulating layer 144 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 144 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 144 provides isolation between the conductive layers 142. Multiple conductive layers, such as 142, may be present, separated by the insulating layer 144.

[0020] The surface 148 of the interposer 140 is bonded to the surface 126 of the antenna substrate 120. The interposer 140 may be bonded to the antenna substrate 120 using direct wafer bonding (DWB). In DWB, the surfaces 148 of the interposer 140 and 126 of the antenna substrate 120 are planarized, polished, and cleaned to be flat and smooth before bonding. The lattice structure of the interface layer can be aligned to optimize adhesion. Water molecules can be applied to surfaces 148 and 126 to assist the bonding process. The surface 148 of the interposer 140 is brought into contact with the surface 126 of the antenna substrate 120. DWB is achieved between surfaces 148 and 126 using chemical bonds and intermolecular interactions, including van der Waals forces, hydrogen bonds, and covalent bonds, at certain temperatures. The DWB temperature range is from ambient temperature to several hundred degrees Celsius. Figure 2d An intermediate portion 140 is shown on the surface 126 of the antenna substrate 120 where the wafer is directly bonded. Alternatively, the intermediate portion 140 is bonded to the antenna substrate 120 using an adhesive.

[0021] In another embodiment, the intermediate portion 140 is formed on the surface 126 of the antenna substrate 120 using a construction interconnect process. A first conductive layer 142 is formed on the surface 126 of the antenna substrate 120. A first insulating layer 144 is formed on the first conductive layer 142. A portion of the first insulating layer 144 is removed to expose the first conductive layer 142. A second conductive layer 142 is formed on and contacts the first insulating layer 144. A second insulating layer 144 is formed on the first insulating layer 144 and the second conductive layer 142. A portion of the second insulating layer 144 is removed to expose the second conductive layer 142. A third conductive layer 142 is formed on and contacts the second insulating layer 144. A third insulating layer 144 is formed on the second insulating layer 144 and the third conductive layer 142. A portion of the third insulating layer 144 is removed to expose the third conductive layer 142. Processing continues until intermediate portion 140 has all the necessary conductive layers 142 and insulating layers 144, as in Figure 2e As shown in the image.

[0022] In any case, the combination of antenna substrate 120 and intermediate portion 140 constitutes Figure 2d or Figure 2e The antenna intermediate part 150 in the middle.

[0023] exist Figure 2f In this configuration, one or more electrical components 152 are disposed on the surface 146 of the intermediate portion 140. The electrical components 152 are positioned on the intermediate portion substrate 140 using pick-and-place operations. For example, the electrical components 152 can interact with components from... Figure 1cSimilar to semiconductor die 104a, bump 114 is oriented toward surface 146. Alternatively, electrical component 152 may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, or IPDs. Bump 114 is contacted with and reflowed into conductive layer 162 for electrical and mechanical interconnection. Figure 2g An electrical component 152 is shown deployed on surface 146 of the intermediary portion 140. The electrical component 152 can be a relatively large device occupying a significant portion of the intermediary portion 140, such as a dual-sided RFIC with interconnecting conductive vias 111. The large size of the electrical component 152 provides more components above both the active surfaces 108 and 110 interconnected by the conductive vias 111. Dual-sided devices are more space-efficient and provide a higher density of components per unit area. The large electrical component 152 can replace many smaller components that conventionally extend across the surface area of ​​the antenna intermediary portion 150. In one embodiment, the electrical component 152 occupies more than 50% of the surface area of ​​the antenna intermediary portion 150. Preferably, the electrical component 152 occupies more than 60% of the surface area of ​​the antenna intermediary portion 150.

[0024] Figure 3a A cross-sectional view of an interconnect substrate or interposer 160 comprising one or more conductive layers 162 and one or more insulating layers 164 is shown. The conductive layer 162 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 162 may be formed using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 162 provides horizontal electrical interconnects across the substrate and vertical electrical interconnects between the top surface 166 and the bottom surface 168 of the substrate 160. Depending on the design and function of the semiconductor dies 104a and 104b and other electrical components, portions of the conductive layer 162 may be electrically shared or electrically isolated. The insulating layer 164 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 164 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 164 provides isolation between the conductive layers 162. Multiple conductive layers, such as 162, can be present, separated by the insulating layer 164.

[0025] exist Figure 3bIn this embodiment, multiple electrical components 170a, 170b, and 170c are deployed on the surface 166 of the intermediate portion 160. Electrical components 170a to 170c are positioned on the intermediate portion substrate 160 using pick-and-place operations. For example, electrical components 170a and 170b may be discrete semiconductor devices, such as resistors, capacitors, inductors, diodes, and transistors, having terminals 172 connected to a conductive layer 162 using solder or conductive paste 174. Electrical component 170c can be coupled to components from... Figure 1e Similar to semiconductor die 104b, bump 114 is oriented toward surface 166 of the interposer substrate 160. Alternatively, electrical components 170a to 170c may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical components, or IPDs. Bump 114 is contacted with and reflowed into conductive layer 162 for electrical and mechanical interconnection. Figure 3c Electrical components 170a to 170c are shown deployed on surface 166 of intermediate portion 160, wherein bumps 114 are electrically and mechanically connected to conductive layer 162.

[0026] The conductive bump material is deposited on surface 168 above conductive layer 162 using evaporation, electroplating, electroless plating, droplet coating, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 162 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 176. In one embodiment, bumps 176 are formed on under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 176 can also be compression bonded or thermocompressed bonded to conductive layer 162. Bumps 176 represent a type of interconnect structure that can be formed on conductive layer 162. The interconnect structure can also use bonded wiring, conductive paste, column bumps, microbumps, or other electrical interconnects. From Figure 3c Electrical components 170a to 170c and an interposer 160 with bumps 176 represent a semiconductor assembly 178. In one embodiment, the semiconductor assembly 178 incorporates a power management system (PMIC), such as electrical component 170c. The PMIC controls the operation of power devices, such as electrical component 152 implemented as an RFIC.

[0027] return Figure 2h , from Figure 3c Semiconductor component 178 was deployed from Figure 2gThe semiconductor component 178 is positioned on the active surface 108 of the electrical component 152 using pick-and-place operations. Bumps 176 are brought into contact with and recirculated through the conductive layer 142 for electrical and mechanical interconnection. Figure 2i A semiconductor assembly 178 is shown deployed on surface 108 of electrical component 152, wherein bumps 176 are electrically and mechanically connected to conductive layer 142.

[0028] exist Figure 2j In this process, an encapsulant or molding compound 180 is deposited on and around the semiconductor assembly 178, electrical component 152, and antenna interposer 150 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 180 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. The encapsulant 180 is non-conductive, provides structural support, and protects the semiconductor device from external factors and contaminants in the environment. A portion of the encapsulant 180 is removed by a grinder 181, exposing region 182 of the interposer 160.

[0029] exist Figure 2k In this configuration, mask 184 is deployed in region 182 above intermediary section 160. Note the separation between mask 184 and surface 185 of encapsulation 180.

[0030] Electrical components 152 and 170a to 170c may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in electrical components 152 and 170a to 170c provide the electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 152 and 170a to 170c include digital circuitry that switches at high frequencies, which may interfere with the operation of the IPDs within the components.

[0031] To address EMI, RFI, harmonic distortion, and inter-device interference, electromagnetic shielding material 186 is applied over the mask 184 and encapsulation 180 covering the semiconductor assembly 178 and the antenna interposer 150, including the side surfaces 188 and 190 of the encapsulation 180 and the antenna interposer 150, as shown in... Figure 2lAs shown in the diagram. Electromagnetic shielding material 186 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 186 can be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and compounds capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0032] exist Figure 2m In this process, a portion of the shielding material 186 on the mask 184 is removed through etching, LDA, or grinding operations, leaving an exposed conductive layer 162 on the surface 166 of the intermediate portion 160. Figure 2n In this configuration, an electrical connector 194 having contacts 196 and bump material or conductive paste 198 is deployed on an exposed conductive layer 162 on the surface 166 of an intermediate portion 160. The bumps 198 are brought into contact with the exposed conductive layer 162 and reflowed or cured to achieve electrical and mechanical interconnection with respect to the conductive layer. Figure 2o The shielding material 186 deployed on the encapsulation 184 and the electrical connector 194 connected to the intermediary 160 and the antenna intermediary 150 are shown.

[0033] Figure 2o This illustrates an AiP module 200 with dual-sided electrical components 152 (active surfaces interconnected by conductive vias 111) deployed between an antenna interposer 150 and semiconductor components 178 (including a PMIC). The electrical components 152 have a larger footprint and accommodate higher density circuitry and functionality due to the nature of their dual-sided structure, which includes conductive vias 111 providing connectivity between the two active sides 108 and 110. By stacking the semiconductor components 178 on top of the electrical components 152 and then stacking the electrical components 152 on top of the antenna interposer 150, the AiP module 200 accommodates the large electrical components 152 while minimizing the overall package size.

[0034] In another embodiment, from Figure 3c Continue by using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable coaters to deposit the encapsulation or molding compound 202 on and around the semiconductor component 178, as in... Figure 4a As shown in the diagram. Components with similar functions are assigned the same reference numerals. Encapsulation 202 can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or a polymer with suitable filler. Encapsulation 202 is non-conductive, provides structural support, and protects the semiconductor device from external factors and contaminants in the environment. Removal of portions of encapsulation 202 by grinding is similar to... Figure 2jThis exposes region 204 of the intermediate portion 160. A semiconductor component 178 having an encapsulation 202 constitutes semiconductor component 210. In one embodiment, semiconductor component 210 incorporates a PMIC, such as electrical component 170c. The PMIC controls power devices, such as electrical component 152 implementing an RFIC.

[0035] exist Figure 4b In this process, conductive bump material is deposited on surface 168 above conductive layer 162 using evaporation, electroplating, electroless plating, droplet coating, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 162 using suitable attachment or bonding processes. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 206. In one embodiment, bumps 206 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 206 can also be compression bonded or thermocompressed bonded to conductive layer 162. Bumps 206 represent a type of interconnect structure that can be formed on conductive layer 162. Interconnect structures can also use bonded wiring, conductive paste, column bumps, microbumps, or other electrical interconnects. Figure 4b The electrical components 170a to 170c and the intermediate portion 160 with bumps 206 represent the semiconductor assembly 210. In one embodiment, the semiconductor assembly 210 incorporates a PMIC, such as the electrical component 170c.

[0036] from Figure 2g Continue by using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicators to deposit the encapsulation or molding compound 214 on and around the electrical component 152 and the antenna intermediary 150, as shown in... Figure 5a As shown in the diagram. Encapsulation 214 can be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with suitable filler. Encapsulation 214 is non-conductive, provides structural support, and protects the semiconductor device from external factors and contaminants in the environment.

[0037] exist Figure 5b In the middle, semiconductor component 210 from Figure 4 is deployed from Figure 5a The semiconductor component 210 is positioned on the active surface 108 of the electrical component 152 using pick-and-place operations. Bumps 206 are brought into contact with and recirculated through the conductive layer 142 for electrical and mechanical interconnection. Figure 5cA semiconductor assembly 210 is shown deployed on surface 108 of electrical component 152, wherein bumps 206 are electrically and mechanically connected to conductive layer 142.

[0038] exist Figure 5d In this process, an underfill material 216, such as epoxy resin, is deposited between the semiconductor component 210 and the electrical component 152.

[0039] exist Figure 5e In this configuration, mask 220 is deployed in region 204 above intermediate section 160. Note the separation between mask 220 and surface 222 of encapsulation 202.

[0040] Electrical components 152 and 170a to 170c may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in electrical components 152 and 170a to 170c provide the electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 152 and 170a to 170c include digital circuitry that switches at high frequencies, which may interfere with the operation of the IPDs within the components.

[0041] To address EMI, RFI, harmonic distortion, and inter-device interference, electromagnetic shielding material 224 is applied over the mask 220 covering the semiconductor assembly 210 and the antenna interposer 150, as well as over the encapsulations 202 and 214, including the side surface 222 of the encapsulation 202 and the side surface 223 of the encapsulation 214, as shown in... Figure 5f As shown in the diagram. Electromagnetic shielding material 224 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 224 can be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and compounds capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0042] exist Figure 5g In this process, a portion of the shielding material 224 on the mask 220 is removed through etching, LDA, or grinding operations, leaving an exposed conductive layer 162 on the surface 166 of the intermediate portion 160. Figure 5h In this configuration, an electrical connector 230 having contacts 232 and bump material or conductive paste 234 is deployed on top of an exposed conductive layer 162 on the surface 166 of the intermediate portion 160, similar to... Figure 2n The bump 234 is brought into contact with the exposed conductive layer 162 and reflowed or cured to enable electrical and mechanical interconnection of the conductive layer.

[0043] Figure 5h AiP module 240 is shown having dual-sided electrical components 152 (interconnected by conductive vias 111) deployed between antenna interposer 150 and semiconductor assembly 210 (including PMIC). The electrical components 152 have a larger footprint and accommodate higher density circuitry and functionality due to the nature of their dual-sided structure, which has conductive vias 111 providing connectivity between the two active sides 108 and 110. By stacking semiconductor assembly 210 on top of electrical components 152 and then stacking electrical components 152 on top of antenna interposer 150, AiP module 240 accommodates large electrical components 152 while minimizing the overall package size.

[0044] Figure 6 The illustration shows an electronic device 400 having a chip carrier substrate or PCB 402, which has multiple semiconductor packages, including AiP modules 200 and 240, deployed on the surface of the PCB 402. Depending on the application, the electronic device 400 may have one type of semiconductor package or multiple types of semiconductor packages.

[0045] Electronic device 400 may be a standalone system using semiconductor packaging to perform one or more electrical functions. Alternatively, electronic device 400 may be a sub-component of a larger system. For example, electronic device 400 may be a part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 400 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density.

[0046] exist Figure 6 In this context, PCB 402 provides a general-purpose substrate for the structural support and electrical interconnection of semiconductor packages deployed on a PCB. Conductive signal traces 404 are formed on the surface of PCB 402 or within layers of PCB 402 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor package, mounted components, and other external system components. Trace 404 also provides power and ground connections to each of the semiconductor packages.

[0047] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly and mechanically deployed on the PCB.

[0048] For illustrative purposes, several types of first-level packages, including bonded wiring packages 406 and flip chips 408, are shown on PCB 402. Additionally, several types of second-level packages, including ball grid arrays (BGAs) 410, bumped chip carriers (BCCs) 412, planar grid arrays (LGAs) 416, multi-chip modules (MCMs) or SIP modules 418, quad flat no-lead packages (QFNs) 420, quad flat packages 422, embedded wafer-level ball grid arrays (eWLBs) 424, and wafer-level chip-scale packages (WLCSPs) 426, are shown deployed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer-level package (Fo-WLP), and WLCSP 426 is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package styles, as well as other electrical components, can be connected to PCB 402. In some embodiments, electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0049] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations to these embodiments can be made without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: Antenna substrate; An electrical component is deployed on an antenna substrate, wherein the electrical component includes a first active surface and a second active surface opposite to the first active surface, and has a conductive via extending between the first active surface and the second active surface. as well as Semiconductor components are deployed on top of electrical components.

2. The semiconductor device of claim 1, further comprising: Encapsulation material is deposited on and around the antenna substrate and electrical components.

3. The semiconductor device of claim 1, further comprising: Encapsulation material, which is deposited on semiconductor components.

4. The semiconductor device of claim 1, further comprising: A shielding layer is deployed on and around the antenna substrate, electrical components, and semiconductor components.

5. The semiconductor device of claim 1, further comprising: Masks are deployed on top of semiconductor components.

6. A semiconductor device, comprising: Antenna substrate; Electrical components are deployed on the antenna substrate; and Semiconductor components are deployed on top of electrical components.

7. The semiconductor device of claim 6, wherein the electrical component includes a first active surface and a second active surface opposite to the first active surface, having a conductive via extending between the first active surface and the second active surface.

8. The semiconductor device of claim 6, further comprising: Encapsulation material is deposited on and around the antenna substrate and electrical components.

9. The semiconductor device of claim 6, further comprising: A shielding layer is deployed on and around the antenna substrate, the first electrical component, and the semiconductor assembly.

10. The semiconductor device of claim 6, further comprising: Masks are deployed on top of semiconductor components.

11. A method for manufacturing a semiconductor device, comprising: Provide antenna substrate; An electrical component is deployed on an antenna substrate, wherein the electrical component includes a first active surface and a second active surface opposite to the first active surface, and has a conductive via extending between the first active surface and the second active surface. as well as Semiconductor components are deployed on top of electrical components.

12. The method of claim 11, further comprising: Encapsulation is deposited on and around the antenna substrate and electrical components.

13. The method of claim 11, further comprising: Encapsulation is deposited on semiconductor components.

14. The method of claim 11, further comprising: A shielding layer is deployed on and around the antenna substrate, electrical components, and semiconductor assemblies.

15. The method of claim 11, further comprising: Deploy masks on top of semiconductor components.

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