Power device compatible with 6-inch wafer production line and method for manufacturing the same

Abstract

The application discloses a power device compatible with a 6-inch wafer production line, which is provided with a substrate, an epitaxial layer, a dielectric stack, an etching stop layer and an interlayer dielectric layer from bottom to top in sequence, is provided with a small-size ohmic contact metal between the epitaxial layer and the dielectric stack, is provided with an intermediate metal layer in the dielectric stack, is provided with a first window on the etching stop layer and directly above the intermediate metal layer, is provided with a stepped first via hole above the intermediate metal layer, is provided with a first metal layer matched with the shape of the first via hole in the first via hole, and the first metal layer is electrically connected with the ohmic contact metal through the intermediate metal layer. The application further discloses a preparation method of the power device. The first metal layer is designed as a stepped structure and the intermediate metal layer is additionally arranged, so that the size of the ohmic contact metal is reduced, the distance between the first metal layer and the gate metal is increased, the chip size is reduced, and the production cost is low.

Description

Technical Field

[0001] This invention relates to semiconductor power devices, and more specifically to a power device compatible with a 6-inch wafer production line and its fabrication method. Background Technology

[0002] Currently, in the field of CMOS integrated circuit chip manufacturing, mature processes generally employ 8-inch or 12-inch wafer production lines to achieve higher integration and production efficiency. However, for many power semiconductor devices, due to relatively large linewidth requirements, production cost control needs, or the characteristics of specific semiconductor materials, their manufacturing still widely relies on 6-inch wafer production lines. In particular, emerging devices based on second-, third-, and even fourth-generation semiconductor materials (such as GaN and SiC) are often manufactured using 6-inch or even 4-inch wafer production lines due to limitations in epitaxial wafer size and process maturity.

[0003] In 6-inch power semiconductor wafer production lines, advanced process capabilities such as dielectric chemical mechanical polishing (CMP) and tungsten plugs are typically lacking. These processes are usually found in 8-inch or 12-inch production lines and are used to achieve high aspect ratio via filling and planarization between multilayer metal interconnects. Therefore, in existing 6-inch production lines, the metal interconnect process flow is typically as follows: first, vias are formed through dielectric etching; due to the lack of CMP and tungsten plug processes, the aspect ratio of the vias needs to be controlled at a low level; then, they are directly filled with subsequent metal layers to achieve electrical connection with the underlying metal layers.

[0004] As the rated operating voltage of power chips increases, the thickness of the dielectric layer between Metal1 and Metal2 must be increased accordingly to withstand higher electric field strengths and ensure device withstand voltage reliability. This increased dielectric layer thickness also leads to a greater depth of the vias. To maintain a low aspect ratio feasible for the process, the lateral dimensions of the vias must be correspondingly enlarged. Simultaneously, to meet safety clearance requirements under high voltage, a greater distance must be maintained between the drain region (Metal1) and the gate metal, making it difficult to extend the drain (Metal1) towards the gate to accommodate the vias above.

[0005] To address these contradictions, existing technologies typically employ two approaches: one is to increase the size of the ohmic metal or ohmic open to provide a larger contact area; the other is to introduce additional irregular structures or bus layouts to achieve the required electrical connections within a limited area. However, these methods not only significantly increase the effective area of ​​the chip, leading to decreased wafer utilization and increased costs, but also make chip layout design more complex, affecting the consistency and reliability of device performance.

[0006] Introducing CMP and tungsten plug processes into existing 6-inch production lines could technically improve via filling capabilities, but it requires significant investment in specialized equipment and large-scale production line modifications and process redevelopment. This not only leads to a sharp increase in production costs but also results in lengthy R&D and certification cycles, making it both economically unfeasible and impractical for many power semiconductor manufacturers.

[0007] Therefore, in view of the above-mentioned process limitations and design challenges of the existing 6-inch mainstream horizontal semiconductor power chip production line, there is an urgent need to propose a power device that can be fully compatible with the existing production line process without the need to introduce complex processes such as CMP or tungsten plugs, and can effectively reduce the metal area required for the via connection area, optimize chip layout, reduce manufacturing costs, and further improve the reliability and performance stability of power chips. Summary of the Invention

[0008] This invention provides a power device compatible with 6-inch wafer production lines, which solves the problems of existing power devices being incompatible with existing 6-inch production line processes, and being large in size and cost.

[0009] The present invention also provides a method for fabricating power devices compatible with 6-inch wafer production lines.

[0010] To achieve the objectives of this invention, a power device compatible with a 6-inch wafer production line is provided. The power device comprises, from bottom to top, a substrate, an epitaxial layer, a dielectric stack, an etch stop layer, and an interlayer dielectric layer. A small-sized ohmic contact metal is provided between the epitaxial layer and the dielectric stack. An intermediate metal layer is provided within the dielectric stack. A first window is provided on the etch stop layer directly above the intermediate metal layer. A stepped first via with a decreasing diameter from top to bottom is provided above the intermediate metal layer. The first via penetrates the interlayer dielectric layer, the first window, and part of the dielectric stack, and is connected to the upper surface of the intermediate metal layer. A first metal layer matching the shape is provided within the first via. The first metal layer is electrically connected to the ohmic contact metal via the intermediate metal layer.

[0011] This invention also provides a method for fabricating a power device compatible with a 6-inch wafer production line, comprising the following steps: a. Provide a substrate and fabricate an epitaxial layer on the substrate; b. Grow a gate dielectric layer in the epitaxial layer; c. Define an ohmic contact region in the gate dielectric layer and form an ohmic contact metal in the ohmic contact region; d. A dielectric stack is formed on the upper surface of the gate dielectric layer and the ohmic contact metal, the dielectric stack including a first dielectric layer and a second dielectric layer connected thereto; e. Form an intermediate metal layer and a gate metal within the dielectric stack; f. Form an etching barrier layer on the dielectric stack; g. Form the first window in the etching barrier layer; h. Form an interlayer dielectric layer on the etch barrier layer; i. A stepped first through-hole and a first metal layer are formed. The first through-hole extends from the upper surface of the interlayer dielectric layer through a first window and a dielectric stack to the upper surface of the intermediate metal layer. The first metal layer fills the first through-hole.

[0012] The beneficial effects of this invention are as follows: 1) Significantly reduced chip size and effectively improved integration: This invention optimizes the metal layer layout, particularly by designing the first metal layer as a stepped structure and adding an intermediate metal layer, thereby reducing the size of the ohmic contact metal and increasing the spacing between the first metal layer and the gate metal. This core design allows for a more compact arrangement of the device's active and interconnect regions, significantly reducing the overall chip area without sacrificing electrical performance, and improving wafer utilization and chip integration.

[0013] 2) Wide process window and high reliability: This invention achieves precise self-aligned etch stop during the formation of the first via by introducing an etch barrier layer with a high etch selectivity. This significantly reduces the stringent requirements for photolithographic alignment accuracy and widens the process window. Simultaneously, this structure effectively protects the underlying fine structures from over-etching damage, improving process stability and long-term device reliability.

[0014] 3) Fully compatible with existing production lines, low manufacturing cost: The entire device structure and fabrication process of this invention are based on standard 6-inch wafer manufacturing processes, without the need to introduce any special process steps. All processes are mature technologies in the industry and can be seamlessly implemented on existing production lines, avoiding the high costs and time investment caused by equipment modification or process development, thus possessing significant industrialization and economic advantages.

[0015] 4) High design flexibility and wide applicability: This invention features high modularity and scalability. By employing a multi-layer stacked structure in the etching barrier layer, stress and passivation effects can be further optimized. By adding a second metal layer and corresponding stepped via interconnects on top of the first metal layer, multi-layer wiring can be easily achieved, meeting the requirements of more complex circuits for wiring density and flexibility. Therefore, the solution of this invention can be widely applied to the manufacture of various mainstream lateral power devices such as LDMOS and GaN HEMT. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0017] Figure 2 This is a schematic diagram of the substrate and epitaxial layer formed in Embodiment 1 of the present invention.

[0018] Figure 3 This is a schematic diagram of the structure formed by the gate dielectric layer in Embodiment 1 of the present invention.

[0019] Figure 4 This is a schematic diagram of the ohmic contact metal formation in Embodiment 1 of the present invention.

[0020] Figure 5 This is a schematic diagram of the structure formed by the dielectric stack in Embodiment 1 of the present invention.

[0021] Figure 6 This is a schematic diagram of the formation of the gate metal and intermediate metal layer in Embodiment 1 of the present invention.

[0022] Figure 7 This is a schematic diagram of the etch barrier layer formed in Embodiment 1 of the present invention.

[0023] Figure 8 This is a schematic diagram of the structure formed by the interlayer dielectric layer in Embodiment 1 of the present invention.

[0024] Figure 9 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0025] Figure 10 yes Figure 9 A schematic diagram of the structure in which the first metal layer has been removed.

[0026] Figure 11 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0027] Figure 12 yes Figure 11 A schematic diagram of the structure in which the second metal layer is removed.

[0028] Figure 13 This is a schematic diagram of the structure of Embodiment 4 of the present invention.

[0029] Figure 14 yes Figure 13 A schematic diagram of the structure in which the first metal layer has been removed.

[0030] Figure 15 This is a flowchart of the preparation method of Embodiment 5 of the present invention. Detailed Implementation

[0031] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Example 1 Please see Figure 1 This embodiment provides a power device compatible with 6-inch wafer production lines. By optimizing the metal layer layout and size design, it achieves chip size reduction and production cost reduction without adding special process steps. The power device, from bottom to top, includes a substrate 10, an epitaxial layer 20, a dielectric stack 30, an etch stop layer 40, and an interlayer dielectric layer 50. An ohmic contact metal 60 is provided between the epitaxial layer 20 and the dielectric stack 30. A first metal layer 70 is provided above the ohmic contact metal 60, and an intermediate metal layer 80 is provided between the first metal layer 70 and the ohmic contact metal 60. By designing the structure of the first metal layer 70 and adding the intermediate metal layer 80, the size of the ohmic contact metal 60 can be reduced and the spacing between the first metal layer 70 and the gate metal 100 can be increased, effectively improving integration and making it suitable for manufacturing various mainstream lateral power devices.

[0033] like Figure 1 , Figure 2 As shown, substrate 10 serves as the mechanical support for the device, responsible for bearing the functional layers above and conducting the heat generated during device operation, ensuring its stability and reliability. The material of substrate 10 can be selected according to the device type, including but not limited to semiconductor materials such as silicon, silicon carbide, or gallium nitride, and can also be compound semiconductors such as gallium arsenide. This embodiment can be widely used in various power devices, including but not limited to PGaN HEMTs, MIS HEMTs, Schottky gate HEMTs, silicon-based MOSFETs, silicon carbide MOSFETs, and gallium arsenide HEMTs.

[0034] like Figure 1 , Figure 2 As shown, an epitaxial layer 20 is grown on the upper surface of the substrate 10. This layer is the core functional material layer of the power device, used to form active regions such as conductive channels and carrier transport regions. The material of the epitaxial layer 20 matches the substrate 10 and can be a single epitaxial layer or a multi-layer heterojunction structure. For example, in GaN-based HEMTs, it typically includes a nucleation layer, a buffer layer, and a barrier layer; in silicon-based or silicon carbide-based MOSFETs, it is an epitaxial silicon layer or a silicon carbide layer with a specific doping concentration. This epitaxial layer 20 can be formed through an epitaxial growth process. Its thickness, doping concentration, composition, and other parameters need to be precisely designed according to the voltage level, current capacity, and other characteristics of the target device to optimize device performance.

[0035] like Figure 1 As shown, a dielectric stack 30 is formed on the epitaxial layer 20, serving to provide electrical insulation, surface passivation, modulate the channel electric field, and form a MOS or MIS gate structure. This dielectric stack 30 can be silicon oxide, silicon nitride, aluminum oxide, high-dielectric-constant materials, or a combination thereof, and can be formed using mature deposition and etching processes from existing production lines. Together with the subsequent etch barrier layer 40, it ensures the integrity and reliability of the device structure. Figure 1 In the illustrated embodiment, the dielectric stack 30 includes a first dielectric layer 31 and a second dielectric layer 32 disposed thereon. The first dielectric layer 31 is disposed on the epitaxial layer 20, and its material preferably has good interface characteristics with the epitaxial layer 20. The second dielectric layer 32 is formed on the surface of the first dielectric layer 31, and its material can be selected from materials with high breakdown field strength, good thermal stability, and compatibility with subsequent processes, such as SiO2, Si3N4, or high-k materials.

[0036] like Figure 1 As shown, an ohmic contact metal 60 is provided between the epitaxial layer 20 and the dielectric stack 30 to achieve low-resistance ohmic contact with the underlying semiconductor material, providing an efficient injection and extraction path for source and drain currents. This ohmic contact metal 60 can be patterned using photolithography, metal deposition (such as electron beam evaporation or sputtering), and lift-off or etching processes to form the required source and drain contact regions. In this embodiment, the ohmic contact metal 60 is designed as a small-sized structure. By precisely controlling its lateral dimensions, such as the width of the contact window, the area occupied by the source and drain active regions can be effectively reduced while meeting current carrying capacity requirements, thereby directly contributing to the reduction of the overall chip size.

[0037] In some embodiments, such as Figure 1 , Figure 3 and Figure 4 As shown, a gate dielectric layer 90 is provided between the epitaxial layer 20 and the dielectric stack 30. An ohmic contact region 91 is defined on the gate dielectric layer 90 through photolithography and etching processes. This ohmic contact region 91 penetrates the gate dielectric layer 90 and exposes the surface of the underlying epitaxial layer 20. The ohmic contact metal 60 has an integrally formed connection portion 61 and an extension portion 62. The connection portion 61 fills the ohmic contact region 91 and forms a direct and reliable ohmic contact with the epitaxial layer 20. The extension portion 62 extends outward from the ohmic contact region, covering part of the upper surface of the gate dielectric layer 90. This extension portion 62 increases the contact area between the metal and the upper interconnect layer, reduces the contact resistance, and improves the mechanical stability of the connection.

[0038] like Figure 1 , Figure 6As shown, an intermediate metal layer 80 is provided directly above the ohmic contact metal 60. This intermediate metal layer 80 has a T-shaped structure, including a vertical portion and a horizontal portion. The vertical portion penetrates the first dielectric layer 31 and connects to the ohmic contact metal 60. The horizontal portion is located within the second dielectric layer 32, with its lower surface covering part of the upper surface of the first dielectric layer 31. Its sides and part of its upper surface are surrounded by the dielectric stack 30 material, thus forming a stable lateral extension support structure and achieving good electrical isolation. The width of the vertical portion of this intermediate metal layer 80 is smaller than the width of the ohmic contact metal 60. This dimensional difference helps to form a smaller first through-hole 51 in subsequent processes, providing the possibility for overall structure miniaturization. During fabrication, as... Figure 5 As shown, an intermediate metal region 311 is first defined on the first dielectric layer 31 using photolithography and etching processes. The intermediate metal region 311 extends from the upper surface of the first dielectric layer 31 to its lower surface, exposing the underlying ohmic contact metal 60. Subsequently, as... Figure 6 As shown, through deposition, filling, and planarization processes, the vertical portion of the intermediate metal layer 80 is formed within the intermediate metal region 311, and simultaneously, the horizontal portion located within the second dielectric layer 32 is formed, ultimately constituting a complete T-shaped intermediate metal layer structure. This structure not only enhances the reliability of the electrical connection between the upper and lower metal layers but also reduces the depth of the pores above it.

[0039] like Figure 1 , Figure 6 As shown, a gate metal 100 is formed between the dielectric stack 30 and the gate dielectric layer 90, constituting the gate electrode of the device and serving as a crucial control terminal for controlling the power device's turn-on and turn-off. The lower surface of the gate metal 100 contacts the gate dielectric layer 90, its upper surface contacts the second dielectric layer 32, and its sides are surrounded by the materials of the first dielectric layer 31 and the second dielectric layer 32, thus achieving good electrical isolation. The gate metal 100 is spatially separated from the intermediate metal layer 80 and is completely electrically insulated by the dielectric stack 30, ensuring no short-circuit risk between the gate signal and the source / drain main current path. The gate metal 100 can subsequently be connected to the first metal layer 70 via a via (not shown in the figure).

[0040] like Figure 1 , Figure 7As shown, an etch barrier layer 40 is formed on the surface of the dielectric stack 30 to protect the underlying structure and expand the process window. To achieve the above functions, the etch barrier layer 40 preferably has a high-density, high etch selectivity (relative to the dielectric stack 30) material. Typical materials include, but are not limited to, aluminum nitride. The etch barrier layer 40 can be formed by standard processes such as plasma-enhanced chemical vapor deposition or atomic layer deposition. Through photolithography and selective etching processes, a first window 41 is formed on the etch barrier layer 40 at a position directly above the intermediate metal layer 80, thereby exposing the connection region of the underlying intermediate metal layer 80 and preparing for the subsequent connection of the first metal layer 70. The width of the first window 41 is smaller than the width of the ohmic contact metal 60. In some embodiments, also through selective etching processes, a second window 42 is formed on the etch barrier layer 40 at a position directly above the gate metal 100 to reserve a channel for electrical connection between the gate metal 100 and the gate interconnect metal layer (which may also be the first metal layer 70).

[0041] like Figure 1 , Figure 7 and Figure 8 As shown, an interlayer dielectric layer 50 is formed on the surface of the etch stop layer 40, serving as the main inter-metal insulating layer of the device to achieve electrical isolation between different metal layers. This interlayer dielectric layer 50 can be made of silicon dioxide, doped silicon glass, or a low dielectric constant material, formed using standard processes such as chemical vapor deposition, and can be reflowed or chemically mechanically polished to achieve surface flatness. To achieve a reliable electrical connection from the surface of the interlayer dielectric layer 50 to the ohmic contact metal 60 below, this embodiment designs a stepped first via 51. This first via 51 penetrates the upper interlayer dielectric layer 50, the first opening 41 of the etch stop layer 40, and the dielectric stack 30, ultimately reaching the upper surface of the intermediate metal layer 80. Specifically, the first via 51 includes a first connection hole 511 and a second connection hole 512. The first connection hole 511 is located at the top, vertically penetrating from the upper surface of the interlayer dielectric layer 50 to its lower surface, and the diameter of this portion is larger than the width of the first opening 41 on the etch stop layer 40 below. The second connecting hole 512 is located at the bottom and extends vertically from the upper surface of the dielectric stack 30 to the upper surface of the intermediate metal layer 80. The diameter of this hole is equal to the width of the first opening 41.

[0042] like Figure 1As shown, on the one hand, when performing dielectric etching at the first via 51, due to the presence of the intermediate metal layer 80, the thickness of the interlayer dielectric layer that needs to be penetrated when etching the first via 51 is thinner than that of conventional dielectrics. Therefore, while maintaining the same aspect ratio, a smaller aperture first via 51 can be achieved, which not only helps to increase device integration density but also reduces the difficulty of the etching process and enhances topography control. At the same time, the intermediate metal layer 80 electrically connects the upper first metal layer 70 and the lower ohmic contact metal 60.

[0043] On the other hand, such as Figure 1 , Figure 8 As shown, during the etching of the dielectric stack 30 and interlayer dielectric layer 50 through which the first via 51 penetrates, the etching first proceeds downwards in the interlayer dielectric layer 50, forming a first connection hole 511 with a larger diameter. When etching reaches the surface of the etch stop layer 40, due to its high etch selectivity, the etch stop layer 40 effectively stops the etching in areas other than the first opening 41 region. Therefore, etching can only continue downwards in the area exposed by the first opening 41, penetrating the underlying dielectric stack 30 to form a second connection hole 512 with a smaller diameter. At the boundary of the first opening 41 of the etch stop layer 40, a step is naturally formed due to the lateral and longitudinal cessation of etching. This results in the first via 51, directly above the intermediate metal layer 80, ultimately presenting a double-step hole structure with a small bottom diameter and a large top diameter.

[0044] Compared to a single high aspect ratio straight hole, the stepped first through hole 51 is decomposed into two continuous holes with smaller aspect ratios. Since the hole of the lower second connecting hole 512 is small enough, the lower intermediate metal layer 80 and ohmic contact metal 60 can be designed with small-sized structures, thereby reducing the overall chip size and increasing the spacing between the first metal layer 70 and the gate metal 100, thus meeting the safety spacing requirements between the first metal layer 70 and the gate metal 100 under high voltage. This solves the problem that the bottom of the existing single high aspect ratio straight hole is too large, resulting in an excessively large chip size.

[0045] like Figure 1 , Figure 8 As shown, a first metal layer 70 with a matching shape is filled inside the first through-hole 51. This first metal layer 70 not only fills the first through-hole 51, but its lower surface forms a large-area, low-resistance contact with the upper surface of the intermediate metal layer 80, and its upper surface extends outwards towards the first connecting hole 511, covering part of the upper surface of the interlayer dielectric layer 50. This first metal layer 70 can be made of a conductive material primarily composed of aluminum, copper, or their alloys, and formed through processes such as sputtering and electroplating.

[0046] Example 2 Please see Figure 9The power device structure compatible with a 6-inch wafer production line provided in this embodiment is largely the same as the power device structure in Embodiment 1. The difference is that the number of etch barrier layers 40 in this embodiment is n, where n > 1. In addition to the etch barrier layer 40 disposed between the dielectric stack 30 and the interlayer dielectric layer 50 in Embodiment 1, n-1 etch barrier layers 40 can be disposed between adjacent layers of the multilayer dielectric layer between the first metal layer 70 and the ohmic contact metal 60. Each etch barrier layer can be defined with windows of specific size and position through independent photolithography and etching processes. When n etch barrier layers are used, n+1 vertically connected holes with different apertures will be formed between the ohmic contact metal 60 and the upper first metal layer 70 through selective etching layer by layer. The apertures of these holes can be gradually reduced from top to bottom or adjusted according to the design, together forming a multi-level stepped composite through-hole structure.

[0047] like Figure 9 In the illustrated embodiment, the etch barrier layer 40 has two layers, including a first etch barrier layer 401 and a second etch barrier layer 402. The dielectric stack 30 includes a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33 disposed between the first dielectric layer 31 and the second dielectric layer 32. Wherein, as... Figure 10 As shown, a first etch barrier layer 401 is disposed between the interlayer dielectric layer 50 and the second dielectric layer 32, and a second etch barrier layer 402 is disposed between the second dielectric layer 32 and the third dielectric layer 33. A third opening 43 is provided on the first etch barrier layer 401 directly above the intermediate metal layer 80, and a fourth opening 44 is provided on the second etch barrier layer 402 directly above the intermediate metal layer 80. The width of the third opening 43 is greater than the width of the fourth opening 44. A stepped first through-hole 51 is provided above the intermediate metal layer 80. When n is 2, the stepped first through-hole 51 penetrates the upper interlayer dielectric layer 50, the third opening 43, the fourth opening 44, and the dielectric stack 30, finally reaching the upper surface of the intermediate metal layer 80. The first via 51 includes a third connecting via 513, a fourth connecting via 514, and a fifth connecting via 515 extending from top to bottom. The third connecting via 513 extends vertically from the upper surface of the interlayer dielectric layer 50 to its lower surface, and its diameter is larger than the width of the third opening 43 on the first etch stop layer 401. The fourth connecting via 514 extends vertically from the upper surface of the second dielectric layer 32 to its lower surface, and its diameter is larger than the width of the fourth opening 44 on the second etch stop layer 402 below it. The fifth connecting via 515 extends vertically from the upper surface of the third dielectric layer 33 to the upper surface of the intermediate metal layer 80, and its diameter is equal to the width of the fourth opening 44 on the second etch stop layer 402.

[0048] By introducing multiple etch stop layers 40, the total dielectric thickness can be "divided" into multiple segments that are easier to etch and fill with metal, ensuring that even with a very thick overall dielectric, the aspect ratio of each segment and the difficulty of metal filling remain controllable. This is to meet the needs of power devices with ultra-thick interlayer dielectric layers or complex dielectric stacks. Since the bottom etch stop layer openings can define an extremely small interface for connection with the ohmic contact metal, and the upper etch stop layer openings can be progressively enlarged, providing ample tolerance for photolithography alignment and metal deposition, the size of the ohmic contact metal 60 can be made even smaller.

[0049] Example 3 Please see Figure 11 The power device structure compatible with 6-inch wafer production lines provided in this embodiment is basically the same as the power device structure in Embodiment 1. The difference is that a second metal layer 110 with m layers is provided on the first metal layer 70, where m is greater than or equal to 1.

[0050] like Figure 11 In the illustrated embodiment, a second metal layer 110 is provided on the first metal layer 70. Specifically, a third dielectric layer 120 and a third etch barrier layer 130 are sequentially formed from bottom to top on the upper surface of the interlayer dielectric layer 50. The third etch barrier layer 130 is made of a high-density, high-etch selectivity material (relative to the third dielectric layer 120), such as aluminum nitride, and is formed by plasma-enhanced chemical vapor deposition or atomic layer deposition. Its main functions include protecting the underlying structure and expanding the process window. Figure 12 As shown, a fifth window 131 is formed on the third etch barrier layer 130 in the region directly above the first metal layer 70 using photolithography and selective etching processes, exposing the surface of the underlying first metal layer 70. The width of the fifth window 131 is designed to be smaller than the width of the first metal layer 70.

[0051] like Figure 11 , Figure 12As shown, a fourth dielectric layer 140 is formed on the surface of the third etch barrier layer 130, which serves as the main intermetallic insulating layer of the device to achieve electrical isolation between different metal layers. To achieve a reliable electrical connection from the surface of the fourth dielectric layer 140 to the underlying first metal layer 70, this embodiment designs a stepped second via 141. This second via 141 penetrates the upper fourth dielectric layer 140, the fifth opening 131 of the third etch barrier layer 130, and the third dielectric layer 120, ultimately reaching the upper surface of the first metal layer 70. Specifically, the second via 141 includes a sixth connecting hole 1411 and a seventh connecting hole 1412. The sixth connecting hole 1411 is located at the top, vertically penetrating from the upper surface of the fourth dielectric layer 140 to its lower surface. The diameter of this portion is larger than the width of the fifth opening 131 on the lower third etch barrier layer 130. The seventh connecting hole 1412 is located at the bottom and extends vertically from the upper surface of the third dielectric layer 120 to the upper surface of the first metal layer 70. The diameter of this hole is equal to the width of the fifth opening 131.

[0052] like Figure 11 , Figure 12 As shown, during the etching of the third dielectric layer 120 and the fourth dielectric layer 140 through which the second via 141 penetrates, the etching first proceeds downwards in the fourth dielectric layer 140, forming a sixth connecting hole 1411 with a larger diameter. When etching reaches the surface of the third etch stop layer 130, due to its high etch selectivity, the third etch stop layer 130 effectively stops the etching in all areas except for the fifth opening 131 region. Therefore, etching can only continue downwards in the area exposed by the fifth opening 131, penetrating the lower third dielectric layer 120 to form a seventh connecting hole 1412 with a smaller diameter. At the boundary of the fifth opening 131 of the third etch stop layer 130, a step is naturally formed due to the lateral and longitudinal cessation of etching. This results in the second via 141, directly above the first metal layer 70, ultimately presenting a double-step hole structure with a small bottom diameter and a large top diameter.

[0053] like Figure 11 , Figure 12 As shown, a second metal layer 110 matching the shape of the second through hole 141 is filled within the second through hole 141. This second metal layer 110 not only fills the second through hole 141, but its lower surface forms a large-area, low-resistance contact with the upper surface of the first metal layer 70, and its upper surface extends outwards towards the sixth connecting hole 1411, covering part of the upper surface of the fourth dielectric layer 140. This second metal layer 110 can be made of a conductive material primarily composed of aluminum, copper, or their alloys, and formed through processes such as sputtering and electroplating.

[0054] In this embodiment, at least one second metal layer 110 is added above the first metal layer 70 of the power device. By introducing a third etch barrier layer 130 with a high etch selectivity and a stepped second via 141 structure, high-density and reliable interconnection between different metal layers is achieved, further improving device integration and wiring flexibility, while maintaining process compatibility with 6-inch production lines.

[0055] Example 4 Please see Figure 13 The power device structure compatible with a 6-inch wafer production line provided in this embodiment is largely the same as the power device structure in Embodiment 3. The difference is that the number of etch barrier layers 40 in this embodiment is n, where n > 1. In addition to the etch barrier layer 40 disposed between the dielectric stack 30 and the interlayer dielectric layer 50 in Embodiment 3, n-1 etch barrier layers 40 can be disposed between adjacent layers of the multilayer dielectric layer between the first metal layer 70 and the ohmic contact metal 60. Each etch barrier layer can be defined with windows of specific size and position through independent photolithography and etching processes. When n etch barrier layers are used, n+1 vertically connected holes with different apertures will be formed between the ohmic contact metal 60 and the upper first metal layer 70 through selective etching layer by layer. The apertures of these holes can be gradually reduced from top to bottom or adjusted according to the design, together forming a multi-level stepped composite through-hole structure.

[0056] like Figure 13 In the illustrated embodiment, the etch barrier layer 40 has two layers, including a first etch barrier layer 401 and a second etch barrier layer 402. The dielectric stack 30 includes a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33 disposed between the first dielectric layer 31 and the second dielectric layer 32. Wherein, as... Figure 13 , Figure 14As shown, a first etch barrier layer 401 is disposed between the interlayer dielectric layer 50 and the second dielectric layer 32. A third window 43 is provided on the first etch barrier layer 401 directly above the intermediate metal layer 80. A second etch barrier layer 402 is disposed between the second dielectric layer 32 and the third dielectric layer 33. A fourth window 44 is provided on the second etch barrier layer 402 directly above the intermediate metal layer 80. The width of the third window 43 is greater than the width of the fourth window 44. A stepped first through-hole 51 is provided above the intermediate metal layer 80. When n is 2 layers, the stepped first through-hole 51 penetrates the upper interlayer dielectric layer 50, the third window 43, the fourth window 44, and the dielectric stack 30, finally reaching the upper surface of the intermediate metal layer 80. The first via 51 includes a third connecting via 513, a fourth connecting via 514, and a fifth connecting via 515 extending from top to bottom. The third connecting via 513 extends vertically from the upper surface of the interlayer dielectric layer 50 to its lower surface, and its diameter is larger than the width of the third opening 43 on the first etch stop layer 401 below it. The fourth connecting via 514 extends vertically from the upper surface of the second dielectric layer 32 to its lower surface, and its diameter is larger than the width of the fourth opening 44 on the second etch stop layer 402 below it. The fifth connecting via 515 extends vertically from the upper surface of the third dielectric layer 33 to the upper surface of the intermediate metal layer 80, and its diameter is equal to the width of the fourth opening 44 on the second etch stop layer 402.

[0057] By introducing multiple etch stop layers 40, the total dielectric thickness can be "divided" into multiple segments that are easier to etch and fill with metal, ensuring that even with a very thick overall dielectric, the aspect ratio of each segment and the difficulty of metal filling remain controllable. This is to meet the needs of power devices with ultra-thick interlayer dielectric layers or complex dielectric stacks. Since the bottom etch stop layer openings can define an extremely small interface for connection with the ohmic contact metal, and the upper etch stop layer openings can be progressively enlarged, providing ample tolerance for photolithography alignment and metal deposition, the size of the ohmic contact metal 60 can be made even smaller.

[0058] Example 5 See Figure 15 This embodiment provides a method for fabricating the aforementioned power device. This method is fully compatible with standard 6-inch wafer manufacturing processes and can achieve device size reduction and increased integration without introducing special process steps. Specifically, it includes the following steps: S10, Provide a substrate and prepare an epitaxial layer.

[0059] In this step, such as Figure 2As shown, a substrate 10 is provided, preferably a low-resistivity silicon substrate, silicon carbide substrate, or sapphire substrate. An epitaxial layer 20 of the desired thickness and doping concentration can be grown on the substrate 10 using an epitaxial growth process. For example, for laterally diffused metal-oxide-semiconductor devices, a P-type or N-type epitaxial silicon layer can be grown, with a thickness ranging from 3 to 10 micrometers, and the resistivity controlled according to the device's voltage withstand requirements. The epitaxial layer 20 can be grown using a chemical vapor deposition process.

[0060] S20. Grow a gate dielectric layer in the epitaxial layer.

[0061] In this step, such as Figure 3 As shown, a gate dielectric layer 90 is formed on the surface of the epitaxial layer 20 by thermal oxidation or chemical vapor deposition. The gate dielectric layer 90 is preferably silicon dioxide or a high-k dielectric material, with a thickness ranging from 20 to 100 nanometers. This layer will serve as the insulating layer for the subsequently formed gate.

[0062] S30, forming an ohmic contact metal.

[0063] In this step, such as Figure 3 , Figure 4 As shown, an ohmic contact region 91 is defined on the gate dielectric layer 90 using photolithography and etching processes. Subsequently, an ohmic contact metal 60 is formed within the ohmic contact region 91 through metal lift-off or etching processes. The ohmic contact metal 60 can be a multilayer metal stack, such as a combination of titanium / titanium nitride / aluminum / copper, with a total thickness of approximately 100-500 nanometers. A rapid thermal annealing process is then performed to ensure good ohmic contact between the metal and the epitaxial layer 20.

[0064] S40, forming a dielectric stack.

[0065] like Figure 5 As shown, a dielectric stack 30 is sequentially deposited on the upper surfaces of the gate dielectric layer 90 and the ohmic contact metal 60, which have completed the ohmic contact, using a plasma-enhanced chemical vapor deposition process. The dielectric stack 30 may include one or more layers of dielectric material, such as a bottom layer of silicon dioxide and a top layer of silicon nitride, with a total thickness of approximately 500-1500 nanometers, for passivation and insulation of the device surface.

[0066] S50, forming the intermediate metal layer and the gate metal.

[0067] like Figure 5 , Figure 6As shown, contact holes are etched within the dielectric stack 30 using photolithography and dry etching processes, exposing the underlying ohmic contact metal 60. Subsequently, a metal layer (such as an aluminum or copper-based alloy) is deposited using sputtering or chemical vapor deposition processes, and patterned by photolithography and etching to simultaneously form an intermediate metal layer 80 connected to the ohmic contact metal 60 and a gate metal 100 located in the active region of the device. The thickness of the intermediate metal layer 80 can be 300-1200 nanometers, and its function is to provide a flatter and lower-resistance connection path for the upper first metal layer.

[0068] S60, forming an etching barrier layer.

[0069] like Figure 7 As shown, an etch barrier layer 40 is deposited on the surface of the dielectric stack 30, which includes an intermediate metal layer 80 and a gate metal 100, using a chemical vapor deposition or atomic layer deposition process. This etch barrier layer 40 is preferably made of a high-density, high-etch selectivity material (relative to the dielectric stack 30), such as aluminum nitride, and has a thickness of approximately 30-100 nanometers. It is used to protect the underlying fine structure during subsequent interlayer dielectric layer etching processes.

[0070] S70, The first window is formed in the etching barrier layer.

[0071] like Figure 7 As shown, a first window 41 is formed on the etch barrier layer 40 in a region corresponding to the intermediate metal layer 80 by photolithography and selective dry etching processes, exposing the surface of the underlying intermediate metal layer 80. The size of the first window 41 is optimized to be smaller than the lateral dimension of the intermediate metal layer 80.

[0072] S80, forming an interlayer dielectric layer.

[0073] like Figure 8 As shown, an interlayer dielectric layer 50 is deposited on the surface of the etching barrier layer 40 and the exposed intermediate metal layer 80 using plasma-enhanced chemical vapor deposition. The interlayer dielectric layer 50 is preferably a dielectric material with good planarization properties, such as silicon dioxide or fluorine-doped silicon dioxide, and has a thickness of approximately 1000-3000 nanometers. After deposition, the surface can be planarized using a chemical mechanical polishing process.

[0074] S90, forming the first through hole and the first metal layer.

[0075] like Figure 8As shown, firstly, a first via 51 is formed on the interlayer dielectric layer 50 by photolithography and dry etching processes. Because of the presence of an etch barrier layer 40 below, the etching process automatically stops when it reaches the area outside the first opening 41, continuing etching only at the exposed first opening 41 until the underlying intermediate metal layer 80 is fully exposed. The first via 51 therefore has self-aligning characteristics, and its bottom dimension is defined by the first opening 41.

[0076] Subsequently, as Figure 1 As shown, a seed layer is deposited by sputtering and then filled by electroplating, or a whole layer of metal is sputtered and then etched by photolithography to fill the first via 51 with metal and simultaneously pattern a first metal layer 70 on the upper surface of the interlayer dielectric layer 50. The first metal layer 70 is electrically connected to the intermediate metal layer 80 through the first via 51 and serves as the main interconnect wiring of the device.

[0077] At this point, the main structure of a highly integrated power device has been fabricated. Subsequently, steps similar to S60-S90 can be repeated as needed to continue building more metal interconnect layers (such as the second metal layer 110) on the interlayer dielectric layer 50 and the first metal layer 70, and finally, the passivation layer windowing, back-side thinning, and metallization processes are completed.

[0078] This fabrication method precisely controls the size and position of the first via 51 by introducing an optimized intermediate metal layer 80 and a highly selective etch barrier layer 40. This allows for a reduction in the size of the ohmic contact metal 60 and an increase in the design spacing between the first metal layer 70 and the gate metal 100. Ultimately, without increasing process complexity, this method effectively reduces the overall chip size and lowers production costs.

[0079] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. A power device compatible with 6-inch wafer production lines, characterized in that, The power device comprises, from bottom to top, a substrate, an epitaxial layer, a dielectric stack, an etch stop layer, and an interlayer dielectric layer. A small-sized ohmic contact metal is provided between the epitaxial layer and the dielectric stack. An intermediate metal layer is provided within the dielectric stack. A first window is provided on the etch stop layer directly above the intermediate metal layer. A stepped first via with a decreasing diameter from top to bottom is provided above the intermediate metal layer. The first via penetrates the interlayer dielectric layer, the first window, and part of the dielectric stack, and is connected to the upper surface of the intermediate metal layer. A first metal layer with a matching shape is provided within the first via. The first metal layer is electrically connected to the ohmic contact metal through the intermediate metal layer. The dielectric stack includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. An intermediate metal region is defined on the first dielectric layer directly above the ohmic contact metal, and the intermediate metal layer is disposed within the intermediate metal region. A gate dielectric layer is provided between the epitaxial layer and the first dielectric layer. An ohmic contact region is defined on the gate dielectric layer. The ohmic contact region penetrates the gate dielectric layer and is connected to a portion of the upper surface of the epitaxial layer. The ohmic contact metal is disposed within the ohmic contact region. The ohmic contact metal has an integrally formed connecting portion and an extension portion. The connecting portion fills the ohmic contact area and is connected to the upper surface of the epitaxial layer. The extension portion extends outward from the ohmic contact area and covers part of the upper surface of the gate dielectric layer. The cross-section of the intermediate metal layer is T-shaped, including a horizontal portion and a vertical portion. The vertical portion is filled in the intermediate metal area, and its horizontal width is smaller than the width of the ohmic contact metal. The horizontal portion is located in the second dielectric layer, and its lower surface covers part of the upper surface of the first dielectric layer. The width of the horizontal portion is greater than the width of the ohmic contact metal. The first via includes a first connecting hole and a second connecting hole that are vertically connected. The first connecting hole extends vertically from the upper surface of the interlayer dielectric layer to its lower surface, and its diameter is larger than the width of the first opening. The second connecting hole extends vertically from the upper surface of the dielectric stack to the upper surface of the intermediate metal layer, and its diameter is equal to the width of the first opening. The etching barrier layer has high density and high etching selectivity.

2. The power device compatible with a 6-inch wafer production line as described in claim 1, characterized in that, The number of etching barrier layers is n layers, where n≥2, and the first through hole consists of n+1 vertically connected holes with progressively smaller diameters.

3. The power device compatible with a 6-inch wafer production line as described in claim 1 or 2, characterized in that, The upper surface of the first metal layer is provided with m second metal layers, where m≥1. The m second metal layers are electrically connected sequentially from top to bottom, and the lower surface of the second metal layer at the bottom is electrically connected to the upper surface of the first metal layer.

4. The power device compatible with a 6-inch wafer production line as described in claim 1, characterized in that, A gate region is defined on the first dielectric layer, and a gate metal is provided in the gate region. The lower surface of the gate metal is connected to the gate dielectric layer, its upper surface is in contact with the second dielectric layer, and its sides are surrounded by the first dielectric layer and the second dielectric layer.

5. The power device compatible with a 6-inch wafer production line as described in claim 2, characterized in that, When n=2, the etching barrier layer includes a first etching barrier layer and a second etching barrier layer. The first etching barrier layer is disposed between the interlayer dielectric layer and the dielectric stack. A third opening is provided on the first etching barrier layer directly above the intermediate metal layer. The second etching barrier layer is disposed within the dielectric stack. A fourth opening is provided on the second etching barrier layer directly above the intermediate metal layer. The width of the third opening is greater than the width of the fourth opening. The first through-hole includes a third connecting hole, a fourth connecting hole, and a fifth connecting hole that extend from top to bottom. The third connecting hole extends vertically from the upper surface of the interlayer dielectric layer to its lower surface, and its diameter is greater than the width of the third opening. The fourth connecting hole extends vertically from the upper surface of the second dielectric layer to its lower surface, and its diameter is greater than the width of the fourth opening. The fifth connecting hole extends vertically from the upper surface of the first dielectric layer to the upper surface of the intermediate metal layer, and its diameter is equal to the width of the fourth opening.

6. The power device compatible with a 6-inch wafer production line as described in claim 3, characterized in that, Where m=1, a second metal layer is provided on the first metal layer, and a third dielectric layer, a third etch barrier layer and a fourth dielectric layer are formed sequentially from bottom to top on the upper surface of the interlayer dielectric layer. A fifth window is formed on the third etch barrier layer corresponding to the area directly above the first metal layer, and the width of the fifth window is smaller than the width of the first metal layer. A stepped second through hole is provided above the first metal layer. The second through hole includes a sixth connecting hole and a seventh connecting hole that are vertically connected. The sixth connecting hole extends vertically from the upper surface of the fourth dielectric layer to its lower surface, and its diameter is greater than the width of the fifth opening. The seventh connecting hole extends vertically from the upper surface of the third dielectric layer to the upper surface of the first metal layer, and its diameter is equal to the width of the fifth opening.

7. A method for fabricating a power device compatible with a 6-inch wafer production line, characterized in that, Includes the following steps: a. Provide a substrate and fabricate an epitaxial layer on the substrate; b. Grow a gate dielectric layer in the epitaxial layer; c. Define an ohmic contact region in the gate dielectric layer and form an ohmic contact metal in the ohmic contact region; d. A dielectric stack is formed on the upper surface of the gate dielectric layer and the ohmic contact metal; e. Form an intermediate metal layer and a gate metal within the dielectric stack; f. Form an etching barrier layer on the dielectric stack; g. Form the first window in the etching barrier layer; h. Form an interlayer dielectric layer on the etch barrier layer; i. A stepped first through-hole and a first metal layer are formed. The first through-hole extends from the upper surface of the interlayer dielectric layer through a first window and a dielectric stack to the upper surface of the intermediate metal layer. The first metal layer fills the first through-hole. The dielectric stack includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. An intermediate metal region is defined on the first dielectric layer directly above the ohmic contact metal, and the intermediate metal layer is disposed within the intermediate metal region. The ohmic contact region penetrates the gate dielectric layer and is connected to a portion of the upper surface of the epitaxial layer. The ohmic contact metal has an integrally formed connecting portion and an extension portion. The connecting portion fills the ohmic contact area and is connected to the upper surface of the epitaxial layer. The extension portion extends outward from the ohmic contact area and covers part of the upper surface of the gate dielectric layer. The cross-section of the intermediate metal layer is T-shaped, including a horizontal portion and a vertical portion. The vertical portion is filled in the intermediate metal area, and its horizontal width is smaller than the width of the ohmic contact metal. The horizontal portion is located in the second dielectric layer, and its lower surface covers part of the upper surface of the first dielectric layer. The width of the horizontal portion is greater than the width of the ohmic contact metal. The first via includes a first connecting hole and a second connecting hole that are vertically connected. The first connecting hole extends vertically from the upper surface of the interlayer dielectric layer to its lower surface, and its diameter is larger than the width of the first opening. The second connecting hole extends vertically from the upper surface of the dielectric stack to the upper surface of the intermediate metal layer, and its diameter is equal to the width of the first opening. The etching barrier layer has high density and high etching selectivity.

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