A power chip package structure of a silicon carbide substrate and a manufacturing method thereof

Abstract

The application relates to a power chip packaging structure of a silicon carbide substrate and a preparation method thereof, wherein the power chip packaging structure of the silicon carbide substrate comprises a substrate made of silicon carbide, first blind grooves and second blind grooves are arranged on two sides of one surface of the substrate, the first blind grooves are used for arranging transmitting chips, and the second blind grooves are used for arranging receiving chips; first blind hole areas and second blind hole areas are arranged between the first blind grooves and the second blind grooves; the first blind hole areas are provided with a plurality of first blind holes with rectangular cross sections; the second blind hole areas are provided with a plurality of second blind holes with rectangular cross sections; the first blind holes are provided with three-dimensional inductors; and the second blind holes are provided with three-dimensional capacitors. The application can effectively realize heat dissipation of a power module, and the device size is relatively small.

Description

Technical Field

[0001] This invention relates to the field of power chip fabrication technology, and in particular to a power chip packaging structure on a silicon carbide substrate and its fabrication method. Background Technology

[0002] Power modules, as core components in power electronic systems that realize voltage conversion and energy transmission, are widely used in new energy vehicles, server power supplies, photovoltaic energy storage, and other fields. As these applications increasingly demand higher power density, conversion efficiency, and miniaturization, traditional power modules are gradually revealing two major technological bottlenecks:

[0003] Firstly, heat dissipation performance is insufficient. Traditional power modules mostly use organic substrates and silicon-based substrates, which have low thermal conductivity. This causes a large amount of heat to accumulate under high-frequency, high-power operation, significantly reducing conversion efficiency and even causing device failure. To solve the heat dissipation problem, existing solutions mostly adopt passive heat dissipation designs such as increasing the size of the heat sink or adding cooling pipes. This not only increases the overall size of the device but also increases system cost and energy consumption.

[0004] Secondly, the components are too large. Inductors and capacitors, as key passive components in power modules, directly determine the overall size of the converter. In existing technologies, inductors mostly adopt a planar spiral structure, which requires a large lateral space to ensure sufficient inductance value, and capacitors are mostly surface-mount capacitors. Planar inductors and surface-mount capacitors have become major bottlenecks restricting the integration and miniaturization of power modules. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the problems of insufficient heat dissipation performance of power modules and excessive device size in the prior art.

[0006] To address the aforementioned technical problems, this invention provides a power chip packaging structure on a silicon carbide substrate, comprising:

[0007] The substrate is made of silicon carbide, and a first blind slot and a second blind slot are formed on both sides of one side of the substrate. The first blind slot is used to set the transmitting chip, and the second blind slot is used to set the receiving chip.

[0008] A first blind hole area and a second blind hole area are provided between the first blind groove and the second blind groove;

[0009] The first blind hole area is provided with a plurality of first blind holes with a rectangular cross-sectional shape;

[0010] The second blind hole area is provided with several second blind holes with a rectangular cross-sectional shape;

[0011] The first blind hole is equipped with a three-dimensional inductor;

[0012] The second blind hole is equipped with a three-dimensional capacitor.

[0013] In one embodiment of the present invention, the first blind hole is a circular hole with a diameter ranging from 30 to 40 μm, and the aspect ratio of the first blind hole is 5 to 10.

[0014] The second blind hole is a circular hole with a diameter ranging from 1 to 5 μm, and the aspect ratio of the second blind hole is 10 to 15.

[0015] In one embodiment of the present invention, the distance between the first blind hole region and the second blind hole region is in the range of 500um-1000um.

[0016] In one embodiment of the present invention, the distance between the first blind groove and the second blind groove is in the range of 1mm-5mm.

[0017] In one embodiment of the present invention, a filler layer is further included, which is laid on the substrate and exposes the pad areas of the transmitter chip and receiver chip, the inductor trace area of ​​the three-dimensional inductor, and the capacitor trace area of ​​the three-dimensional capacitor by photolithography.

[0018] In one embodiment of the present invention, a metal redistribution layer is provided on the filling layer for realizing the packaging wiring of the transmitter chip and the receiver chip, as well as realizing the connection between the three-dimensional inductor and the three-dimensional capacitor.

[0019] In one embodiment of the present invention, an insulating layer is provided on the metal redistribution layer, the insulating layer is used to cover the metal redistribution layer, and at the same time exposes the external connection area of ​​the metal redistribution layer, the external connection area being provided with a solder portion.

[0020] In one embodiment of the present invention, the three-dimensional inductor is a three-dimensional spiral inductor, and the three-dimensional capacitor is a MIM capacitor. The MIM capacitor includes two metal layers M and a dielectric I located between the two metal layers M. The metal M is any one of titanium nitride, chromium, and copper, and the dielectric I is any one of hafnium oxide, aluminum oxide, and silicon nitride.

[0021] In one embodiment of the present invention, a bottom filling layer is provided on the other side of the substrate, and the inductor trace area at the bottom of the three-dimensional inductor is exposed by photolithography, and a bottom metal redistribution layer is provided in the inductor trace area at the bottom.

[0022] To address the aforementioned technical problems, this invention provides a method for fabricating a power chip packaging structure on a silicon carbide substrate, comprising:

[0023] Step S1: Dry etching is used to form the first blind trench, the second blind trench, the first blind via region, and the second blind via region on one side of the substrate;

[0024] Step S2: A three-dimensional capacitor is formed in the second blind hole region by three chemical vapor depositions of metal, dielectric, and metal, and a three-dimensional inductor is set in the first blind hole region by electroplating.

[0025] Step S3: Place the transmitting chip in the first blind slot and the receiving chip in the second blind slot;

[0026] Step S4: A filling layer is fabricated on the upper surface of the substrate on which the three-dimensional capacitor, three-dimensional inductor, transmitter chip, and receiver chip are arranged. The pad areas of the transmitter chip and receiver chip are exposed on the filling layer by photolithography, while the inductor wiring area of ​​the three-dimensional inductor and the capacitor wiring area of ​​the three-dimensional capacitor are also exposed.

[0027] Step S5: Set a metal redistribution layer on the fill layer to realize the packaging wiring of the transmitter chip and the receiver chip, as well as to realize the connection between the three-dimensional inductor and the three-dimensional capacitor.

[0028] Step S6: An insulating layer is provided on the metal redistribution layer to cover the metal redistribution layer while exposing the external interconnection area of ​​the metal redistribution layer;

[0029] Step S7: Isolate and protect one side of the substrate, and then thin the other side of the substrate to expose the bottom of the three-dimensional inductor via. Lay a bottom fill layer on the thinned substrate surface, and at the same time expose the inductor trace area at the bottom of the three-dimensional inductor by photolithography. Set a bottom metal redistribution layer in the inductor trace area at the bottom.

[0030] Step S8: Set up the soldering part in the external connection area to complete the preparation of the power chip package structure.

[0031] To solve the above-mentioned technical problems, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the power chip fabrication method described above.

[0032] To address the aforementioned technical problems, the present invention provides a computer-readable storage medium storing a computer program thereon, wherein when the computer program is executed by a processor, it implements the steps of the power chip fabrication method described above.

[0033] Compared with the prior art, the above-described technical solution of the present invention has the following advantages:

[0034] The power chip packaging structure of this invention uses silicon carbide (SiC) as its substrate. Silicon carbide has a thermal conductivity 2.3 to 3.3 times that of Si and 8 to 11 times that of GaAs, effectively solving the heat buildup problem during high-power operation of the power module and preventing the Q-value of the three-dimensional inductor from decreasing due to high temperatures. Furthermore, the silicon carbide substrate offers high resistance and process compatibility, enabling the monolithic integration of three-dimensional spiral inductors, three-dimensional capacitors, and power chips. Compared to traditional external inductor and capacitor solutions, this results in a smaller volume. Silicon carbide as a substrate also provides high-temperature resistance and radiation resistance, extending the lifespan of the DC-DC converter compared to Si substrate solutions, making it suitable for high-reliability applications such as automotive and aerospace.

[0035] The power chip packaging structure of this invention has a simple and reliable overall design, making it suitable for large-scale promotion. Attached Figure Description

[0036] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0037] Figure 1 This is a schematic diagram of a blind groove and blind hole structure formed on a substrate in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of a structure in which a chip is disposed in a blind slot and a three-dimensional inductor and capacitor are disposed in a blind via in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of a filling layer structure on a substrate in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of a structure in which a metal redistribution layer is provided on the filler layer in an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of an insulating layer structure provided on a metal redistribution layer in an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of the bottom filling layer and bottom metal redistribution layer structure prepared on the other side of the substrate in an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of a structure in which a welding part is provided on the outer connection area of ​​the metal redistribution layer in an embodiment of the present invention. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0045] Example 1

[0046] Reference Figures 1-7 As shown, this invention relates to a power chip packaging structure, comprising:

[0047] The substrate 3 has a first blind slot 4-1 and a second blind slot 4-2 on both sides of one side of the substrate 3. The first blind slot 4-1 is used to set the transmitting chip 1, and the second blind slot 4-2 is used to set the receiving chip 2.

[0048] A first blind hole area 5-1 and a second blind hole area 5-2 are provided between the first blind groove 4-1 and the second blind groove 4-2;

[0049] The first blind hole area 5-1 is provided with a plurality of first blind holes 6-1 with a rectangular cross-sectional shape;

[0050] The second blind hole area 5-2 is provided with several second blind holes 6-2 with a rectangular cross-sectional shape;

[0051] The first blind hole 6-1 is provided with a three-dimensional inductor 7;

[0052] The second blind hole 6-2 is provided with a three-dimensional capacitor 8.

[0053] The following is a detailed description of this embodiment:

[0054] Furthermore, substrate 3 is made of silicon carbide.

[0055] Furthermore, the first blind hole 6-1 is a circular hole with a diameter ranging from 30-40 μm, and the aspect ratio of the first blind hole 6-1 is 5-10. (This embodiment...) Figure 1 Four first blind holes 6-1 are provided. The second blind holes 6-2 are circular holes with a diameter ranging from 1-5 μm, and the aspect ratio of the second blind holes 6-2 is 10-15. (This embodiment...) Figure 1 Four second blind holes 6-2 are provided. In other embodiments, the first blind hole 6-1 and the second blind hole 6-2 can be square holes or hexagonal holes.

[0056] Furthermore, the distance between the first blind hole region 5-1 and the second blind hole region 5-2 ranges from 500um to 1000um.

[0057] Furthermore, the distance between the first blind slot 4-1 and the second blind slot 4-2 ranges from 1mm to 5mm.

[0058] Furthermore, in this embodiment, the three-dimensional inductor 7 and the three-dimensional capacitor 8 are manufactured using an integrated process, avoiding the increase in parasitic parameters caused by splicing multiple components. In addition, the high-density integration of the three-dimensional capacitor 8 can significantly improve the integration of the power module and the system power supply performance.

[0059] Furthermore, the three-dimensional inductor 7 is a three-dimensional spiral inductor.

[0060] Furthermore, the three-dimensional capacitor 8 is a MIM capacitor, which includes two metal layers M and a dielectric I located between the two metal layers M. The metal M is any one of titanium nitride, chromium, and copper, preferably titanium nitride with a thickness of 200 nm. The dielectric I is any one of hafnium oxide, aluminum oxide, and silicon nitride, preferably hafnium oxide with a thickness of 20 nm. Tungsten is then deposited to fill the vias of the metal M located at the top of the substrate 3 (i.e., not in contact with the second blind via 6-2).

[0061] Furthermore, both the transmitting chip 1 and the receiving chip 2 are connected to the substrate 3 via an adhesive.

[0062] This embodiment also includes a filler layer 9, which is laid on the substrate 3 and exposes the pad areas of the transmitter chip 1 and receiver chip 2, the inductor wiring area of ​​the three-dimensional inductor 7 (i.e., the area of ​​the three-dimensional inductor 7 not covered by the filler layer 9) and the capacitor wiring area of ​​the three-dimensional capacitor 8 (i.e., the area of ​​the three-dimensional capacitor 8 not covered by the filler layer 9) by photolithography.

[0063] Furthermore, the filler layer 9 is made of an insulating polymer, which is polyimide.

[0064] Furthermore, a metal redistribution layer 10 (using conductive metal) is disposed on the fill layer 9 to realize the packaging wiring of the transmitter chip 1 (pad area) and the receiver chip 2 (pad area), as well as to realize the connection between the three-dimensional inductor 7 (inductor wiring area) and the three-dimensional capacitor 8 (capacitor wiring area). At the same time, an encapsulation layer 10-1 is also disposed in the metal redistribution layer 10. The encapsulation layer 10-1 is used to prevent short circuits in the metal connections of the metal redistribution layer 10. The encapsulation layer 10-1 is made of an insulating polymer (polyimide).

[0065] Furthermore, an insulating layer 11 is provided on the metal redistribution layer 10, the insulating layer 11 is used to cover the metal redistribution layer 10, while exposing the external connection area 12 (i.e. a part of the metal redistribution layer 10), the external connection area 12 is provided with a solder part 15, the solder part 15 is used to connect with external electronic components.

[0066] Furthermore, after the insulating layer 11 is formed on the substrate 3, temporary bonding adhesive 13 and temporary bonding carrier 14 are sequentially formed on the insulating layer 11 to protect the module already fabricated on one side of the substrate 3. The substrate 3 is then thinned on the other side to expose the bottom of the vias of the three-dimensional inductor 7. Simultaneously, a bottom filler layer 9-a (made of polyimide) is laid on the thinned substrate 3 to expose the bottom inductor trace area of ​​the three-dimensional inductor 7 (i.e., the area at the bottom of the three-dimensional inductor 7 not covered by the bottom filler layer 9-a). A bottom metal redistribution layer 10-a, which is a conductive metal, is formed in this bottom inductor trace area. The bottom metal redistribution layer 10-a is part of the three-dimensional inductor 7. The three-dimensional inductor 7 as a whole consists of upper and lower metal traces and the three-dimensional inductor 7 in the middle.

[0067] Furthermore, the soldering part 15 is any one of nickel-palladium-gold, nickel-gold, titanium-copper solder pads, or BGA solder balls.

[0068] Example 2

[0069] This embodiment provides a method for fabricating a power chip packaging structure on a silicon carbide substrate. Please refer to [link to relevant documentation]. Figures 1-7 ,include:

[0070] Step S1: Dry etching is used to form a first blind trench 4-1, a second blind trench 4-2, a first blind via region 5-1, and a second blind via region 5-2 on one side of the substrate 3;

[0071] Step S2: A three-dimensional capacitor 8 is formed in the second blind hole region 5-2 by three chemical vapor deposition of metal, dielectric and metal, and a three-dimensional inductor 7 is set in the first blind hole region 5-1 by electroplating.

[0072] Step S3: Place the transmitting chip 1 in the first blind slot 4-1 and place the receiving chip 2 in the second blind slot 4-2;

[0073] Step S4: A filling layer 9 is fabricated on the upper surface of the substrate 3 on which the three-dimensional capacitor 8, three-dimensional inductor 7, transmitter chip 1, and receiver chip 2 are arranged. The pad areas of transmitter chip 1 and receiver chip 2 are exposed on the filling layer 9 by photolithography, while the inductor wiring area of ​​three-dimensional inductor 7 and the capacitor wiring area of ​​three-dimensional capacitor 8 are also exposed.

[0074] Step S5: A metal redistribution layer 10 is provided on the fill layer 9 to realize the packaging wiring of the transmitter chip 1 and the receiver chip 2, and to realize the connection between the three-dimensional inductor 7 and the three-dimensional capacitor 8.

[0075] Step S6: An insulating layer 11 is provided on the metal redistribution layer 10 to cover the metal redistribution layer 10, while exposing the external connection area 12 of the metal redistribution layer 10.

[0076] Step S7: Isolate and protect one side of the substrate 3, and then thin the other side of the substrate 3 to expose the bottom of the via of the three-dimensional inductor 7. Lay a bottom fill layer 9-a on the thinned surface of the substrate 3, and at the same time expose the inductor trace area at the bottom of the three-dimensional inductor 7 by photolithography. Set a bottom metal redistribution layer 10-a in the inductor trace area at the bottom.

[0077] Step S8: Set the welding part 15 in the external connection area 12 to complete the preparation of the power chip packaging structure.

[0078] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A power chip packaging structure on a silicon carbide substrate, characterized in that, include: The substrate (3) is made of silicon carbide. A first blind slot (4-1) and a second blind slot (4-2) are provided on both sides of one side of the substrate (3). The first blind slot (4-1) is used to set the transmitting chip (1), and the second blind slot (4-2) is used to set the receiving chip (2). A first blind hole area (5-1) and a second blind hole area (5-2) are provided between the first blind groove (4-1) and the second blind groove (4-2); The first blind hole area (5-1) is provided with a number of first blind holes (6-1) with a rectangular cross-sectional shape. The second blind hole area (5-2) has several second blind holes (6-2) with a rectangular cross-sectional shape. The first blind hole (6-1) is provided with a three-dimensional inductor (7); The second blind hole (6-2) is provided with a three-dimensional capacitor (8).

2. The power chip packaging structure on a silicon carbide substrate according to claim 1, characterized in that: The first blind hole (6-1) is a circular hole with a diameter ranging from 30 to 40 μm, and the aspect ratio of the first blind hole (6-1) is 5 to 10. The second blind hole (6-2) is a circular hole with a diameter ranging from 1 to 5 μm, and the aspect ratio of the second blind hole (6-2) is 10 to 15.

3. The power chip packaging structure on a silicon carbide substrate according to claim 1, characterized in that: The distance between the first blind hole region (5-1) and the second blind hole region (5-2) ranges from 500um to 1000um.

4. The power chip packaging structure according to claim 1, characterized in that: The distance between the first blind groove (4-1) and the second blind groove (4-2) ranges from 1mm to 5mm.

5. The power chip packaging structure on a silicon carbide substrate according to claim 1, characterized in that: It also includes a filler layer (9), which is laid on top of the substrate (3) and exposes the pad areas of the transmitter chip (1) and receiver chip (2) by photolithography, the inductor wiring area of ​​the three-dimensional inductor (7), and the capacitor wiring area of ​​the three-dimensional capacitor (8).

6. The power chip packaging structure on a silicon carbide substrate according to claim 5, characterized in that: A metal redistribution layer (10) is provided on the filling layer (9) to realize the packaging wiring of the transmitter chip (1) and the receiver chip (2), and to realize the connection between the three-dimensional inductor (7) and the three-dimensional capacitor (8).

7. The power chip packaging structure on a silicon carbide substrate according to claim 6, characterized in that: An insulating layer (11) is provided on the metal redistribution layer (10). The insulating layer (11) is used to cover the metal redistribution layer (10) and expose the external connection area (12) of the metal redistribution layer (10). The external connection area (12) is provided with a solder part (13).

8. The power chip packaging structure on a silicon carbide substrate according to claim 1, characterized in that: The three-dimensional inductor (7) is a three-dimensional spiral inductor, and the three-dimensional capacitor (8) is a MIM capacitor. The MIM capacitor includes two metal layers M and a dielectric I located between the two metal layers M. The metal M is any one of titanium nitride, chromium, and copper, and the dielectric I is any one of hafnium oxide, aluminum oxide, and silicon nitride.

9. The power chip packaging structure on a silicon carbide substrate according to claim 1, characterized in that: The other side of the substrate (3) is provided with a bottom filling layer (9-a), and the inductance trace area at the bottom of the three-dimensional inductor (7) is exposed by photolithography. A bottom metal redistribution layer (10-a) is provided in the inductance trace area at the bottom.

10. A method for fabricating a power chip packaging structure on a silicon carbide substrate, characterized in that, include: Step S1: On one side of the substrate (3), a first blind trench (4-1), a second blind trench (4-2), a first blind hole area (5-1), and a second blind hole area (5-2) are etched by dry etching. Step S2: A three-dimensional capacitor (8) is formed in the second blind hole region (5-2) by three chemical vapor deposition of metal, dielectric and metal, and a three-dimensional inductor (7) is set in the first blind hole region (5-1) by electroplating. Step S3: Place the transmitting chip (1) in the first blind slot (4-1) and place the receiving chip (2) in the second blind slot (4-2); Step S4: A filling layer (9) is fabricated on the upper surface of the substrate (3) on which the three-dimensional capacitor (8), three-dimensional inductor (7), transmitter chip (1), and receiver chip (2) are arranged. The pad areas of transmitter chip (1) and receiver chip (2) are exposed on the filling layer (9) by photolithography, while the inductor wiring area of ​​the three-dimensional inductor (7) and the capacitor wiring area of ​​the three-dimensional capacitor (8) are exposed. Step S5: Set a metal redistribution layer (10) on the fill layer (9) to realize the packaging wiring of the transmitter chip (1) and the receiver chip (2), and to realize the connection between the three-dimensional inductor (7) and the three-dimensional capacitor (8); Step S6: An insulating layer (11) is provided on the metal redistribution layer (10) to cover the metal redistribution layer (10) while exposing the external connection area (12) of the metal redistribution layer (10). Step S7: Isolate and protect one side of the substrate (3), and then thin the other side of the substrate (3) to expose the bottom of the via of the three-dimensional inductor (7). Lay a bottom fill layer (9-a) on the thinned substrate (3) surface, and at the same time expose the inductor trace area at the bottom of the three-dimensional inductor (7) by photolithography. Set a bottom metal redistribution layer (10-a) in the inductor trace area at the bottom. Step S8: Set the welding part (15) in the external connection area (12) to complete the preparation of the power chip packaging structure.

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